1 /* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2006 Dave Airlie 4 * Copyright 2007 Maarten Maathuis 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 23 * DEALINGS IN THE SOFTWARE. 24 */ 25 #include <linux/pm_runtime.h> 26 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/drm_fourcc.h> 29 #include <drm/drm_plane_helper.h> 30 #include <drm/drm_vblank.h> 31 32 #include "nouveau_drv.h" 33 #include "nouveau_reg.h" 34 #include "nouveau_ttm.h" 35 #include "nouveau_bo.h" 36 #include "nouveau_gem.h" 37 #include "nouveau_encoder.h" 38 #include "nouveau_connector.h" 39 #include "nouveau_crtc.h" 40 #include "hw.h" 41 #include "nvreg.h" 42 #include "nouveau_fbcon.h" 43 #include "disp.h" 44 #include "nouveau_dma.h" 45 46 #include <subdev/bios/pll.h> 47 #include <subdev/clk.h> 48 49 static int 50 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 51 struct drm_framebuffer *old_fb); 52 53 static void 54 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 55 { 56 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 57 crtcstate->CRTC[index]); 58 } 59 60 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) 61 { 62 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 63 struct drm_device *dev = crtc->dev; 64 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 65 66 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; 67 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { 68 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; 69 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; 70 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); 71 } 72 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); 73 } 74 75 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) 76 { 77 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 78 struct drm_device *dev = crtc->dev; 79 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 80 81 nv_crtc->sharpness = level; 82 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */ 83 level += 0x40; 84 regp->ramdac_634 = level; 85 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); 86 } 87 88 #define PLLSEL_VPLL1_MASK \ 89 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \ 90 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2) 91 #define PLLSEL_VPLL2_MASK \ 92 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \ 93 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2) 94 #define PLLSEL_TV_MASK \ 95 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \ 96 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \ 97 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \ 98 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2) 99 100 /* NV4x 0x40.. pll notes: 101 * gpu pll: 0x4000 + 0x4004 102 * ?gpu? pll: 0x4008 + 0x400c 103 * vpll1: 0x4010 + 0x4014 104 * vpll2: 0x4018 + 0x401c 105 * mpll: 0x4020 + 0x4024 106 * mpll: 0x4038 + 0x403c 107 * 108 * the first register of each pair has some unknown details: 109 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?) 110 * bits 20-23: (mpll) something to do with post divider? 111 * bits 28-31: related to single stage mode? (bit 8/12) 112 */ 113 114 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock) 115 { 116 struct drm_device *dev = crtc->dev; 117 struct nouveau_drm *drm = nouveau_drm(dev); 118 struct nvkm_bios *bios = nvxx_bios(&drm->client.device); 119 struct nvkm_clk *clk = nvxx_clk(&drm->client.device); 120 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 121 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 122 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index]; 123 struct nvkm_pll_vals *pv = ®p->pllvals; 124 struct nvbios_pll pll_lim; 125 126 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0, 127 &pll_lim)) 128 return; 129 130 /* NM2 == 0 is used to determine single stage mode on two stage plls */ 131 pv->NM2 = 0; 132 133 /* for newer nv4x the blob uses only the first stage of the vpll below a 134 * certain clock. for a certain nv4b this is 150MHz. since the max 135 * output frequency of the first stage for this card is 300MHz, it is 136 * assumed the threshold is given by vco1 maxfreq/2 137 */ 138 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6, 139 * not 8, others unknown), the blob always uses both plls. no problem 140 * has yet been observed in allowing the use a single stage pll on all 141 * nv43 however. the behaviour of single stage use is untested on nv40 142 */ 143 if (drm->client.device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2)) 144 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2)); 145 146 147 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv)) 148 return; 149 150 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK; 151 152 /* The blob uses this always, so let's do the same */ 153 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 154 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE; 155 /* again nv40 and some nv43 act more like nv3x as described above */ 156 if (drm->client.device.info.chipset < 0x41) 157 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL | 158 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL; 159 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK; 160 161 if (pv->NM2) 162 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n", 163 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P); 164 else 165 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n", 166 pv->N1, pv->M1, pv->log2P); 167 168 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 169 } 170 171 static void 172 nv_crtc_dpms(struct drm_crtc *crtc, int mode) 173 { 174 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 175 struct drm_device *dev = crtc->dev; 176 struct nouveau_drm *drm = nouveau_drm(dev); 177 unsigned char seq1 = 0, crtc17 = 0; 178 unsigned char crtc1A; 179 180 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, 181 nv_crtc->index); 182 183 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */ 184 return; 185 186 nv_crtc->last_dpms = mode; 187 188 if (nv_two_heads(dev)) 189 NVSetOwner(dev, nv_crtc->index); 190 191 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */ 192 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index, 193 NV_CIO_CRE_RPC1_INDEX) & ~0xC0; 194 switch (mode) { 195 case DRM_MODE_DPMS_STANDBY: 196 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */ 197 seq1 = 0x20; 198 crtc17 = 0x80; 199 crtc1A |= 0x80; 200 break; 201 case DRM_MODE_DPMS_SUSPEND: 202 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */ 203 seq1 = 0x20; 204 crtc17 = 0x80; 205 crtc1A |= 0x40; 206 break; 207 case DRM_MODE_DPMS_OFF: 208 /* Screen: Off; HSync: Off, VSync: Off */ 209 seq1 = 0x20; 210 crtc17 = 0x00; 211 crtc1A |= 0xC0; 212 break; 213 case DRM_MODE_DPMS_ON: 214 default: 215 /* Screen: On; HSync: On, VSync: On */ 216 seq1 = 0x00; 217 crtc17 = 0x80; 218 break; 219 } 220 221 NVVgaSeqReset(dev, nv_crtc->index, true); 222 /* Each head has it's own sequencer, so we can turn it off when we want */ 223 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20); 224 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1); 225 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80); 226 mdelay(10); 227 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17); 228 NVVgaSeqReset(dev, nv_crtc->index, false); 229 230 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A); 231 } 232 233 static void 234 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) 235 { 236 struct drm_device *dev = crtc->dev; 237 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 238 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 239 struct drm_framebuffer *fb = crtc->primary->fb; 240 241 /* Calculate our timings */ 242 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1; 243 int horizStart = (mode->crtc_hsync_start >> 3) + 1; 244 int horizEnd = (mode->crtc_hsync_end >> 3) + 1; 245 int horizTotal = (mode->crtc_htotal >> 3) - 5; 246 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1; 247 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1; 248 int vertDisplay = mode->crtc_vdisplay - 1; 249 int vertStart = mode->crtc_vsync_start - 1; 250 int vertEnd = mode->crtc_vsync_end - 1; 251 int vertTotal = mode->crtc_vtotal - 2; 252 int vertBlankStart = mode->crtc_vdisplay - 1; 253 int vertBlankEnd = mode->crtc_vtotal - 1; 254 255 struct drm_encoder *encoder; 256 bool fp_output = false; 257 258 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 259 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 260 261 if (encoder->crtc == crtc && 262 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS || 263 nv_encoder->dcb->type == DCB_OUTPUT_TMDS)) 264 fp_output = true; 265 } 266 267 if (fp_output) { 268 vertStart = vertTotal - 3; 269 vertEnd = vertTotal - 2; 270 vertBlankStart = vertStart; 271 horizStart = horizTotal - 5; 272 horizEnd = horizTotal - 2; 273 horizBlankEnd = horizTotal + 4; 274 #if 0 275 if (dev->overlayAdaptor && drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 276 /* This reportedly works around some video overlay bandwidth problems */ 277 horizTotal += 2; 278 #endif 279 } 280 281 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 282 vertTotal |= 1; 283 284 #if 0 285 ErrorF("horizDisplay: 0x%X \n", horizDisplay); 286 ErrorF("horizStart: 0x%X \n", horizStart); 287 ErrorF("horizEnd: 0x%X \n", horizEnd); 288 ErrorF("horizTotal: 0x%X \n", horizTotal); 289 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart); 290 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd); 291 ErrorF("vertDisplay: 0x%X \n", vertDisplay); 292 ErrorF("vertStart: 0x%X \n", vertStart); 293 ErrorF("vertEnd: 0x%X \n", vertEnd); 294 ErrorF("vertTotal: 0x%X \n", vertTotal); 295 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart); 296 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd); 297 #endif 298 299 /* 300 * compute correct Hsync & Vsync polarity 301 */ 302 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)) 303 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) { 304 305 regp->MiscOutReg = 0x23; 306 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 307 regp->MiscOutReg |= 0x40; 308 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 309 regp->MiscOutReg |= 0x80; 310 } else { 311 int vdisplay = mode->vdisplay; 312 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 313 vdisplay *= 2; 314 if (mode->vscan > 1) 315 vdisplay *= mode->vscan; 316 if (vdisplay < 400) 317 regp->MiscOutReg = 0xA3; /* +hsync -vsync */ 318 else if (vdisplay < 480) 319 regp->MiscOutReg = 0x63; /* -hsync +vsync */ 320 else if (vdisplay < 768) 321 regp->MiscOutReg = 0xE3; /* -hsync -vsync */ 322 else 323 regp->MiscOutReg = 0x23; /* +hsync +vsync */ 324 } 325 326 /* 327 * Time Sequencer 328 */ 329 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00; 330 /* 0x20 disables the sequencer */ 331 if (mode->flags & DRM_MODE_FLAG_CLKDIV2) 332 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29; 333 else 334 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21; 335 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F; 336 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00; 337 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E; 338 339 /* 340 * CRTC 341 */ 342 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; 343 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; 344 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; 345 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | 346 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0); 347 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; 348 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | 349 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0); 350 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; 351 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | 352 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) | 353 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) | 354 (1 << 4) | 355 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) | 356 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) | 357 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) | 358 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8); 359 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; 360 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) | 361 1 << 6 | 362 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9); 363 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; 364 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; 365 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; 366 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; 367 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; 368 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; 369 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; 370 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); 371 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; 372 /* framebuffer can be larger than crtc scanout area. */ 373 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; 374 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; 375 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; 376 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; 377 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; 378 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; 379 380 /* 381 * Some extended CRTC registers (they are not saved with the rest of the vga regs). 382 */ 383 384 /* framebuffer can be larger than crtc scanout area. */ 385 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 386 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 387 regp->CRTC[NV_CIO_CRE_42] = 388 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 389 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? 390 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; 391 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | 392 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) | 393 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) | 394 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) | 395 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10); 396 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | 397 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) | 398 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) | 399 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8); 400 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | 401 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) | 402 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) | 403 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11); 404 405 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 406 horizTotal = (horizTotal >> 1) & ~1; 407 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; 408 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); 409 } else 410 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ 411 412 /* 413 * Graphics Display Controller 414 */ 415 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00; 416 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00; 417 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00; 418 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00; 419 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00; 420 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */ 421 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */ 422 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F; 423 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF; 424 425 regp->Attribute[0] = 0x00; /* standard colormap translation */ 426 regp->Attribute[1] = 0x01; 427 regp->Attribute[2] = 0x02; 428 regp->Attribute[3] = 0x03; 429 regp->Attribute[4] = 0x04; 430 regp->Attribute[5] = 0x05; 431 regp->Attribute[6] = 0x06; 432 regp->Attribute[7] = 0x07; 433 regp->Attribute[8] = 0x08; 434 regp->Attribute[9] = 0x09; 435 regp->Attribute[10] = 0x0A; 436 regp->Attribute[11] = 0x0B; 437 regp->Attribute[12] = 0x0C; 438 regp->Attribute[13] = 0x0D; 439 regp->Attribute[14] = 0x0E; 440 regp->Attribute[15] = 0x0F; 441 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */ 442 /* Non-vga */ 443 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00; 444 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */ 445 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00; 446 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00; 447 } 448 449 /** 450 * Sets up registers for the given mode/adjusted_mode pair. 451 * 452 * The clocks, CRTCs and outputs attached to this CRTC must be off. 453 * 454 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 455 * be easily turned on/off after this. 456 */ 457 static void 458 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) 459 { 460 struct drm_device *dev = crtc->dev; 461 struct nouveau_drm *drm = nouveau_drm(dev); 462 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 463 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 464 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index]; 465 const struct drm_framebuffer *fb = crtc->primary->fb; 466 struct drm_encoder *encoder; 467 bool lvds_output = false, tmds_output = false, tv_output = false, 468 off_chip_digital = false; 469 470 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 471 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); 472 bool digital = false; 473 474 if (encoder->crtc != crtc) 475 continue; 476 477 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) 478 digital = lvds_output = true; 479 if (nv_encoder->dcb->type == DCB_OUTPUT_TV) 480 tv_output = true; 481 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) 482 digital = tmds_output = true; 483 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) 484 off_chip_digital = true; 485 } 486 487 /* Registers not directly related to the (s)vga mode */ 488 489 /* What is the meaning of this register? */ 490 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */ 491 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); 492 493 regp->crtc_eng_ctrl = 0; 494 /* Except for rare conditions I2C is enabled on the primary crtc */ 495 if (nv_crtc->index == 0) 496 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C; 497 #if 0 498 /* Set overlay to desired crtc. */ 499 if (dev->overlayAdaptor) { 500 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev); 501 if (pPriv->overlayCRTC == nv_crtc->index) 502 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY; 503 } 504 #endif 505 506 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */ 507 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | 508 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | 509 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM; 510 if (drm->client.device.info.chipset >= 0x11) 511 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32; 512 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 513 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE; 514 515 /* Unblock some timings */ 516 regp->CRTC[NV_CIO_CRE_53] = 0; 517 regp->CRTC[NV_CIO_CRE_54] = 0; 518 519 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */ 520 if (lvds_output) 521 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; 522 else if (tmds_output) 523 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; 524 else 525 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; 526 527 /* These values seem to vary */ 528 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */ 529 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; 530 531 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); 532 533 /* probably a scratch reg, but kept for cargo-cult purposes: 534 * bit0: crtc0?, head A 535 * bit6: lvds, head A 536 * bit7: (only in X), head A 537 */ 538 if (nv_crtc->index == 0) 539 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; 540 541 /* The blob seems to take the current value from crtc 0, add 4 to that 542 * and reuse the old value for crtc 1 */ 543 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY]; 544 if (!nv_crtc->index) 545 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; 546 547 /* the blob sometimes sets |= 0x10 (which is the same as setting |= 548 * 1 << 30 on 0x60.830), for no apparent reason */ 549 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; 550 551 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 552 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; 553 554 regp->crtc_830 = mode->crtc_vdisplay - 3; 555 regp->crtc_834 = mode->crtc_vdisplay - 1; 556 557 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 558 /* This is what the blob does */ 559 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850); 560 561 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) 562 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT); 563 564 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 565 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC; 566 else 567 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC; 568 569 /* Some misc regs */ 570 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 571 regp->CRTC[NV_CIO_CRE_85] = 0xFF; 572 regp->CRTC[NV_CIO_CRE_86] = 0x1; 573 } 574 575 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; 576 /* Enable slaved mode (called MODE_TV in nv4ref.h) */ 577 if (lvds_output || tmds_output || tv_output) 578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); 579 580 /* Generic PRAMDAC regs */ 581 582 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) 583 /* Only bit that bios and blob set. */ 584 regp->nv10_cursync = (1 << 25); 585 586 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | 587 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | 588 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON; 589 if (fb->format->depth == 16) 590 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 591 if (drm->client.device.info.chipset >= 0x11) 592 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG; 593 594 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */ 595 regp->tv_setup = 0; 596 597 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); 598 599 /* Some values the blob sets */ 600 regp->ramdac_8c0 = 0x100; 601 regp->ramdac_a20 = 0x0; 602 regp->ramdac_a24 = 0xfffff; 603 regp->ramdac_a34 = 0x1; 604 } 605 606 static int 607 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) 608 { 609 struct nv04_display *disp = nv04_display(crtc->dev); 610 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); 611 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 612 int ret; 613 614 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, false); 615 if (ret == 0) { 616 if (disp->image[nv_crtc->index]) 617 nouveau_bo_unpin(disp->image[nv_crtc->index]); 618 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]); 619 } 620 621 return ret; 622 } 623 624 /** 625 * Sets up registers for the given mode/adjusted_mode pair. 626 * 627 * The clocks, CRTCs and outputs attached to this CRTC must be off. 628 * 629 * This shouldn't enable any clocks, CRTCs, or outputs, but they should 630 * be easily turned on/off after this. 631 */ 632 static int 633 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, 634 struct drm_display_mode *adjusted_mode, 635 int x, int y, struct drm_framebuffer *old_fb) 636 { 637 struct drm_device *dev = crtc->dev; 638 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 639 struct nouveau_drm *drm = nouveau_drm(dev); 640 int ret; 641 642 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); 643 drm_mode_debug_printmodeline(adjusted_mode); 644 645 ret = nv_crtc_swap_fbs(crtc, old_fb); 646 if (ret) 647 return ret; 648 649 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */ 650 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1); 651 652 nv_crtc_mode_set_vga(crtc, adjusted_mode); 653 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */ 654 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 655 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); 656 nv_crtc_mode_set_regs(crtc, adjusted_mode); 657 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); 658 return 0; 659 } 660 661 static void nv_crtc_save(struct drm_crtc *crtc) 662 { 663 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 664 struct drm_device *dev = crtc->dev; 665 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; 666 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index]; 667 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg; 668 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index]; 669 670 if (nv_two_heads(crtc->dev)) 671 NVSetOwner(crtc->dev, nv_crtc->index); 672 673 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); 674 675 /* init some state to saved value */ 676 state->sel_clk = saved->sel_clk & ~(0x5 << 16); 677 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; 678 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK); 679 crtc_state->gpio_ext = crtc_saved->gpio_ext; 680 } 681 682 static void nv_crtc_restore(struct drm_crtc *crtc) 683 { 684 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 685 struct drm_device *dev = crtc->dev; 686 int head = nv_crtc->index; 687 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; 688 689 if (nv_two_heads(crtc->dev)) 690 NVSetOwner(crtc->dev, head); 691 692 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); 693 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); 694 695 nv_crtc->last_dpms = NV_DPMS_CLEARED; 696 } 697 698 static void nv_crtc_prepare(struct drm_crtc *crtc) 699 { 700 struct drm_device *dev = crtc->dev; 701 struct nouveau_drm *drm = nouveau_drm(dev); 702 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 703 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 704 705 if (nv_two_heads(dev)) 706 NVSetOwner(dev, nv_crtc->index); 707 708 drm_crtc_vblank_off(crtc); 709 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); 710 711 NVBlankScreen(dev, nv_crtc->index, true); 712 713 /* Some more preparation. */ 714 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA); 715 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) { 716 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900); 717 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000); 718 } 719 } 720 721 static void nv_crtc_commit(struct drm_crtc *crtc) 722 { 723 struct drm_device *dev = crtc->dev; 724 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; 725 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 726 727 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 728 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); 729 730 #ifdef __BIG_ENDIAN 731 /* turn on LFB swapping */ 732 { 733 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR); 734 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG); 735 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp); 736 } 737 #endif 738 739 funcs->dpms(crtc, DRM_MODE_DPMS_ON); 740 drm_crtc_vblank_on(crtc); 741 } 742 743 static void nv_crtc_destroy(struct drm_crtc *crtc) 744 { 745 struct nv04_display *disp = nv04_display(crtc->dev); 746 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 747 748 if (!nv_crtc) 749 return; 750 751 drm_crtc_cleanup(crtc); 752 753 if (disp->image[nv_crtc->index]) 754 nouveau_bo_unpin(disp->image[nv_crtc->index]); 755 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 756 757 nouveau_bo_unmap(nv_crtc->cursor.nvbo); 758 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 759 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 760 kfree(nv_crtc); 761 } 762 763 static void 764 nv_crtc_gamma_load(struct drm_crtc *crtc) 765 { 766 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 767 struct drm_device *dev = nv_crtc->base.dev; 768 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs; 769 u16 *r, *g, *b; 770 int i; 771 772 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; 773 r = crtc->gamma_store; 774 g = r + crtc->gamma_size; 775 b = g + crtc->gamma_size; 776 777 for (i = 0; i < 256; i++) { 778 rgbs[i].r = *r++ >> 8; 779 rgbs[i].g = *g++ >> 8; 780 rgbs[i].b = *b++ >> 8; 781 } 782 783 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); 784 } 785 786 static void 787 nv_crtc_disable(struct drm_crtc *crtc) 788 { 789 struct nv04_display *disp = nv04_display(crtc->dev); 790 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 791 if (disp->image[nv_crtc->index]) 792 nouveau_bo_unpin(disp->image[nv_crtc->index]); 793 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]); 794 } 795 796 static int 797 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, 798 uint32_t size, 799 struct drm_modeset_acquire_ctx *ctx) 800 { 801 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 802 803 /* We need to know the depth before we upload, but it's possible to 804 * get called before a framebuffer is bound. If this is the case, 805 * mark the lut values as dirty by setting depth==0, and it'll be 806 * uploaded on the first mode_set_base() 807 */ 808 if (!nv_crtc->base.primary->fb) { 809 nv_crtc->lut.depth = 0; 810 return 0; 811 } 812 813 nv_crtc_gamma_load(crtc); 814 815 return 0; 816 } 817 818 static int 819 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, 820 struct drm_framebuffer *passed_fb, 821 int x, int y, bool atomic) 822 { 823 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 824 struct drm_device *dev = crtc->dev; 825 struct nouveau_drm *drm = nouveau_drm(dev); 826 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 827 struct drm_framebuffer *drm_fb; 828 struct nouveau_framebuffer *fb; 829 int arb_burst, arb_lwm; 830 831 NV_DEBUG(drm, "index %d\n", nv_crtc->index); 832 833 /* no fb bound */ 834 if (!atomic && !crtc->primary->fb) { 835 NV_DEBUG(drm, "No FB bound\n"); 836 return 0; 837 } 838 839 /* If atomic, we want to switch to the fb we were passed, so 840 * now we update pointers to do that. 841 */ 842 if (atomic) { 843 drm_fb = passed_fb; 844 fb = nouveau_framebuffer(passed_fb); 845 } else { 846 drm_fb = crtc->primary->fb; 847 fb = nouveau_framebuffer(crtc->primary->fb); 848 } 849 850 nv_crtc->fb.offset = fb->nvbo->bo.offset; 851 852 if (nv_crtc->lut.depth != drm_fb->format->depth) { 853 nv_crtc->lut.depth = drm_fb->format->depth; 854 nv_crtc_gamma_load(crtc); 855 } 856 857 /* Update the framebuffer format. */ 858 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; 859 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; 860 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 861 if (drm_fb->format->depth == 16) 862 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL; 863 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); 864 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, 865 regp->ramdac_gen_ctrl); 866 867 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; 868 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = 869 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8); 870 regp->CRTC[NV_CIO_CRE_42] = 871 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11); 872 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); 873 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); 874 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); 875 876 /* Update the framebuffer location. */ 877 regp->fb_start = nv_crtc->fb.offset & ~3; 878 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->format->cpp[0]); 879 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); 880 881 /* Update the arbitration parameters. */ 882 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8, 883 &arb_burst, &arb_lwm); 884 885 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; 886 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; 887 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); 888 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); 889 890 if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) { 891 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; 892 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); 893 } 894 895 return 0; 896 } 897 898 static int 899 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 900 struct drm_framebuffer *old_fb) 901 { 902 int ret = nv_crtc_swap_fbs(crtc, old_fb); 903 if (ret) 904 return ret; 905 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); 906 } 907 908 static int 909 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, 910 struct drm_framebuffer *fb, 911 int x, int y, enum mode_set_atomic state) 912 { 913 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 914 struct drm_device *dev = drm->dev; 915 916 if (state == ENTER_ATOMIC_MODE_SET) 917 nouveau_fbcon_accel_save_disable(dev); 918 else 919 nouveau_fbcon_accel_restore(dev); 920 921 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); 922 } 923 924 static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 925 struct nouveau_bo *dst) 926 { 927 int width = nv_cursor_width(dev); 928 uint32_t pixel; 929 int i, j; 930 931 for (i = 0; i < width; i++) { 932 for (j = 0; j < width; j++) { 933 pixel = nouveau_bo_rd32(src, i*64 + j); 934 935 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16 936 | (pixel & 0xf80000) >> 9 937 | (pixel & 0xf800) >> 6 938 | (pixel & 0xf8) >> 3); 939 } 940 } 941 } 942 943 static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src, 944 struct nouveau_bo *dst) 945 { 946 uint32_t pixel; 947 int alpha, i; 948 949 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha 950 * cursors (though NPM in combination with fp dithering may not work on 951 * nv11, from "nv" driver history) 952 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the 953 * blob uses, however we get given PM cursors so we use PM mode 954 */ 955 for (i = 0; i < 64 * 64; i++) { 956 pixel = nouveau_bo_rd32(src, i); 957 958 /* hw gets unhappy if alpha <= rgb values. for a PM image "less 959 * than" shouldn't happen; fix "equal to" case by adding one to 960 * alpha channel (slightly inaccurate, but so is attempting to 961 * get back to NPM images, due to limits of integer precision) 962 */ 963 alpha = pixel >> 24; 964 if (alpha > 0 && alpha < 255) 965 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24); 966 967 #ifdef __BIG_ENDIAN 968 { 969 struct nouveau_drm *drm = nouveau_drm(dev); 970 971 if (drm->client.device.info.chipset == 0x11) { 972 pixel = ((pixel & 0x000000ff) << 24) | 973 ((pixel & 0x0000ff00) << 8) | 974 ((pixel & 0x00ff0000) >> 8) | 975 ((pixel & 0xff000000) >> 24); 976 } 977 } 978 #endif 979 980 nouveau_bo_wr32(dst, i, pixel); 981 } 982 } 983 984 static int 985 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, 986 uint32_t buffer_handle, uint32_t width, uint32_t height) 987 { 988 struct nouveau_drm *drm = nouveau_drm(crtc->dev); 989 struct drm_device *dev = drm->dev; 990 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 991 struct nouveau_bo *cursor = NULL; 992 struct drm_gem_object *gem; 993 int ret = 0; 994 995 if (!buffer_handle) { 996 nv_crtc->cursor.hide(nv_crtc, true); 997 return 0; 998 } 999 1000 if (width != 64 || height != 64) 1001 return -EINVAL; 1002 1003 gem = drm_gem_object_lookup(file_priv, buffer_handle); 1004 if (!gem) 1005 return -ENOENT; 1006 cursor = nouveau_gem_object(gem); 1007 1008 ret = nouveau_bo_map(cursor); 1009 if (ret) 1010 goto out; 1011 1012 if (drm->client.device.info.chipset >= 0x11) 1013 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1014 else 1015 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo); 1016 1017 nouveau_bo_unmap(cursor); 1018 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset; 1019 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset); 1020 nv_crtc->cursor.show(nv_crtc, true); 1021 out: 1022 drm_gem_object_put_unlocked(gem); 1023 return ret; 1024 } 1025 1026 static int 1027 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) 1028 { 1029 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); 1030 1031 nv_crtc->cursor.set_pos(nv_crtc, x, y); 1032 return 0; 1033 } 1034 1035 static int 1036 nouveau_crtc_set_config(struct drm_mode_set *set, 1037 struct drm_modeset_acquire_ctx *ctx) 1038 { 1039 struct drm_device *dev; 1040 struct nouveau_drm *drm; 1041 int ret; 1042 struct drm_crtc *crtc; 1043 bool active = false; 1044 if (!set || !set->crtc) 1045 return -EINVAL; 1046 1047 dev = set->crtc->dev; 1048 1049 /* get a pm reference here */ 1050 ret = pm_runtime_get_sync(dev->dev); 1051 if (ret < 0 && ret != -EACCES) 1052 return ret; 1053 1054 ret = drm_crtc_helper_set_config(set, ctx); 1055 1056 drm = nouveau_drm(dev); 1057 1058 /* if we get here with no crtcs active then we can drop a reference */ 1059 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1060 if (crtc->enabled) 1061 active = true; 1062 } 1063 1064 pm_runtime_mark_last_busy(dev->dev); 1065 /* if we have active crtcs and we don't have a power ref, 1066 take the current one */ 1067 if (active && !drm->have_disp_power_ref) { 1068 drm->have_disp_power_ref = true; 1069 return ret; 1070 } 1071 /* if we have no active crtcs, then drop the power ref 1072 we got before */ 1073 if (!active && drm->have_disp_power_ref) { 1074 pm_runtime_put_autosuspend(dev->dev); 1075 drm->have_disp_power_ref = false; 1076 } 1077 /* drop the power reference we got coming in here */ 1078 pm_runtime_put_autosuspend(dev->dev); 1079 return ret; 1080 } 1081 1082 struct nv04_page_flip_state { 1083 struct list_head head; 1084 struct drm_pending_vblank_event *event; 1085 struct drm_crtc *crtc; 1086 int bpp, pitch; 1087 u64 offset; 1088 }; 1089 1090 static int 1091 nv04_finish_page_flip(struct nouveau_channel *chan, 1092 struct nv04_page_flip_state *ps) 1093 { 1094 struct nouveau_fence_chan *fctx = chan->fence; 1095 struct nouveau_drm *drm = chan->drm; 1096 struct drm_device *dev = drm->dev; 1097 struct nv04_page_flip_state *s; 1098 unsigned long flags; 1099 1100 spin_lock_irqsave(&dev->event_lock, flags); 1101 1102 if (list_empty(&fctx->flip)) { 1103 NV_ERROR(drm, "unexpected pageflip\n"); 1104 spin_unlock_irqrestore(&dev->event_lock, flags); 1105 return -EINVAL; 1106 } 1107 1108 s = list_first_entry(&fctx->flip, struct nv04_page_flip_state, head); 1109 if (s->event) { 1110 drm_crtc_arm_vblank_event(s->crtc, s->event); 1111 } else { 1112 /* Give up ownership of vblank for page-flipped crtc */ 1113 drm_crtc_vblank_put(s->crtc); 1114 } 1115 1116 list_del(&s->head); 1117 if (ps) 1118 *ps = *s; 1119 kfree(s); 1120 1121 spin_unlock_irqrestore(&dev->event_lock, flags); 1122 return 0; 1123 } 1124 1125 int 1126 nv04_flip_complete(struct nvif_notify *notify) 1127 { 1128 struct nouveau_cli *cli = (void *)notify->object->client; 1129 struct nouveau_drm *drm = cli->drm; 1130 struct nouveau_channel *chan = drm->channel; 1131 struct nv04_page_flip_state state; 1132 1133 if (!nv04_finish_page_flip(chan, &state)) { 1134 nv_set_crtc_base(drm->dev, drm_crtc_index(state.crtc), 1135 state.offset + state.crtc->y * 1136 state.pitch + state.crtc->x * 1137 state.bpp / 8); 1138 } 1139 1140 return NVIF_NOTIFY_KEEP; 1141 } 1142 1143 static int 1144 nv04_page_flip_emit(struct nouveau_channel *chan, 1145 struct nouveau_bo *old_bo, 1146 struct nouveau_bo *new_bo, 1147 struct nv04_page_flip_state *s, 1148 struct nouveau_fence **pfence) 1149 { 1150 struct nouveau_fence_chan *fctx = chan->fence; 1151 struct nouveau_drm *drm = chan->drm; 1152 struct drm_device *dev = drm->dev; 1153 unsigned long flags; 1154 int ret; 1155 1156 /* Queue it to the pending list */ 1157 spin_lock_irqsave(&dev->event_lock, flags); 1158 list_add_tail(&s->head, &fctx->flip); 1159 spin_unlock_irqrestore(&dev->event_lock, flags); 1160 1161 /* Synchronize with the old framebuffer */ 1162 ret = nouveau_fence_sync(old_bo, chan, false, false); 1163 if (ret) 1164 goto fail; 1165 1166 /* Emit the pageflip */ 1167 ret = RING_SPACE(chan, 2); 1168 if (ret) 1169 goto fail; 1170 1171 BEGIN_NV04(chan, NvSubSw, NV_SW_PAGE_FLIP, 1); 1172 OUT_RING (chan, 0x00000000); 1173 FIRE_RING (chan); 1174 1175 ret = nouveau_fence_new(chan, false, pfence); 1176 if (ret) 1177 goto fail; 1178 1179 return 0; 1180 fail: 1181 spin_lock_irqsave(&dev->event_lock, flags); 1182 list_del(&s->head); 1183 spin_unlock_irqrestore(&dev->event_lock, flags); 1184 return ret; 1185 } 1186 1187 static int 1188 nv04_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 1189 struct drm_pending_vblank_event *event, u32 flags, 1190 struct drm_modeset_acquire_ctx *ctx) 1191 { 1192 const int swap_interval = (flags & DRM_MODE_PAGE_FLIP_ASYNC) ? 0 : 1; 1193 struct drm_device *dev = crtc->dev; 1194 struct nouveau_drm *drm = nouveau_drm(dev); 1195 struct nouveau_bo *old_bo = nouveau_framebuffer(crtc->primary->fb)->nvbo; 1196 struct nouveau_bo *new_bo = nouveau_framebuffer(fb)->nvbo; 1197 struct nv04_page_flip_state *s; 1198 struct nouveau_channel *chan; 1199 struct nouveau_cli *cli; 1200 struct nouveau_fence *fence; 1201 struct nv04_display *dispnv04 = nv04_display(dev); 1202 int head = nouveau_crtc(crtc)->index; 1203 int ret; 1204 1205 chan = drm->channel; 1206 if (!chan) 1207 return -ENODEV; 1208 cli = (void *)chan->user.client; 1209 1210 s = kzalloc(sizeof(*s), GFP_KERNEL); 1211 if (!s) 1212 return -ENOMEM; 1213 1214 if (new_bo != old_bo) { 1215 ret = nouveau_bo_pin(new_bo, TTM_PL_FLAG_VRAM, true); 1216 if (ret) 1217 goto fail_free; 1218 } 1219 1220 mutex_lock(&cli->mutex); 1221 ret = ttm_bo_reserve(&new_bo->bo, true, false, NULL); 1222 if (ret) 1223 goto fail_unpin; 1224 1225 /* synchronise rendering channel with the kernel's channel */ 1226 ret = nouveau_fence_sync(new_bo, chan, false, true); 1227 if (ret) { 1228 ttm_bo_unreserve(&new_bo->bo); 1229 goto fail_unpin; 1230 } 1231 1232 if (new_bo != old_bo) { 1233 ttm_bo_unreserve(&new_bo->bo); 1234 1235 ret = ttm_bo_reserve(&old_bo->bo, true, false, NULL); 1236 if (ret) 1237 goto fail_unpin; 1238 } 1239 1240 /* Initialize a page flip struct */ 1241 *s = (struct nv04_page_flip_state) 1242 { { }, event, crtc, fb->format->cpp[0] * 8, fb->pitches[0], 1243 new_bo->bo.offset }; 1244 1245 /* Keep vblanks on during flip, for the target crtc of this flip */ 1246 drm_crtc_vblank_get(crtc); 1247 1248 /* Emit a page flip */ 1249 if (swap_interval) { 1250 ret = RING_SPACE(chan, 8); 1251 if (ret) 1252 goto fail_unreserve; 1253 1254 BEGIN_NV04(chan, NvSubImageBlit, 0x012c, 1); 1255 OUT_RING (chan, 0); 1256 BEGIN_NV04(chan, NvSubImageBlit, 0x0134, 1); 1257 OUT_RING (chan, head); 1258 BEGIN_NV04(chan, NvSubImageBlit, 0x0100, 1); 1259 OUT_RING (chan, 0); 1260 BEGIN_NV04(chan, NvSubImageBlit, 0x0130, 1); 1261 OUT_RING (chan, 0); 1262 } 1263 1264 nouveau_bo_ref(new_bo, &dispnv04->image[head]); 1265 1266 ret = nv04_page_flip_emit(chan, old_bo, new_bo, s, &fence); 1267 if (ret) 1268 goto fail_unreserve; 1269 mutex_unlock(&cli->mutex); 1270 1271 /* Update the crtc struct and cleanup */ 1272 crtc->primary->fb = fb; 1273 1274 nouveau_bo_fence(old_bo, fence, false); 1275 ttm_bo_unreserve(&old_bo->bo); 1276 if (old_bo != new_bo) 1277 nouveau_bo_unpin(old_bo); 1278 nouveau_fence_unref(&fence); 1279 return 0; 1280 1281 fail_unreserve: 1282 drm_crtc_vblank_put(crtc); 1283 ttm_bo_unreserve(&old_bo->bo); 1284 fail_unpin: 1285 mutex_unlock(&cli->mutex); 1286 if (old_bo != new_bo) 1287 nouveau_bo_unpin(new_bo); 1288 fail_free: 1289 kfree(s); 1290 return ret; 1291 } 1292 1293 static const struct drm_crtc_funcs nv04_crtc_funcs = { 1294 .cursor_set = nv04_crtc_cursor_set, 1295 .cursor_move = nv04_crtc_cursor_move, 1296 .gamma_set = nv_crtc_gamma_set, 1297 .set_config = nouveau_crtc_set_config, 1298 .page_flip = nv04_crtc_page_flip, 1299 .destroy = nv_crtc_destroy, 1300 }; 1301 1302 static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = { 1303 .dpms = nv_crtc_dpms, 1304 .prepare = nv_crtc_prepare, 1305 .commit = nv_crtc_commit, 1306 .mode_set = nv_crtc_mode_set, 1307 .mode_set_base = nv04_crtc_mode_set_base, 1308 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic, 1309 .disable = nv_crtc_disable, 1310 }; 1311 1312 static const uint32_t modeset_formats[] = { 1313 DRM_FORMAT_XRGB8888, 1314 DRM_FORMAT_RGB565, 1315 DRM_FORMAT_XRGB1555, 1316 }; 1317 1318 static struct drm_plane * 1319 create_primary_plane(struct drm_device *dev) 1320 { 1321 struct drm_plane *primary; 1322 int ret; 1323 1324 primary = kzalloc(sizeof(*primary), GFP_KERNEL); 1325 if (primary == NULL) { 1326 DRM_DEBUG_KMS("Failed to allocate primary plane\n"); 1327 return NULL; 1328 } 1329 1330 /* possible_crtc's will be filled in later by crtc_init */ 1331 ret = drm_universal_plane_init(dev, primary, 0, 1332 &drm_primary_helper_funcs, 1333 modeset_formats, 1334 ARRAY_SIZE(modeset_formats), NULL, 1335 DRM_PLANE_TYPE_PRIMARY, NULL); 1336 if (ret) { 1337 kfree(primary); 1338 primary = NULL; 1339 } 1340 1341 return primary; 1342 } 1343 1344 int 1345 nv04_crtc_create(struct drm_device *dev, int crtc_num) 1346 { 1347 struct nouveau_crtc *nv_crtc; 1348 int ret; 1349 1350 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL); 1351 if (!nv_crtc) 1352 return -ENOMEM; 1353 1354 nv_crtc->lut.depth = 0; 1355 1356 nv_crtc->index = crtc_num; 1357 nv_crtc->last_dpms = NV_DPMS_CLEARED; 1358 1359 nv_crtc->save = nv_crtc_save; 1360 nv_crtc->restore = nv_crtc_restore; 1361 1362 drm_crtc_init_with_planes(dev, &nv_crtc->base, 1363 create_primary_plane(dev), NULL, 1364 &nv04_crtc_funcs, NULL); 1365 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs); 1366 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256); 1367 1368 ret = nouveau_bo_new(&nouveau_drm(dev)->client, 64*64*4, 0x100, 1369 TTM_PL_FLAG_VRAM, 0, 0x0000, NULL, NULL, 1370 &nv_crtc->cursor.nvbo); 1371 if (!ret) { 1372 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false); 1373 if (!ret) { 1374 ret = nouveau_bo_map(nv_crtc->cursor.nvbo); 1375 if (ret) 1376 nouveau_bo_unpin(nv_crtc->cursor.nvbo); 1377 } 1378 if (ret) 1379 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); 1380 } 1381 1382 nv04_cursor_init(nv_crtc); 1383 1384 return 0; 1385 } 1386