1 /* 2 * Copyright 1993-2003 NVIDIA, Corporation 3 * Copyright 2007-2009 Stuart Bennett 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 19 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 20 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 */ 23 24 #include "nouveau_drv.h" 25 #include "nouveau_reg.h" 26 #include "hw.h" 27 28 /****************************************************************************\ 29 * * 30 * The video arbitration routines calculate some "magic" numbers. Fixes * 31 * the snow seen when accessing the framebuffer without it. * 32 * It just works (I hope). * 33 * * 34 \****************************************************************************/ 35 36 struct nv_fifo_info { 37 int lwm; 38 int burst; 39 }; 40 41 struct nv_sim_state { 42 int pclk_khz; 43 int mclk_khz; 44 int nvclk_khz; 45 int bpp; 46 int mem_page_miss; 47 int mem_latency; 48 int memory_type; 49 int memory_width; 50 int two_heads; 51 }; 52 53 static void 54 nv04_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb) 55 { 56 int pagemiss, cas, width, bpp; 57 int nvclks, mclks, pclks, crtpagemiss; 58 int found, mclk_extra, mclk_loop, cbs, m1, p1; 59 int mclk_freq, pclk_freq, nvclk_freq; 60 int us_m, us_n, us_p, crtc_drain_rate; 61 int cpm_us, us_crt, clwm; 62 63 pclk_freq = arb->pclk_khz; 64 mclk_freq = arb->mclk_khz; 65 nvclk_freq = arb->nvclk_khz; 66 pagemiss = arb->mem_page_miss; 67 cas = arb->mem_latency; 68 width = arb->memory_width >> 6; 69 bpp = arb->bpp; 70 cbs = 128; 71 72 pclks = 2; 73 nvclks = 10; 74 mclks = 13 + cas; 75 mclk_extra = 3; 76 found = 0; 77 78 while (!found) { 79 found = 1; 80 81 mclk_loop = mclks + mclk_extra; 82 us_m = mclk_loop * 1000 * 1000 / mclk_freq; 83 us_n = nvclks * 1000 * 1000 / nvclk_freq; 84 us_p = nvclks * 1000 * 1000 / pclk_freq; 85 86 crtc_drain_rate = pclk_freq * bpp / 8; 87 crtpagemiss = 2; 88 crtpagemiss += 1; 89 cpm_us = crtpagemiss * pagemiss * 1000 * 1000 / mclk_freq; 90 us_crt = cpm_us + us_m + us_n + us_p; 91 clwm = us_crt * crtc_drain_rate / (1000 * 1000); 92 clwm++; 93 94 m1 = clwm + cbs - 512; 95 p1 = m1 * pclk_freq / mclk_freq; 96 p1 = p1 * bpp / 8; 97 if ((p1 < m1 && m1 > 0) || clwm > 519) { 98 found = !mclk_extra; 99 mclk_extra--; 100 } 101 if (clwm < 384) 102 clwm = 384; 103 104 fifo->lwm = clwm; 105 fifo->burst = cbs; 106 } 107 } 108 109 static void 110 nv10_calc_arb(struct nv_fifo_info *fifo, struct nv_sim_state *arb) 111 { 112 int fill_rate, drain_rate; 113 int pclks, nvclks, mclks, xclks; 114 int pclk_freq, nvclk_freq, mclk_freq; 115 int fill_lat, extra_lat; 116 int max_burst_o, max_burst_l; 117 int fifo_len, min_lwm, max_lwm; 118 const int burst_lat = 80; /* Maximum allowable latency due 119 * to the CRTC FIFO burst. (ns) */ 120 121 pclk_freq = arb->pclk_khz; 122 nvclk_freq = arb->nvclk_khz; 123 mclk_freq = arb->mclk_khz; 124 125 fill_rate = mclk_freq * arb->memory_width / 8; /* kB/s */ 126 drain_rate = pclk_freq * arb->bpp / 8; /* kB/s */ 127 128 fifo_len = arb->two_heads ? 1536 : 1024; /* B */ 129 130 /* Fixed FIFO refill latency. */ 131 132 pclks = 4; /* lwm detect. */ 133 134 nvclks = 3 /* lwm -> sync. */ 135 + 2 /* fbi bus cycles (1 req + 1 busy) */ 136 + 1 /* 2 edge sync. may be very close to edge so 137 * just put one. */ 138 + 1 /* fbi_d_rdv_n */ 139 + 1 /* Fbi_d_rdata */ 140 + 1; /* crtfifo load */ 141 142 mclks = 1 /* 2 edge sync. may be very close to edge so 143 * just put one. */ 144 + 1 /* arb_hp_req */ 145 + 5 /* tiling pipeline */ 146 + 2 /* latency fifo */ 147 + 2 /* memory request to fbio block */ 148 + 7; /* data returned from fbio block */ 149 150 /* Need to accumulate 256 bits for read */ 151 mclks += (arb->memory_type == 0 ? 2 : 1) 152 * arb->memory_width / 32; 153 154 fill_lat = mclks * 1000 * 1000 / mclk_freq /* minimum mclk latency */ 155 + nvclks * 1000 * 1000 / nvclk_freq /* nvclk latency */ 156 + pclks * 1000 * 1000 / pclk_freq; /* pclk latency */ 157 158 /* Conditional FIFO refill latency. */ 159 160 xclks = 2 * arb->mem_page_miss + mclks /* Extra latency due to 161 * the overlay. */ 162 + 2 * arb->mem_page_miss /* Extra pagemiss latency. */ 163 + (arb->bpp == 32 ? 8 : 4); /* Margin of error. */ 164 165 extra_lat = xclks * 1000 * 1000 / mclk_freq; 166 167 if (arb->two_heads) 168 /* Account for another CRTC. */ 169 extra_lat += fill_lat + extra_lat + burst_lat; 170 171 /* FIFO burst */ 172 173 /* Max burst not leading to overflows. */ 174 max_burst_o = (1 + fifo_len - extra_lat * drain_rate / (1000 * 1000)) 175 * (fill_rate / 1000) / ((fill_rate - drain_rate) / 1000); 176 fifo->burst = min(max_burst_o, 1024); 177 178 /* Max burst value with an acceptable latency. */ 179 max_burst_l = burst_lat * fill_rate / (1000 * 1000); 180 fifo->burst = min(max_burst_l, fifo->burst); 181 182 fifo->burst = rounddown_pow_of_two(fifo->burst); 183 184 /* FIFO low watermark */ 185 186 min_lwm = (fill_lat + extra_lat) * drain_rate / (1000 * 1000) + 1; 187 max_lwm = fifo_len - fifo->burst 188 + fill_lat * drain_rate / (1000 * 1000) 189 + fifo->burst * drain_rate / fill_rate; 190 191 fifo->lwm = min_lwm + 10 * (max_lwm - min_lwm) / 100; /* Empirical. */ 192 } 193 194 static void 195 nv04_update_arb(struct drm_device *dev, int VClk, int bpp, 196 int *burst, int *lwm) 197 { 198 struct nouveau_drm *drm = nouveau_drm(dev); 199 struct nvif_object *device = &nouveau_drm(dev)->client.device.object; 200 struct nv_fifo_info fifo_data; 201 struct nv_sim_state sim_data; 202 int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY); 203 int NVClk = nouveau_hw_get_clock(dev, PLL_CORE); 204 uint32_t cfg1 = nvif_rd32(device, NV04_PFB_CFG1); 205 206 sim_data.pclk_khz = VClk; 207 sim_data.mclk_khz = MClk; 208 sim_data.nvclk_khz = NVClk; 209 sim_data.bpp = bpp; 210 sim_data.two_heads = nv_two_heads(dev); 211 if ((dev->pdev->device & 0xffff) == 0x01a0 /*CHIPSET_NFORCE*/ || 212 (dev->pdev->device & 0xffff) == 0x01f0 /*CHIPSET_NFORCE2*/) { 213 uint32_t type; 214 int domain = pci_domain_nr(dev->pdev->bus); 215 216 pci_read_config_dword(pci_get_domain_bus_and_slot(domain, 0, 1), 217 0x7c, &type); 218 219 sim_data.memory_type = (type >> 12) & 1; 220 sim_data.memory_width = 64; 221 sim_data.mem_latency = 3; 222 sim_data.mem_page_miss = 10; 223 } else { 224 sim_data.memory_type = nvif_rd32(device, NV04_PFB_CFG0) & 0x1; 225 sim_data.memory_width = (nvif_rd32(device, NV_PEXTDEV_BOOT_0) & 0x10) ? 128 : 64; 226 sim_data.mem_latency = cfg1 & 0xf; 227 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1); 228 } 229 230 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT) 231 nv04_calc_arb(&fifo_data, &sim_data); 232 else 233 nv10_calc_arb(&fifo_data, &sim_data); 234 235 *burst = ilog2(fifo_data.burst >> 4); 236 *lwm = fifo_data.lwm >> 3; 237 } 238 239 static void 240 nv20_update_arb(int *burst, int *lwm) 241 { 242 unsigned int fifo_size, burst_size, graphics_lwm; 243 244 fifo_size = 2048; 245 burst_size = 512; 246 graphics_lwm = fifo_size - burst_size; 247 248 *burst = ilog2(burst_size >> 5); 249 *lwm = graphics_lwm >> 3; 250 } 251 252 void 253 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) 254 { 255 struct nouveau_drm *drm = nouveau_drm(dev); 256 257 if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) 258 nv04_update_arb(dev, vclk, bpp, burst, lwm); 259 else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ || 260 (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) { 261 *burst = 128; 262 *lwm = 0x0480; 263 } else 264 nv20_update_arb(burst, lwm); 265 } 266