xref: /linux/drivers/gpu/drm/mxsfb/mxsfb_regs.h (revision e5c86679d5e864947a52fb31e45a425dea3e7fa9)
1 /*
2  * Copyright (C) 2010 Juergen Beisert, Pengutronix
3  * Copyright (C) 2016 Marek Vasut <marex@denx.de>
4  *
5  * i.MX23/i.MX28/i.MX6SX MXSFB LCD controller driver.
6  *
7  * This program is free software; you can redistribute it and/or
8  * modify it under the terms of the GNU General Public License
9  * as published by the Free Software Foundation; either version 2
10  * of the License, or (at your option) any later version.
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #ifndef __MXSFB_REGS_H__
18 #define __MXSFB_REGS_H__
19 
20 #define REG_SET	4
21 #define REG_CLR	8
22 
23 #define LCDC_CTRL			0x00
24 #define LCDC_CTRL1			0x10
25 #define LCDC_V3_TRANSFER_COUNT		0x20
26 #define LCDC_V4_TRANSFER_COUNT		0x30
27 #define LCDC_V4_CUR_BUF			0x40
28 #define LCDC_V4_NEXT_BUF		0x50
29 #define LCDC_V3_CUR_BUF			0x30
30 #define LCDC_V3_NEXT_BUF		0x40
31 #define LCDC_VDCTRL0			0x70
32 #define LCDC_VDCTRL1			0x80
33 #define LCDC_VDCTRL2			0x90
34 #define LCDC_VDCTRL3			0xa0
35 #define LCDC_VDCTRL4			0xb0
36 #define LCDC_V4_DEBUG0			0x1d0
37 #define LCDC_V3_DEBUG0			0x1f0
38 
39 #define CTRL_SFTRST			(1 << 31)
40 #define CTRL_CLKGATE			(1 << 30)
41 #define CTRL_BYPASS_COUNT		(1 << 19)
42 #define CTRL_VSYNC_MODE			(1 << 18)
43 #define CTRL_DOTCLK_MODE		(1 << 17)
44 #define CTRL_DATA_SELECT		(1 << 16)
45 #define CTRL_SET_BUS_WIDTH(x)		(((x) & 0x3) << 10)
46 #define CTRL_GET_BUS_WIDTH(x)		(((x) >> 10) & 0x3)
47 #define CTRL_BUS_WIDTH_MASK		(0x3 << 10)
48 #define CTRL_SET_WORD_LENGTH(x)		(((x) & 0x3) << 8)
49 #define CTRL_GET_WORD_LENGTH(x)		(((x) >> 8) & 0x3)
50 #define CTRL_MASTER			(1 << 5)
51 #define CTRL_DF16			(1 << 3)
52 #define CTRL_DF18			(1 << 2)
53 #define CTRL_DF24			(1 << 1)
54 #define CTRL_RUN			(1 << 0)
55 
56 #define CTRL1_FIFO_CLEAR		(1 << 21)
57 #define CTRL1_SET_BYTE_PACKAGING(x)	(((x) & 0xf) << 16)
58 #define CTRL1_GET_BYTE_PACKAGING(x)	(((x) >> 16) & 0xf)
59 #define CTRL1_CUR_FRAME_DONE_IRQ_EN	(1 << 13)
60 #define CTRL1_CUR_FRAME_DONE_IRQ	(1 << 9)
61 
62 #define TRANSFER_COUNT_SET_VCOUNT(x)	(((x) & 0xffff) << 16)
63 #define TRANSFER_COUNT_GET_VCOUNT(x)	(((x) >> 16) & 0xffff)
64 #define TRANSFER_COUNT_SET_HCOUNT(x)	((x) & 0xffff)
65 #define TRANSFER_COUNT_GET_HCOUNT(x)	((x) & 0xffff)
66 
67 #define VDCTRL0_ENABLE_PRESENT		(1 << 28)
68 #define VDCTRL0_VSYNC_ACT_HIGH		(1 << 27)
69 #define VDCTRL0_HSYNC_ACT_HIGH		(1 << 26)
70 #define VDCTRL0_DOTCLK_ACT_FALLING	(1 << 25)
71 #define VDCTRL0_ENABLE_ACT_HIGH		(1 << 24)
72 #define VDCTRL0_VSYNC_PERIOD_UNIT	(1 << 21)
73 #define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT	(1 << 20)
74 #define VDCTRL0_HALF_LINE		(1 << 19)
75 #define VDCTRL0_HALF_LINE_MODE		(1 << 18)
76 #define VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
77 #define VDCTRL0_GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff)
78 
79 #define VDCTRL2_SET_HSYNC_PERIOD(x)	((x) & 0x3ffff)
80 #define VDCTRL2_GET_HSYNC_PERIOD(x)	((x) & 0x3ffff)
81 
82 #define VDCTRL3_MUX_SYNC_SIGNALS	(1 << 29)
83 #define VDCTRL3_VSYNC_ONLY		(1 << 28)
84 #define SET_HOR_WAIT_CNT(x)		(((x) & 0xfff) << 16)
85 #define GET_HOR_WAIT_CNT(x)		(((x) >> 16) & 0xfff)
86 #define SET_VERT_WAIT_CNT(x)		((x) & 0xffff)
87 #define GET_VERT_WAIT_CNT(x)		((x) & 0xffff)
88 
89 #define VDCTRL4_SET_DOTCLK_DLY(x)	(((x) & 0x7) << 29) /* v4 only */
90 #define VDCTRL4_GET_DOTCLK_DLY(x)	(((x) >> 29) & 0x7) /* v4 only */
91 #define VDCTRL4_SYNC_SIGNALS_ON		(1 << 18)
92 #define SET_DOTCLK_H_VALID_DATA_CNT(x)	((x) & 0x3ffff)
93 
94 #define DEBUG0_HSYNC			(1 < 26)
95 #define DEBUG0_VSYNC			(1 < 25)
96 
97 #define MXSFB_MIN_XRES			120
98 #define MXSFB_MIN_YRES			120
99 #define MXSFB_MAX_XRES			0xffff
100 #define MXSFB_MAX_YRES			0xffff
101 
102 #define RED 0
103 #define GREEN 1
104 #define BLUE 2
105 #define TRANSP 3
106 
107 #define STMLCDIF_8BIT  1 /* pixel data bus to the display is of 8 bit width */
108 #define STMLCDIF_16BIT 0 /* pixel data bus to the display is of 16 bit width */
109 #define STMLCDIF_18BIT 2 /* pixel data bus to the display is of 18 bit width */
110 #define STMLCDIF_24BIT 3 /* pixel data bus to the display is of 24 bit width */
111 
112 #define MXSFB_SYNC_DATA_ENABLE_HIGH_ACT	(1 << 6)
113 #define MXSFB_SYNC_DOTCLK_FALLING_ACT	(1 << 7) /* negative edge sampling */
114 
115 #endif /* __MXSFB_REGS_H__ */
116