1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 4 * 5 * This code is based on drivers/gpu/drm/mxsfb/mxsfb* 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/media-bus-format.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/spinlock.h> 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_bridge.h> 19 #include <drm/drm_color_mgmt.h> 20 #include <drm/drm_connector.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_encoder.h> 23 #include <drm/drm_fb_dma_helper.h> 24 #include <drm/drm_fourcc.h> 25 #include <drm/drm_framebuffer.h> 26 #include <drm/drm_gem_atomic_helper.h> 27 #include <drm/drm_gem_dma_helper.h> 28 #include <drm/drm_plane.h> 29 #include <drm/drm_print.h> 30 #include <drm/drm_vblank.h> 31 32 #include "lcdif_drv.h" 33 #include "lcdif_regs.h" 34 35 struct lcdif_crtc_state { 36 struct drm_crtc_state base; /* always be the first member */ 37 u32 bus_format; 38 u32 bus_flags; 39 }; 40 41 static inline struct lcdif_crtc_state * 42 to_lcdif_crtc_state(struct drm_crtc_state *s) 43 { 44 return container_of(s, struct lcdif_crtc_state, base); 45 } 46 47 /* ----------------------------------------------------------------------------- 48 * CRTC 49 */ 50 51 /* 52 * For conversion from YCbCr to RGB, the CSC operates as follows: 53 * 54 * |R| |A1 A2 A3| |Y + D1| 55 * |G| = |B1 B2 B3| * |Cb + D2| 56 * |B| |C1 C2 C3| |Cr + D3| 57 * 58 * The A, B and C coefficients are expressed as Q2.8 fixed point values, and 59 * the D coefficients as Q0.8. Despite the reference manual stating the 60 * opposite, the D1, D2 and D3 offset values are added to Y, Cb and Cr, not 61 * subtracted. They must thus be programmed with negative values. 62 */ 63 static const u32 lcdif_yuv2rgb_coeffs[3][2][6] = { 64 [DRM_COLOR_YCBCR_BT601] = { 65 [DRM_COLOR_YCBCR_LIMITED_RANGE] = { 66 /* 67 * BT.601 limited range: 68 * 69 * |R| |1.1644 0.0000 1.5960| |Y - 16 | 70 * |G| = |1.1644 -0.3917 -0.8129| * |Cb - 128| 71 * |B| |1.1644 2.0172 0.0000| |Cr - 128| 72 */ 73 CSC0_COEF0_A1(0x12a) | CSC0_COEF0_A2(0x000), 74 CSC0_COEF1_A3(0x199) | CSC0_COEF1_B1(0x12a), 75 CSC0_COEF2_B2(0x79c) | CSC0_COEF2_B3(0x730), 76 CSC0_COEF3_C1(0x12a) | CSC0_COEF3_C2(0x204), 77 CSC0_COEF4_C3(0x000) | CSC0_COEF4_D1(0x1f0), 78 CSC0_COEF5_D2(0x180) | CSC0_COEF5_D3(0x180), 79 }, 80 [DRM_COLOR_YCBCR_FULL_RANGE] = { 81 /* 82 * BT.601 full range: 83 * 84 * |R| |1.0000 0.0000 1.4020| |Y - 0 | 85 * |G| = |1.0000 -0.3441 -0.7141| * |Cb - 128| 86 * |B| |1.0000 1.7720 0.0000| |Cr - 128| 87 */ 88 CSC0_COEF0_A1(0x100) | CSC0_COEF0_A2(0x000), 89 CSC0_COEF1_A3(0x167) | CSC0_COEF1_B1(0x100), 90 CSC0_COEF2_B2(0x7a8) | CSC0_COEF2_B3(0x749), 91 CSC0_COEF3_C1(0x100) | CSC0_COEF3_C2(0x1c6), 92 CSC0_COEF4_C3(0x000) | CSC0_COEF4_D1(0x000), 93 CSC0_COEF5_D2(0x180) | CSC0_COEF5_D3(0x180), 94 }, 95 }, 96 [DRM_COLOR_YCBCR_BT709] = { 97 [DRM_COLOR_YCBCR_LIMITED_RANGE] = { 98 /* 99 * Rec.709 limited range: 100 * 101 * |R| |1.1644 0.0000 1.7927| |Y - 16 | 102 * |G| = |1.1644 -0.2132 -0.5329| * |Cb - 128| 103 * |B| |1.1644 2.1124 0.0000| |Cr - 128| 104 */ 105 CSC0_COEF0_A1(0x12a) | CSC0_COEF0_A2(0x000), 106 CSC0_COEF1_A3(0x1cb) | CSC0_COEF1_B1(0x12a), 107 CSC0_COEF2_B2(0x7c9) | CSC0_COEF2_B3(0x778), 108 CSC0_COEF3_C1(0x12a) | CSC0_COEF3_C2(0x21d), 109 CSC0_COEF4_C3(0x000) | CSC0_COEF4_D1(0x1f0), 110 CSC0_COEF5_D2(0x180) | CSC0_COEF5_D3(0x180), 111 }, 112 [DRM_COLOR_YCBCR_FULL_RANGE] = { 113 /* 114 * Rec.709 full range: 115 * 116 * |R| |1.0000 0.0000 1.5748| |Y - 0 | 117 * |G| = |1.0000 -0.1873 -0.4681| * |Cb - 128| 118 * |B| |1.0000 1.8556 0.0000| |Cr - 128| 119 */ 120 CSC0_COEF0_A1(0x100) | CSC0_COEF0_A2(0x000), 121 CSC0_COEF1_A3(0x193) | CSC0_COEF1_B1(0x100), 122 CSC0_COEF2_B2(0x7d0) | CSC0_COEF2_B3(0x788), 123 CSC0_COEF3_C1(0x100) | CSC0_COEF3_C2(0x1db), 124 CSC0_COEF4_C3(0x000) | CSC0_COEF4_D1(0x000), 125 CSC0_COEF5_D2(0x180) | CSC0_COEF5_D3(0x180), 126 }, 127 }, 128 [DRM_COLOR_YCBCR_BT2020] = { 129 [DRM_COLOR_YCBCR_LIMITED_RANGE] = { 130 /* 131 * BT.2020 limited range: 132 * 133 * |R| |1.1644 0.0000 1.6787| |Y - 16 | 134 * |G| = |1.1644 -0.1874 -0.6505| * |Cb - 128| 135 * |B| |1.1644 2.1418 0.0000| |Cr - 128| 136 */ 137 CSC0_COEF0_A1(0x12a) | CSC0_COEF0_A2(0x000), 138 CSC0_COEF1_A3(0x1ae) | CSC0_COEF1_B1(0x12a), 139 CSC0_COEF2_B2(0x7d0) | CSC0_COEF2_B3(0x759), 140 CSC0_COEF3_C1(0x12a) | CSC0_COEF3_C2(0x224), 141 CSC0_COEF4_C3(0x000) | CSC0_COEF4_D1(0x1f0), 142 CSC0_COEF5_D2(0x180) | CSC0_COEF5_D3(0x180), 143 }, 144 [DRM_COLOR_YCBCR_FULL_RANGE] = { 145 /* 146 * BT.2020 full range: 147 * 148 * |R| |1.0000 0.0000 1.4746| |Y - 0 | 149 * |G| = |1.0000 -0.1646 -0.5714| * |Cb - 128| 150 * |B| |1.0000 1.8814 0.0000| |Cr - 128| 151 */ 152 CSC0_COEF0_A1(0x100) | CSC0_COEF0_A2(0x000), 153 CSC0_COEF1_A3(0x179) | CSC0_COEF1_B1(0x100), 154 CSC0_COEF2_B2(0x7d6) | CSC0_COEF2_B3(0x76e), 155 CSC0_COEF3_C1(0x100) | CSC0_COEF3_C2(0x1e2), 156 CSC0_COEF4_C3(0x000) | CSC0_COEF4_D1(0x000), 157 CSC0_COEF5_D2(0x180) | CSC0_COEF5_D3(0x180), 158 }, 159 }, 160 }; 161 162 static void lcdif_set_formats(struct lcdif_drm_private *lcdif, 163 struct drm_plane_state *plane_state, 164 const u32 bus_format) 165 { 166 struct drm_device *drm = lcdif->drm; 167 const u32 format = plane_state->fb->format->format; 168 bool in_yuv = false; 169 bool out_yuv = false; 170 171 switch (bus_format) { 172 case MEDIA_BUS_FMT_RGB565_1X16: 173 writel(DISP_PARA_LINE_PATTERN_RGB565, 174 lcdif->base + LCDC_V8_DISP_PARA); 175 break; 176 case MEDIA_BUS_FMT_RGB888_1X24: 177 writel(DISP_PARA_LINE_PATTERN_RGB888, 178 lcdif->base + LCDC_V8_DISP_PARA); 179 break; 180 case MEDIA_BUS_FMT_UYVY8_1X16: 181 writel(DISP_PARA_LINE_PATTERN_UYVY_H, 182 lcdif->base + LCDC_V8_DISP_PARA); 183 out_yuv = true; 184 break; 185 default: 186 dev_err(drm->dev, "Unknown media bus format 0x%x\n", bus_format); 187 break; 188 } 189 190 switch (format) { 191 /* RGB Formats */ 192 case DRM_FORMAT_RGB565: 193 writel(CTRLDESCL0_5_BPP_16_RGB565, 194 lcdif->base + LCDC_V8_CTRLDESCL0_5); 195 break; 196 case DRM_FORMAT_RGB888: 197 writel(CTRLDESCL0_5_BPP_24_RGB888, 198 lcdif->base + LCDC_V8_CTRLDESCL0_5); 199 break; 200 case DRM_FORMAT_XRGB1555: 201 writel(CTRLDESCL0_5_BPP_16_ARGB1555, 202 lcdif->base + LCDC_V8_CTRLDESCL0_5); 203 break; 204 case DRM_FORMAT_XRGB4444: 205 writel(CTRLDESCL0_5_BPP_16_ARGB4444, 206 lcdif->base + LCDC_V8_CTRLDESCL0_5); 207 break; 208 case DRM_FORMAT_XBGR8888: 209 writel(CTRLDESCL0_5_BPP_32_ABGR8888, 210 lcdif->base + LCDC_V8_CTRLDESCL0_5); 211 break; 212 case DRM_FORMAT_XRGB8888: 213 writel(CTRLDESCL0_5_BPP_32_ARGB8888, 214 lcdif->base + LCDC_V8_CTRLDESCL0_5); 215 break; 216 217 /* YUV Formats */ 218 case DRM_FORMAT_YUYV: 219 writel(CTRLDESCL0_5_BPP_YCbCr422 | CTRLDESCL0_5_YUV_FORMAT_VY2UY1, 220 lcdif->base + LCDC_V8_CTRLDESCL0_5); 221 in_yuv = true; 222 break; 223 case DRM_FORMAT_YVYU: 224 writel(CTRLDESCL0_5_BPP_YCbCr422 | CTRLDESCL0_5_YUV_FORMAT_UY2VY1, 225 lcdif->base + LCDC_V8_CTRLDESCL0_5); 226 in_yuv = true; 227 break; 228 case DRM_FORMAT_UYVY: 229 writel(CTRLDESCL0_5_BPP_YCbCr422 | CTRLDESCL0_5_YUV_FORMAT_Y2VY1U, 230 lcdif->base + LCDC_V8_CTRLDESCL0_5); 231 in_yuv = true; 232 break; 233 case DRM_FORMAT_VYUY: 234 writel(CTRLDESCL0_5_BPP_YCbCr422 | CTRLDESCL0_5_YUV_FORMAT_Y2UY1V, 235 lcdif->base + LCDC_V8_CTRLDESCL0_5); 236 in_yuv = true; 237 break; 238 239 default: 240 dev_err(drm->dev, "Unknown pixel format 0x%x\n", format); 241 break; 242 } 243 244 /* 245 * The CSC differentiates between "YCbCr" and "YUV", but the reference 246 * manual doesn't detail how they differ. Experiments showed that the 247 * luminance value is unaffected, only the calculations involving chroma 248 * values differ. The YCbCr mode behaves as expected, with chroma values 249 * being offset by 128. The YUV mode isn't fully understood. 250 */ 251 if (!in_yuv && out_yuv) { 252 /* RGB -> YCbCr */ 253 writel(CSC0_CTRL_CSC_MODE_RGB2YCbCr, 254 lcdif->base + LCDC_V8_CSC0_CTRL); 255 256 /* 257 * CSC: BT.601 Limited Range RGB to YCbCr coefficients. 258 * 259 * |Y | | 0.2568 0.5041 0.0979| |R| |16 | 260 * |Cb| = |-0.1482 -0.2910 0.4392| * |G| + |128| 261 * |Cr| | 0.4392 0.4392 -0.3678| |B| |128| 262 */ 263 writel(CSC0_COEF0_A2(0x081) | CSC0_COEF0_A1(0x041), 264 lcdif->base + LCDC_V8_CSC0_COEF0); 265 writel(CSC0_COEF1_B1(0x7db) | CSC0_COEF1_A3(0x019), 266 lcdif->base + LCDC_V8_CSC0_COEF1); 267 writel(CSC0_COEF2_B3(0x070) | CSC0_COEF2_B2(0x7b6), 268 lcdif->base + LCDC_V8_CSC0_COEF2); 269 writel(CSC0_COEF3_C2(0x7a2) | CSC0_COEF3_C1(0x070), 270 lcdif->base + LCDC_V8_CSC0_COEF3); 271 writel(CSC0_COEF4_D1(0x010) | CSC0_COEF4_C3(0x7ee), 272 lcdif->base + LCDC_V8_CSC0_COEF4); 273 writel(CSC0_COEF5_D3(0x080) | CSC0_COEF5_D2(0x080), 274 lcdif->base + LCDC_V8_CSC0_COEF5); 275 } else if (in_yuv && !out_yuv) { 276 /* YCbCr -> RGB */ 277 const u32 *coeffs = 278 lcdif_yuv2rgb_coeffs[plane_state->color_encoding] 279 [plane_state->color_range]; 280 281 writel(CSC0_CTRL_CSC_MODE_YCbCr2RGB, 282 lcdif->base + LCDC_V8_CSC0_CTRL); 283 284 writel(coeffs[0], lcdif->base + LCDC_V8_CSC0_COEF0); 285 writel(coeffs[1], lcdif->base + LCDC_V8_CSC0_COEF1); 286 writel(coeffs[2], lcdif->base + LCDC_V8_CSC0_COEF2); 287 writel(coeffs[3], lcdif->base + LCDC_V8_CSC0_COEF3); 288 writel(coeffs[4], lcdif->base + LCDC_V8_CSC0_COEF4); 289 writel(coeffs[5], lcdif->base + LCDC_V8_CSC0_COEF5); 290 } else { 291 /* RGB -> RGB, YCbCr -> YCbCr: bypass colorspace converter. */ 292 writel(CSC0_CTRL_BYPASS, lcdif->base + LCDC_V8_CSC0_CTRL); 293 } 294 } 295 296 static void lcdif_set_mode(struct lcdif_drm_private *lcdif, u32 bus_flags) 297 { 298 struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode; 299 u32 ctrl = 0; 300 301 if (m->flags & DRM_MODE_FLAG_NHSYNC) 302 ctrl |= CTRL_INV_HS; 303 if (m->flags & DRM_MODE_FLAG_NVSYNC) 304 ctrl |= CTRL_INV_VS; 305 if (bus_flags & DRM_BUS_FLAG_DE_LOW) 306 ctrl |= CTRL_INV_DE; 307 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 308 ctrl |= CTRL_INV_PXCK; 309 310 writel(ctrl, lcdif->base + LCDC_V8_CTRL); 311 312 writel(DISP_SIZE_DELTA_Y(m->vdisplay) | 313 DISP_SIZE_DELTA_X(m->hdisplay), 314 lcdif->base + LCDC_V8_DISP_SIZE); 315 316 writel(HSYN_PARA_BP_H(m->htotal - m->hsync_end) | 317 HSYN_PARA_FP_H(m->hsync_start - m->hdisplay), 318 lcdif->base + LCDC_V8_HSYN_PARA); 319 320 writel(VSYN_PARA_BP_V(m->vtotal - m->vsync_end) | 321 VSYN_PARA_FP_V(m->vsync_start - m->vdisplay), 322 lcdif->base + LCDC_V8_VSYN_PARA); 323 324 writel(VSYN_HSYN_WIDTH_PW_V(m->vsync_end - m->vsync_start) | 325 VSYN_HSYN_WIDTH_PW_H(m->hsync_end - m->hsync_start), 326 lcdif->base + LCDC_V8_VSYN_HSYN_WIDTH); 327 328 writel(CTRLDESCL0_1_HEIGHT(m->vdisplay) | 329 CTRLDESCL0_1_WIDTH(m->hdisplay), 330 lcdif->base + LCDC_V8_CTRLDESCL0_1); 331 332 /* 333 * Undocumented P_SIZE and T_SIZE register but those written in the 334 * downstream kernel those registers control the AXI burst size. As of 335 * now there are two known values: 336 * 1 - 128Byte 337 * 2 - 256Byte 338 * Downstream set it to 256B burst size to improve the memory 339 * efficiency so set it here too. 340 */ 341 ctrl = CTRLDESCL0_3_STATE_CLEAR_VSYNC | 342 CTRLDESCL0_3_P_SIZE(2) | CTRLDESCL0_3_T_SIZE(2) | 343 CTRLDESCL0_3_PITCH(lcdif->crtc.primary->state->fb->pitches[0]); 344 writel(ctrl, lcdif->base + LCDC_V8_CTRLDESCL0_3); 345 } 346 347 static void lcdif_enable_controller(struct lcdif_drm_private *lcdif) 348 { 349 u32 reg; 350 351 /* Set FIFO Panic watermarks, low 1/3, high 2/3 . */ 352 writel(FIELD_PREP(PANIC0_THRES_LOW_MASK, 1 * PANIC0_THRES_MAX / 3) | 353 FIELD_PREP(PANIC0_THRES_HIGH_MASK, 2 * PANIC0_THRES_MAX / 3), 354 lcdif->base + LCDC_V8_PANIC0_THRES); 355 356 /* 357 * Enable FIFO Panic, this does not generate interrupt, but 358 * boosts NoC priority based on FIFO Panic watermarks. 359 */ 360 writel(INT_ENABLE_D1_PLANE_PANIC_EN, 361 lcdif->base + LCDC_V8_INT_ENABLE_D1); 362 363 reg = readl(lcdif->base + LCDC_V8_DISP_PARA); 364 reg |= DISP_PARA_DISP_ON; 365 writel(reg, lcdif->base + LCDC_V8_DISP_PARA); 366 367 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5); 368 reg |= CTRLDESCL0_5_EN; 369 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5); 370 } 371 372 static void lcdif_disable_controller(struct lcdif_drm_private *lcdif) 373 { 374 u32 reg; 375 int ret; 376 377 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5); 378 /* Disable the layer for DMA. */ 379 reg &= ~CTRLDESCL0_5_EN; 380 /* 381 * It is necessary to wait for the full frame to finish streaming 382 * through the DMA engine before we can safely disable it by removing 383 * the DISP_PARA_DISP_ON bit. Disabling it in-flight can leave the 384 * hardware confused and unable to resume streaming for the next frame. 385 */ 386 reg |= CTRLDESCL0_5_SHADOW_LOAD_EN; 387 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5); 388 389 /* Wait for the frame to finish or timeout after 50 ms. */ 390 ret = readl_poll_timeout(lcdif->base + LCDC_V8_CTRLDESCL0_5, 391 reg, !(reg & CTRLDESCL0_5_SHADOW_LOAD_EN), 392 200, 50000); 393 if (ret) 394 drm_err(lcdif->drm, "Timed out waiting for final vblank!\n"); 395 396 reg = readl(lcdif->base + LCDC_V8_DISP_PARA); 397 reg &= ~DISP_PARA_DISP_ON; 398 writel(reg, lcdif->base + LCDC_V8_DISP_PARA); 399 400 /* Disable FIFO Panic NoC priority booster. */ 401 writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D1); 402 } 403 404 static void lcdif_reset_block(struct lcdif_drm_private *lcdif) 405 { 406 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_SET); 407 readl(lcdif->base + LCDC_V8_CTRL); 408 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR); 409 readl(lcdif->base + LCDC_V8_CTRL); 410 } 411 412 static void lcdif_crtc_mode_set_nofb(struct drm_crtc_state *crtc_state, 413 struct drm_plane_state *plane_state) 414 { 415 struct lcdif_crtc_state *lcdif_crtc_state = to_lcdif_crtc_state(crtc_state); 416 struct drm_device *drm = crtc_state->crtc->dev; 417 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(drm); 418 struct drm_display_mode *m = &crtc_state->adjusted_mode; 419 420 DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n", 421 m->clock, (int)(clk_get_rate(lcdif->clk) / 1000)); 422 DRM_DEV_DEBUG_DRIVER(drm->dev, "Bridge bus_flags: 0x%08X\n", 423 lcdif_crtc_state->bus_flags); 424 DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags); 425 426 /* Mandatory eLCDIF reset as per the Reference Manual */ 427 lcdif_reset_block(lcdif); 428 429 lcdif_set_formats(lcdif, plane_state, lcdif_crtc_state->bus_format); 430 431 lcdif_set_mode(lcdif, lcdif_crtc_state->bus_flags); 432 } 433 434 static int lcdif_crtc_atomic_check(struct drm_crtc *crtc, 435 struct drm_atomic_commit *state) 436 { 437 struct drm_device *drm = crtc->dev; 438 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 439 crtc); 440 struct lcdif_crtc_state *lcdif_crtc_state = to_lcdif_crtc_state(crtc_state); 441 bool has_primary = crtc_state->plane_mask & 442 drm_plane_mask(crtc->primary); 443 struct drm_connector_state *connector_state; 444 struct drm_connector *connector; 445 struct drm_encoder *encoder; 446 struct drm_bridge_state *bridge_state; 447 u32 bus_format, bus_flags; 448 bool format_set = false, flags_set = false; 449 int ret, i; 450 451 /* The primary plane has to be enabled when the CRTC is active. */ 452 if (crtc_state->active && !has_primary) 453 return -EINVAL; 454 455 ret = drm_atomic_add_affected_planes(state, crtc); 456 if (ret) 457 return ret; 458 459 /* Try to find consistent bus format and flags across first bridges. */ 460 for_each_new_connector_in_state(state, connector, connector_state, i) { 461 if (!connector_state->crtc) 462 continue; 463 464 encoder = connector_state->best_encoder; 465 466 struct drm_bridge *bridge __free(drm_bridge_put) = 467 drm_bridge_chain_get_first_bridge(encoder); 468 if (!bridge) 469 continue; 470 471 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 472 if (!bridge_state) 473 bus_format = MEDIA_BUS_FMT_FIXED; 474 else 475 bus_format = bridge_state->input_bus_cfg.format; 476 477 if (bus_format == MEDIA_BUS_FMT_FIXED) { 478 dev_warn(drm->dev, 479 "[ENCODER:%d:%s]'s bridge does not provide bus format, assuming MEDIA_BUS_FMT_RGB888_1X24.\n" 480 "Please fix bridge driver by handling atomic_get_input_bus_fmts.\n", 481 encoder->base.id, encoder->name); 482 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 483 } else if (!bus_format) { 484 /* If all else fails, default to RGB888_1X24 */ 485 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 486 } 487 488 if (!format_set) { 489 lcdif_crtc_state->bus_format = bus_format; 490 format_set = true; 491 } else if (lcdif_crtc_state->bus_format != bus_format) { 492 DRM_DEV_DEBUG_DRIVER(drm->dev, "inconsistent bus format\n"); 493 return -EINVAL; 494 } 495 496 if (bridge->timings) 497 bus_flags = bridge->timings->input_bus_flags; 498 else if (bridge_state) 499 bus_flags = bridge_state->input_bus_cfg.flags; 500 else 501 bus_flags = 0; 502 503 if (!flags_set) { 504 lcdif_crtc_state->bus_flags = bus_flags; 505 flags_set = true; 506 } else if (lcdif_crtc_state->bus_flags != bus_flags) { 507 DRM_DEV_DEBUG_DRIVER(drm->dev, "inconsistent bus flags\n"); 508 return -EINVAL; 509 } 510 } 511 512 return 0; 513 } 514 515 static void lcdif_crtc_atomic_flush(struct drm_crtc *crtc, 516 struct drm_atomic_commit *state) 517 { 518 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev); 519 struct drm_pending_vblank_event *event; 520 u32 reg; 521 522 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5); 523 reg |= CTRLDESCL0_5_SHADOW_LOAD_EN; 524 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5); 525 526 event = crtc->state->event; 527 crtc->state->event = NULL; 528 529 if (!event) 530 return; 531 532 spin_lock_irq(&crtc->dev->event_lock); 533 if (drm_crtc_vblank_get(crtc) == 0) 534 drm_crtc_arm_vblank_event(crtc, event); 535 else 536 drm_crtc_send_vblank_event(crtc, event); 537 spin_unlock_irq(&crtc->dev->event_lock); 538 } 539 540 static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc, 541 struct drm_atomic_commit *state) 542 { 543 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev); 544 struct drm_crtc_state *new_cstate = drm_atomic_get_new_crtc_state(state, crtc); 545 struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state, 546 crtc->primary); 547 struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode; 548 struct drm_device *drm = lcdif->drm; 549 dma_addr_t paddr; 550 551 clk_set_rate(lcdif->clk, m->clock * 1000); 552 553 pm_runtime_get_sync(drm->dev); 554 555 lcdif_crtc_mode_set_nofb(new_cstate, new_pstate); 556 557 /* Write cur_buf as well to avoid an initial corrupt frame */ 558 paddr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0); 559 if (paddr) { 560 writel(lower_32_bits(paddr), 561 lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4); 562 writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)), 563 lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4); 564 } 565 lcdif_enable_controller(lcdif); 566 567 drm_crtc_vblank_on(crtc); 568 } 569 570 static void lcdif_crtc_atomic_disable(struct drm_crtc *crtc, 571 struct drm_atomic_commit *state) 572 { 573 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev); 574 struct drm_device *drm = lcdif->drm; 575 struct drm_pending_vblank_event *event; 576 577 drm_crtc_vblank_off(crtc); 578 579 lcdif_disable_controller(lcdif); 580 581 spin_lock_irq(&drm->event_lock); 582 event = crtc->state->event; 583 if (event) { 584 crtc->state->event = NULL; 585 drm_crtc_send_vblank_event(crtc, event); 586 } 587 spin_unlock_irq(&drm->event_lock); 588 589 pm_runtime_put_sync(drm->dev); 590 } 591 592 static void lcdif_crtc_atomic_destroy_state(struct drm_crtc *crtc, 593 struct drm_crtc_state *state) 594 { 595 __drm_atomic_helper_crtc_destroy_state(state); 596 kfree(to_lcdif_crtc_state(state)); 597 } 598 599 static void lcdif_crtc_reset(struct drm_crtc *crtc) 600 { 601 struct lcdif_crtc_state *state; 602 603 if (crtc->state) 604 lcdif_crtc_atomic_destroy_state(crtc, crtc->state); 605 606 crtc->state = NULL; 607 608 state = kzalloc_obj(*state); 609 if (state) 610 __drm_atomic_helper_crtc_reset(crtc, &state->base); 611 } 612 613 static struct drm_crtc_state * 614 lcdif_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 615 { 616 struct lcdif_crtc_state *old = to_lcdif_crtc_state(crtc->state); 617 struct lcdif_crtc_state *new; 618 619 if (WARN_ON(!crtc->state)) 620 return NULL; 621 622 new = kzalloc_obj(*new); 623 if (!new) 624 return NULL; 625 626 __drm_atomic_helper_crtc_duplicate_state(crtc, &new->base); 627 628 new->bus_format = old->bus_format; 629 new->bus_flags = old->bus_flags; 630 631 return &new->base; 632 } 633 634 static int lcdif_crtc_enable_vblank(struct drm_crtc *crtc) 635 { 636 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev); 637 638 /* Clear and enable VBLANK IRQ */ 639 writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0); 640 writel(INT_ENABLE_D0_VS_BLANK_EN, lcdif->base + LCDC_V8_INT_ENABLE_D0); 641 642 return 0; 643 } 644 645 static void lcdif_crtc_disable_vblank(struct drm_crtc *crtc) 646 { 647 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev); 648 649 /* Disable and clear VBLANK IRQ */ 650 writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D0); 651 writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0); 652 } 653 654 static const struct drm_crtc_helper_funcs lcdif_crtc_helper_funcs = { 655 .atomic_check = lcdif_crtc_atomic_check, 656 .atomic_flush = lcdif_crtc_atomic_flush, 657 .atomic_enable = lcdif_crtc_atomic_enable, 658 .atomic_disable = lcdif_crtc_atomic_disable, 659 }; 660 661 static const struct drm_crtc_funcs lcdif_crtc_funcs = { 662 .reset = lcdif_crtc_reset, 663 .destroy = drm_crtc_cleanup, 664 .set_config = drm_atomic_helper_set_config, 665 .page_flip = drm_atomic_helper_page_flip, 666 .atomic_duplicate_state = lcdif_crtc_atomic_duplicate_state, 667 .atomic_destroy_state = lcdif_crtc_atomic_destroy_state, 668 .enable_vblank = lcdif_crtc_enable_vblank, 669 .disable_vblank = lcdif_crtc_disable_vblank, 670 }; 671 672 /* ----------------------------------------------------------------------------- 673 * Planes 674 */ 675 676 static int lcdif_plane_atomic_check(struct drm_plane *plane, 677 struct drm_atomic_commit *state) 678 { 679 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, 680 plane); 681 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(plane->dev); 682 struct drm_crtc_state *crtc_state; 683 684 crtc_state = drm_atomic_get_new_crtc_state(state, 685 &lcdif->crtc); 686 687 return drm_atomic_helper_check_plane_state(plane_state, crtc_state, 688 DRM_PLANE_NO_SCALING, 689 DRM_PLANE_NO_SCALING, 690 false, true); 691 } 692 693 static void lcdif_plane_primary_atomic_update(struct drm_plane *plane, 694 struct drm_atomic_commit *state) 695 { 696 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(plane->dev); 697 struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state, 698 plane); 699 dma_addr_t paddr; 700 701 paddr = drm_fb_dma_get_gem_addr(new_pstate->fb, new_pstate, 0); 702 if (paddr) { 703 writel(lower_32_bits(paddr), 704 lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4); 705 writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)), 706 lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4); 707 } 708 } 709 710 static bool lcdif_format_mod_supported(struct drm_plane *plane, 711 uint32_t format, 712 uint64_t modifier) 713 { 714 return modifier == DRM_FORMAT_MOD_LINEAR; 715 } 716 717 static const struct drm_plane_helper_funcs lcdif_plane_primary_helper_funcs = { 718 .atomic_check = lcdif_plane_atomic_check, 719 .atomic_update = lcdif_plane_primary_atomic_update, 720 }; 721 722 static const struct drm_plane_funcs lcdif_plane_funcs = { 723 .format_mod_supported = lcdif_format_mod_supported, 724 .update_plane = drm_atomic_helper_update_plane, 725 .disable_plane = drm_atomic_helper_disable_plane, 726 .destroy = drm_plane_cleanup, 727 .reset = drm_atomic_helper_plane_reset, 728 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 729 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 730 }; 731 732 static const u32 lcdif_primary_plane_formats[] = { 733 /* RGB */ 734 DRM_FORMAT_RGB565, 735 DRM_FORMAT_RGB888, 736 DRM_FORMAT_XBGR8888, 737 DRM_FORMAT_XRGB1555, 738 DRM_FORMAT_XRGB4444, 739 DRM_FORMAT_XRGB8888, 740 741 /* Packed YCbCr */ 742 DRM_FORMAT_YUYV, 743 DRM_FORMAT_YVYU, 744 DRM_FORMAT_UYVY, 745 DRM_FORMAT_VYUY, 746 }; 747 748 static const u64 lcdif_modifiers[] = { 749 DRM_FORMAT_MOD_LINEAR, 750 DRM_FORMAT_MOD_INVALID 751 }; 752 753 /* ----------------------------------------------------------------------------- 754 * Initialization 755 */ 756 757 int lcdif_kms_init(struct lcdif_drm_private *lcdif) 758 { 759 const u32 supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) | 760 BIT(DRM_COLOR_YCBCR_BT709) | 761 BIT(DRM_COLOR_YCBCR_BT2020); 762 const u32 supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 763 BIT(DRM_COLOR_YCBCR_FULL_RANGE); 764 struct drm_crtc *crtc = &lcdif->crtc; 765 int ret; 766 767 drm_plane_helper_add(&lcdif->planes.primary, 768 &lcdif_plane_primary_helper_funcs); 769 ret = drm_universal_plane_init(lcdif->drm, &lcdif->planes.primary, 1, 770 &lcdif_plane_funcs, 771 lcdif_primary_plane_formats, 772 ARRAY_SIZE(lcdif_primary_plane_formats), 773 lcdif_modifiers, DRM_PLANE_TYPE_PRIMARY, 774 NULL); 775 if (ret) 776 return ret; 777 778 ret = drm_plane_create_color_properties(&lcdif->planes.primary, 779 supported_encodings, 780 supported_ranges, 781 DRM_COLOR_YCBCR_BT601, 782 DRM_COLOR_YCBCR_LIMITED_RANGE); 783 if (ret) 784 return ret; 785 786 drm_crtc_helper_add(crtc, &lcdif_crtc_helper_funcs); 787 return drm_crtc_init_with_planes(lcdif->drm, crtc, 788 &lcdif->planes.primary, NULL, 789 &lcdif_crtc_funcs, NULL); 790 } 791