1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7 8<enum name="vgt_event_type" varset="chip"> 9 <value name="VS_DEALLOC" value="0"/> 10 <value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/> 11 <value name="VS_DONE_TS" value="2"/> 12 <value name="PS_DONE_TS" value="3"/> 13 <doc> 14 Flushes dirty data from UCHE, and also writes a GPU timestamp to 15 the address if one is provided. 16 </doc> 17 <value name="CACHE_FLUSH_TS" value="4"/> 18 <value name="CONTEXT_DONE" value="5"/> 19 <value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/> 20 <value name="VIZQUERY_START" value="7" variants="A2XX"/> 21 <value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/> 22 <value name="VIZQUERY_END" value="8" variants="A2XX"/> 23 <value name="SC_WAIT_WC" value="9" variants="A2XX"/> 24 <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX-"/> 25 <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX-"/> 26 <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX-"/> 27 <!-- Not sure that these 4 events don't have the same meaning as on A5XX+ --> 28 <value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/> 29 <value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/> 30 <value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/> 31 <value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/> 32 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/> 33 <doc> 34 If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed 35 sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main 36 memory, skipping UCHE. 37 </doc> 38 <value name="ZPASS_DONE" value="21"/> 39 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/> 40 41 <doc> 42 Writes the GPU timestamp to the address that follows, once RB 43 access and flushes are complete. 44 </doc> 45 <value name="RB_DONE_TS" value="22" variants="A3XX-"/> 46 47 <value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/> 48 <value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/> 49 <value name="VS_FETCH_DONE" value="27"/> 50 <value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/> 51 52 <!-- a5xx events --> 53 <value name="WT_DONE_TS" value="8" variants="A5XX-"/> 54 <value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/> 55 <value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/> 56 <value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/> 57 <value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/> 58 <value name="FLUSH_SO_0" value="17" variants="A5XX-"/> 59 <value name="FLUSH_SO_1" value="18" variants="A5XX-"/> 60 <value name="FLUSH_SO_2" value="19" variants="A5XX-"/> 61 <value name="FLUSH_SO_3" value="20" variants="A5XX-"/> 62 63 <doc> 64 Invalidates depth attachment data from the CCU. We assume this 65 happens in the last stage. 66 </doc> 67 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/> 68 69 <doc> 70 Invalidates color attachment data from the CCU. We assume this 71 happens in the last stage. 72 </doc> 73 <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/> 74 75 <doc> 76 Flushes the small cache used by CP_EVENT_WRITE::BLIT (which, 77 along with its registers, would be better named RESOLVE). 78 </doc> 79 <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/> 80 81 <doc> 82 Flushes depth attachment data from the CCU. We assume this 83 happens in the last stage. 84 </doc> 85 <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/> 86 87 <doc> 88 Flushes color attachment data from the CCU. We assume this 89 happens in the last stage. 90 </doc> 91 <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/> 92 93 <doc> 94 2D blit to resolve GMEM to system memory (skipping CCU) at the 95 end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for 96 more general blitting. 97 </doc> 98 <value name="BLIT" value="30" variants="A5XX-"/> 99 100 <doc> 101 Flip between the primary and secondary LRZ buffers. This is used 102 for concurrent binning, so that BV can write to one buffer while 103 BR reads from the other. 104 </doc> 105 <value name="LRZ_FLIP_BUFFER" value="36" variants="A7XX"/> 106 107 <doc> 108 Clears based on GRAS_LRZ_CNTL configuration, could clear 109 fast-clear buffer or LRZ direction. 110 LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which 111 could be expressed by enum: 112 CUR_DIR_DISABLED = 0x0 113 CUR_DIR_GE = 0x1 114 CUR_DIR_LE = 0x2 115 CUR_DIR_UNSET = 0x3 116 Clear of direction means setting the direction to CUR_DIR_UNSET. 117 </doc> 118 <value name="LRZ_CLEAR" value="37" variants="A5XX-"/> 119 120 <value name="LRZ_FLUSH" value="38" variants="A5XX-"/> 121 <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/> 122 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/> 123 <value name="UNK_40" value="40" variants="A7XX"/> 124 <value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/> 125 <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/> 126 <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/> 127 <value name="UNK_2C" value="44" variants="A5XX-"/> 128 <value name="UNK_2D" value="45" variants="A5XX-"/> 129 130 <!-- a6xx events --> 131 <doc> 132 Invalidates UCHE. 133 </doc> 134 <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/> 135 136 <value name="LABEL" value="63" variants="A6XX-"/> 137 138 <!-- note, some of these are the same as a6xx, just named differently --> 139 140 <doc> Doesn't seem to do anything </doc> 141 <value name="DUMMY_EVENT" value="1" variants="A7XX"/> 142 <value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/> 143 <value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/> 144 <value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/> 145 <value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/> 146 <value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/> 147 <value name="CCU_RESOLVE" value="30" variants="A7XX"/> 148 <value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/> 149 <value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/> 150 <value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/> 151 <value name="CACHE_RESET" value="48" variants="A7XX"/> 152 <value name="CACHE_CLEAN" value="49" variants="A7XX"/> 153 <!-- TODO: deal with name conflicts with other gens --> 154 <value name="CACHE_FLUSH7" value="50" variants="A7XX"/> 155 <value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/> 156</enum> 157 158<enum name="pc_di_primtype"> 159 <value name="DI_PT_NONE" value="0"/> 160 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: --> 161 <value name="DI_PT_POINTLIST_PSIZE" value="1"/> 162 <value name="DI_PT_LINELIST" value="2"/> 163 <value name="DI_PT_LINESTRIP" value="3"/> 164 <value name="DI_PT_TRILIST" value="4"/> 165 <value name="DI_PT_TRIFAN" value="5"/> 166 <value name="DI_PT_TRISTRIP" value="6"/> 167 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx --> 168 <value name="DI_PT_RECTLIST" value="8"/> 169 <value name="DI_PT_POINTLIST" value="9"/> 170 <value name="DI_PT_LINE_ADJ" value="0xa"/> 171 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/> 172 <value name="DI_PT_TRI_ADJ" value="0xc"/> 173 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/> 174 175 <value name="DI_PT_PATCHES0" value="0x1f"/> 176 <value name="DI_PT_PATCHES1" value="0x20"/> 177 <value name="DI_PT_PATCHES2" value="0x21"/> 178 <value name="DI_PT_PATCHES3" value="0x22"/> 179 <value name="DI_PT_PATCHES4" value="0x23"/> 180 <value name="DI_PT_PATCHES5" value="0x24"/> 181 <value name="DI_PT_PATCHES6" value="0x25"/> 182 <value name="DI_PT_PATCHES7" value="0x26"/> 183 <value name="DI_PT_PATCHES8" value="0x27"/> 184 <value name="DI_PT_PATCHES9" value="0x28"/> 185 <value name="DI_PT_PATCHES10" value="0x29"/> 186 <value name="DI_PT_PATCHES11" value="0x2a"/> 187 <value name="DI_PT_PATCHES12" value="0x2b"/> 188 <value name="DI_PT_PATCHES13" value="0x2c"/> 189 <value name="DI_PT_PATCHES14" value="0x2d"/> 190 <value name="DI_PT_PATCHES15" value="0x2e"/> 191 <value name="DI_PT_PATCHES16" value="0x2f"/> 192 <value name="DI_PT_PATCHES17" value="0x30"/> 193 <value name="DI_PT_PATCHES18" value="0x31"/> 194 <value name="DI_PT_PATCHES19" value="0x32"/> 195 <value name="DI_PT_PATCHES20" value="0x33"/> 196 <value name="DI_PT_PATCHES21" value="0x34"/> 197 <value name="DI_PT_PATCHES22" value="0x35"/> 198 <value name="DI_PT_PATCHES23" value="0x36"/> 199 <value name="DI_PT_PATCHES24" value="0x37"/> 200 <value name="DI_PT_PATCHES25" value="0x38"/> 201 <value name="DI_PT_PATCHES26" value="0x39"/> 202 <value name="DI_PT_PATCHES27" value="0x3a"/> 203 <value name="DI_PT_PATCHES28" value="0x3b"/> 204 <value name="DI_PT_PATCHES29" value="0x3c"/> 205 <value name="DI_PT_PATCHES30" value="0x3d"/> 206 <value name="DI_PT_PATCHES31" value="0x3e"/> 207</enum> 208 209<enum name="pc_di_src_sel"> 210 <value name="DI_SRC_SEL_DMA" value="0"/> 211 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/> 212 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/> 213 <value name="DI_SRC_SEL_AUTO_XFB" value="3"/> 214</enum> 215 216<enum name="pc_di_face_cull_sel"> 217 <value name="DI_FACE_CULL_NONE" value="0"/> 218 <value name="DI_FACE_CULL_FETCH" value="1"/> 219 <value name="DI_FACE_BACKFACE_CULL" value="2"/> 220 <value name="DI_FACE_FRONTFACE_CULL" value="3"/> 221</enum> 222 223<enum name="pc_di_index_size"> 224 <value name="INDEX_SIZE_IGN" value="0"/> 225 <value name="INDEX_SIZE_16_BIT" value="0"/> 226 <value name="INDEX_SIZE_32_BIT" value="1"/> 227 <value name="INDEX_SIZE_8_BIT" value="2"/> 228 <value name="INDEX_SIZE_INVALID"/> 229</enum> 230 231<enum name="pc_di_vis_cull_mode"> 232 <value name="IGNORE_VISIBILITY" value="0"/> 233 <value name="USE_VISIBILITY" value="1"/> 234</enum> 235 236<enum name="adreno_pm4_packet_type"> 237 <value name="CP_TYPE0_PKT" value="0x00000000"/> 238 <value name="CP_TYPE1_PKT" value="0x40000000"/> 239 <value name="CP_TYPE2_PKT" value="0x80000000"/> 240 <value name="CP_TYPE3_PKT" value="0xc0000000"/> 241 <value name="CP_TYPE4_PKT" value="0x40000000"/> 242 <value name="CP_TYPE7_PKT" value="0x70000000"/> 243</enum> 244 245<!-- 246 Note that in some cases, the same packet id is recycled on a later 247 generation, so variants attribute is used to distinguish. They 248 may not be completely accurate, we would probably have to analyze 249 the pfp and me/pm4 firmware to verify the packet is actually 250 handled on a particular generation. But it is at least enough to 251 disambiguate the packet-id's that were re-used for different 252 packets starting with a5xx. 253 --> 254<enum name="adreno_pm4_type3_packets" varset="chip"> 255 <doc>initialize CP's micro-engine</doc> 256 <value name="CP_ME_INIT" value="0x48"/> 257 <doc>skip N 32-bit words to get to the next packet</doc> 258 <value name="CP_NOP" value="0x10"/> 259 <doc> 260 indirect buffer dispatch. prefetch parser uses this packet 261 type to determine whether to pre-fetch the IB 262 </doc> 263 <value name="CP_PREEMPT_ENABLE" value="0x1c" variants="A5XX"/> 264 <value name="CP_PREEMPT_TOKEN" value="0x1e" variants="A5XX"/> 265 <value name="CP_INDIRECT_BUFFER" value="0x3f"/> 266 <doc> 267 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to 268 another buffer at the same level. Must be at the end of IB, and 269 doesn't work with draw state IB's. 270 </doc> 271 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/> 272 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc> 273 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/> 274 <doc> 275 Waits for the IDLE state of the engine before further drawing. 276 This is pipelined, so the CP may continue. 277 </doc> 278 <value name="CP_WAIT_FOR_IDLE" value="0x26"/> 279 <doc>wait until a register or memory location is a specific value</doc> 280 <value name="CP_WAIT_REG_MEM" value="0x3c"/> 281 <doc>wait until a register location is equal to a specific value</doc> 282 <value name="CP_WAIT_REG_EQ" value="0x52"/> 283 <doc>wait until a register location is >= a specific value</doc> 284 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/> 285 <doc>wait until a read completes</doc> 286 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/> 287 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc> 288 <!-- 289 NOTE: CP_WAIT_IB_PFD_COMPLETE unimplemented at least since a5xx fw, and 290 recycled for something new on a7xx 291 --> 292 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/> 293 <doc>register read/modify/write</doc> 294 <value name="CP_REG_RMW" value="0x21"/> 295 <doc>Set binning configuration registers</doc> 296 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/> 297 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/> 298 <doc>reads register in chip and writes to memory</doc> 299 <value name="CP_REG_TO_MEM" value="0x3e"/> 300 <doc>write N 32-bit words to memory</doc> 301 <value name="CP_MEM_WRITE" value="0x3d"/> 302 <doc>write CP_PROG_COUNTER value to memory</doc> 303 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/> 304 <doc>conditional execution of a sequence of packets</doc> 305 <value name="CP_COND_EXEC" value="0x44"/> 306 <doc>conditional write to memory or register</doc> 307 <value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/> 308 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/> 309 <doc>generate an event that creates a write to memory when completed</doc> 310 <value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/> 311 <value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/> 312 <doc>generate a VS|PS_done event</doc> 313 <value name="CP_EVENT_WRITE_SHD" value="0x58"/> 314 <doc>generate a cache flush done event</doc> 315 <value name="CP_EVENT_WRITE_CFL" value="0x59"/> 316 <doc>generate a z_pass done event</doc> 317 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/> 318 <doc> 319 not sure the real name, but this seems to be what is used for 320 opencl, instead of CP_DRAW_INDX.. 321 </doc> 322 <value name="CP_RUN_OPENCL" value="0x31"/> 323 <doc>initiate fetch of index buffer and draw</doc> 324 <value name="CP_DRAW_INDX" value="0x22"/> 325 <doc>draw using supplied indices in packet</doc> 326 <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx --> 327 <doc>initiate fetch of index buffer and binIDs and draw</doc> 328 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/> 329 <doc>initiate fetch of bin IDs and draw using supplied indices</doc> 330 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/> 331 <doc>begin/end initiator for viz query extent processing</doc> 332 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/> 333 <doc>fetch state sub-blocks and initiate shader code DMAs</doc> 334 <value name="CP_SET_STATE" value="0x25"/> 335 <doc>load constant into chip and to memory</doc> 336 <value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/> 337 <doc>load sequencer instruction memory (pointer-based)</doc> 338 <value name="CP_IM_LOAD" value="0x27"/> 339 <doc>load sequencer instruction memory (code embedded in packet)</doc> 340 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/> 341 <doc>load constants from a location in memory</doc> 342 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/> 343 <doc>selective invalidation of state pointers</doc> 344 <value name="CP_INVALIDATE_STATE" value="0x3b"/> 345 <doc>dynamically changes shader instruction memory partition</doc> 346 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/> 347 <doc>sets the 64-bit BIN_MASK register in the PFP</doc> 348 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/> 349 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc> 350 <value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/> 351 <doc>updates the current context, if needed</doc> 352 <value name="CP_CONTEXT_UPDATE" value="0x5e"/> 353 <doc>generate interrupt from the command stream</doc> 354 <value name="CP_INTERRUPT" value="0x40"/> 355 <doc>copy sequencer instruction memory to system memory</doc> 356 <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/> 357 358 <!-- For a20x --> 359<!-- TODO handle variants.. 360 <doc> 361 Program an offset that will added to the BIN_BASE value of 362 the 3D_DRAW_INDX_BIN packet 363 </doc> 364 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/> 365 --> 366 367 <!-- for a22x --> 368 <doc> 369 sets draw initiator flags register in PFP, gets bitwise-ORed into 370 every draw initiator 371 </doc> 372 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/> 373 <doc>sets the register protection mode</doc> 374 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/> 375 376 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/> 377 378 <!-- for a3xx --> 379 <doc>load high level sequencer command</doc> 380 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/> 381 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/> 382 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc> 383 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a" variants="A3XX-A5XX"/> 384 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc> 385 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/> 386 <doc>Load a buffer with pre-fetch enabled</doc> 387 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/> 388 <doc>Set bin (?)</doc> 389 <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/> 390 391 <doc>test 2 memory locations to dword values specified</doc> 392 <value name="CP_TEST_TWO_MEMS" value="0x71"/> 393 394 <doc>Write register, ignoring context state for context sensitive registers</doc> 395 <value name="CP_REG_WR_NO_CTXT" value="0x78"/> 396 397 <doc>Record the real-time when this packet is processed by PFP</doc> 398 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/> 399 400 <!-- Used to switch GPU between secure and non-secure modes --> 401 <value name="CP_SET_SECURE_MODE" value="0x66"/> 402 403 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc> 404 <value name="CP_WAIT_FOR_ME" value="0x13"/> 405 406 <!-- for a4xx --> 407 <doc> 408 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple 409 groups of registers. Looks like it can be used to create state 410 objects in GPU memory, and on state change only emit pointer 411 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU 412 overhead: 413 414 (A4x) save PM4 stream pointers to execute upon a visible draw 415 </doc> 416 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/> 417 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/> 418 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/> 419 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/> 420 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX-"/> 421 <value name="CP_DRAW_AUTO" value="0x24"/> 422 423 <doc> 424 Enable or disable predication globally. Also resets the 425 predicate to "passing" and the local bit to enabled when 426 enabling global predication. 427 </doc> 428 <value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/> 429 430 <doc> 431 Enable or disable predication locally. Unlike globally enabling 432 predication, this packet doesn't touch any other state. 433 Predication only happens when enabled globally and locally and a 434 predicate has been set. This should be used for internal draws 435 which aren't supposed to use the predication state: 436 437 CP_DRAW_PRED_ENABLE_LOCAL(0) 438 ... do draw... 439 CP_DRAW_PRED_ENABLE_LOCAL(1) 440 </doc> 441 <value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/> 442 443 <doc> 444 Latch a draw predicate into the internal register. 445 </doc> 446 <value name="CP_DRAW_PRED_SET" value="0x4e"/> 447 448 <doc> 449 for A4xx 450 Write to register with address that does not fit into type-0 pkt 451 </doc> 452 <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/> 453 454 <doc>copy from ME scratch RAM to a register</doc> 455 <value name="CP_SCRATCH_TO_REG" value="0x4d"/> 456 457 <doc>Copy from REG to ME scratch RAM</doc> 458 <value name="CP_REG_TO_SCRATCH" value="0x4a"/> 459 460 <doc>Wait for memory writes to complete</doc> 461 <value name="CP_WAIT_MEM_WRITES" value="0x12"/> 462 463 <doc>Conditional execution based on register comparison</doc> 464 <value name="CP_COND_REG_EXEC" value="0x47"/> 465 466 <doc>Memory to REG copy</doc> 467 <value name="CP_MEM_TO_REG" value="0x42"/> 468 469 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX-"/> 470 <value name="CP_EXEC_CS" value="0x33"/> 471 472 <doc> 473 for a5xx 474 </doc> 475 <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/> 476 <!-- switches SMMU pagetable, used on a5xx+ only --> 477 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/> 478 <!-- for a6xx --> 479 <doc>Tells CP the current mode of GPU operation</doc> 480 <value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/> 481 <doc>Instruct CP to set a few internal CP registers</doc> 482 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX-"/> 483 <!-- 484 pairs of regid and value.. seems to be used to program some TF 485 related regs: 486 --> 487 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/> 488 <!-- A5XX Enable yield in RB only --> 489 <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/> 490 <doc> 491 Enables IB2 skipping. If both GLOBAL and LOCAL are 1 and 492 nothing is left in the visibility stream, then 493 CP_INDIRECT_BUFFER will be skipped, and draws will early return 494 from their IB. 495 </doc> 496 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/> 497 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/> 498 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/> 499 <value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/> 500 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/> 501 <!-- Enable/Disable/Defer A5x global preemption model --> 502 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/> 503 <!-- Enable/Disable A5x local preemption model --> 504 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/> 505 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx --> 506 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX-"/> 507 <!-- Inform CP about current render mode (needed for a5xx preemption) --> 508 <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/> 509 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/> 510 <!-- check if this works on earlier.. --> 511 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/> 512 513 <doc> 514 General purpose 2D blit engine for image transfers and mipmap 515 generation. Reads through UCHE, writes through the CCU cache in 516 the PS stage. 517 </doc> 518 <value name="CP_BLIT" value="0x2c" variants="A5XX-"/> 519 520 <!-- Test specified bit in specified register and set predicate --> 521 <value name="CP_REG_TEST" value="0x39" variants="A5XX-"/> 522 523 <!-- 524 Seems to set the mode flags which control which CP_SET_DRAW_STATE 525 packets are executed, based on their ENABLE_MASK values 526 527 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE 528 packets w/ ENABLE_MASK & 0x6 to execute immediately 529 --> 530 <value name="CP_SET_MODE" value="0x63" variants="A6XX-"/> 531 532 <!-- 533 Seems like there are now separate blocks of state for VS vs FS/CS 534 (probably these amounts to geometry vs fragments so that geometry 535 stage of the pipeline for next draw can start while fragment stage 536 of current draw is still running. The format of the payload of the 537 packets is the same, the only difference is the offsets of the regs 538 the firmware code that handles the packet writes. 539 540 Note that for CL, starting with a6xx, the preferred # of local 541 threads is no longer the same as the max, implying that the shader 542 core can now run warps from unrelated shaders (ie. 543 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs 544 CL_KERNEL_WORK_GROUP_SIZE) 545 --> 546 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/> 547 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/> 548 <!-- 549 Note: For UAV state (Image/SSBOs) which have shared state across 550 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for 551 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are 552 interchangable. 553 --> 554 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/> 555 556 <!-- internal packets: --> 557 <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/> 558 <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/> 559 <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/> 560 <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/> 561 <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/> 562 <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/> 563 <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/> 564 <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/> 565 566 <!-- internal jumptable entries on a6xx+, possibly a5xx: --> 567 568 <!-- jmptable entry used to handle type4 packet on a5xx+: --> 569 <value name="PKT4" value="0x04" variants="A5XX-"/> 570 <!-- called when ROQ is empty, "returns" from an IB or merged sequence of IBs --> 571 <value name="IN_IB_END" value="0x0a" variants="A6XX-"/> 572 <!-- handles IFPC save/restore --> 573 <value name="IN_GMU_INTERRUPT" value="0x0b" variants="A6XX-"/> 574 <!-- preemption/context-swtich routine --> 575 <value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/> 576 577 <!-- TODO do these exist on A5xx? --> 578 <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX-"/> 579 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/> 580 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/> 581 <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/> 582 <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/> 583 <value name="CP_MEMCPY" value="0x75" variants="A6XX-"/> 584 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX-"/> 585 <!-- A750+, set in place of CP_SET_BIN_DATA5_OFFSET but has different values --> 586 <value name="CP_SET_UNK_BIN_DATA" value="0x2d" variants="A7XX-"/> 587 <doc> 588 Write CP_CONTEXT_SWITCH_*_INFO from CP to the following dwords, 589 and forcibly switch to the indicated context. 590 </doc> 591 <value name="CP_CONTEXT_SWITCH" value="0x54" variants="A6XX"/> 592 <value name="CP_SET_AMBLE" value="0x55" variants="A6XX-"/> 593 594 <!-- 595 Seems to always have the payload: 596 00000002 00008801 00004010 597 or: 598 00000002 00008801 00004090 599 or: 600 00000002 00008801 00000010 601 00000002 00008801 00010010 602 00000002 00008801 00d64010 603 ... 604 Note set for compute shaders.. 605 Is 0x8801 a register offset? 606 This appears to be a special sort of register write packet 607 more or less, but the firmware has some special handling.. 608 Seems like it intercepts/modifies certain register offsets, 609 but others are treated like a normal PKT4 reg write. I 610 guess there are some registers that the fw controls certain 611 bits. 612 --> 613 <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/> 614 615 <doc> 616 These first appear in a650_sqe.bin. They can in theory be used 617 to loop any sequence of IB1 commands, but in practice they are 618 used to loop over bins. There is a fixed-size per-iteration 619 prefix, used to set per-bin state, and then the following IB1 620 commands are executed until CP_END_BIN which are always the same 621 for each iteration and usually contain a list of 622 CP_INDIRECT_BUFFER calls to IB2 commands which setup state and 623 execute restore/draw/save commands. This replaces the previous 624 technique of just repeating the CP_INDIRECT_BUFFER calls and 625 "unrolling" the loop. 626 </doc> 627 <value name="CP_START_BIN" value="0x50" variants="A6XX-"/> 628 <value name="CP_END_BIN" value="0x51" variants="A6XX-"/> 629 630 <doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc> 631 <value name="CP_PREEMPT_DISABLE" value="0x6c" variants="A6XX"/> 632 633 <value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/> 634 <value name="CP_GLOBAL_TIMESTAMP" value="0x15" variants="A7XX-"/> <!-- payload 1 dword --> 635 <value name="CP_LOCAL_TIMESTAMP" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x15 --> 636 <value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/> 637 <!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for GMEM save/restore?--> 638 <value name="CP_RESOURCE_LIST" value="0x18" variants="A7XX-"/> 639 <doc> Can clear BV/BR counters, or wait until one catches up to another </doc> 640 <value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/> 641 <doc> Clears, adds to local, or adds to global timestamp </doc> 642 <value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/> 643 <!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? --> 644 <value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/> 645 <doc> 646 Write to a scratch memory that is read by CP_REG_TEST with 647 SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers. 648 However it uses the same memory space. 649 </doc> 650 <value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/> 651 652 <doc> 653 Executes an array of fixed-size command buffers where each 654 buffer is assumed to have one draw call, skipping buffers with 655 non-visible draw calls. 656 </doc> 657 <value name="CP_FIXED_STRIDE_DRAW_TABLE" value="0x7f" variants="A7XX-"/> 658 659 <doc>Reset various on-chip state used for synchronization</doc> 660 <value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/> 661 662 <doc>Invalidates the "CCHE" introduced on a740</doc> 663 <value name="CP_CCHE_INVALIDATE" value="0x3a" variants="A7XX-"/> 664 665 <value name="CP_SCOPE_CNTL" value="0x6c" variants="A7XX-"/> 666</enum> 667 668 669<domain name="CP_LOAD_STATE" width="32"> 670 <doc>Load state, a3xx (and later?)</doc> 671 <enum name="adreno_state_block"> 672 <value name="SB_VERT_TEX" value="0"/> 673 <value name="SB_VERT_MIPADDR" value="1"/> 674 <value name="SB_FRAG_TEX" value="2"/> 675 <value name="SB_FRAG_MIPADDR" value="3"/> 676 <value name="SB_VERT_SHADER" value="4"/> 677 <value name="SB_GEOM_SHADER" value="5"/> 678 <value name="SB_FRAG_SHADER" value="6"/> 679 <value name="SB_COMPUTE_SHADER" value="7"/> 680 </enum> 681 <enum name="adreno_state_type"> 682 <value name="ST_SHADER" value="0"/> 683 <value name="ST_CONSTANTS" value="1"/> 684 </enum> 685 <enum name="adreno_state_src"> 686 <value name="SS_DIRECT" value="0"> 687 <doc>inline with the CP_LOAD_STATE packet</doc> 688 </value> 689 <value name="SS_INVALID_ALL_IC" value="2"/> 690 <value name="SS_INVALID_PART_IC" value="3"/> 691 <value name="SS_INDIRECT" value="4"> 692 <doc>in buffer pointed to by EXT_SRC_ADDR</doc> 693 </value> 694 <value name="SS_INDIRECT_TCM" value="5"/> 695 <value name="SS_INDIRECT_STM" value="6"/> 696 </enum> 697 <reg32 offset="0" name="0"> 698 <bitfield name="DST_OFF" low="0" high="15" type="uint"/> 699 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/> 700 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/> 701 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 702 </reg32> 703 <reg32 offset="1" name="1"> 704 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/> 705 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 706 </reg32> 707</domain> 708 709<domain name="CP_LOAD_STATE4" width="32" varset="chip"> 710 <doc>Load state, a4xx+</doc> 711 <enum name="a4xx_state_block"> 712 <!-- 713 unknown: 0x7 and 0xf <- seen in compute shader 714 715 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption? 716 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains 717 the gpuaddr of the following shader constants block. DST_OFF seems 718 to specify which shader stage: 719 720 16 -> vert 721 36 -> tcs 722 56 -> tes 723 76 -> geom 724 96 -> frag 725 726 Example: 727 728opcode: CP_LOAD_STATE4 (30) (12 dwords) 729 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 } 730 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 } 731 { EXT_SRC_ADDR_HI = 0 } 732 0000: c0264100 00000000 00000000 00000000 733 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000 734 735opcode: CP_LOAD_STATE4 (30) (4 dwords) 736 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 } 737 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 } 738 { EXT_SRC_ADDR_HI = 0 } 739 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 740 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 741 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000 742 743 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords. 744 745 --> 746 <value name="SB4_VS_TEX" value="0x0"/> 747 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS --> 748 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES --> 749 <value name="SB4_GS_TEX" value="0x3"/> 750 <value name="SB4_FS_TEX" value="0x4"/> 751 <value name="SB4_CS_TEX" value="0x5"/> 752 <value name="SB4_VS_SHADER" value="0x8"/> 753 <value name="SB4_HS_SHADER" value="0x9"/> 754 <value name="SB4_DS_SHADER" value="0xa"/> 755 <value name="SB4_GS_SHADER" value="0xb"/> 756 <value name="SB4_FS_SHADER" value="0xc"/> 757 <value name="SB4_CS_SHADER" value="0xd"/> 758 <!-- 759 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each), 760 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each) 761 762 Compute has it's own dedicated SSBO state, it seems, but the rest 763 of the stages share state 764 --> 765 <value name="SB4_SSBO" value="0xe"/> 766 <value name="SB4_CS_SSBO" value="0xf"/> 767 </enum> 768 <enum name="a4xx_state_type"> 769 <value name="ST4_SHADER" value="0"/> 770 <value name="ST4_CONSTANTS" value="1"/> 771 <value name="ST4_UBO" value="2"/> 772 </enum> 773 <enum name="a4xx_state_src"> 774 <value name="SS4_DIRECT" value="0"/> 775 <value name="SS4_INDIRECT" value="2"/> 776 </enum> 777 <reg32 offset="0" name="0"> 778 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 779 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/> 780 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/> 781 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 782 </reg32> 783 <reg32 offset="1" name="1"> 784 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/> 785 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 786 </reg32> 787 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 788 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 789 </reg32> 790</domain> 791 792<!-- looks basically same CP_LOAD_STATE4 --> 793<domain name="CP_LOAD_STATE6" width="32" varset="chip"> 794 <doc>Load state, a6xx+</doc> 795 <enum name="a6xx_state_block"> 796 <value name="SB6_VS_TEX" value="0x0"/> 797 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS --> 798 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES --> 799 <value name="SB6_GS_TEX" value="0x3"/> 800 <value name="SB6_FS_TEX" value="0x4"/> 801 <value name="SB6_CS_TEX" value="0x5"/> 802 <value name="SB6_VS_SHADER" value="0x8"/> 803 <value name="SB6_HS_SHADER" value="0x9"/> 804 <value name="SB6_DS_SHADER" value="0xa"/> 805 <value name="SB6_GS_SHADER" value="0xb"/> 806 <value name="SB6_FS_SHADER" value="0xc"/> 807 <value name="SB6_CS_SHADER" value="0xd"/> 808 <value name="SB6_UAV" value="0xe"/> 809 <value name="SB6_CS_UAV" value="0xf"/> 810 </enum> 811 <enum name="a6xx_state_type"> 812 <value name="ST6_SHADER" value="0"/> 813 <value name="ST6_CONSTANTS" value="1"/> 814 <value name="ST6_UBO" value="2"/> 815 <value name="ST6_UAV" value="3"/> 816 </enum> 817 <enum name="a6xx_state_src"> 818 <value name="SS6_DIRECT" value="0"/> 819 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? --> 820 <value name="SS6_INDIRECT" value="2"/> 821 <doc> 822 SS6_UBO used by the a6xx vulkan blob with tesselation constants 823 in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset) 824 to load constants from a UBO loaded with DST_OFF = 14 and offset 0, 825 EXT_SRC_ADDR = 0xe0000 826 (offset is a guess, should be in bytes given that maxUniformBufferRange=64k) 827 </doc> 828 <value name="SS6_UBO" value="3"/> 829 </enum> 830 <reg32 offset="0" name="0"> 831 <bitfield name="DST_OFF" low="0" high="13" type="uint"/> 832 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/> 833 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/> 834 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/> 835 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/> 836 </reg32> 837 <reg32 offset="1" name="1"> 838 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/> 839 </reg32> 840 <reg32 offset="2" name="2"> 841 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/> 842 </reg32> 843 <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/> 844</domain> 845 846<bitset name="vgt_draw_initiator" inline="yes"> 847 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 848 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 849 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/> 850 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/> 851 <bitfield name="NOT_EOP" pos="12" type="boolean"/> 852 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/> 853 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/> 854 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/> 855</bitset> 856 857<!-- changed on a4xx: --> 858<enum name="a4xx_index_size"> 859 <value name="INDEX4_SIZE_8_BIT" value="0"/> 860 <value name="INDEX4_SIZE_16_BIT" value="1"/> 861 <value name="INDEX4_SIZE_32_BIT" value="2"/> 862</enum> 863 864<enum name="a6xx_patch_type"> 865 <value name="TESS_QUADS" value="0"/> 866 <value name="TESS_TRIANGLES" value="1"/> 867 <value name="TESS_ISOLINES" value="2"/> 868</enum> 869 870<bitset name="vgt_draw_initiator_a4xx" inline="yes"> 871 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 --> 872 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/> 873 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/> 874 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/> 875 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/> 876 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/> 877 <bitfield name="GS_ENABLE" pos="16" type="boolean"/> 878 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/> 879</bitset> 880 881<domain name="CP_DRAW_INDX" width="32"> 882 <reg32 offset="0" name="0"> 883 <bitfield name="VIZ_QUERY" low="0" high="31"/> 884 </reg32> 885 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 886 <reg32 offset="2" name="2"> 887 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 888 </reg32> 889 <reg32 offset="3" name="3"> 890 <bitfield name="INDX_BASE" low="0" high="31"/> 891 </reg32> 892 <reg32 offset="4" name="4"> 893 <bitfield name="INDX_SIZE" low="0" high="31"/> 894 </reg32> 895</domain> 896 897<domain name="CP_DRAW_INDX_2" width="32"> 898 <reg32 offset="0" name="0"> 899 <bitfield name="VIZ_QUERY" low="0" high="31"/> 900 </reg32> 901 <reg32 offset="1" name="1" type="vgt_draw_initiator"/> 902 <reg32 offset="2" name="2"> 903 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 904 </reg32> 905 <!-- followed by NUM_INDICES indices.. --> 906</domain> 907 908<domain name="CP_DRAW_INDX_OFFSET" width="32"> 909 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 910 <reg32 offset="1" name="1"> 911 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> 912 </reg32> 913 <reg32 offset="2" name="2"> 914 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/> 915 </reg32> 916 <reg32 offset="3" name="3"> 917 <bitfield name="FIRST_INDX" low="0" high="31"/> 918 </reg32> 919 920 <stripe varset="chip" variants="A5XX-"> 921 <reg32 offset="4" name="4"> 922 <bitfield name="INDX_BASE_LO" low="0" high="31"/> 923 </reg32> 924 <reg32 offset="5" name="5"> 925 <bitfield name="INDX_BASE_HI" low="0" high="31"/> 926 </reg32> 927 <reg64 offset="4" name="INDX_BASE" type="address"/> 928 <reg32 offset="6" name="6"> 929 <!-- max # of elements in index buffer --> 930 <bitfield name="MAX_INDICES" low="0" high="31"/> 931 </reg32> 932 </stripe> 933 934 <reg32 offset="4" name="4"> 935 <bitfield name="INDX_BASE" low="0" high="31" type="address"/> 936 </reg32> 937 938 <reg32 offset="5" name="5"> 939 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 940 </reg32> 941</domain> 942 943<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 944 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 945 <stripe varset="chip" variants="A4XX"> 946 <reg32 offset="1" name="1"> 947 <bitfield name="INDIRECT" low="0" high="31"/> 948 </reg32> 949 </stripe> 950 <stripe varset="chip" variants="A5XX-"> 951 <reg32 offset="1" name="1"> 952 <bitfield name="INDIRECT_LO" low="0" high="31"/> 953 </reg32> 954 <reg32 offset="2" name="2"> 955 <bitfield name="INDIRECT_HI" low="0" high="31"/> 956 </reg32> 957 <reg64 offset="1" name="INDIRECT" type="address"/> 958 </stripe> 959</domain> 960 961<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 962 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 963 <stripe varset="chip" variants="A4XX"> 964 <reg32 offset="1" name="1"> 965 <bitfield name="INDX_BASE" low="0" high="31"/> 966 </reg32> 967 <reg32 offset="2" name="2"> 968 <!-- max # of bytes in index buffer --> 969 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/> 970 </reg32> 971 <reg32 offset="3" name="3"> 972 <bitfield name="INDIRECT" low="0" high="31"/> 973 </reg32> 974 </stripe> 975 <stripe varset="chip" variants="A5XX-"> 976 <reg32 offset="1" name="1"> 977 <bitfield name="INDX_BASE_LO" low="0" high="31"/> 978 </reg32> 979 <reg32 offset="2" name="2"> 980 <bitfield name="INDX_BASE_HI" low="0" high="31"/> 981 </reg32> 982 <reg64 offset="1" name="INDX_BASE" type="address"/> 983 <reg32 offset="3" name="3"> 984 <!-- max # of elements in index buffer --> 985 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/> 986 </reg32> 987 <reg32 offset="4" name="4"> 988 <bitfield name="INDIRECT_LO" low="0" high="31"/> 989 </reg32> 990 <reg32 offset="5" name="5"> 991 <bitfield name="INDIRECT_HI" low="0" high="31"/> 992 </reg32> 993 <reg64 offset="4" name="INDIRECT" type="address"/> 994 </stripe> 995</domain> 996 997<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-"> 998 <enum name="a6xx_draw_indirect_opcode"> 999 <value name="INDIRECT_OP_NORMAL" value="0x2"/> 1000 <value name="INDIRECT_OP_INDEXED" value="0x4"/> 1001 <value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/> 1002 <value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/> 1003 </enum> 1004 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 1005 <reg32 offset="1" name="1"> 1006 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/> 1007 <doc> 1008 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will 1009 be updated for each draw to {draw_id, first_vertex, first_instance, 0} 1010 value of 0 disables it 1011 </doc> 1012 <bitfield name="DST_OFF" low="8" high="21" type="hex"/> 1013 </reg32> 1014 <reg32 offset="2" name="DRAW_COUNT" type="uint"/> 1015 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL"> 1016 <reg64 offset="3" name="INDIRECT" type="address"/> 1017 <reg32 offset="5" name="STRIDE" type="uint"/> 1018 </stripe> 1019 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED" prefix="INDEXED"> 1020 <reg64 offset="3" name="INDEX" type="address"/> 1021 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 1022 <reg64 offset="6" name="INDIRECT" type="address"/> 1023 <reg32 offset="8" name="STRIDE" type="uint"/> 1024 </stripe> 1025 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT" prefix="INDIRECT"> 1026 <reg64 offset="3" name="INDIRECT" type="address"/> 1027 <reg64 offset="5" name="INDIRECT_COUNT" type="address"/> 1028 <reg32 offset="7" name="STRIDE" type="uint"/> 1029 </stripe> 1030 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED" prefix="INDIRECT_INDEXED"> 1031 <reg64 offset="3" name="INDEX" type="address"/> 1032 <reg32 offset="5" name="MAX_INDICES" type="uint"/> 1033 <reg64 offset="6" name="INDIRECT" type="address"/> 1034 <reg64 offset="8" name="INDIRECT_COUNT" type="address"/> 1035 <reg32 offset="10" name="STRIDE" type="uint"/> 1036 </stripe> 1037</domain> 1038 1039<domain name="CP_DRAW_AUTO" width="32"> 1040 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/> 1041 <reg32 offset="1" name="1"> 1042 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/> 1043 </reg32> 1044 <reg64 offset="2" name="NUM_VERTICES_BASE" type="address"/> 1045 <reg32 offset="4" name="4"> 1046 <bitfield name="NUM_VERTICES_OFFSET" low="0" high="31" type="uint"/> 1047 </reg32> 1048 <reg32 offset="5" name="5"> 1049 <bitfield name="STRIDE" low="0" high="31" type="uint"/> 1050 </reg32> 1051</domain> 1052 1053<domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip"> 1054 <reg32 offset="0" name="0"> 1055 <bitfield name="ENABLE" pos="0" type="boolean"/> 1056 </reg32> 1057</domain> 1058 1059<domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip"> 1060 <reg32 offset="0" name="0"> 1061 <bitfield name="ENABLE" pos="0" type="boolean"/> 1062 </reg32> 1063</domain> 1064 1065<domain name="CP_DRAW_PRED_SET" width="32" varset="chip"> 1066 <enum name="cp_draw_pred_src"> 1067 <!-- 1068 Sources 1-4 seem to be about combining reading 1069 SO/primitive queries and setting the predicate, which is 1070 a DX11-specific optimization (since in DX11 you can only 1071 predicate on the result of queries). 1072 --> 1073 <value name="PRED_SRC_MEM" value="5"> 1074 <doc> 1075 Read a 64-bit value at the given address and 1076 test if it equals/doesn't equal 0. 1077 </doc> 1078 </value> 1079 </enum> 1080 <enum name="cp_draw_pred_test"> 1081 <value name="NE_0_PASS" value="0"/> 1082 <value name="EQ_0_PASS" value="1"/> 1083 </enum> 1084 <reg32 offset="0" name="0"> 1085 <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/> 1086 <bitfield name="TEST" pos="8" type="cp_draw_pred_test"/> 1087 </reg32> 1088 <reg64 offset="1" name="MEM_ADDR" type="address"/> 1089</domain> 1090 1091<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-"> 1092 <array offset="0" stride="3" length="100"> 1093 <reg32 offset="0" name="0"> 1094 <bitfield name="COUNT" low="0" high="15" type="uint"/> 1095 <bitfield name="DIRTY" pos="16" type="boolean"/> 1096 <bitfield name="DISABLE" pos="17" type="boolean"/> 1097 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/> 1098 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/> 1099 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/> 1100 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/> 1101 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/> 1102 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/> 1103 </reg32> 1104 <reg32 offset="1" name="1"> 1105 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/> 1106 </reg32> 1107 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1108 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/> 1109 </reg32> 1110 </array> 1111</domain> 1112 1113<domain name="CP_SET_BIN" width="32"> 1114 <doc>value at offset 0 always seems to be 0x00000000..</doc> 1115 <reg32 offset="0" name="0"/> 1116 <reg32 offset="1" name="1"> 1117 <bitfield name="X1" low="0" high="15" type="uint"/> 1118 <bitfield name="Y1" low="16" high="31" type="uint"/> 1119 </reg32> 1120 <reg32 offset="2" name="2"> 1121 <bitfield name="X2" low="0" high="15" type="uint"/> 1122 <bitfield name="Y2" low="16" high="31" type="uint"/> 1123 </reg32> 1124</domain> 1125 1126<domain name="CP_SET_BIN_DATA" width="32"> 1127 <reg32 offset="0" name="0"> 1128 <!-- corresponds to VSC_PIPE[n].DATA_ADDR --> 1129 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/> 1130 </reg32> 1131 <reg32 offset="1" name="1"> 1132 <!-- seesm to correspond to VSC_SIZE_ADDRESS --> 1133 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/> 1134 </reg32> 1135</domain> 1136 1137<enum name="a7xx_abs_mask_mode"> 1138 <value name="ABS_MASK" value="0x1"/> 1139 <value name="NO_ABS_MASK" value="0x0"/> 1140</enum> 1141 1142<domain name="CP_SET_BIN_DATA5" width="32"> 1143 <reg32 offset="0" name="0"> 1144 <bitfield name="VSC_MASK" low="0" high="15" type="hex"> 1145 <doc> 1146 A mask of bins, starting at VSC_N, whose 1147 visibility is OR'd together. A value of 0 is 1148 interpreted as 1 (i.e. just use VSC_N for 1149 visbility) for backwards compatibility. Only 1150 exists on a7xx. 1151 </doc> 1152 </bitfield> 1153 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 1154 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 1155 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 1156 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 1157 <bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes"> 1158 <doc> 1159 If this field is 1, VSC_MASK and VSC_N are 1160 ignored and instead a new ordinal immediately 1161 after specifies the full 32-bit mask of bins 1162 to use. The mask is "absolute" instead of 1163 relative to VSC_N. 1164 </doc> 1165 </bitfield> 1166 </reg32> 1167 <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> 1168 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1169 <reg32 offset="1" name="1"> 1170 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1171 </reg32> 1172 <reg32 offset="2" name="2"> 1173 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1174 </reg32> 1175 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1176 <reg32 offset="3" name="3"> 1177 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1178 </reg32> 1179 <reg32 offset="4" name="4"> 1180 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1181 </reg32> 1182 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1183 <reg32 offset="5" name="5"> 1184 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1185 </reg32> 1186 <reg32 offset="6" name="6"> 1187 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1188 </reg32> 1189 <!-- 1190 a7xx adds a few more addresses to the end of the pkt 1191 --> 1192 <reg64 offset="7" name="7"/> 1193 <reg64 offset="9" name="9"/> 1194 </stripe> 1195 <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> 1196 <reg32 offset="1" name="ABS_MASK"/> 1197 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1198 <reg32 offset="2" name="2"> 1199 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1200 </reg32> 1201 <reg32 offset="3" name="3"> 1202 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1203 </reg32> 1204 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1205 <reg32 offset="4" name="4"> 1206 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1207 </reg32> 1208 <reg32 offset="5" name="5"> 1209 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1210 </reg32> 1211 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1212 <reg32 offset="6" name="6"> 1213 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1214 </reg32> 1215 <reg32 offset="7" name="7"> 1216 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1217 </reg32> 1218 <!-- 1219 a7xx adds a few more addresses to the end of the pkt 1220 --> 1221 <reg64 offset="8" name="8"/> 1222 <reg64 offset="10" name="10"/> 1223 </stripe> 1224</domain> 1225 1226<domain name="CP_SET_BIN_DATA5_OFFSET" width="32"> 1227 <doc> 1228 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the 1229 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful 1230 for Vulkan where these values aren't known when the command 1231 stream is recorded. 1232 </doc> 1233 <reg32 offset="0" name="0"> 1234 <bitfield name="VSC_MASK" low="0" high="15" type="hex"/> 1235 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: --> 1236 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 1237 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: --> 1238 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 1239 <bitfield name="ABS_MASK" pos="28" type="a7xx_abs_mask_mode" addvariant="yes"/> 1240 </reg32> 1241 <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> 1242 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1243 <reg32 offset="1" name="1"> 1244 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 1245 </reg32> 1246 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1247 <reg32 offset="2" name="2"> 1248 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1249 </reg32> 1250 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1251 <reg32 offset="3" name="3"> 1252 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1253 </reg32> 1254 </stripe> 1255 <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> 1256 <reg32 offset="1" name="ABS_MASK"/> 1257 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1258 <reg32 offset="2" name="2"> 1259 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/> 1260 </reg32> 1261 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1262 <reg32 offset="3" name="3"> 1263 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/> 1264 </reg32> 1265 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS --> 1266 <reg32 offset="4" name="4"> 1267 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/> 1268 </reg32> 1269 </stripe> 1270</domain> 1271 1272<domain name="CP_REG_RMW" width="32"> 1273 <doc> 1274 Modifies DST_REG using two sources that can either be registers 1275 or immediates. If SRC1_ADD is set, then do the following: 1276 1277 $dst = (($dst & $src0) rot $rotate) + $src1 1278 1279 Otherwise: 1280 1281 $dst = (($dst & $src0) rot $rotate) | $src1 1282 1283 Here "rot" means rotate left. 1284 </doc> 1285 <reg32 offset="0" name="0"> 1286 <bitfield name="DST_REG" low="0" high="17" type="hex"/> 1287 <bitfield name="DST_SCRATCH" pos="19" type="boolean" varset="chip" variants="A7XX-"/> 1288 <!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME --> 1289 <bitfield name="SKIP_WAIT_FOR_ME" pos="23" type="boolean" varset="chip" variants="A7XX-"/> 1290 <bitfield name="ROTATE" low="24" high="28" type="uint"/> 1291 <bitfield name="SRC1_ADD" pos="29" type="boolean"/> 1292 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/> 1293 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/> 1294 </reg32> 1295 <reg32 offset="1" name="1"> 1296 <bitfield name="SRC0" low="0" high="31" type="uint"/> 1297 </reg32> 1298 <reg32 offset="2" name="2"> 1299 <bitfield name="SRC1" low="0" high="31" type="uint"/> 1300 </reg32> 1301</domain> 1302 1303<domain name="CP_REG_TO_MEM" width="32"> 1304 <reg32 offset="0" name="0"> 1305 <bitfield name="REG" low="0" high="17" type="hex"/> 1306 <!-- number of registers/dwords copied is max(CNT, 1). --> 1307 <bitfield name="CNT" low="18" high="29" type="uint"/> 1308 <bitfield name="64B" pos="30" type="boolean"/> 1309 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1310 </reg32> 1311 <reg32 offset="1" name="1"> 1312 <bitfield name="DEST" low="0" high="31"/> 1313 </reg32> 1314 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1315 <bitfield name="DEST_HI" low="0" high="31"/> 1316 </reg32> 1317</domain> 1318 1319<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32"> 1320 <doc> 1321 Like CP_REG_TO_MEM, but the memory address to write to can be 1322 offsetted using either one or two registers or scratch 1323 registers. 1324 </doc> 1325 <reg32 offset="0" name="0"> 1326 <bitfield name="REG" low="0" high="17" type="hex"/> 1327 <!-- number of registers/dwords copied is max(CNT, 1). --> 1328 <bitfield name="CNT" low="18" high="29" type="uint"/> 1329 <bitfield name="64B" pos="30" type="boolean"/> 1330 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1331 </reg32> 1332 <reg32 offset="1" name="1"> 1333 <bitfield name="DEST" low="0" high="31"/> 1334 </reg32> 1335 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1336 <bitfield name="DEST_HI" low="0" high="31"/> 1337 </reg32> 1338 <reg32 offset="3" name="3"> 1339 <bitfield name="OFFSET0" low="0" high="17" type="hex"/> 1340 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/> 1341 </reg32> 1342 <!-- followed by an optional identical OFFSET1 dword --> 1343</domain> 1344 1345<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32"> 1346 <doc> 1347 Like CP_REG_TO_MEM, but the memory address to write to can be 1348 offsetted using a DWORD in memory. 1349 </doc> 1350 <reg32 offset="0" name="0"> 1351 <bitfield name="REG" low="0" high="17" type="hex"/> 1352 <!-- number of registers/dwords copied is max(CNT, 1). --> 1353 <bitfield name="CNT" low="18" high="29" type="uint"/> 1354 <bitfield name="64B" pos="30" type="boolean"/> 1355 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1356 </reg32> 1357 <reg32 offset="1" name="1"> 1358 <bitfield name="DEST" low="0" high="31"/> 1359 </reg32> 1360 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1361 <bitfield name="DEST_HI" low="0" high="31"/> 1362 </reg32> 1363 <reg32 offset="3" name="3"> 1364 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/> 1365 </reg32> 1366 <reg32 offset="4" name="4"> 1367 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/> 1368 </reg32> 1369</domain> 1370 1371<domain name="CP_MEM_TO_REG" width="32"> 1372 <reg32 offset="0" name="0"> 1373 <bitfield name="REG" low="0" high="17" type="hex"/> 1374 <!-- number of registers/dwords copied is max(CNT, 1). --> 1375 <bitfield name="CNT" low="19" high="29" type="uint"/> 1376 <!-- shift each DWORD left by 2 while copying --> 1377 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/> 1378 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 --> 1379 <bitfield name="UNK31" pos="31" type="boolean"/> 1380 </reg32> 1381 <reg32 offset="1" name="1"> 1382 <bitfield name="SRC" low="0" high="31"/> 1383 </reg32> 1384 <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1385 <bitfield name="SRC_HI" low="0" high="31"/> 1386 </reg32> 1387</domain> 1388 1389<domain name="CP_MEM_TO_MEM" width="32"> 1390 <reg32 offset="0" name="0"> 1391 <!-- 1392 not sure how many src operands we have, but the low 1393 bits negate the n'th src argument. 1394 --> 1395 <bitfield name="NEG_A" pos="0" type="boolean"/> 1396 <bitfield name="NEG_B" pos="1" type="boolean"/> 1397 <bitfield name="NEG_C" pos="2" type="boolean"/> 1398 1399 <!-- if set treat src/dst as 64bit values --> 1400 <bitfield name="DOUBLE" pos="29" type="boolean"/> 1401 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand --> 1402 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/> 1403 <!-- some other kind of wait --> 1404 <bitfield name="UNK31" pos="31" type="boolean"/> 1405 </reg32> 1406 <!-- 1407 followed by sequence of addresses.. the first is the 1408 destination and the rest are N src addresses which are 1409 summed (after being negated if NEG_x bit set) allowing 1410 to do things like 'result += end - start' (which turns 1411 out to be useful for queries and accumulating results 1412 across multiple tiles) 1413 --> 1414</domain> 1415 1416<domain name="CP_MEMCPY" width="32"> 1417 <reg32 offset="0" name="0"> 1418 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 1419 </reg32> 1420 <reg32 offset="1" name="1"> 1421 <bitfield name="SRC_LO" low="0" high="31" type="hex"/> 1422 </reg32> 1423 <reg32 offset="2" name="2"> 1424 <bitfield name="SRC_HI" low="0" high="31" type="hex"/> 1425 </reg32> 1426 <reg32 offset="3" name="3"> 1427 <bitfield name="DST_LO" low="0" high="31" type="hex"/> 1428 </reg32> 1429 <reg32 offset="4" name="4"> 1430 <bitfield name="DST_HI" low="0" high="31" type="hex"/> 1431 </reg32> 1432</domain> 1433 1434<domain name="CP_REG_TO_SCRATCH" width="32"> 1435 <reg32 offset="0" name="0"> 1436 <bitfield name="REG" low="0" high="17" type="hex"/> 1437 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1438 <!-- number of registers/dwords copied is CNT + 1. --> 1439 <bitfield name="CNT" low="24" high="26" type="uint"/> 1440 <!-- skip implied CP_WAIT_FOR_IDLE + CP_WAIT_FOR_ME --> 1441 <bitfield name="SKIP_WAIT_FOR_ME" pos="27" type="boolean" varset="chip" variants="A7XX-"/> 1442 </reg32> 1443</domain> 1444 1445<domain name="CP_SCRATCH_TO_REG" width="32"> 1446 <reg32 offset="0" name="0"> 1447 <bitfield name="REG" low="0" high="17" type="hex"/> 1448 <!-- note: CP_MEM_TO_REG always sets this when writing to the register --> 1449 <bitfield name="UNK18" pos="18" type="boolean"/> 1450 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1451 <!-- number of registers/dwords copied is CNT + 1. --> 1452 <bitfield name="CNT" low="24" high="26" type="uint"/> 1453 </reg32> 1454</domain> 1455 1456<domain name="CP_SCRATCH_WRITE" width="32"> 1457 <reg32 offset="0" name="0"> 1458 <bitfield name="SCRATCH" low="20" high="22" type="uint"/> 1459 </reg32> 1460 <!-- followed by one or more DWORDs to write to scratch registers --> 1461</domain> 1462 1463<domain name="CP_MEM_WRITE" width="32"> 1464 <reg32 offset="0" name="0"> 1465 <bitfield name="ADDR_LO" low="0" high="31"/> 1466 </reg32> 1467 <reg32 offset="1" name="1"> 1468 <bitfield name="ADDR_HI" low="0" high="31"/> 1469 </reg32> 1470 <!-- followed by the DWORDs to write --> 1471</domain> 1472 1473<enum name="cp_cond_function"> 1474 <value value="0" name="WRITE_ALWAYS"/> 1475 <value value="1" name="WRITE_LT"/> 1476 <value value="2" name="WRITE_LE"/> 1477 <value value="3" name="WRITE_EQ"/> 1478 <value value="4" name="WRITE_NE"/> 1479 <value value="5" name="WRITE_GE"/> 1480 <value value="6" name="WRITE_GT"/> 1481</enum> 1482 1483<domain name="CP_COND_WRITE" width="32"> 1484 <reg32 offset="0" name="0"> 1485 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1486 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/> 1487 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1488 </reg32> 1489 <reg32 offset="1" name="1"> 1490 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/> 1491 </reg32> 1492 <reg32 offset="2" name="2"> 1493 <bitfield name="REF" low="0" high="31"/> 1494 </reg32> 1495 <reg32 offset="3" name="3"> 1496 <bitfield name="MASK" low="0" high="31"/> 1497 </reg32> 1498 <reg32 offset="4" name="4"> 1499 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/> 1500 </reg32> 1501 <reg32 offset="5" name="5"> 1502 <bitfield name="WRITE_DATA" low="0" high="31"/> 1503 </reg32> 1504</domain> 1505 1506<enum name="poll_memory_type"> 1507 <value value="0" name="POLL_REGISTER"/> 1508 <value value="1" name="POLL_MEMORY"/> 1509 <value value="2" name="POLL_SCRATCH"/> 1510 <value value="3" name="POLL_ON_CHIP" varset="chip" variants="A7XX-"/> 1511</enum> 1512 1513<domain name="CP_COND_WRITE5" width="32"> 1514 <reg32 offset="0" name="0"> 1515 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1516 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1517 <!-- POLL_REGISTER polls a register at POLL_ADDR_LO. --> 1518 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1519 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1520 </reg32> 1521 <reg32 offset="1" name="1"> 1522 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1523 </reg32> 1524 <reg32 offset="2" name="2"> 1525 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1526 </reg32> 1527 <reg32 offset="3" name="3"> 1528 <bitfield name="REF" low="0" high="31"/> 1529 </reg32> 1530 <reg32 offset="4" name="4"> 1531 <bitfield name="MASK" low="0" high="31"/> 1532 </reg32> 1533 <reg32 offset="5" name="5"> 1534 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/> 1535 </reg32> 1536 <reg32 offset="6" name="6"> 1537 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/> 1538 </reg32> 1539 <reg32 offset="7" name="7"> 1540 <bitfield name="WRITE_DATA" low="0" high="31"/> 1541 </reg32> 1542</domain> 1543 1544<domain name="CP_WAIT_MEM_GTE" width="32"> 1545 <doc> 1546 Wait until a memory value is greater than or equal to the 1547 reference, using signed comparison. 1548 </doc> 1549 <reg32 offset="0" name="0"> 1550 <!-- Reserved for flags, presumably? Unused in FW --> 1551 <bitfield name="RESERVED" low="0" high="31" type="hex"/> 1552 </reg32> 1553 <reg32 offset="1" name="1"> 1554 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1555 </reg32> 1556 <reg32 offset="2" name="2"> 1557 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1558 </reg32> 1559 <reg32 offset="3" name="3"> 1560 <bitfield name="REF" low="0" high="31"/> 1561 </reg32> 1562</domain> 1563 1564<domain name="CP_WAIT_REG_MEM" width="32"> 1565 <doc> 1566 This uses the same internal comparison as CP_COND_WRITE, 1567 but waits until the comparison is true instead. It busy-loops in 1568 the CP for the given number of cycles before trying again. 1569 </doc> 1570 <reg32 offset="0" name="0"> 1571 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/> 1572 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/> 1573 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1574 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1575 </reg32> 1576 <reg32 offset="1" name="1"> 1577 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1578 </reg32> 1579 <reg32 offset="2" name="2"> 1580 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1581 </reg32> 1582 <reg32 offset="3" name="3"> 1583 <bitfield name="REF" low="0" high="31"/> 1584 </reg32> 1585 <reg32 offset="4" name="4"> 1586 <bitfield name="MASK" low="0" high="31"/> 1587 </reg32> 1588 <reg32 offset="5" name="5"> 1589 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/> 1590 </reg32> 1591</domain> 1592 1593<domain name="CP_WAIT_TWO_REGS" width="32"> 1594 <doc> 1595 Waits for REG0 to not be 0 or REG1 to not equal REF 1596 </doc> 1597 <reg32 offset="0" name="0"> 1598 <bitfield name="REG0" low="0" high="17" type="hex"/> 1599 </reg32> 1600 <reg32 offset="1" name="1"> 1601 <bitfield name="REG1" low="0" high="17" type="hex"/> 1602 </reg32> 1603 <reg32 offset="2" name="2"> 1604 <bitfield name="REF" low="0" high="31" type="uint"/> 1605 </reg32> 1606</domain> 1607 1608<domain name="CP_DISPATCH_COMPUTE" width="32"> 1609 <reg32 offset="0" name="0"/> 1610 <reg32 offset="1" name="1"> 1611 <bitfield name="X" low="0" high="31"/> 1612 </reg32> 1613 <reg32 offset="2" name="2"> 1614 <bitfield name="Y" low="0" high="31"/> 1615 </reg32> 1616 <reg32 offset="3" name="3"> 1617 <bitfield name="Z" low="0" high="31"/> 1618 </reg32> 1619</domain> 1620 1621<domain name="CP_SET_RENDER_MODE" width="32"> 1622 <enum name="render_mode_cmd"> 1623 <value value="1" name="BYPASS"/> 1624 <value value="2" name="BINNING"/> 1625 <value value="3" name="GMEM"/> 1626 <value value="5" name="BLIT2D"/> 1627 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? --> 1628 <value value="7" name="BLIT2DSCALE"/> 1629 <!-- 8 set before going back to BYPASS exiting 2D --> 1630 <value value="8" name="END2D"/> 1631 </enum> 1632 <reg32 offset="0" name="0"> 1633 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/> 1634 <!-- 1635 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in 1636 0x21xx range.. possibly (at least some) a5xx variants have a 1637 2d core? 1638 --> 1639 </reg32> 1640 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1641 <reg32 offset="1" name="1"> 1642 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1643 </reg32> 1644 <reg32 offset="2" name="2"> 1645 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1646 </reg32> 1647 <reg32 offset="3" name="3"> 1648 <!-- 1649 set when in GMEM.. maybe indicates GMEM contents need to be 1650 preserved on ctx switch? 1651 --> 1652 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/> 1653 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/> 1654 </reg32> 1655 <reg32 offset="4" name="4"/> 1656 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1657 <reg32 offset="5" name="5"> 1658 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1659 </reg32> 1660 <reg32 offset="6" name="6"> 1661 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1662 </reg32> 1663 <reg32 offset="7" name="7"> 1664 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1665 </reg32> 1666</domain> 1667 1668<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword --> 1669<domain name="CP_COMPUTE_CHECKPOINT" width="32"> 1670 <!-- I think first buffer is for GPU to save context in case of ctx switch? --> 1671 <reg32 offset="0" name="0"> 1672 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1673 </reg32> 1674 <reg32 offset="1" name="1"> 1675 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1676 </reg32> 1677 <reg32 offset="2" name="2"> 1678 </reg32> 1679 <reg32 offset="3" name="3"/> 1680 <!-- second buffer looks like some cmdstream.. length in dwords: --> 1681 <reg32 offset="4" name="4"> 1682 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/> 1683 </reg32> 1684 <reg32 offset="5" name="5"> 1685 <bitfield name="ADDR_1_LO" low="0" high="31"/> 1686 </reg32> 1687 <reg32 offset="6" name="6"> 1688 <bitfield name="ADDR_1_HI" low="0" high="31"/> 1689 </reg32> 1690 <reg32 offset="7" name="7"/> 1691</domain> 1692 1693<domain name="CP_PERFCOUNTER_ACTION" width="32"> 1694 <reg32 offset="0" name="0"> 1695 </reg32> 1696 <reg32 offset="1" name="1"> 1697 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1698 </reg32> 1699 <reg32 offset="2" name="2"> 1700 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1701 </reg32> 1702</domain> 1703 1704<domain varset="chip" name="CP_EVENT_WRITE" width="32"> 1705 <reg32 offset="0" name="0"> 1706 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/> 1707 <!-- when set, write back timestamp instead of value from packet: --> 1708 <bitfield name="TIMESTAMP" pos="30" type="boolean"/> 1709 <bitfield name="IRQ" pos="31" type="boolean"/> 1710 </reg32> 1711 <!-- 1712 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for 1713 context switch? 1714 --> 1715 <reg32 offset="1" name="1"> 1716 <bitfield name="ADDR_0_LO" low="0" high="31"/> 1717 </reg32> 1718 <reg32 offset="2" name="2"> 1719 <bitfield name="ADDR_0_HI" low="0" high="31"/> 1720 </reg32> 1721 <reg32 offset="3" name="3"> 1722 <!-- ??? --> 1723 </reg32> 1724</domain> 1725 1726<domain varset="chip" name="CP_EVENT_WRITE7" width="32"> 1727 <enum name="event_write_src"> 1728 <!-- Write payload[0] --> 1729 <value value="0" name="EV_WRITE_USER_32B"/> 1730 <!-- Write payload[0] payload[1] --> 1731 <value value="1" name="EV_WRITE_USER_64B"/> 1732 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) --> 1733 <value value="2" name="EV_WRITE_TIMESTAMP_SUM"/> 1734 <value value="3" name="EV_WRITE_ALWAYSON"/> 1735 <!-- Write payload[1] regs starting at payload[0] offset --> 1736 <value value="4" name="EV_WRITE_REGS_CONTENT"/> 1737 </enum> 1738 1739 <enum name="event_write_dst"> 1740 <value value="0" name="EV_DST_RAM"/> 1741 <value value="1" name="EV_DST_ONCHIP"/> 1742 </enum> 1743 1744 <reg32 offset="0" name="0"> 1745 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/> 1746 <bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/> 1747 <!-- Write sample count at (iova + 16) --> 1748 <bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/> 1749 <!-- *(iova + 8) += *(iova + 16) - *iova --> 1750 <bitfield name="WRITE_ACCUM_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/> 1751 1752 <!-- Next 4 flags are valid to set only when concurrent binning is enabled --> 1753 <!-- Increment 16b BV counter. Valid only in BV pipe --> 1754 <bitfield name="INC_BV_COUNT" pos="16" type="boolean"/> 1755 <!-- Increment 16b BR counter. Valid only in BR pipe --> 1756 <bitfield name="INC_BR_COUNT" pos="17" type="boolean"/> 1757 <bitfield name="CLEAR_RENDER_RESOURCE" pos="18" type="boolean"/> 1758 <bitfield name="CLEAR_LRZ_RESOURCE" pos="19" type="boolean"/> 1759 1760 <bitfield name="WRITE_SRC" low="20" high="22" type="event_write_src"/> 1761 <bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/> 1762 <!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. --> 1763 <bitfield name="WRITE_ENABLED" pos="27" type="boolean"/> 1764 <bitfield name="IRQ" pos="31" type="boolean"/> 1765 </reg32> 1766 1767 <stripe varset="event_write_dst" variants="EV_DST_RAM"> 1768 <reg64 offset="1" name="1" type="waddress"/> 1769 <reg32 offset="3" name="3"> 1770 <bitfield name="PAYLOAD_0" low="0" high="31"/> 1771 </reg32> 1772 <reg32 offset="4" name="4"> 1773 <bitfield name="PAYLOAD_1" low="0" high="31"/> 1774 </reg32> 1775 </stripe> 1776 1777 <stripe varset="event_write_dst" variants="EV_DST_ONCHIP"> 1778 <reg32 offset="1" name="1"> 1779 <bitfield name="ONCHIP_ADDR_0" low="0" high="31"/> 1780 </reg32> 1781 <reg32 offset="3" name="3"> 1782 <bitfield name="PAYLOAD_0" low="0" high="31"/> 1783 </reg32> 1784 <reg32 offset="4" name="4"> 1785 <bitfield name="PAYLOAD_1" low="0" high="31"/> 1786 </reg32> 1787 </stripe> 1788</domain> 1789 1790<domain name="CP_BLIT" width="32"> 1791 <enum name="cp_blit_cmd"> 1792 <value value="0" name="BLIT_OP_FILL"/> 1793 <value value="1" name="BLIT_OP_COPY"/> 1794 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation --> 1795 </enum> 1796 <reg32 offset="0" name="0"> 1797 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/> 1798 </reg32> 1799 <reg32 offset="1" name="1"> 1800 <bitfield name="SRC_X1" low="0" high="13" type="uint"/> 1801 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/> 1802 </reg32> 1803 <reg32 offset="2" name="2"> 1804 <bitfield name="SRC_X2" low="0" high="13" type="uint"/> 1805 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/> 1806 </reg32> 1807 <reg32 offset="3" name="3"> 1808 <bitfield name="DST_X1" low="0" high="13" type="uint"/> 1809 <bitfield name="DST_Y1" low="16" high="29" type="uint"/> 1810 </reg32> 1811 <reg32 offset="4" name="4"> 1812 <bitfield name="DST_X2" low="0" high="13" type="uint"/> 1813 <bitfield name="DST_Y2" low="16" high="29" type="uint"/> 1814 </reg32> 1815</domain> 1816 1817<domain name="CP_EXEC_CS" width="32"> 1818 <reg32 offset="0" name="0"> 1819 </reg32> 1820 <reg32 offset="1" name="1"> 1821 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/> 1822 </reg32> 1823 <reg32 offset="2" name="2"> 1824 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/> 1825 </reg32> 1826 <reg32 offset="3" name="3"> 1827 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/> 1828 </reg32> 1829</domain> 1830 1831<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-"> 1832 <reg32 offset="0" name="0"> 1833 </reg32> 1834 <stripe varset="chip" variants="A4XX"> 1835 <reg32 offset="1" name="1"> 1836 <bitfield name="ADDR" low="0" high="31"/> 1837 </reg32> 1838 <reg32 offset="2" name="2"> 1839 <!-- localsize is value minus one: --> 1840 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1841 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1842 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1843 </reg32> 1844 </stripe> 1845 <stripe varset="chip" variants="A5XX-"> 1846 <reg32 offset="1" name="1"> 1847 <bitfield name="ADDR_LO" low="0" high="31"/> 1848 </reg32> 1849 <reg32 offset="2" name="2"> 1850 <bitfield name="ADDR_HI" low="0" high="31"/> 1851 </reg32> 1852 <reg32 offset="3" name="3"> 1853 <!-- localsize is value minus one: --> 1854 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 1855 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 1856 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 1857 </reg32> 1858 </stripe> 1859</domain> 1860 1861<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1862 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc> 1863 <enum name="set_marker_mode"> 1864 <value value="0" name="SET_RENDER_MODE"/> 1865 <!-- IFPC - inter-frame power collapse --> 1866 <value value="1" name="SET_IFPC_MODE"/> 1867 </enum> 1868 <enum name="a6xx_ifpc_mode"> 1869 <value value="0" name="IFPC_ENABLE"/> 1870 <value value="1" name="IFPC_DISABLE"/> 1871 </enum> 1872 <enum name="a6xx_marker"> 1873 <value value="1" name="RM6_DIRECT_RENDER"/> 1874 <value value="2" name="RM6_BIN_VISIBILITY"/> 1875 <value value="3" name="RM6_BIN_DIRECT"/> 1876 <value value="4" name="RM6_BIN_RENDER_START"/> 1877 <value value="5" name="RM6_BIN_END_OF_DRAWS"/> 1878 <value value="6" name="RM6_BIN_RESOLVE"/> 1879 <value value="7" name="RM6_BIN_RENDER_END"/> 1880 <value value="8" name="RM6_COMPUTE"/> 1881 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) --> 1882 1883 <!-- 1884 These values come from a6xx_set_marker() in the 1885 downstream kernel, and they can only be set by the kernel 1886 --> 1887 <value value="0xd" name="RM6_IB1LIST_START"/> 1888 <value value="0xe" name="RM6_IB1LIST_END"/> 1889 </enum> 1890 <reg32 offset="0" name="0"> 1891 <!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) --> 1892 <bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/> 1893 1894 <bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1895 <!-- used by preemption to determine if GMEM needs to be saved or not --> 1896 <bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/> 1897 1898 <bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/> 1899 1900 <!-- 1901 CP_SET_MARKER is used with these bits to create a 1902 critical section around a workaround for ray tracing. 1903 The workaround happens after BVH building, and appears 1904 to invalidate the RTU's BVH node cache. It makes sure 1905 that only one of BR/BV/LPAC is executing the 1906 workaround at a time, and no draws using RT on BV/LPAC 1907 are executing while the workaround is executed on BR (or 1908 vice versa, that no draws on BV/BR using RT are executed 1909 while the workaround executes on LPAC), by 1910 hooking subsequent CP_EVENT_WRITE/CP_DRAW_*/CP_EXEC_CS. 1911 The blob usage is: 1912 1913 CP_SET_MARKER(RT_WA_START) 1914 ... workaround here ... 1915 CP_SET_MARKER(RT_WA_END) 1916 ... 1917 CP_SET_MARKER(SHADER_USES_RT) 1918 CP_DRAW_INDX(...) or CP_EXEC_CS(...) 1919 --> 1920 <bitfield name="SHADER_USES_RT" pos="9" type="boolean" variants="A7XX-"/> 1921 <bitfield name="RT_WA_START" pos="10" type="boolean" variants="A7XX-"/> 1922 <bitfield name="RT_WA_END" pos="11" type="boolean" variants="A7XX-"/> 1923 </reg32> 1924</domain> 1925 1926<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1927 <doc>Set internal CP registers, used to indicate context save data addresses</doc> 1928 <enum name="pseudo_reg"> 1929 <value value="0" name="SMMU_INFO"/> 1930 <value value="1" name="NON_SECURE_SAVE_ADDR"/> 1931 <value value="2" name="SECURE_SAVE_ADDR"/> 1932 <value value="3" name="NON_PRIV_SAVE_ADDR"/> 1933 <value value="4" name="COUNTER"/> 1934 1935 <!-- 1936 On a6xx the registers are set directly and CP_SET_BIN_DATA5_OFFSET reads them, 1937 but that doesn't work with concurrent binning because BR will be reading from 1938 a different set of streams than BV is writing, so on a7xx we have these 1939 pseudo-regs instead, which do the right thing. 1940 1941 The corresponding VSC registers exist, and they're written by BV when it 1942 encounters CP_SET_PSEUDO_REG. When BR later encounters the same CP_SET_PSEUDO_REG 1943 it will only write some private scratch registers which are read by 1944 CP_SET_BIN_DATA5_OFFSET. 1945 1946 If concurrent binning is disabled then BR also does binning so it will also 1947 write the "real" registers in BR. 1948 --> 1949 <value value="8" name="VSC_PIPE_DATA_DRAW_BASE"/> 1950 <value value="9" name="VSC_SIZE_BASE"/> 1951 <value value="10" name="VSC_PIPE_DATA_PRIM_BASE"/> 1952 <value value="11" name="UNK_STRM_ADDRESS"/> 1953 <value value="12" name="UNK_STRM_SIZE_ADDRESS"/> 1954 1955 <value value="16" name="BINDLESS_BASE_0_ADDR"/> 1956 <value value="17" name="BINDLESS_BASE_1_ADDR"/> 1957 <value value="18" name="BINDLESS_BASE_2_ADDR"/> 1958 <value value="19" name="BINDLESS_BASE_3_ADDR"/> 1959 <value value="20" name="BINDLESS_BASE_4_ADDR"/> 1960 <value value="21" name="BINDLESS_BASE_5_ADDR"/> 1961 <value value="22" name="BINDLESS_BASE_6_ADDR"/> 1962 </enum> 1963 <array offset="0" stride="3" length="100"> 1964 <reg32 offset="0" name="0"> 1965 <bitfield name="PSEUDO_REG" low="0" high="10" type="pseudo_reg"/> 1966 </reg32> 1967 <reg32 offset="1" name="1"> 1968 <bitfield name="LO" low="0" high="31"/> 1969 </reg32> 1970 <reg32 offset="2" name="2"> 1971 <bitfield name="HI" low="0" high="31"/> 1972 </reg32> 1973 </array> 1974</domain> 1975 1976<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-"> 1977 <doc> 1978 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC. 1979 So: 1980 1981 opcode: CP_REG_TEST (39) (2 dwords) 1982 { REG = 0xc10 | BIT = 0 } 1983 0000: 70b90001 00000c10 1984 opcode: CP_COND_REG_EXEC (47) (3 dwords) 1985 0000: 70c70002 10000000 00000004 1986 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords) 1987 1988 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at 1989 offset 0x0c10 is 1 1990 </doc> 1991 <enum name="source_type"> 1992 <value value="0" name="SOURCE_REG"/> 1993 <!-- Don't confuse with scratch registers, this is a separate memory 1994 written into by CP_MEM_TO_SCRATCH_MEM. --> 1995 <value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/> 1996 </enum> 1997 <reg32 offset="0" name="0"> 1998 <!-- the register to test --> 1999 <bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/> 2000 <bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATCH_MEM"/> 2001 <bitfield name="SOURCE" pos="18" type="source_type" addvariant="yes"/> 2002 <!-- the bit to test --> 2003 <bitfield name="BIT" low="20" high="24" type="uint"/> 2004 <!-- skip implied CP_WAIT_FOR_ME --> 2005 <bitfield name="SKIP_WAIT_FOR_ME" pos="25" type="boolean"/> 2006 <!-- the predicate bit to set (new in gen3+) --> 2007 <bitfield name="PRED_BIT" low="26" high="30" type="uint"/> 2008 <!-- update the predicate reg directly (new in gen3+) --> 2009 <bitfield name="PRED_UPDATE" pos="31" type="boolean"/> 2010 </reg32> 2011 2012 <!-- 2013 In PRED_UPDATE mode, the predicate reg is updated directly using two 2014 more dwords, ignoring other bits: 2015 2016 PRED_REG = (PRED_REG & ~PRED_MASK) | (PRED_VAL & PRED_MASK); 2017 --> 2018 <reg32 offset="1" name="PRED_MASK" type="hex"/> 2019 <reg32 offset="2" name="PRED_VAL" type="hex"/> 2020</domain> 2021 2022<!-- I *think* this existed at least as far back as a4xx --> 2023<domain name="CP_COND_REG_EXEC" width="32"> 2024 <enum name="compare_mode"> 2025 <!-- use the predicate bit set by CP_REG_TEST --> 2026 <value value="1" name="PRED_TEST"/> 2027 <!-- compare two registers directly for equality --> 2028 <value value="2" name="REG_COMPARE"/> 2029 <!-- test if certain render modes are set via CP_SET_MARKER --> 2030 <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/> 2031 <!-- compare REG0 for equality with immediate --> 2032 <value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/> 2033 <!-- test which of BR/BV are enabled --> 2034 <value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/> 2035 </enum> 2036 <reg32 offset="0" name="0" varset="compare_mode"> 2037 <bitfield name="REG0" low="0" high="17" variants="REG_COMPARE" type="hex"/> 2038 2039 <!-- the predicate bit to test (new in gen3+) --> 2040 <bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST" type="uint"/> 2041 <bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-" type="boolean"/> 2042 <!-- With REG_COMPARE instead of register read from ONCHIP memory --> 2043 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/> 2044 2045 <!-- 2046 Note: these bits have the same meaning, and use the same 2047 internal mechanism as the bits in CP_SET_DRAW_STATE. 2048 When RENDER_MODE is selected, they're used as 2049 a bitmask of which modes pass the test. 2050 --> 2051 2052 <!-- RM6_BIN_VISIBILITY --> 2053 <bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/> 2054 <!-- all others --> 2055 <bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/> 2056 <!-- RM6_DIRECT_RENDER --> 2057 <bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/> 2058 2059 <bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/> 2060 <bitfield name="BR" pos="26" variants="THREAD_MODE" type="boolean"/> 2061 <bitfield name="LPAC" pos="27" variants="THREAD_MODE" type="boolean"/> 2062 2063 <bitfield name="MODE" low="28" high="31" type="compare_mode" addvariant="yes"/> 2064 </reg32> 2065 2066 <stripe varset="compare_mode" variants="PRED_TEST"> 2067 <reg32 offset="1" name="1"> 2068 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 2069 </reg32> 2070 </stripe> 2071 2072 <stripe varset="compare_mode" variants="REG_COMPARE"> 2073 <reg32 offset="1" name="1"> 2074 <bitfield name="REG1" low="0" high="17" type="hex"/> 2075 <!-- Instead of register read from ONCHIP memory --> 2076 <bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/> 2077 </reg32> 2078 </stripe> 2079 2080 <stripe varset="compare_mode" variants="RENDER_MODE"> 2081 <reg32 offset="1" name="1"> 2082 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 2083 </reg32> 2084 </stripe> 2085 2086 <stripe varset="compare_mode" variants="REG_COMPARE_IMM"> 2087 <reg32 offset="1" name="1"> 2088 <bitfield name="IMM" low="0" high="31"/> 2089 </reg32> 2090 </stripe> 2091 2092 <stripe varset="compare_mode" variants="THREAD_MODE"> 2093 <reg32 offset="1" name="1"> 2094 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 2095 </reg32> 2096 </stripe> 2097 2098 <reg32 offset="2" name="2"> 2099 <bitfield name="DWORDS" low="0" high="23" type="uint"/> 2100 </reg32> 2101</domain> 2102 2103<domain name="CP_COND_EXEC" width="32"> 2104 <doc> 2105 Executes the following DWORDs of commands if the dword at ADDR0 2106 is not equal to 0 and the dword at ADDR1 is less than REF 2107 (signed comparison). 2108 </doc> 2109 <reg32 offset="0" name="0"> 2110 <bitfield name="ADDR0_LO" low="0" high="31"/> 2111 </reg32> 2112 <reg32 offset="1" name="1"> 2113 <bitfield name="ADDR0_HI" low="0" high="31"/> 2114 </reg32> 2115 <reg32 offset="2" name="2"> 2116 <bitfield name="ADDR1_LO" low="0" high="31"/> 2117 </reg32> 2118 <reg32 offset="3" name="3"> 2119 <bitfield name="ADDR1_HI" low="0" high="31"/> 2120 </reg32> 2121 <reg32 offset="4" name="4"> 2122 <bitfield name="REF" low="0" high="31"/> 2123 </reg32> 2124 <reg32 offset="5" name="5"> 2125 <bitfield name="DWORDS" low="0" high="31" type="uint"/> 2126 </reg32> 2127</domain> 2128 2129<domain name="CP_SET_AMBLE" width="32"> 2130 <doc> 2131 Used by the userspace and kernel drivers to set various IB's 2132 which are executed during context save/restore for handling 2133 state that isn't restored by the context switch routine itself. 2134 </doc> 2135 <enum name="amble_type"> 2136 <value name="PREAMBLE_AMBLE_TYPE" value="0"> 2137 <doc>Executed unconditionally when switching back to the context.</doc> 2138 </value> 2139 <value name="BIN_PREAMBLE_AMBLE_TYPE" value="1"> 2140 <doc> 2141 Executed when switching back after switching 2142 away during execution of 2143 a CP_SET_MARKER packet with RM6_BIN_RENDER_END as the 2144 payload *and* skipsaverestore is set. This is 2145 expected to restore static register values not 2146 saved when skipsaverestore is set. 2147 </doc> 2148 </value> 2149 <value name="POSTAMBLE_AMBLE_TYPE" value="2"> 2150 <doc> 2151 Executed when switching away from the context, 2152 except for context switches initiated via 2153 CP_YIELD. 2154 </doc> 2155 </value> 2156 <value name="KMD_AMBLE_TYPE" value="3"> 2157 <doc> 2158 This can only be set by the RB (i.e. the kernel) 2159 and executes with protected mode off, but 2160 is otherwise similar to POSTAMBLE_AMBLE_TYPE. 2161 </doc> 2162 </value> 2163 </enum> 2164 <reg32 offset="0" name="0"> 2165 <bitfield name="ADDR_LO" low="0" high="31"/> 2166 </reg32> 2167 <reg32 offset="1" name="1"> 2168 <bitfield name="ADDR_HI" low="0" high="31"/> 2169 </reg32> 2170 <reg32 offset="2" name="2"> 2171 <bitfield name="DWORDS" low="0" high="19" type="uint"/> 2172 <bitfield name="TYPE" low="20" high="21" type="amble_type"/> 2173 </reg32> 2174</domain> 2175 2176<domain name="CP_REG_WRITE" width="32"> 2177 <enum name="reg_tracker"> 2178 <doc> 2179 Keep shadow copies of these registers and only set them 2180 when drawing, avoiding redundant writes: 2181 - VPC_CNTL_0 2182 - HLSQ_CONTROL_1_REG 2183 - HLSQ_UNKNOWN_B980 2184 </doc> 2185 <value name="TRACK_CNTL_REG" value="0x1"/> 2186 <doc> 2187 Track RB_RENDER_CNTL, and insert a WFI in the following 2188 situation: 2189 - There is a write that disables binning 2190 - There was a draw with binning left enabled, but in 2191 BYPASS mode 2192 Presumably this is a hang workaround? 2193 </doc> 2194 <value name="TRACK_RENDER_CNTL" value="0x2"/> 2195 <doc> 2196 Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of 2197 the data to write is 0. Used by the Vulkan blob with 2198 PC_MULTIVIEW_CNTL, but this isn't predicated on particular 2199 register(s) like the others. 2200 </doc> 2201 <value name="UNK_EVENT_WRITE" value="0x4"/> 2202 <doc> 2203 Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and 2204 GRAS_LRZ_VIEW_INFO with previous values, and if one of 2205 the following is true: 2206 - GRAS_LRZ_CNTL::GREATER has changed 2207 - GRAS_LRZ_CNTL::DIR has changed, the old value is not 2208 CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED 2209 - GRAS_LRZ_VIEW_INFO has changed 2210 then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE 2211 forced to 1. 2212 Only exists in a650_sqe.fw. 2213 </doc> 2214 <value name="TRACK_LRZ" value="0x8"/> 2215 </enum> 2216 <reg32 offset="0" name="0"> 2217 <bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/> 2218 </reg32> 2219 <reg32 offset="1" name="1"/> 2220 <reg32 offset="2" name="2"/> 2221</domain> 2222 2223<domain name="CP_SMMU_TABLE_UPDATE" width="32"> 2224 <doc> 2225 Note that the SMMU's definition of TTBRn can take different forms 2226 depending on the pgtable format. But a5xx+ only uses aarch64 2227 format. 2228 </doc> 2229 <reg32 offset="0" name="0"> 2230 <bitfield name="TTBR0_LO" low="0" high="31"/> 2231 </reg32> 2232 <reg32 offset="1" name="1"> 2233 <bitfield name="TTBR0_HI" low="0" high="15"/> 2234 <bitfield name="ASID" low="16" high="31"/> 2235 </reg32> 2236 <reg32 offset="2" name="2"> 2237 <doc>Unused, does not apply to aarch64 pgtable format</doc> 2238 <bitfield name="CONTEXTIDR" low="0" high="31"/> 2239 </reg32> 2240 <reg32 offset="3" name="3"> 2241 <bitfield name="CONTEXTBANK" low="0" high="31"/> 2242 </reg32> 2243</domain> 2244 2245<domain name="CP_START_BIN" width="32"> 2246 <reg32 offset="0" name="BIN_COUNT" type="uint"/> 2247 <reg64 offset="1" name="PREFIX_ADDR" type="address"/> 2248 <reg32 offset="3" name="PREFIX_DWORDS"> 2249 <doc> 2250 Size of prefix for each bin. For each bin index i, the 2251 prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are 2252 executed in an IB2 before the IB1 commands following 2253 this packet. 2254 </doc> 2255 </reg32> 2256 <reg32 offset="4" name="BODY_DWORDS"> 2257 <doc>Number of dwords after this packet until CP_END_BIN</doc> 2258 </reg32> 2259</domain> 2260 2261<domain name="CP_WAIT_TIMESTAMP" width="32"> 2262 <enum name="ts_wait_value_src"> 2263 <!-- Wait for value at memory address to be >= SRC_0 (signed comparison) --> 2264 <value value="0" name="TS_WAIT_GE_32B"/> 2265 <!-- Wait for value at memory address to be >= SRC_0 (unsigned) --> 2266 <value value="1" name="TS_WAIT_GE_64B"/> 2267 <!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) --> 2268 <value value="2" name="TS_WAIT_GE_TIMESTAMP_SUM"/> 2269 </enum> 2270 2271 <enum name="ts_wait_type"> 2272 <value value="0" name="TS_WAIT_RAM"/> 2273 <value value="1" name="TS_WAIT_ONCHIP"/> 2274 </enum> 2275 2276 <reg32 offset="0" name="0"> 2277 <bitfield name="WAIT_VALUE_SRC" low="0" high="1" type="ts_wait_value_src"/> 2278 <bitfield name="WAIT_DST" pos="4" type="ts_wait_type" addvariant="yes"/> 2279 </reg32> 2280 2281 <stripe varset="ts_wait_type" variants="TS_WAIT_RAM"> 2282 <reg64 offset="1" name="ADDR" type="address"/> 2283 </stripe> 2284 2285 <stripe varset="ts_wait_type" variants="TS_WAIT_ONCHIP"> 2286 <reg32 offset="1" name="ONCHIP_ADDR_0" low="0" high="31"/> 2287 </stripe> 2288 2289 <reg32 offset="3" name="SRC_0"/> 2290 <reg32 offset="4" name="SRC_1"/> 2291</domain> 2292 2293<domain name="CP_BV_BR_COUNT_OPS" width="32"> 2294 <enum name="pipe_count_op"> 2295 <value name="PIPE_CLEAR_BV_BR" value="0x1"/> 2296 <value name="PIPE_SET_BR_OFFSET" value="0x2"/> 2297 <!-- Wait until for BV_counter > BR_counter --> 2298 <value name="PIPE_BR_WAIT_FOR_BV" value="0x3"/> 2299 <!-- Wait until (BR_counter + BR_OFFSET) > BV_counter --> 2300 <value name="PIPE_BV_WAIT_FOR_BR" value="0x4"/> 2301 </enum> 2302 <reg32 offset="0" name="0"> 2303 <bitfield name="OP" low="0" high="3" type="pipe_count_op"/> 2304 </reg32> 2305 <reg32 offset="1" name="1"> 2306 <bitfield name="BR_OFFSET" low="0" high="15" type="uint"/> 2307 </reg32> 2308</domain> 2309 2310<domain name="CP_MODIFY_TIMESTAMP" width="32"> 2311 <enum name="timestamp_op"> 2312 <value name="MODIFY_TIMESTAMP_CLEAR" value="0"/> 2313 <value name="MODIFY_TIMESTAMP_ADD_GLOBAL" value="1"/> 2314 <value name="MODIFY_TIMESTAMP_ADD_LOCAL" value="2"/> 2315 </enum> 2316 <reg32 offset="0" name="0"> 2317 <bitfield name="ADD" low="0" high="7" type="uint"/> 2318 <bitfield name="OP" low="28" high="31" type="timestamp_op"/> 2319 </reg32> 2320</domain> 2321 2322<domain name="CP_MEM_TO_SCRATCH_MEM" width="32"> 2323 <doc> 2324 Best guess is that it is a faster way to fetch all the VSC_CHANNEL_VISIBILITY registers 2325 and keep them in a local scratch memory instead of fetching every time 2326 when skipping IBs. 2327 </doc> 2328 <reg32 offset="0" name="0"> 2329 <bitfield name="CNT" low="0" high="5" type="uint"/> 2330 </reg32> 2331 <reg32 offset="1" name="1"> 2332 <doc>Scratch memory size is 48 dwords`</doc> 2333 <bitfield name="OFFSET" low="0" high="5" type="uint"/> 2334 </reg32> 2335 <reg32 offset="2" name="2"> 2336 <bitfield name="SRC" low="0" high="31"/> 2337 </reg32> 2338 <reg32 offset="3" name="3"> 2339 <bitfield name="SRC_HI" low="0" high="31"/> 2340 </reg32> 2341</domain> 2342 2343<domain name="CP_THREAD_CONTROL" width="32"> 2344 <enum name="cp_thread"> 2345 <value name="CP_SET_THREAD_BR" value="1"/> <!-- Render --> 2346 <value name="CP_SET_THREAD_BV" value="2"/> <!-- Visibility --> 2347 <value name="CP_SET_THREAD_BOTH" value="3"/> 2348 </enum> 2349 <reg32 offset="0" name="0"> 2350 <bitfield low="0" high="1" name="THREAD" type="cp_thread"/> 2351 <bitfield pos="27" name="CONCURRENT_BIN_DISABLE" type="boolean"/> 2352 <bitfield pos="31" name="SYNC_THREADS" type="boolean"/> 2353 </reg32> 2354</domain> 2355 2356<domain name="CP_FIXED_STRIDE_DRAW_TABLE" width="32"> 2357 <reg64 offset="0" name="IB_BASE"/> 2358 <reg32 offset="2" name="2"> 2359 <!-- STRIDE * COUNT --> 2360 <bitfield name="IB_SIZE" low="0" high="11"/> 2361 <bitfield name="STRIDE" low="20" high="31"/> 2362 </reg32> 2363 <reg32 offset="3" name="3"> 2364 <bitfield name="COUNT" low="0" high="31"/> 2365 </reg32> 2366</domain> 2367 2368<domain name="CP_RESET_CONTEXT_STATE" width="32"> 2369 <reg32 offset="0" name="0"> 2370 <bitfield name="CLEAR_ON_CHIP_TS" pos="0" type="boolean"/> 2371 <bitfield name="CLEAR_RESOURCE_TABLE" pos="1" type="boolean"/> 2372 <bitfield name="CLEAR_BV_BR_COUNTER" pos="2" type="boolean"/> 2373 <bitfield name="RESET_GLOBAL_LOCAL_TS" pos="3" type="boolean"/> 2374 </reg32> 2375</domain> 2376 2377<domain name="CP_SCOPE_CNTL" width="32"> 2378 <enum name="cp_scope"> 2379 <value value="0" name="INTERRUPTS"/> 2380 </enum> 2381 <reg32 offset="0" name="0"> 2382 <bitfield name="DISABLE_PREEMPTION" pos="0" type="boolean"/> 2383 <bitfield low="28" high="31" name="SCOPE" type="cp_scope"/> 2384 </reg32> 2385</domain> 2386 2387<domain name="CP_INDIRECT_BUFFER" width="32" varset="chip" prefix="chip" variants="A5XX-"> 2388 <reg64 offset="0" name="IB_BASE" type="address"/> 2389 <reg32 offset="2" name="2"> 2390 <bitfield name="IB_SIZE" low="0" high="19"/> 2391 </reg32> 2392</domain> 2393 2394</database> 2395 2396