xref: /linux/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.json (revision 637315cb400eed1dbe721954fea437a61a2d65b2)
1*5442bafdSRob Clark{
2*5442bafdSRob Clark    "chip": "A8XX",
3*5442bafdSRob Clark    "groups": [
4*5442bafdSRob Clark        {
5*5442bafdSRob Clark            "name": "CP",
6*5442bafdSRob Clark            "num": 14,
7*5442bafdSRob Clark            "reserved": [ 0 ],
8*5442bafdSRob Clark            "select": "CP_PERFCTR_CP_SEL",
9*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_CP",
10*5442bafdSRob Clark            "countable_type": "a8xx_cp_perfcounter_select"
11*5442bafdSRob Clark        },
12*5442bafdSRob Clark        {
13*5442bafdSRob Clark            "name": "RBBM",
14*5442bafdSRob Clark            "num": 4,
15*5442bafdSRob Clark            "select": "RBBM_PERFCTR_RBBM_SEL",
16*5442bafdSRob Clark            "slice_select": [ "RBBM_SLICE_PERFCTR_RBBM_SEL" ],
17*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_RBBM",
18*5442bafdSRob Clark            "countable_type": "a8xx_rbbm_perfcounter_select"
19*5442bafdSRob Clark        },
20*5442bafdSRob Clark        {
21*5442bafdSRob Clark            "name": "PC",
22*5442bafdSRob Clark            "pipe": "BR",
23*5442bafdSRob Clark            "num": 8,
24*5442bafdSRob Clark            "select": "PC_PERFCTR_PC_SEL",
25*5442bafdSRob Clark            "slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ],
26*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_PC",
27*5442bafdSRob Clark            "countable_type": "a8xx_pc_perfcounter_select"
28*5442bafdSRob Clark        },
29*5442bafdSRob Clark        {
30*5442bafdSRob Clark            "name": "VFD",
31*5442bafdSRob Clark            "pipe": "BR",
32*5442bafdSRob Clark            "num": 8,
33*5442bafdSRob Clark            "select": "VFD_PERFCTR_VFD_SEL",
34*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_VFD",
35*5442bafdSRob Clark            "countable_type": "a8xx_vfd_perfcounter_select"
36*5442bafdSRob Clark        },
37*5442bafdSRob Clark        {
38*5442bafdSRob Clark            "name": "HLSQ",
39*5442bafdSRob Clark            "pipe": "BR",
40*5442bafdSRob Clark            "num": 6,
41*5442bafdSRob Clark            "select": "SP_PERFCTR_HLSQ_SEL",
42*5442bafdSRob Clark            "slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ],
43*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_HLSQ",
44*5442bafdSRob Clark            "countable_type": "a8xx_hlsq_perfcounter_select"
45*5442bafdSRob Clark        },
46*5442bafdSRob Clark        {
47*5442bafdSRob Clark            "name": "VPC",
48*5442bafdSRob Clark            "pipe": "BR",
49*5442bafdSRob Clark            "num": 6,
50*5442bafdSRob Clark            "select": "VPC_PERFCTR_VPC_SEL",
51*5442bafdSRob Clark            "slice_select": [ "VPC_PERFCTR_VPC_SEL_1", "VPC_PERFCTR_VPC_SEL_2" ],
52*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_VPC",
53*5442bafdSRob Clark            "countable_type": "a8xx_vpc_perfcounter_select"
54*5442bafdSRob Clark        },
55*5442bafdSRob Clark        {
56*5442bafdSRob Clark            "name": "TSE",
57*5442bafdSRob Clark            "pipe": "BR",
58*5442bafdSRob Clark            "num": 4,
59*5442bafdSRob Clark            "select": "GRAS_PERFCTR_TSE_SEL",
60*5442bafdSRob Clark            "slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ],
61*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_TSE",
62*5442bafdSRob Clark            "countable_type": "a8xx_tse_perfcounter_select"
63*5442bafdSRob Clark        },
64*5442bafdSRob Clark        {
65*5442bafdSRob Clark            "name": "RAS",
66*5442bafdSRob Clark            "pipe": "BR",
67*5442bafdSRob Clark            "num": 4,
68*5442bafdSRob Clark            "select": "GRAS_PERFCTR_RAS_SEL",
69*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_RAS",
70*5442bafdSRob Clark            "countable_type": "a8xx_ras_perfcounter_select"
71*5442bafdSRob Clark        },
72*5442bafdSRob Clark        {
73*5442bafdSRob Clark            "name": "UCHE",
74*5442bafdSRob Clark            "num": 24,
75*5442bafdSRob Clark            "select": "UCHE_PERFCTR_UCHE_SEL",
76*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_UCHE",
77*5442bafdSRob Clark            "countable_type": "a8xx_uche_perfcounter_select"
78*5442bafdSRob Clark        },
79*5442bafdSRob Clark        {
80*5442bafdSRob Clark            "name": "TP",
81*5442bafdSRob Clark            "pipe": "BR",
82*5442bafdSRob Clark            "num": 12,
83*5442bafdSRob Clark            "select": "TPL1_PERFCTR_TP_SEL",
84*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_TP",
85*5442bafdSRob Clark            "countable_type": "a8xx_tp_perfcounter_select"
86*5442bafdSRob Clark        },
87*5442bafdSRob Clark        {
88*5442bafdSRob Clark            "name": "SP",
89*5442bafdSRob Clark            "pipe": "BR",
90*5442bafdSRob Clark            "num": 24,
91*5442bafdSRob Clark            "select": "SP_PERFCTR_SP_SEL",
92*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_SP",
93*5442bafdSRob Clark            "countable_type": "a8xx_sp_perfcounter_select"
94*5442bafdSRob Clark        },
95*5442bafdSRob Clark        {
96*5442bafdSRob Clark            "name": "RB",
97*5442bafdSRob Clark            "pipe": "BR",
98*5442bafdSRob Clark            "num": 8,
99*5442bafdSRob Clark            "select": "RB_PERFCTR_RB_SEL",
100*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_RB",
101*5442bafdSRob Clark            "countable_type": "a8xx_rb_perfcounter_select"
102*5442bafdSRob Clark        },
103*5442bafdSRob Clark        {
104*5442bafdSRob Clark            "name": "VSC",
105*5442bafdSRob Clark            "num": 2,
106*5442bafdSRob Clark            "select": "VSC_PERFCTR_VSC_SEL",
107*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_VSC",
108*5442bafdSRob Clark            "countable_type": "a8xx_vsc_perfcounter_select"
109*5442bafdSRob Clark        },
110*5442bafdSRob Clark        {
111*5442bafdSRob Clark            "name": "CCU",
112*5442bafdSRob Clark            "pipe": "BR",
113*5442bafdSRob Clark            "num": 5,
114*5442bafdSRob Clark            "select": "RB_PERFCTR_CCU_SEL",
115*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_CCU",
116*5442bafdSRob Clark            "countable_type": "a8xx_ccu_perfcounter_select"
117*5442bafdSRob Clark        },
118*5442bafdSRob Clark        {
119*5442bafdSRob Clark            "name": "LRZ",
120*5442bafdSRob Clark            "pipe": "BR",
121*5442bafdSRob Clark            "num": 4,
122*5442bafdSRob Clark            "select": "GRAS_PERFCTR_LRZ_SEL",
123*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_LRZ",
124*5442bafdSRob Clark            "countable_type": "a8xx_lrz_perfcounter_select"
125*5442bafdSRob Clark        },
126*5442bafdSRob Clark        {
127*5442bafdSRob Clark            "name": "CMP",
128*5442bafdSRob Clark            "pipe": "BR",
129*5442bafdSRob Clark            "num": 4,
130*5442bafdSRob Clark            "select": "RB_PERFCTR_CMP_SEL",
131*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_CMP",
132*5442bafdSRob Clark            "countable_type": "a8xx_cmp_perfcounter_select"
133*5442bafdSRob Clark        },
134*5442bafdSRob Clark        {
135*5442bafdSRob Clark            "name": "UFC",
136*5442bafdSRob Clark            "pipe": "BR",
137*5442bafdSRob Clark            "num": 4,
138*5442bafdSRob Clark            "select": "RB_PERFCTR_UFC_SEL",
139*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_UFC",
140*5442bafdSRob Clark            "countable_type": "a8xx_ufc_perfcounter_select"
141*5442bafdSRob Clark        },
142*5442bafdSRob Clark        {
143*5442bafdSRob Clark            "name": "BV_CP",
144*5442bafdSRob Clark            "num": 7,
145*5442bafdSRob Clark            "select_offset": 14,
146*5442bafdSRob Clark            "select": "CP_PERFCTR_CP_SEL",
147*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_CP",
148*5442bafdSRob Clark            "countable_type": "a8xx_cp_perfcounter_select"
149*5442bafdSRob Clark        },
150*5442bafdSRob Clark        {
151*5442bafdSRob Clark            "name": "BV_PC",
152*5442bafdSRob Clark            "pipe": "BV",
153*5442bafdSRob Clark            "num": 8,
154*5442bafdSRob Clark            "select_offset": 8,
155*5442bafdSRob Clark            "select": "PC_PERFCTR_PC_SEL",
156*5442bafdSRob Clark            "slice_select": [ "PC_SLICE_PERFCTR_PC_SEL" ],
157*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_PC",
158*5442bafdSRob Clark            "countable_type": "a8xx_pc_perfcounter_select"
159*5442bafdSRob Clark        },
160*5442bafdSRob Clark        {
161*5442bafdSRob Clark            "name": "BV_VFD",
162*5442bafdSRob Clark            "pipe": "BV",
163*5442bafdSRob Clark            "num": 8,
164*5442bafdSRob Clark            "select_offset": 8,
165*5442bafdSRob Clark            "select": "VFD_PERFCTR_VFD_SEL",
166*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_VFD",
167*5442bafdSRob Clark            "countable_type": "a8xx_vfd_perfcounter_select"
168*5442bafdSRob Clark        },
169*5442bafdSRob Clark        {
170*5442bafdSRob Clark            "name": "BV_VPC",
171*5442bafdSRob Clark            "pipe": "BV",
172*5442bafdSRob Clark            "num": 6,
173*5442bafdSRob Clark            "select_offset": 6,
174*5442bafdSRob Clark            "select": "VPC_PERFCTR_VPC_SEL",
175*5442bafdSRob Clark            "slice_select": [ "VPC_PERFCTR_VPC_SEL_1", "VPC_PERFCTR_VPC_SEL_2" ],
176*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_VPC",
177*5442bafdSRob Clark            "countable_type": "a8xx_vpc_perfcounter_select"
178*5442bafdSRob Clark        },
179*5442bafdSRob Clark        {
180*5442bafdSRob Clark            "name": "BV_TP",
181*5442bafdSRob Clark            "pipe": "BV",
182*5442bafdSRob Clark            "num": 8,
183*5442bafdSRob Clark            "select_offset": 12,
184*5442bafdSRob Clark            "select": "TPL1_PERFCTR_TP_SEL",
185*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_TP",
186*5442bafdSRob Clark            "countable_type": "a8xx_tp_perfcounter_select"
187*5442bafdSRob Clark        },
188*5442bafdSRob Clark        {
189*5442bafdSRob Clark            "name": "BV_SP",
190*5442bafdSRob Clark            "pipe": "BV",
191*5442bafdSRob Clark            "num": 12,
192*5442bafdSRob Clark            "select_offset": 24,
193*5442bafdSRob Clark            "select": "SP_PERFCTR_SP_SEL",
194*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_SP",
195*5442bafdSRob Clark            "countable_type": "a8xx_sp_perfcounter_select"
196*5442bafdSRob Clark        },
197*5442bafdSRob Clark        {
198*5442bafdSRob Clark            "name": "BV_UFC",
199*5442bafdSRob Clark            "pipe": "BV",
200*5442bafdSRob Clark            "num": 2,
201*5442bafdSRob Clark            "select_offset": 4,
202*5442bafdSRob Clark            "select": "RB_PERFCTR_UFC_SEL",
203*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_UFC",
204*5442bafdSRob Clark            "countable_type": "a8xx_ufc_perfcounter_select"
205*5442bafdSRob Clark        },
206*5442bafdSRob Clark        {
207*5442bafdSRob Clark            "name": "BV_TSE",
208*5442bafdSRob Clark            "pipe": "BV",
209*5442bafdSRob Clark            "num": 4,
210*5442bafdSRob Clark            "select": "GRAS_PERFCTR_TSE_SEL",
211*5442bafdSRob Clark            "slice_select": [ "GRAS_PERFCTR_TSEFE_SEL" ],
212*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_TSE",
213*5442bafdSRob Clark            "countable_type": "a8xx_tse_perfcounter_select"
214*5442bafdSRob Clark        },
215*5442bafdSRob Clark        {
216*5442bafdSRob Clark            "name": "BV_RAS",
217*5442bafdSRob Clark            "pipe": "BV",
218*5442bafdSRob Clark            "num": 4,
219*5442bafdSRob Clark            "select": "GRAS_PERFCTR_RAS_SEL",
220*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_RAS",
221*5442bafdSRob Clark            "countable_type": "a8xx_ras_perfcounter_select"
222*5442bafdSRob Clark        },
223*5442bafdSRob Clark        {
224*5442bafdSRob Clark            "name": "BV_LRZ",
225*5442bafdSRob Clark            "pipe": "BV",
226*5442bafdSRob Clark            "num": 4,
227*5442bafdSRob Clark            "select": "GRAS_PERFCTR_LRZ_SEL",
228*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_LRZ",
229*5442bafdSRob Clark            "countable_type": "a8xx_lrz_perfcounter_select"
230*5442bafdSRob Clark        },
231*5442bafdSRob Clark        {
232*5442bafdSRob Clark            "name": "BV_HLSQ",
233*5442bafdSRob Clark            "pipe": "BV",
234*5442bafdSRob Clark            "num": 6,
235*5442bafdSRob Clark            "select": "SP_PERFCTR_HLSQ_SEL",
236*5442bafdSRob Clark            "slice_select": [ "SP_PERFCTR_HLSQ_SEL_2" ],
237*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_HLSQ",
238*5442bafdSRob Clark            "countable_type": "a8xx_hlsq_perfcounter_select"
239*5442bafdSRob Clark        }
240*5442bafdSRob Clark    ]
241*5442bafdSRob Clark}
242