xref: /linux/drivers/gpu/drm/msm/registers/adreno/a7xx_perfcntrs.json (revision 637315cb400eed1dbe721954fea437a61a2d65b2) 
1*5442bafdSRob Clark{
2*5442bafdSRob Clark    "chip": "A7XX",
3*5442bafdSRob Clark    "groups": [
4*5442bafdSRob Clark        {
5*5442bafdSRob Clark            "name": "CP",
6*5442bafdSRob Clark            "num": 14,
7*5442bafdSRob Clark            "reserved": [ 0 ],
8*5442bafdSRob Clark            "select": "CP_PERFCTR_CP_SEL",
9*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_CP",
10*5442bafdSRob Clark            "countable_type": "a7xx_cp_perfcounter_select"
11*5442bafdSRob Clark        },
12*5442bafdSRob Clark        {
13*5442bafdSRob Clark            "name": "RBBM",
14*5442bafdSRob Clark            "num": 4,
15*5442bafdSRob Clark            "select": "RBBM_PERFCTR_RBBM_SEL",
16*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_RBBM",
17*5442bafdSRob Clark            "countable_type": "a7xx_rbbm_perfcounter_select"
18*5442bafdSRob Clark        },
19*5442bafdSRob Clark        {
20*5442bafdSRob Clark            "name": "PC",
21*5442bafdSRob Clark            "pipe": "BR",
22*5442bafdSRob Clark            "num": 8,
23*5442bafdSRob Clark            "select": "PC_PERFCTR_PC_SEL",
24*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_PC",
25*5442bafdSRob Clark            "countable_type": "a7xx_pc_perfcounter_select"
26*5442bafdSRob Clark        },
27*5442bafdSRob Clark        {
28*5442bafdSRob Clark            "name": "VFD",
29*5442bafdSRob Clark            "pipe": "BR",
30*5442bafdSRob Clark            "num": 8,
31*5442bafdSRob Clark            "select": "VFD_PERFCTR_VFD_SEL",
32*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_VFD",
33*5442bafdSRob Clark            "countable_type": "a7xx_vfd_perfcounter_select"
34*5442bafdSRob Clark        },
35*5442bafdSRob Clark        {
36*5442bafdSRob Clark            "name": "HLSQ",
37*5442bafdSRob Clark            "pipe": "BR",
38*5442bafdSRob Clark            "num": 6,
39*5442bafdSRob Clark            "select": "SP_PERFCTR_HLSQ_SEL",
40*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_HLSQ",
41*5442bafdSRob Clark            "countable_type": "a7xx_hlsq_perfcounter_select"
42*5442bafdSRob Clark        },
43*5442bafdSRob Clark        {
44*5442bafdSRob Clark            "name": "VPC",
45*5442bafdSRob Clark            "pipe": "BR",
46*5442bafdSRob Clark            "num": 6,
47*5442bafdSRob Clark            "select": "VPC_PERFCTR_VPC_SEL",
48*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_VPC",
49*5442bafdSRob Clark            "countable_type": "a7xx_vpc_perfcounter_select"
50*5442bafdSRob Clark        },
51*5442bafdSRob Clark        {
52*5442bafdSRob Clark            "name": "TSE",
53*5442bafdSRob Clark            "pipe": "BR",
54*5442bafdSRob Clark            "num": 4,
55*5442bafdSRob Clark            "select": "GRAS_PERFCTR_TSE_SEL",
56*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_TSE",
57*5442bafdSRob Clark            "countable_type": "a7xx_tse_perfcounter_select"
58*5442bafdSRob Clark        },
59*5442bafdSRob Clark        {
60*5442bafdSRob Clark            "name": "RAS",
61*5442bafdSRob Clark            "pipe": "BR",
62*5442bafdSRob Clark            "num": 4,
63*5442bafdSRob Clark            "select": "GRAS_PERFCTR_RAS_SEL",
64*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_RAS",
65*5442bafdSRob Clark            "countable_type": "a7xx_ras_perfcounter_select"
66*5442bafdSRob Clark        },
67*5442bafdSRob Clark        {
68*5442bafdSRob Clark            "name": "UCHE",
69*5442bafdSRob Clark            "num": 12,
70*5442bafdSRob Clark            "select": "UCHE_PERFCTR_UCHE_SEL",
71*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_UCHE",
72*5442bafdSRob Clark            "countable_type": "a7xx_uche_perfcounter_select"
73*5442bafdSRob Clark        },
74*5442bafdSRob Clark        {
75*5442bafdSRob Clark            "name": "TP",
76*5442bafdSRob Clark            "pipe": "BR",
77*5442bafdSRob Clark            "num": 12,
78*5442bafdSRob Clark            "select": "TPL1_PERFCTR_TP_SEL",
79*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_TP",
80*5442bafdSRob Clark            "countable_type": "a7xx_tp_perfcounter_select"
81*5442bafdSRob Clark        },
82*5442bafdSRob Clark        {
83*5442bafdSRob Clark            "name": "SP",
84*5442bafdSRob Clark            "pipe": "BR",
85*5442bafdSRob Clark            "num": 24,
86*5442bafdSRob Clark            "select": "SP_PERFCTR_SP_SEL",
87*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_SP",
88*5442bafdSRob Clark            "countable_type": "a7xx_sp_perfcounter_select"
89*5442bafdSRob Clark        },
90*5442bafdSRob Clark        {
91*5442bafdSRob Clark            "name": "RB",
92*5442bafdSRob Clark            "num": 8,
93*5442bafdSRob Clark            "select": "RB_PERFCTR_RB_SEL",
94*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_RB",
95*5442bafdSRob Clark            "countable_type": "a7xx_rb_perfcounter_select"
96*5442bafdSRob Clark        },
97*5442bafdSRob Clark        {
98*5442bafdSRob Clark            "name": "VSC",
99*5442bafdSRob Clark            "num": 2,
100*5442bafdSRob Clark            "select": "VSC_PERFCTR_VSC_SEL",
101*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_VSC",
102*5442bafdSRob Clark            "countable_type": "a7xx_vsc_perfcounter_select"
103*5442bafdSRob Clark        },
104*5442bafdSRob Clark        {
105*5442bafdSRob Clark            "name": "CCU",
106*5442bafdSRob Clark            "num": 5,
107*5442bafdSRob Clark            "select": "RB_PERFCTR_CCU_SEL",
108*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_CCU",
109*5442bafdSRob Clark            "countable_type": "a7xx_ccu_perfcounter_select"
110*5442bafdSRob Clark        },
111*5442bafdSRob Clark        {
112*5442bafdSRob Clark            "name": "LRZ",
113*5442bafdSRob Clark            "pipe": "BR",
114*5442bafdSRob Clark            "num": 4,
115*5442bafdSRob Clark            "select": "GRAS_PERFCTR_LRZ_SEL",
116*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_LRZ",
117*5442bafdSRob Clark            "countable_type": "a7xx_lrz_perfcounter_select"
118*5442bafdSRob Clark        },
119*5442bafdSRob Clark        {
120*5442bafdSRob Clark            "name": "CMP",
121*5442bafdSRob Clark            "num": 4,
122*5442bafdSRob Clark            "select": "RB_PERFCTR_CMP_SEL",
123*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_CMP",
124*5442bafdSRob Clark            "countable_type": "a7xx_cmp_perfcounter_select"
125*5442bafdSRob Clark        },
126*5442bafdSRob Clark        {
127*5442bafdSRob Clark            "name": "UFC",
128*5442bafdSRob Clark            "pipe": "BR",
129*5442bafdSRob Clark            "num": 4,
130*5442bafdSRob Clark            "select": "RB_PERFCTR_UFC_SEL",
131*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_UFC",
132*5442bafdSRob Clark            "countable_type": "a7xx_ufc_perfcounter_select"
133*5442bafdSRob Clark        },
134*5442bafdSRob Clark        {
135*5442bafdSRob Clark            "name": "BV_CP",
136*5442bafdSRob Clark            "num": 7,
137*5442bafdSRob Clark            "select": "CP_BV_PERFCTR_CP_SEL",
138*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_CP",
139*5442bafdSRob Clark            "countable_type": "a7xx_cp_perfcounter_select"
140*5442bafdSRob Clark        },
141*5442bafdSRob Clark        {
142*5442bafdSRob Clark            "name": "BV_PC",
143*5442bafdSRob Clark            "pipe": "BV",
144*5442bafdSRob Clark            "num": 8,
145*5442bafdSRob Clark            "select_offset": 8,
146*5442bafdSRob Clark            "select": "PC_PERFCTR_PC_SEL",
147*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_PC",
148*5442bafdSRob Clark            "countable_type": "a7xx_pc_perfcounter_select"
149*5442bafdSRob Clark        },
150*5442bafdSRob Clark        {
151*5442bafdSRob Clark            "name": "BV_VFD",
152*5442bafdSRob Clark            "pipe": "BV",
153*5442bafdSRob Clark            "num": 8,
154*5442bafdSRob Clark            "select_offset": 8,
155*5442bafdSRob Clark            "select": "VFD_PERFCTR_VFD_SEL",
156*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_VFD",
157*5442bafdSRob Clark            "countable_type": "a7xx_vfd_perfcounter_select"
158*5442bafdSRob Clark        },
159*5442bafdSRob Clark        {
160*5442bafdSRob Clark            "name": "BV_VPC",
161*5442bafdSRob Clark            "pipe": "BV",
162*5442bafdSRob Clark            "num": 6,
163*5442bafdSRob Clark            "select_offset": 6,
164*5442bafdSRob Clark            "select": "VPC_PERFCTR_VPC_SEL",
165*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_VPC",
166*5442bafdSRob Clark            "countable_type": "a7xx_vpc_perfcounter_select"
167*5442bafdSRob Clark        },
168*5442bafdSRob Clark        {
169*5442bafdSRob Clark            "name": "BV_TP",
170*5442bafdSRob Clark            "pipe": "BV",
171*5442bafdSRob Clark            "num": 6,
172*5442bafdSRob Clark            "select_offset": 12,
173*5442bafdSRob Clark            "select": "TPL1_PERFCTR_TP_SEL",
174*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_TP",
175*5442bafdSRob Clark            "countable_type": "a7xx_tp_perfcounter_select"
176*5442bafdSRob Clark        },
177*5442bafdSRob Clark        {
178*5442bafdSRob Clark            "name": "BV_SP",
179*5442bafdSRob Clark            "pipe": "BV",
180*5442bafdSRob Clark            "num": 12,
181*5442bafdSRob Clark            "select_offset": 24,
182*5442bafdSRob Clark            "select": "SP_PERFCTR_SP_SEL",
183*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_SP",
184*5442bafdSRob Clark            "countable_type": "a7xx_sp_perfcounter_select"
185*5442bafdSRob Clark        },
186*5442bafdSRob Clark        {
187*5442bafdSRob Clark            "name": "BV_UFC",
188*5442bafdSRob Clark            "pipe": "BV",
189*5442bafdSRob Clark            "num": 2,
190*5442bafdSRob Clark            "select_offset": 4,
191*5442bafdSRob Clark            "select": "RB_PERFCTR_UFC_SEL",
192*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_UFC",
193*5442bafdSRob Clark            "countable_type": "a7xx_ufc_perfcounter_select"
194*5442bafdSRob Clark        },
195*5442bafdSRob Clark        {
196*5442bafdSRob Clark            "name": "BV_TSE",
197*5442bafdSRob Clark            "pipe": "BV",
198*5442bafdSRob Clark            "num": 4,
199*5442bafdSRob Clark            "select": "GRAS_PERFCTR_TSE_SEL",
200*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_TSE",
201*5442bafdSRob Clark            "countable_type": "a7xx_tse_perfcounter_select"
202*5442bafdSRob Clark        },
203*5442bafdSRob Clark        {
204*5442bafdSRob Clark            "name": "BV_RAS",
205*5442bafdSRob Clark            "pipe": "BV",
206*5442bafdSRob Clark            "num": 4,
207*5442bafdSRob Clark            "select": "GRAS_PERFCTR_RAS_SEL",
208*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_RAS",
209*5442bafdSRob Clark            "countable_type": "a7xx_ras_perfcounter_select"
210*5442bafdSRob Clark        },
211*5442bafdSRob Clark        {
212*5442bafdSRob Clark            "name": "BV_LRZ",
213*5442bafdSRob Clark            "pipe": "BV",
214*5442bafdSRob Clark            "num": 4,
215*5442bafdSRob Clark            "select": "GRAS_PERFCTR_LRZ_SEL",
216*5442bafdSRob Clark            "counter": "RBBM_PERFCTR_BV_LRZ",
217*5442bafdSRob Clark            "countable_type": "a7xx_lrz_perfcounter_select"
218*5442bafdSRob Clark        },
219*5442bafdSRob Clark        {
220*5442bafdSRob Clark            "name": "BV_HLSQ",
221*5442bafdSRob Clark            "pipe": "BV",
222*5442bafdSRob Clark            "num": 6,
223*5442bafdSRob Clark            "select": "SP_PERFCTR_HLSQ_SEL",
224*5442bafdSRob Clark            "counter": "RBBM_PERFCTR2_HLSQ",
225*5442bafdSRob Clark            "countable_type": "a7xx_hlsq_perfcounter_select"
226*5442bafdSRob Clark        }
227*5442bafdSRob Clark    ]
228*5442bafdSRob Clark}
229