1*5442bafdSRob Clark{ 2*5442bafdSRob Clark "chip": "A6XX", 3*5442bafdSRob Clark "groups": [ 4*5442bafdSRob Clark { 5*5442bafdSRob Clark "name": "CP", 6*5442bafdSRob Clark "num": 14, 7*5442bafdSRob Clark "reserved": [ 0 ], 8*5442bafdSRob Clark "select": "CP_PERFCTR_CP_SEL", 9*5442bafdSRob Clark "counter": "RBBM_PERFCTR_CP", 10*5442bafdSRob Clark "countable_type": "a6xx_cp_perfcounter_select" 11*5442bafdSRob Clark }, 12*5442bafdSRob Clark { 13*5442bafdSRob Clark "name": "CCU", 14*5442bafdSRob Clark "num": 5, 15*5442bafdSRob Clark "select": "RB_PERFCTR_CCU_SEL", 16*5442bafdSRob Clark "counter": "RBBM_PERFCTR_CCU", 17*5442bafdSRob Clark "countable_type": "a6xx_ccu_perfcounter_select" 18*5442bafdSRob Clark }, 19*5442bafdSRob Clark { 20*5442bafdSRob Clark "name": "TSE", 21*5442bafdSRob Clark "num": 4, 22*5442bafdSRob Clark "select": "GRAS_PERFCTR_TSE_SEL", 23*5442bafdSRob Clark "counter": "RBBM_PERFCTR_TSE", 24*5442bafdSRob Clark "countable_type": "a6xx_tse_perfcounter_select" 25*5442bafdSRob Clark }, 26*5442bafdSRob Clark { 27*5442bafdSRob Clark "name": "RAS", 28*5442bafdSRob Clark "num": 4, 29*5442bafdSRob Clark "select": "GRAS_PERFCTR_RAS_SEL", 30*5442bafdSRob Clark "counter": "RBBM_PERFCTR_RAS", 31*5442bafdSRob Clark "countable_type": "a6xx_ras_perfcounter_select" 32*5442bafdSRob Clark }, 33*5442bafdSRob Clark { 34*5442bafdSRob Clark "name": "LRZ", 35*5442bafdSRob Clark "num": 4, 36*5442bafdSRob Clark "select": "GRAS_PERFCTR_LRZ_SEL", 37*5442bafdSRob Clark "counter": "RBBM_PERFCTR_LRZ", 38*5442bafdSRob Clark "countable_type": "a6xx_lrz_perfcounter_select" 39*5442bafdSRob Clark }, 40*5442bafdSRob Clark { 41*5442bafdSRob Clark "name": "CMP", 42*5442bafdSRob Clark "num": 4, 43*5442bafdSRob Clark "select": "RB_PERFCTR_CMP_SEL", 44*5442bafdSRob Clark "counter": "RBBM_PERFCTR_CMP", 45*5442bafdSRob Clark "countable_type": "a6xx_cmp_perfcounter_select" 46*5442bafdSRob Clark }, 47*5442bafdSRob Clark { 48*5442bafdSRob Clark "name": "HLSQ", 49*5442bafdSRob Clark "num": 6, 50*5442bafdSRob Clark "select": "HLSQ_PERFCTR_HLSQ_SEL", 51*5442bafdSRob Clark "counter": "RBBM_PERFCTR_HLSQ", 52*5442bafdSRob Clark "countable_type": "a6xx_hlsq_perfcounter_select" 53*5442bafdSRob Clark }, 54*5442bafdSRob Clark { 55*5442bafdSRob Clark "name": "PC", 56*5442bafdSRob Clark "num": 8, 57*5442bafdSRob Clark "select": "PC_PERFCTR_PC_SEL", 58*5442bafdSRob Clark "counter": "RBBM_PERFCTR_PC", 59*5442bafdSRob Clark "countable_type": "a6xx_pc_perfcounter_select" 60*5442bafdSRob Clark }, 61*5442bafdSRob Clark { 62*5442bafdSRob Clark "name": "RB", 63*5442bafdSRob Clark "num": 8, 64*5442bafdSRob Clark "select": "RB_PERFCTR_RB_SEL", 65*5442bafdSRob Clark "counter": "RBBM_PERFCTR_RB", 66*5442bafdSRob Clark "countable_type": "a6xx_rb_perfcounter_select" 67*5442bafdSRob Clark }, 68*5442bafdSRob Clark { 69*5442bafdSRob Clark "name": "SP", 70*5442bafdSRob Clark "num": 24, 71*5442bafdSRob Clark "reserved": [ 0 ], 72*5442bafdSRob Clark "select": "SP_PERFCTR_SP_SEL", 73*5442bafdSRob Clark "counter": "RBBM_PERFCTR_SP", 74*5442bafdSRob Clark "countable_type": "a6xx_sp_perfcounter_select" 75*5442bafdSRob Clark }, 76*5442bafdSRob Clark { 77*5442bafdSRob Clark "name": "TP", 78*5442bafdSRob Clark "num": 12, 79*5442bafdSRob Clark "select": "TPL1_PERFCTR_TP_SEL", 80*5442bafdSRob Clark "counter": "RBBM_PERFCTR_TP", 81*5442bafdSRob Clark "countable_type": "a6xx_tp_perfcounter_select" 82*5442bafdSRob Clark }, 83*5442bafdSRob Clark { 84*5442bafdSRob Clark "name": "UCHE", 85*5442bafdSRob Clark "num": 12, 86*5442bafdSRob Clark "select": "UCHE_PERFCTR_UCHE_SEL", 87*5442bafdSRob Clark "counter": "RBBM_PERFCTR_UCHE", 88*5442bafdSRob Clark "countable_type": "a6xx_uche_perfcounter_select" 89*5442bafdSRob Clark }, 90*5442bafdSRob Clark { 91*5442bafdSRob Clark "name": "VFD", 92*5442bafdSRob Clark "num": 8, 93*5442bafdSRob Clark "select": "VFD_PERFCTR_VFD_SEL", 94*5442bafdSRob Clark "counter": "RBBM_PERFCTR_VFD", 95*5442bafdSRob Clark "countable_type": "a6xx_vfd_perfcounter_select" 96*5442bafdSRob Clark }, 97*5442bafdSRob Clark { 98*5442bafdSRob Clark "name": "VPC", 99*5442bafdSRob Clark "num": 6, 100*5442bafdSRob Clark "select": "VPC_PERFCTR_VPC_SEL", 101*5442bafdSRob Clark "counter": "RBBM_PERFCTR_VPC", 102*5442bafdSRob Clark "countable_type": "a6xx_vpc_perfcounter_select" 103*5442bafdSRob Clark }, 104*5442bafdSRob Clark { 105*5442bafdSRob Clark "name": "VSC", 106*5442bafdSRob Clark "num": 2, 107*5442bafdSRob Clark "select": "VSC_PERFCTR_VSC_SEL", 108*5442bafdSRob Clark "counter": "RBBM_PERFCTR_VSC", 109*5442bafdSRob Clark "countable_type": "a6xx_vsc_perfcounter_select" 110*5442bafdSRob Clark } 111*5442bafdSRob Clark ] 112*5442bafdSRob Clark} 113