1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7<import file="adreno/adreno_pm4.xml"/> 8<import file="adreno/a6xx_enums.xml"/> 9<import file="adreno/a7xx_enums.xml"/> 10<import file="adreno/a8xx_enums.xml"/> 11<import file="adreno/a6xx_perfcntrs.xml"/> 12<import file="adreno/a7xx_perfcntrs.xml"/> 13<import file="adreno/a6xx_descriptors.xml"/> 14<import file="adreno/a8xx_descriptors.xml"/> 15 16<!-- 17Each register that is actually being used by driver should have "usage" defined, 18currently there are following usages: 19- "cmd" - the register is used outside of renderpass and blits, 20 roughly corresponds to registers used in ib1 for Freedreno 21- "rp_blit" - the register is used inside renderpass or blits 22 (ib2 for Freedreno) 23 24It is expected that register with "cmd" usage may be written into only at 25the start of the command buffer (ib1), while "rp_blit" usage indicates that register 26is either overwritten by renderpass/blit (ib2) or not used if not overwritten 27by a particular renderpass/blit. 28--> 29 30<domain name="A6XX" width="32" prefix="variant" varset="chip"> 31 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip"> 32 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/> 33 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/> 34 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/> 35 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/> 36 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/> 37 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/> 38 <bitfield name="CP_SW" pos="8" type="boolean"/> 39 <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/> 40 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/> 41 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/> 42 <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/> 43 <bitfield name="CP_IB2" pos="13" type="boolean"/> 44 <bitfield name="CP_IB1" pos="14" type="boolean"/> 45 <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/> 46 <!-- Same as above but different name??: --> 47 <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/> 48 <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/> 49 <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/> 50 <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/> 51 <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/> 52 <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/> 53 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/> 54 <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/> 55 <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/> 56 <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/> 57 <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/> 58 <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/> 59 <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/> 60 <bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/> 61 <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/> 62 <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/> 63 </bitset> 64 65 <!-- 66 Note the _LPAC bits probably *actually* first appeared in a660, but the 67 _BV bits are new in a7xx 68 --> 69 <bitset name="A6XX_CP_INT" varset="chip"> 70 <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/> 71 <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/> 72 <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/> 73 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/> 74 <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/> 75 <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/> 76 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/> 77 <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/> 78 <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/> 79 <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/> 80 <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/> 81 <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/> 82 <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/> 83 <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/> 84 <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/> 85 <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/> 86 <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/> 87 </bitset> 88 89 <bitset name="A8XX_CP_GLOBAL_INT_MASK" inline="no" varset="chip"> 90 <bitfield name="HWFAULTBR" pos="0" type="boolean"/> 91 <bitfield name="HWFAULTBV" pos="1" type="boolean"/> 92 <bitfield name="HWFAULTLPAC" pos="2" type="boolean"/> 93 <bitfield name="HWFAULTAQE0" pos="3" type="boolean"/> 94 <bitfield name="HWFAULTAQE1" pos="4" type="boolean"/> 95 <bitfield name="HWFAULTDDEBR" pos="5" type="boolean"/> 96 <bitfield name="HWFAULTDDEBV" pos="6" type="boolean"/> 97 <bitfield name="SWFAULTBR" pos="16" type="boolean"/> 98 <bitfield name="SWFAULTBV" pos="17" type="boolean"/> 99 <bitfield name="SWFAULTLPAC" pos="18" type="boolean"/> 100 <bitfield name="SWFAULTAQE0" pos="19" type="boolean"/> 101 <bitfield name="SWFAULTAQE1" pos="20" type="boolean"/> 102 <bitfield name="SWFAULTDDEBR" pos="21" type="boolean"/> 103 <bitfield name="SWFAULTDDEBV" pos="22" type="boolean"/> 104 </bitset> 105 106 <bitset name="A8XX_CP_INTERRUPT_STATUS_MASK_PIPE" inline="no" varset="chip"> 107 <bitfield name="CSFRBWRAP" pos="0" type="boolean"/> 108 <bitfield name="CSFIB1WRAP" pos="1" type="boolean"/> 109 <bitfield name="CSFIB2WRAP" pos="2" type="boolean"/> 110 <bitfield name="CSFIB3WRAP" pos="3" type="boolean"/> 111 <bitfield name="CSFSDSWRAP" pos="4" type="boolean"/> 112 <bitfield name="CSFMRBWRAP" pos="5" type="boolean"/> 113 <bitfield name="CSFVSDWRAP" pos="6" type="boolean"/> 114 <bitfield name="OPCODEERROR" pos="8" type="boolean"/> 115 <bitfield name="VSDPARITYERROR" pos="9" type="boolean"/> 116 <bitfield name="REGISTERPROTECTIONERROR" pos="10" type="boolean"/> 117 <bitfield name="ILLEGALINSTRUCTION" pos="11" type="boolean"/> 118 <bitfield name="SMMUFAULT" pos="12" type="boolean"/> 119 <bitfield name="VBIFRESPCLIENT" pos="13" type="boolean"/> 120 <bitfield name="VBIFRESPTYPE" pos="19" type="boolean"/> 121 <bitfield name="VBIFRESPREAD" pos="21" type="boolean"/> 122 <bitfield name="VBIFRESP" pos="22" type="boolean"/> 123 <bitfield name="RTWROVF" pos="23" type="boolean"/> 124 <bitfield name="LRZRTWROVF" pos="24" type="boolean"/> 125 <bitfield name="LRZRTREFCNTOVF" pos="25" type="boolean"/> 126 <bitfield name="LRZRTCLRRESMISS" pos="26" type="boolean"/> 127 </bitset> 128 129 <bitset name="A8XX_CP_HW_FAULT_STATUS_MASK_PIPE" inline="no" varset="chip"> 130 <bitfield name="CSFRBFAULT" pos="0" type="boolean"/> 131 <bitfield name="CSFIB1FAULT" pos="1" type="boolean"/> 132 <bitfield name="CSFIB2FAULT" pos="2" type="boolean"/> 133 <bitfield name="CSFIB3FAULT" pos="3" type="boolean"/> 134 <bitfield name="CSFSDSFAULT" pos="4" type="boolean"/> 135 <bitfield name="CSFMRBFAULT" pos="5" type="boolean"/> 136 <bitfield name="CSFVSDFAULT" pos="6" type="boolean"/> 137 <bitfield name="SQEREADBURSTOVF" pos="8" type="boolean"/> 138 <bitfield name="EVENTENGINEOVF" pos="9" type="boolean"/> 139 <bitfield name="UCODEERROR" pos="10" type="boolean"/> 140 </bitset> 141 142 <reg64 offset="0x0800" name="CP_RB_BASE"/> 143 <reg32 offset="0x0802" name="CP_RB_CNTL"/> 144 <reg32 offset="0x0803" name="CP_RB_RPTR_WR" variants="A7XX-"/> 145 <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/> 146 <reg32 offset="0x0806" name="CP_RB_RPTR"/> 147 <reg32 offset="0x0807" name="CP_RB_WPTR"/> 148 <reg32 offset="0x0808" name="CP_RB_RPTR_ADDR_BV" variants="A8XX-"/> 149 <reg32 offset="0x080a" name="CP_RB_RPTR_BV" variants="A8XX-"/> 150 <reg64 offset="0x080b" name="CP_RB_BASE_LPAC" variants="A8XX-"/> 151 <reg32 offset="0x080d" name="CP_RB_CNTL_LPAC" variants="A8XX-"/> 152 <reg32 offset="0x080e" name="CP_RB_RPTR_WR_LPAC" variants="A8XX-"/> 153 <reg64 offset="0x080f" name="CP_RB_RPTR_ADDR_LPAC" variants="A8XX-"/> 154 <reg32 offset="0x0811" name="CP_RB_RPTR_LPAC" variants="A8XX-"/> 155 <reg32 offset="0x0812" name="CP_RB_WPTR_LPAC" variants="A8XX-"/> 156 <reg32 offset="0x0814" name="CP_SMMU_STREAM_ID_LPAC" variants="A8XX-"/> 157 <reg32 offset="0x0808" name="CP_SQE_CNTL" variants="A6XX-A7XX"/> 158 <reg32 offset="0x0815" name="CP_SQE_CNTL" variants="A8XX-"/> 159 <reg64 offset="0x0816" name="CP_SQE_INSTR_BASE" variants="A8XX-"/> 160 <reg64 offset="0x0818" name="CP_AQE_INSTR_BASE_0" variants="A8XX-"/> 161 <reg64 offset="0x081a" name="CP_AQE_INSTR_BASE_1" variants="A8XX-"/> 162 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS" variants="A6XX-A7XX"> 163 <!-- Note, layout defined by microcode --> 164 <bitfield name="IFPC" pos="0" type="boolean"/> 165 </reg32> 166 <reg32 offset="0x0822" name="CP_CP2GMU_STATUS" variants="A8XX-"> 167 <bitfield name="IFPC" pos="0" type="boolean"/> 168 </reg32> 169 <reg32 offset="0x0821" name="CP_HW_FAULT" variants="A6XX-A7XX"/> 170 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT" variants="A6XX-A7XX"/> 171 172 <bitset name="a6xx_cp_protect_status" inline="yes"> 173 <bitfield name="ADDR" low="0" high="17"/> 174 <bitfield name="READ" pos="20" type="boolean"/> 175 <bitfield name="CP_HALTED" pos="21" type="boolean"/> 176 <bitfield name="ACCESS_VIOLATION" pos="22" type="boolean"/> 177 </bitset> 178 179 <reg32 offset="0x0824" name="CP_PROTECT_STATUS" type="a6xx_cp_protect_status" variants="A6XX-A7XX"/> 180 <reg32 offset="0x084f" name="CP_PROTECT_STATUS_PIPE" type="a6xx_cp_protect_status" variants="A8XX-"/> 181 <reg32 offset="0x0825" name="CP_STATUS_1" variants="A6XX-A7XX"/> 182 183 <reg32 offset="0x0825" name="CP_SEMAPHORE_REG_0" variants="A8XX-"/> 184 <array offset="0x082a" name="CP_SCRATCH_GLOBAL" stride="1" length="4" variants="A8XX-"> 185 <reg32 offset="0x0" name="REG"/> 186 </array> 187 <array offset="0x0830" name="CP_SCRATCH_PIPE" stride="1" length="5" variants="A8XX-"> 188 <reg32 offset="0x0" name="REG"/> 189 </array> 190 191 <reg32 offset="0x0840" name="CP_RL_ERROR_DETAILS_0" variants="A8XX-"/> 192 <reg32 offset="0x0841" name="CP_RL_ERROR_DETAILS_1" variants="A8XX-"/> 193 194 <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE" variants="A6XX-A7XX"/> 195 <reg32 offset="0x0840" name="CP_MISC_CNTL" variants="A6XX-A7XX"/> 196 <reg32 offset="0x084c" name="CP_MISC_CNTL" variants="A8XX-"/> 197 198 <reg32 offset="0x08b0" name="CP_SQE_ICACHE_CNTL_PIPE" variants="A8XX-"/> 199 <reg32 offset="0x08b1" name="CP_SQE_DCACHE_CNTL_PIPE" variants="A8XX-"/> 200 <reg32 offset="0x08b3" name="CP_HW_FAULT_STATUS_PIPE" variants="A8XX-"/> 201 <reg32 offset="0x08b4" name="CP_HW_FAULT_STATUS_MASK_PIPE" variants="A8XX-"/> 202 <reg32 offset="0x08b5" name="CP_INTERRUPT_STATUS_GLOBAL" type="A8XX_CP_GLOBAL_INT_MASK" variants="A8XX-"/> 203 <reg32 offset="0x08b6" name="CP_INTERRUPT_STATUS_MASK_GLOBAL" type="A8XX_CP_GLOBAL_INT_MASK" variants="A8XX-"/> 204 <reg32 offset="0x08b7" name="CP_INTERRUPT_STATUS_PIPE" type="A8XX_CP_INTERRUPT_STATUS_MASK_PIPE" variants="A8XX-"/> 205 <reg32 offset="0x08b8" name="CP_INTERRUPT_STATUS_MASK_PIPE" variants="A8XX-"/> 206 <reg32 offset="0x08b9" name="CP_PIPE_STATUS_PIPE" variants="A8XX-"/> 207 <reg32 offset="0x08ba" name="CP_GPU_BATCH_ID_PIPE" variants="A8XX-"/> 208 <reg32 offset="0x08bb" name="CP_SQE_STATUS_PIPE" variants="A8XX-"/> 209 210 <bitset name="a6xx_cp_apriv_cntl" inline="yes"> 211 <!-- Crashdumper writes --> 212 <bitfield pos="6" name="CDWRITE" type="boolean"/> 213 <!-- Crashdumper reads --> 214 <bitfield pos="5" name="CDREAD" type="boolean"/> 215 <!-- CP Scratch reg copy to mem --> 216 <bitfield pos="4" name="SCRATCHWT" type="boolean"/> 217 <!-- RPTR shadow writes --> 218 <bitfield pos="3" name="RBRPWB" type="boolean"/> 219 <!-- Memory accesses from PM4 packets in the ringbuffer --> 220 <bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/> 221 <!-- Ringbuffer reads --> 222 <bitfield pos="1" name="RBFETCH" type="boolean"/> 223 <!-- Instruction cache fetches --> 224 <bitfield pos="0" name="ICACHE" type="boolean"/> 225 </bitset> 226 227 <reg32 offset="0x0844" name="CP_APRIV_CNTL" type="a6xx_cp_apriv_cntl" variants="A6XX-A7XX"/> 228 <reg32 offset="0x084d" name="CP_APRIV_CNTL_PIPE" type="a6xx_cp_apriv_cntl" variants="A8XX-"/> 229 230 <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: --> 231 <reg32 offset="0x08c0" name="CP_PREEMPT_THRESHOLD" variants="A6XX-A7XX"/> 232 <reg32 offset="0x08ec" name="CP_PREEMPT_THRESHOLD" variants="A8XX-"/> 233 <!-- all the threshold values seem to be in units of quad-dwords: --> 234 <reg32 offset="0x08c1" name="CP_ROQ_THRESHOLDS_1" variants="A6XX"> 235 <doc> 236 b0..7 identifies where MRB data starts (and RB data ends) 237 b8.15 identifies where VSD data starts (and MRB data ends) 238 b16..23 identifies where IB1 data starts (and RB data ends) 239 b24..31 identifies where IB2 data starts (and IB1 data ends) 240 </doc> 241 <bitfield name="MRB_START" low="0" high="7" shr="2"/> 242 <bitfield name="VSD_START" low="8" high="15" shr="2"/> 243 <bitfield name="IB1_START" low="16" high="23" shr="2"/> 244 <bitfield name="IB2_START" low="24" high="31" shr="2"/> 245 </reg32> 246 <reg32 offset="0x08c2" name="CP_ROQ_THRESHOLDS_2" variants="A6XX"> 247 <doc> 248 low bits identify where CP_SET_DRAW_STATE stateobj 249 processing starts (and IB2 data ends). I'm guessing 250 b8 is part of this since (from downstream kgsl): 251 252 /* ROQ sizes are twice as big on a640/a680 than on a630 */ 253 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) { 254 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 255 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C); 256 } ... 257 </doc> 258 <bitfield name="SDS_START" low="0" high="8" shr="2"/> 259 <!-- total ROQ size: --> 260 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/> 261 </reg32> 262 <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE" variants="A6XX"/> 263 <reg32 offset="0x0841" name="CP_CHICKEN_DBG" variants="A6XX-A7XX"/> 264 <reg32 offset="0x08b2" name="CP_CHICKEN_DBG_PIPE" variants="A8XX-"/> 265 <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 266 <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL" variants="A6XX-A7XX"/> 267 <reg32 offset="0x084b" name="CP_DBG_ECO_CNTL" variants="A8XX-"/> 268 269 <bitset name="a6xx_cp_protect_cntl" inline="yes"> 270 <bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/> 271 <bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/> 272 <bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/> 273 </bitset> 274 275 <reg32 offset="0x084f" name="CP_PROTECT_CNTL" type="a6xx_cp_protect_cntl" variants="A6XX-A7XX"/> 276 <bitset name="a8xx_cp_protect_cntl" inline="yes"> 277 <bitfield name="HALT_SQE_RANGE" low="16" high="31"/> 278 <bitfield name="LAST_SPAN_INF_RANGE" pos="3" type="boolean"/> 279 <bitfield name="ACCESS_FAULT_ON_VIOL_EN" pos="1" type="boolean"/> 280 <bitfield name="ACCESS_PROT_EN" pos="0" type="boolean"/> 281 </bitset> 282 283 <reg32 offset="0x084e" name="CP_PROTECT_CNTL_PIPE" type="a8xx_cp_protect_cntl" variants="A8XX-"/> 284 285 <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8" variants="A6XX-A7XX"> 286 <reg32 offset="0x0" name="REG" type="uint"/> 287 </array> 288 <array offset="0x0850" name="CP_PROTECT" stride="1" length="32" variants="A6XX-A7XX"> 289 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 290 </array> 291 <array offset="0x0850" name="CP_PROTECT_GLOBAL" stride="1" length="64" variants="A8XX-"> 292 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 293 </array> 294 <array offset="0x08a0" name="CP_PROTECT_PIPE" stride="1" length="16" variants="A8XX-"> 295 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 296 </array> 297 298 <bitset name="a6xx_cp_context_switch_cntl" inline="yes"> 299 <bitfield name="STOP" pos="0" type="boolean"/> 300 <bitfield name="LEVEL" low="6" high="7"/> 301 <bitfield name="USES_GMEM" pos="8" type="boolean"/> 302 <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/> 303 </bitset> 304 305 <reg32 offset="0x08a0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A6XX-A7XX"/> 306 <reg32 offset="0x08c0" name="CP_CONTEXT_SWITCH_CNTL" type="a6xx_cp_context_switch_cntl" variants="A8XX-"/> 307 308 <reg64 offset="0x08a1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A6XX-A7XX"/> 309 <reg64 offset="0x08a3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/> 310 <reg64 offset="0x08a5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A6XX-A7XX"/> 311 <reg64 offset="0x08a7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A6XX-A7XX"/> 312 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX"/> 313 314 <reg64 offset="0x08c1" name="CP_CONTEXT_SWITCH_SMMU_INFO" variants="A8XX-"/> 315 <reg64 offset="0x08c3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR" variants="A8XX-"/> 316 <reg64 offset="0x08c5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR" variants="A8XX-"/> 317 <reg64 offset="0x08c7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR" variants="A8XX-"/> 318 <reg32 offset="0x08cb" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A8XX-"/> 319 320 <array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="14" variants="A6XX-A7XX"/> 321 <array offset="0x08d0" name="CP_PERFCTR_CP_SEL" stride="1" length="21" variants="A8XX-"/> 322 <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX"/> 323 <reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE" variants="A6XX-A7XX"/> 324 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL" variants="A6XX-A7XX"/> 325 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS" variants="A6XX-A7XX"/> 326 <reg64 offset="0x0842" name="CP_CRASH_DUMP_SCRIPT_BASE" variants="A8XX-"/> 327 <reg32 offset="0x0844" name="CP_CRASH_DUMP_CNTL" variants="A8XX-"/> 328 <reg32 offset="0x0845" name="CP_CRASH_DUMP_STATUS" variants="A8XX-"/> 329 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR" variants="A6XX-A7XX"/> 330 <reg32 offset="0x0909" name="CP_SQE_STAT_DATA" variants="A6XX-A7XX"/> 331 <reg32 offset="0x090a" name="CP_DRAW_STATE_ADDR" variants="A6XX-A7XX"/> 332 <reg32 offset="0x090b" name="CP_DRAW_STATE_DATA" variants="A6XX-A7XX"/> 333 <reg32 offset="0x090c" name="CP_ROQ_DBG_ADDR" variants="A6XX-A7XX"/> 334 <reg32 offset="0x090d" name="CP_ROQ_DBG_DATA" variants="A6XX-A7XX"/> 335 <reg32 offset="0x090e" name="CP_MEM_POOL_DBG_ADDR" variants="A6XX-A7XX"/> 336 <reg32 offset="0x090f" name="CP_MEM_POOL_DBG_DATA" variants="A6XX-A7XX"/> 337 <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR" variants="A6XX-A7XX"/> 338 <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA" variants="A6XX-A7XX"/> 339 340 <reg32 offset="0x08f0" name="CP_SQE_STAT_ADDR_PIPE" variants="A8XX-"/> 341 <reg32 offset="0x08f1" name="CP_SQE_STAT_DATA_PIPE" variants="A8XX-"/> 342 <reg32 offset="0x08f2" name="CP_DRAW_STATE_ADDR_PIPE" variants="A8XX-"/> 343 <reg32 offset="0x08f3" name="CP_DRAW_STATE_DATA_PIPE" variants="A8XX-"/> 344 <reg32 offset="0x08f4" name="CP_ROQ_DBG_ADDR_PIPE" variants="A8XX-"/> 345 <reg32 offset="0x08f5" name="CP_ROQ_DBG_DATA_PIPE" variants="A8XX-"/> 346 <reg32 offset="0x08f6" name="CP_MEM_POOL_DBG_ADDR_PIPE" variants="A8XX-"/> 347 <reg32 offset="0x08f7" name="CP_MEM_POOL_DBG_DATA_PIPE" variants="A8XX-"/> 348 <reg32 offset="0x08f8" name="CP_SQE_UCODE_DBG_ADDR_PIPE" variants="A8XX-"/> 349 <reg32 offset="0x08f9" name="CP_SQE_UCODE_DBG_DATA_PIPE" variants="A8XX-"/> 350 <reg32 offset="0x08fa" name="CP_RESOURCE_TABLE_DBG_ADDR_BV" variants="A8XX-"/> 351 <reg32 offset="0x08fb" name="CP_RESOURCE_TABLE_DBG_DATA_BV" variants="A8XX-"/> 352 <reg32 offset="0x08fc" name="CP_FIFO_DBG_ADDR_LPAC" variants="A8XX-"/> 353 <reg32 offset="0x08fd" name="CP_FIFO_DBG_DATA_LPAC" variants="A8XX-"/> 354 <reg32 offset="0x08fe" name="CP_FIFO_DBG_ADDR_DDE_PIPE" variants="A8XX-"/> 355 <reg32 offset="0x08ff" name="CP_FIFO_DBG_DATA_DDE_PIPE" variants="A8XX-"/> 356 357 <reg32 offset="0x0b00" name="CP_SLICE_MEM_POOL_DBG_ADDR_PIPE" variants="A8XX-"/> 358 <reg32 offset="0x0b01" name="CP_SLICE_MEM_POOL_DBG_DATA_PIPE" variants="A8XX-"/> 359 <reg32 offset="0x0b93" name="CP_SLICE_CHICKEN_DBG_PIPE" variants="A8XX-"/> 360 361 <reg64 offset="0x0928" name="CP_IB1_BASE" variants="A6XX-A7XX"/> 362 <reg32 offset="0x092a" name="CP_IB1_REM_SIZE" variants="A6XX-A7XX"/> 363 <reg64 offset="0x092b" name="CP_IB2_BASE" variants="A6XX-A7XX"/> 364 <reg32 offset="0x092d" name="CP_IB2_REM_SIZE" variants="A6XX-A7XX"/> 365 <!-- SDS == CP_SET_DRAW_STATE: --> 366 <reg64 offset="0x092e" name="CP_SDS_BASE" variants="A6XX-A7XX"/> 367 <reg32 offset="0x0930" name="CP_SDS_REM_SIZE" variants="A6XX-A7XX"/> 368 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware --> 369 <reg64 offset="0x0931" name="CP_MRB_BASE" variants="A6XX-A7XX"/> 370 <reg32 offset="0x0933" name="CP_MRB_REM_SIZE" variants="A6XX-A7XX"/> 371 <!-- 372 VSD == Visibility Stream Decode 373 This is used by CP to read the draw stream and skip empty draws 374 --> 375 <reg64 offset="0x0934" name="CP_VSD_BASE" variants="A6XX-A7XX"/> 376 377 <reg64 offset="0x0900" name="CP_IB1_BASE" variants="A8XX-"/> 378 <reg32 offset="0x0902" name="CP_IB1_REM_SIZE" variants="A8XX-"/> 379 <reg32 offset="0x0903" name="CP_IB1_INIT_SIZE" variants="A8XX-"/> 380 <reg64 offset="0x0904" name="CP_IB2_BASE" variants="A8XX-"/> 381 <reg32 offset="0x0906" name="CP_IB2_REM_SIZE" variants="A8XX-"/> 382 <reg32 offset="0x0907" name="CP_IB2_INIT_SIZE" variants="A8XX-"/> 383 <reg64 offset="0x0908" name="CP_IB3_BASE" variants="A8XX-"/> 384 <reg32 offset="0x090a" name="CP_IB3_REM_SIZE" variants="A8XX-"/> 385 <reg32 offset="0x090b" name="CP_IB3_INIT_SIZE" variants="A8XX-"/> 386 <reg64 offset="0x090c" name="CP_SDS_BASE" variants="A8XX-"/> 387 <reg32 offset="0x090e" name="CP_SDS_REM_SIZE" variants="A8XX-"/> 388 <reg32 offset="0x090f" name="CP_SDS_INIT_SIZE" variants="A8XX-"/> 389 <reg64 offset="0x0910" name="CP_MRB_BASE" variants="A8XX-"/> 390 <reg32 offset="0x0912" name="CP_MRB_REM_SIZE" variants="A8XX-"/> 391 <reg32 offset="0x0913" name="CP_MRB_INIT_SIZE" variants="A8XX-"/> 392 <reg64 offset="0x0914" name="CP_VSD_BASE" variants="A8XX-"/> 393 <reg32 offset="0x0916" name="CP_VSD_REM_SIZE" variants="A8XX-"/> 394 <reg32 offset="0x0917" name="CP_VSD_INIT_SIZE" variants="A8XX-"/> 395 396 <bitset name="a6xx_roq_status" inline="yes"> 397 <bitfield name="RPTR" low="0" high="9"/> 398 <bitfield name="WPTR" low="16" high="25"/> 399 </bitset> 400 <reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 401 <reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 402 <reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 403 <reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 404 <reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 405 <reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status" variants="A6XX-A7XX"/> 406 407 <reg32 offset="0x0920" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 408 <reg32 offset="0x0921" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 409 <reg32 offset="0x0922" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 410 <reg32 offset="0x0923" name="CP_ROQ_IB3_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 411 <reg32 offset="0x0924" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 412 <reg32 offset="0x0925" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 413 <reg32 offset="0x0926" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status" variants="A8XX-"/> 414 415 <reg32 offset="0x0943" name="CP_IB1_INIT_SIZE" variants="A6XX-A7XX"/> 416 <reg32 offset="0x0944" name="CP_IB2_INIT_SIZE" variants="A6XX-A7XX"/> 417 <reg32 offset="0x0945" name="CP_SDS_INIT_SIZE" variants="A6XX-A7XX"/> 418 <reg32 offset="0x0946" name="CP_MRB_INIT_SIZE" variants="A6XX-A7XX"/> 419 <reg32 offset="0x0947" name="CP_VSD_INIT_SIZE" variants="A6XX-A7XX"/> 420 421 <bitset name="a6xx_cp_roq_avail" inline="yes"> 422 <doc>number of remaining dwords incl current dword being consumed?</doc> 423 <bitfield name="REM" low="16" high="31"/> 424 </bitset> 425 426 <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 427 <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 428 <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 429 <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 430 <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 431 <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD" type="a6xx_cp_roq_avail" variants="A6XX-A7XX"/> 432 433 <reg32 offset="0x0918" name="CP_ROQ_AVAIL_RB" type="a6xx_cp_roq_avail" variants="A8XX-"/> 434 <reg32 offset="0x0919" name="CP_ROQ_AVAIL_IB1" type="a6xx_cp_roq_avail" variants="A8XX-"/> 435 <reg32 offset="0x091a" name="CP_ROQ_AVAIL_IB2" type="a6xx_cp_roq_avail" variants="A8XX-"/> 436 <reg32 offset="0x091b" name="CP_ROQ_AVAIL_IB3" type="a6xx_cp_roq_avail" variants="A8XX-"/> 437 <reg32 offset="0x091c" name="CP_ROQ_AVAIL_SDS" type="a6xx_cp_roq_avail" variants="A8XX-"/> 438 <reg32 offset="0x091d" name="CP_ROQ_AVAIL_MRB" type="a6xx_cp_roq_avail" variants="A8XX-"/> 439 <reg32 offset="0x091e" name="CP_ROQ_AVAIL_VSD" type="a6xx_cp_roq_avail" variants="A8XX-"/> 440 441 <bitset name="a7xx_aperture_cntl" inline="yes"> 442 <bitfield name="PIPE" low="12" high="13" type="adreno_pipe"/> 443 <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/> 444 <bitfield name="CONTEXT" low="4" high="5"/> 445 </bitset> 446 <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER" variants="A6XX-A7XX"/> 447 <reg64 offset="0x0982" name="CP_ALWAYS_ON_CONTEXT" variants="A6XX-A7XX"/> 448 <reg64 offset="0x08e7" name="CP_ALWAYS_ON_COUNTER" variants="A8XX-"/> 449 <reg64 offset="0x08e9" name="CP_ALWAYS_ON_CONTEXT" variants="A8XX-"/> 450 <reg32 offset="0x098d" name="CP_AHB_CNTL" variants="A6XX-A7XX"/> 451 <reg32 offset="0x0838" name="CP_AHB_CNTL" variants="A8XX-"/> 452 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/> 453 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX"/> 454 <reg32 offset="0x0A01" name="CP_APERTURE_CNTL_SQE" variants="A6XX"/> 455 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/> 456 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX"/> 457 458 <array offset="0x0a9c" name="CP_RESERVED_REG" stride="1" length="4" variants="A7XX"/> 459 <array offset="0x0958" name="CP_RESERVED_REG" stride="1" length="4" variants="A8XX-"/> 460 461 <bitset name="a8xx_aperture_cntl" inline="yes"> 462 <bitfield name="CONTEXTID3D" low="4" high="5"/> 463 <bitfield name="CLUSTERID" low="8" high="11"/> 464 <bitfield name="PIPEID" low="12" high="15"/> 465 <bitfield name="SLICEID" low="16" high="18"/> 466 <bitfield name="USESLICEID" pos="23" type="boolean"/> 467 </bitset> 468 469 <reg32 offset="0x081c" name="CP_APERTURE_CNTL_HOST" type="a8xx_aperture_cntl" variants="A8XX-"/> 470 <reg32 offset="0x081d" name="CP_APERTURE_CNTL_GMU" type="a8xx_aperture_cntl" variants="A8XX-"/> 471 <reg32 offset="0x081e" name="CP_APERTURE_CNTL_CD" type="a8xx_aperture_cntl" variants="A8XX-"/> 472 473 <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX"/> 474 <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX"/> 475 <reg32 offset="0x0a66" name="CP_BV_RB_RPTR" variants="A7XX"/> 476 <reg64 offset="0x0a6d" name="CP_BV_IB1_BASE" variants="A7XX"/> 477 <reg32 offset="0x0a70" name="CP_BV_IB1_REM_SIZE" variants="A7XX"/> 478 <reg64 offset="0x0a71" name="CP_BV_IB2_BASE" variants="A7XX"/> 479 <reg32 offset="0x0a74" name="CP_BV_IB2_REM_SIZE" variants="A7XX"/> 480 <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX"/> 481 <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX"/> 482 <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX"/> 483 <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX"/> 484 <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX"/> 485 <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX"/> 486 <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX"/> 487 <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX"/> 488 489 <reg32 offset="0x0a8f" name="CP_BV_ROQ_AVAIL_RB" variants="A7XX"> 490 <doc>number of remaining dwords incl current dword being consumed?</doc> 491 <bitfield name="REM" low="16" high="31"/> 492 </reg32> 493 <reg32 offset="0x0a90" name="CP_BV_ROQ_AVAIL_IB1" variants="A7XX"> 494 <doc>number of remaining dwords incl current dword being consumed?</doc> 495 <bitfield name="REM" low="16" high="31"/> 496 </reg32> 497 <reg32 offset="0x0a91" name="CP_BV_ROQ_AVAIL_IB2" variants="A7XX"> 498 <doc>number of remaining dwords incl current dword being consumed?</doc> 499 <bitfield name="REM" low="16" high="31"/> 500 </reg32> 501 502 <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX"/> 503 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX"/> 504 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX"/> 505 506 <reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX"/> 507 <reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX"/> 508 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX"/> 509 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX"/> 510 511 <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX"/> 512 <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX"/> 513 <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX"/> 514 <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX"/> 515 <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX"/> 516 <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX"/> 517 <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX"/> 518 519 <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX"/> 520 <reg32 offset="0x0b34" name="CP_LPAC_PROG_FIFO_SIZE" variants="A7XX"/> 521 <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX"/> 522 <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX"/> 523 <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX"/> 524 <reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL" variants="A6XX-A7XX"/> 525 <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE" variants="A6XX-A7XX"/> 526 527 <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX"/> 528 <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX"/> 529 <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX"/> 530 531 <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX"/> 532 <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX"/> 533 <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX"/> 534 <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX"/> 535 <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX"/> 536 <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX"/> 537 <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX"/> 538 <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX"/> 539 <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX"/> 540 <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX"/> 541 <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX"/> 542 <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX"/> 543 544 <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 545 <reg32 offset="0x0018" name="RBBM_GPR0_CNTL" variants="A6XX"/> 546 <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/> 547 <reg32 offset="0x006a" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/> 548 <reg32 offset="0x0210" name="RBBM_STATUS" variants="A6XX-A7XX"> 549 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/> 550 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/> 551 <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/> 552 <bitfield pos="20" name="VSC_BUSY" type="boolean"/> 553 <bitfield pos="19" name="TPL1_BUSY" type="boolean"/> 554 <bitfield pos="18" name="SP_BUSY" type="boolean"/> 555 <bitfield pos="17" name="UCHE_BUSY" type="boolean"/> 556 <bitfield pos="16" name="VPC_BUSY" type="boolean"/> 557 <bitfield pos="15" name="VFD_BUSY" type="boolean"/> 558 <bitfield pos="14" name="TESS_BUSY" type="boolean"/> 559 <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/> 560 <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/> 561 <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/> 562 <bitfield pos="10" name="LRZ_BUSY" type="boolean"/> 563 <bitfield pos="9" name="A2D_BUSY" type="boolean"/> 564 <bitfield pos="8" name="CCU_BUSY" type="boolean"/> 565 <bitfield pos="7" name="RB_BUSY" type="boolean"/> 566 <bitfield pos="6" name="RAS_BUSY" type="boolean"/> 567 <bitfield pos="5" name="TSE_BUSY" type="boolean"/> 568 <bitfield pos="4" name="VBIF_BUSY" type="boolean"/> 569 <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/> 570 <bitfield pos="2" name="CP_BUSY" type="boolean"/> 571 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/> 572 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/> 573 </reg32> 574 <reg32 offset="0x0211" name="RBBM_STATUS1" variants="A6XX-A7XX"/> 575 <reg32 offset="0x0212" name="RBBM_STATUS2" variants="A6XX-A7XX"/> 576 <reg32 offset="0x0213" name="RBBM_STATUS3" variants="A6XX-A7XX"> 577 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/> 578 </reg32> 579 580 <reg32 offset="0x012" name="RBBM_STATUS" variants="A8XX-"> 581 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/> 582 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/> 583 <bitfield pos="21" name="SLICE_BUSY_IGN_CP" type="boolean"/> 584 <bitfield pos="20" name="CP_SLICE_BUSY" type="boolean"/> 585 <bitfield pos="19" name="UNSLICE_BUSY_IGN_AHB" type="boolean"/> 586 <bitfield pos="18" name="UNSLICE_BUSY_IGN_AHB_CP" type="boolean"/> 587 <bitfield pos="17" name="CP_SLICE_RL_BUSY" type="boolean"/> 588 <bitfield pos="14" name="UNSLICE_TOP_BUSY" type="boolean"/> 589 <bitfield pos="13" name="UFC_BUSY" type="boolean"/> 590 <bitfield pos="12" name="HLSQ_BUSY" type="boolean"/> 591 <bitfield pos="11" name="VSC_BUSY" type="boolean"/> 592 <bitfield pos="10" name="UCHE_BUSY" type="boolean"/> 593 <bitfield pos="9" name="VPC_BUSY" type="boolean"/> 594 <bitfield pos="8" name="PC_BUSY" type="boolean"/> 595 <bitfield pos="7" name="CMP_BUSY" type="boolean"/> 596 <bitfield pos="6" name="DCMP_BUSY" type="boolean"/> 597 <bitfield pos="5" name="VBIF_GX_BUSY" type="boolean"/> 598 <bitfield pos="4" name="DBGC_PERF_BUSY" type="boolean"/> 599 <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/> 600 <bitfield pos="2" name="CP_BUSY" type="boolean"/> 601 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/> 602 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/> 603 </reg32> 604 <reg32 offset="0x013" name="RBBM_STATUS1" variants="A8XX-"/> 605 <reg32 offset="0x015" name="RBBM_GFX_STATUS" variants="A8XX-"/> 606 <reg32 offset="0x016" name="RBBM_GFX_STATUS1" variants="A8XX-"/> 607 <reg32 offset="0x018" name="RBBM_LPAC_STATUS" variants="A8XX-"/> 608 <reg32 offset="0x01a" name="RBBM_GFX_BR_STATUS" variants="A8XX-"/> 609 <reg32 offset="0x01c" name="RBBM_GFX_BV_STATUS" variants="A8XX-"/> 610 <reg32 offset="0x01e" name="RBBM_MISC_STATUS" variants="A8XX-"> 611 <bitfield pos="0" name="SMMU_STALLED_ON_FAULT" type="boolean"/> 612 </reg32> 613 614 <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS" variants="A6XX"/> 615 616 <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX"/> 617 <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX"/> 618 <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX"/> 619 <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX"/> 620 <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX"/> 621 <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX"/> 622 623 <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX"/> 624 <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX"/> 625 <reg32 offset="0x0071" name="RBBM_SW_FUSE_INT_STATUS" variants="A8XX-"/> 626 <reg32 offset="0x0072" name="RBBM_SW_FUSE_INT_MASK" variants="A8XX-"/> 627 628 <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/> 629 <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/> 630 <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/> 631 <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/> 632 <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/> 633 <array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/> 634 <array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/> 635 <array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/> 636 <array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/> 637 <array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/> 638 <array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/> 639 <array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/> 640 <array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/> 641 <array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/> 642 <array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/> 643 <array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/> 644 645 <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX"/> 646 <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX"/> 647 <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX"/> 648 <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX"/> 649 <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX"/> 650 <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX"/> 651 <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX"/> 652 <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX"/> 653 <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX"/> 654 <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX"/> 655 <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX"/> 656 <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX"/> 657 <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX"/> 658 <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX"/> 659 <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX"/> 660 <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX"/> 661 <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX"/> 662 <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX"/> 663 <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX"/> 664 <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX"/> 665 <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX"/> 666 <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX"/> 667 <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX"/> 668 <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX"/> 669 <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX"/> 670 <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX"/> 671 <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX"/> 672 <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX"/> 673 674 <array offset="0x01b0" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A8XX"/> 675 <array offset="0x01cc" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A8XX"/> 676 <array offset="0x01d4" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A8XX"/> 677 <array offset="0x01e4" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A8XX"/> 678 <array offset="0x01f4" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A8XX"/> 679 <array offset="0x0200" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A8XX"/> 680 <array offset="0x020c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A8XX"/> 681 <array offset="0x0216" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A8XX"/> 682 <array offset="0x021e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A8XX"/> 683 <array offset="0x0226" name="RBBM_PERFCTR_UCHE" stride="2" length="24" variants="A8XX"/> 684 <array offset="0x0256" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A8XX"/> 685 <array offset="0x026e" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A8XX"/> 686 <array offset="0x029e" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A8XX"/> 687 <array offset="0x02ae" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A8XX"/> 688 <array offset="0x02b2" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A8XX"/> 689 <array offset="0x02ba" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A8XX"/> 690 <array offset="0x02c2" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A8XX"/> 691 <array offset="0x02e2" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A8XX"/> 692 <array offset="0x02ee" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A8XX"/> 693 <array offset="0x02fc" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A8XX"/> 694 <array offset="0x0314" name="RBBM_PERFCTR2_TP" stride="2" length="8" variants="A8XX"/> 695 <array offset="0x0324" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A8XX"/> 696 <array offset="0x0328" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A8XX"/> 697 <array offset="0x0338" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A8XX"/> 698 <array offset="0x0348" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A8XX"/> 699 <array offset="0x0354" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A8XX"/> 700 <array offset="0x035c" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A8XX"/> 701 <array offset="0x0364" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A8XX"/> 702 <array offset="0x036c" name="RBBM_PERFCTR_BV_CCU" stride="2" length="3" variants="A8XX"/> 703 <array offset="0x0372" name="RBBM_PERFCTR_BV_RB" stride="2" length="6" variants="A8XX"/> 704 705 <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL" variants="A6XX-A7XX"/> 706 <reg32 offset="0x0460" name="RBBM_PERFCTR_CNTL" variants="A8XX-"/> 707 <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0" variants="A6XX"/> 708 <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1" variants="A6XX"/> 709 <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2" variants="A6XX"/> 710 <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3" variants="A6XX"/> 711 <reg64 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE" variants="A6XX"/> 712 <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 713 <array offset="0x0441" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A8XX-"/> 714 <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED" variants="A6XX-A7XX"/> 715 <reg32 offset="0x019e" name="RBBM_PERFCTR_GPU_BUSY_MASKED" variants="A8XX-"/> 716 <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD" variants="A6XX-A7XX"/> 717 <reg32 offset="0x0449" name="RBBM_PERFCTR_SRAM_INIT_CMD" variants="A8XX-"/> 718 <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS" variants="A6XX-A7XX"/> 719 <reg32 offset="0x019f" name="RBBM_PERFCTR_SRAM_INIT_STATUS" variants="A8XX-"/> 720 <reg32 offset="0x01a1" name="RBBM_PERFCTR_FLUSH_HOST_STATUS" variants="A8XX-"/> 721 <reg32 offset="0x044c" name="RBBM_PERFCTR_FLUSH_HOST_CMD" variants="A8XX-"/> 722 <reg32 offset="0x0533" name="RBBM_ISDB_CNT" variants="A6XX-A7XX"/> 723 <reg32 offset="0x002d" name="RBBM_ISDB_CNT" variants="A8XX-"/> 724 <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL" variants="A6XX-A7XX"/> 725 <reg32 offset="0x0440" name="RBBM_NC_MODE_CNTL" variants="A8XX-"/> 726 <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX"/> 727 <reg32 offset="0x002e" name="RBBM_SNAPSHOT_STATUS" variants="A8XX-"/> 728 729 <reg32 offset="0x500" name="RBBM_SLICE_PERFCTR_CNTL" variants="A8XX-"/> 730 <reg32 offset="0x58f" name="RBBM_SLICE_INTERFACE_HANG_INT_CNTL" variants="A8XX-"/> 731 <array offset="0x5e0" name="RBBM_SLICE_PERFCTR_RBBM_SEL" stride="1" length="4" variants="A8XX-"/> 732 <reg32 offset="0x5e8" name="RBBM_SLICE_PERFCTR_SRAM_INIT_CMD" variants="A8XX-"/> 733 <reg32 offset="0x5eb" name="RBBM_SLICE_PERFCTR_FLUSH_HOST_CMD" variants="A8XX-"/> 734 <reg32 offset="0x5ec" name="RBBM_SLICE_NC_MODE_CNTL" variants="A8XX-"/> 735 736 <!--- 737 This block of registers aren't tied to perf counters. They 738 count various geometry stats, for example number of 739 vertices in, number of primnitives assembled etc. 740 --> 741 742 <reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES" variants="A6XX-A7XX"/> 743 <reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES" variants="A6XX-A7XX"/> 744 <reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS" variants="A6XX-A7XX"/> 745 <reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS" variants="A6XX-A7XX"/> 746 <reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS" variants="A6XX-A7XX"/> 747 <reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS" variants="A6XX-A7XX"/> 748 <reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES" variants="A6XX-A7XX"/> 749 <reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS" variants="A6XX-A7XX"/> 750 <reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES" variants="A6XX-A7XX"/> 751 <reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS" variants="A6XX-A7XX"/> 752 <reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS" variants="A6XX-A7XX"/> 753 754 <reg64 offset="0x0380" name="RBBM_PIPESTAT_IAVERTICES" variants="A8XX-"/> 755 <reg64 offset="0x0382" name="RBBM_PIPESTAT_IAPRIMITIVES" variants="A8XX-"/> 756 <reg64 offset="0x0384" name="RBBM_PIPESTAT_VSINVOCATIONS" variants="A8XX-"/> 757 <reg64 offset="0x0386" name="RBBM_PIPESTAT_GSINVOCATIONS" variants="A8XX-"/> 758 <reg64 offset="0x0388" name="RBBM_PIPESTAT_GSPRIMITIVES" variants="A8XX-"/> 759 <reg64 offset="0x038a" name="RBBM_PIPESTAT_CINVOCATIONS" variants="A8XX-"/> 760 <reg64 offset="0x038c" name="RBBM_PIPESTAT_CPRIMITIVES" variants="A8XX-"/> 761 <reg64 offset="0x038e" name="RBBM_PIPESTAT_PSINVOCATIONS" variants="A8XX-"/> 762 <reg64 offset="0x0390" name="RBBM_PIPESTAT_HSINVOCATIONS" variants="A8XX-"/> 763 <reg64 offset="0x0392" name="RBBM_PIPESTAT_DSINVOCATIONS" variants="A8XX-"/> 764 <reg64 offset="0x0394" name="RBBM_PIPESTAT_CSINVOCATIONS" variants="A8XX-"/> 765 <reg64 offset="0x0396" name="RBBM_PIPESTAT_ASINVOCATIONS" variants="A8XX-"/> 766 <reg64 offset="0x0398" name="RBBM_PIPESTAT_MSINVOCATIONS" variants="A8XX-"/> 767 <reg64 offset="0x039a" name="RBBM_PIPESTAT_MSPRIMITIVES" variants="A8XX-"/> 768 769 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> 770 <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/> 771 <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/> 772 <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/> 773 <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 774 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/> 775 <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL" variants="A6XX"/> 776 <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL" variants="A6XX-A7XX"/> 777 <reg32 offset="0x00008" name="RBBM_GBIF_CLIENT_QOS_CNTL" variants="A8XX-"/> 778 <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A6XX-A7XX"/> 779 <reg32 offset="0x0000a" name="RBBM_GBIF_HALT" variants="A8XX-"/> 780 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A6XX-A7XX"/> 781 <reg32 offset="0x0000b" name="RBBM_GBIF_HALT_ACK" variants="A8XX-"/> 782 <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD" variants="A6XX"> 783 <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/> 784 </reg32> 785 786 <reg32 offset="0x01a" name="RBBM_WAIT_IDLE_CLOCKS_CNTL" variants="A6XX-A7XX"/> 787 <reg32 offset="0x01b" name="RBBM_WAIT_IDLE_CLOCKS_CNTL2" variants="A6XX-A7XX"/> 788 <reg32 offset="0x010" name="RBBM_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/> 789 <reg32 offset="0x011" name="RBBM_WAIT_IDLE_CLOCKS_CNTL2" variants="A8XX-"/> 790 791 <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL" variants="A6XX-A7XX"/> 792 <reg32 offset="0x0002f" name="RBBM_INTERFACE_HANG_INT_CNTL" variants="A8XX-"/> 793 <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/> 794 <reg32 offset="0x00061" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/> 795 <reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK" variants="A6XX-A7XX"/> 796 <reg32 offset="0x00062" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK" variants="A8XX-"/> 797 <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX"/> 798 <reg32 offset="0x00064" name="RBBM_INT_2_MASK" variants="A8XX-"/> 799 <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT" variants="A6XX-A7XX"/> 800 <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD" variants="A6XX-A7XX"/> 801 <reg32 offset="0x00073" name="RBBM_SW_RESET_CMD" variants="A8XX-"/> 802 <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT" variants="A6XX-A7XX"/> 803 <reg32 offset="0x00029" name="RBBM_RAC_THRESHOLD_CNT" variants="A8XX-"/> 804 <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD" variants="A6XX"/> 805 <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2" variants="A6XX"/> 806 <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX"/> 807 <reg32 offset="0x0009a" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A8XX-"/> 808 <reg32 offset="0x07d" name="RBBM_POWER_UP_RESET_SW_OVERRIDE" variants="A8XX-"/> 809 <reg32 offset="0x07e" name="RBBM_POWER_UP_RESET_SW_BV_OVERRIDE" variants="A8XX-"/> 810 <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL" variants="A6XX-A7XX"/> 811 <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0" variants="A6XX-A7XX"/> 812 <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1" variants="A6XX-A7XX"/> 813 <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2" variants="A6XX-A7XX"/> 814 <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3" variants="A6XX-A7XX"/> 815 <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0" variants="A6XX-A7XX"/> 816 <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1" variants="A6XX-A7XX"/> 817 <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2" variants="A6XX-A7XX"/> 818 <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3" variants="A6XX-A7XX"/> 819 <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0" variants="A6XX-A7XX"/> 820 <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1" variants="A6XX-A7XX"/> 821 <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2" variants="A6XX-A7XX"/> 822 <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3" variants="A6XX-A7XX"/> 823 <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0" variants="A6XX-A7XX"/> 824 <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1" variants="A6XX-A7XX"/> 825 <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2" variants="A6XX-A7XX"/> 826 <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3" variants="A6XX-A7XX"/> 827 <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0" variants="A6XX-A7XX"/> 828 <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1" variants="A6XX-A7XX"/> 829 <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2" variants="A6XX-A7XX"/> 830 <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3" variants="A6XX-A7XX"/> 831 <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0" variants="A6XX-A7XX"/> 832 <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1" variants="A6XX-A7XX"/> 833 <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2" variants="A6XX-A7XX"/> 834 <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3" variants="A6XX-A7XX"/> 835 <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0" variants="A6XX-A7XX"/> 836 <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1" variants="A6XX-A7XX"/> 837 <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2" variants="A6XX-A7XX"/> 838 <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3" variants="A6XX-A7XX"/> 839 <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0" variants="A6XX-A7XX"/> 840 <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1" variants="A6XX-A7XX"/> 841 <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2" variants="A6XX-A7XX"/> 842 <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3" variants="A6XX-A7XX"/> 843 <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0" variants="A6XX-A7XX"/> 844 <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1" variants="A6XX-A7XX"/> 845 <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2" variants="A6XX-A7XX"/> 846 <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3" variants="A6XX-A7XX"/> 847 <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0" variants="A6XX-A7XX"/> 848 <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1" variants="A6XX-A7XX"/> 849 <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2" variants="A6XX-A7XX"/> 850 <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3" variants="A6XX-A7XX"/> 851 <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0" variants="A6XX-A7XX"/> 852 <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1" variants="A6XX-A7XX"/> 853 <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2" variants="A6XX-A7XX"/> 854 <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3" variants="A6XX-A7XX"/> 855 <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0" variants="A6XX-A7XX"/> 856 <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1" variants="A6XX-A7XX"/> 857 <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2" variants="A6XX-A7XX"/> 858 <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3" variants="A6XX-A7XX"/> 859 <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0" variants="A6XX-A7XX"/> 860 <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1" variants="A6XX-A7XX"/> 861 <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2" variants="A6XX-A7XX"/> 862 <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3" variants="A6XX-A7XX"/> 863 <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0" variants="A6XX-A7XX"/> 864 <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1" variants="A6XX-A7XX"/> 865 <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2" variants="A6XX-A7XX"/> 866 <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3" variants="A6XX-A7XX"/> 867 <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0" variants="A6XX-A7XX"/> 868 <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1" variants="A6XX-A7XX"/> 869 <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2" variants="A6XX-A7XX"/> 870 <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3" variants="A6XX-A7XX"/> 871 <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0" variants="A6XX-A7XX"/> 872 <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1" variants="A6XX-A7XX"/> 873 <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2" variants="A6XX-A7XX"/> 874 <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3" variants="A6XX-A7XX"/> 875 <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0" variants="A6XX-A7XX"/> 876 <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1" variants="A6XX-A7XX"/> 877 <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2" variants="A6XX-A7XX"/> 878 <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3" variants="A6XX-A7XX"/> 879 <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0" variants="A6XX-A7XX"/> 880 <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1" variants="A6XX-A7XX"/> 881 <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2" variants="A6XX-A7XX"/> 882 <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3" variants="A6XX-A7XX"/> 883 <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0" variants="A6XX-A7XX"/> 884 <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1" variants="A6XX-A7XX"/> 885 <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2" variants="A6XX-A7XX"/> 886 <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3" variants="A6XX-A7XX"/> 887 <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0" variants="A6XX-A7XX"/> 888 <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1" variants="A6XX-A7XX"/> 889 <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2" variants="A6XX-A7XX"/> 890 <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3" variants="A6XX-A7XX"/> 891 <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC" variants="A6XX-A7XX"/> 892 <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC" variants="A6XX-A7XX"/> 893 <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC" variants="A6XX-A7XX"/> 894 <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC" variants="A6XX-A7XX"/> 895 <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM" variants="A6XX-A7XX"/> 896 <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM" variants="A6XX-A7XX"/> 897 <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM" variants="A6XX-A7XX"/> 898 <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE" variants="A6XX-A7XX"/> 899 <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE" variants="A6XX-A7XX"/> 900 <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE" variants="A6XX-A7XX"/> 901 <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE" variants="A6XX-A7XX"/> 902 <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE" variants="A6XX-A7XX"/> 903 <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE" variants="A6XX-A7XX"/> 904 <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD" variants="A6XX-A7XX"/> 905 <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD" variants="A6XX-A7XX"/> 906 <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD" variants="A6XX-A7XX"/> 907 <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC" variants="A6XX-A7XX"/> 908 <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC" variants="A6XX-A7XX"/> 909 <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC" variants="A6XX-A7XX"/> 910 <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2" variants="A6XX-A7XX"/> 911 <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX" variants="A6XX-A7XX"/> 912 <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX" variants="A6XX-A7XX"/> 913 <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX" variants="A6XX-A7XX"/> 914 <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ" variants="A6XX-A7XX"/> 915 <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ" variants="A6XX-A7XX"/> 916 <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ" variants="A6XX-A7XX"/> 917 <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX"/> 918 <reg32 offset="0x0009b" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A8XX-"/> 919 <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX"/> 920 <reg32 offset="0x0009c" name="RBBM_CGC_P2S_TRIG_CMD" variants="A8XX-"/> 921 <reg32 offset="0x00120" name="RBBM_CGC_P2S_CNTL" variants="A7XX"/> 922 <reg32 offset="0x0009d" name="RBBM_CGC_P2S_CNTL" variants="A8XX-"/> 923 <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE" variants="A6XX"/> 924 <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE" variants="A6XX-A7XX"/> 925 <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE" variants="A6XX"/> 926 <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX"> 927 <bitfield name="TXDONE" pos="0" type="boolean"/> 928 </reg32> 929 <reg32 offset="0x09f" name="RBBM_CGC_P2S_STATUS" variants="A8XX-"> 930 <bitfield name="TXDONE" pos="0" type="boolean"/> 931 </reg32> 932 <reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE" variants="A6XX-A7XX"/> 933 <reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE" variants="A6XX-A7XX"/> 934 <reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE" variants="A6XX-A7XX"/> 935 <reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB" variants="A6XX-A7XX"/> 936 <reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB" variants="A6XX-A7XX"/> 937 <reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB" variants="A6XX-A7XX"/> 938 <reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC" variants="A6XX-A7XX"/> 939 <reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC" variants="A6XX-A7XX"/> 940 <reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC" variants="A6XX-A7XX"/> 941 <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX"/> 942 <reg32 offset="0x00195" name="RBBM_CGC_0_PC" variants="A7XX"/> 943 <reg32 offset="0x0010b" name="RBBM_CGC_0_PC" variants="A8XX-"/> 944 945 <reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL" variants="A6XX-A7XX"/> 946 <reg32 offset="0x00009" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL" variants="A8XX-"/> 947 948 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/> 949 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/> 950 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/> 951 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A6XX"> 952 <bitfield high="7" low="0" name="PING_INDEX"/> 953 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 954 </reg32> 955 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A7XX-"> 956 <bitfield high="7" low="0" name="PING_INDEX"/> 957 <bitfield high="24" low="16" name="PING_BLK_SEL"/> 958 </reg32> 959 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT"> 960 <bitfield high="5" low="0" name="TRACEEN"/> 961 <bitfield high="14" low="12" name="GRANU"/> 962 <bitfield high="31" low="28" name="SEGT"/> 963 </reg32> 964 <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM"> 965 <bitfield high="27" low="24" name="ENABLE"/> 966 </reg32> 967 <reg32 offset="0x0606" name="DBGC_CFG_DBGBUS_OPL"/> 968 <reg32 offset="0x0607" name="DBGC_CFG_DBGBUS_OPE"/> 969 <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/> 970 <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/> 971 <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/> 972 <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/> 973 <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/> 974 <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/> 975 <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/> 976 <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/> 977 <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0"> 978 <bitfield high="3" low="0" name="BYTEL0"/> 979 <bitfield high="7" low="4" name="BYTEL1"/> 980 <bitfield high="11" low="8" name="BYTEL2"/> 981 <bitfield high="15" low="12" name="BYTEL3"/> 982 <bitfield high="19" low="16" name="BYTEL4"/> 983 <bitfield high="23" low="20" name="BYTEL5"/> 984 <bitfield high="27" low="24" name="BYTEL6"/> 985 <bitfield high="31" low="28" name="BYTEL7"/> 986 </reg32> 987 <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1"> 988 <bitfield high="3" low="0" name="BYTEL8"/> 989 <bitfield high="7" low="4" name="BYTEL9"/> 990 <bitfield high="11" low="8" name="BYTEL10"/> 991 <bitfield high="15" low="12" name="BYTEL11"/> 992 <bitfield high="19" low="16" name="BYTEL12"/> 993 <bitfield high="23" low="20" name="BYTEL13"/> 994 <bitfield high="27" low="24" name="BYTEL14"/> 995 <bitfield high="31" low="28" name="BYTEL15"/> 996 </reg32> 997 <reg32 offset="0x0612" name="DBGC_CFG_DBGBUS_IVTE_0"/> 998 <reg32 offset="0x0613" name="DBGC_CFG_DBGBUS_IVTE_1"/> 999 <reg32 offset="0x0614" name="DBGC_CFG_DBGBUS_IVTE_2"/> 1000 <reg32 offset="0x0615" name="DBGC_CFG_DBGBUS_IVTE_3"/> 1001 <reg32 offset="0x0616" name="DBGC_CFG_DBGBUS_MASKE_0"/> 1002 <reg32 offset="0x0617" name="DBGC_CFG_DBGBUS_MASKE_1"/> 1003 <reg32 offset="0x0618" name="DBGC_CFG_DBGBUS_MASKE_2"/> 1004 <reg32 offset="0x0619" name="DBGC_CFG_DBGBUS_MASKE_3"/> 1005 <reg32 offset="0x061a" name="DBGC_CFG_DBGBUS_NIBBLEE"/> 1006 <reg32 offset="0x061b" name="DBGC_CFG_DBGBUS_PTRC0"/> 1007 <reg32 offset="0x061c" name="DBGC_CFG_DBGBUS_PTRC1"/> 1008 <reg32 offset="0x061d" name="DBGC_CFG_DBGBUS_LOADREG"/> 1009 <reg32 offset="0x061e" name="DBGC_CFG_DBGBUS_IDX"/> 1010 <reg32 offset="0x061f" name="DBGC_CFG_DBGBUS_CLRC"/> 1011 <reg32 offset="0x0620" name="DBGC_CFG_DBGBUS_LOADIVT"/> 1012 <reg32 offset="0x0621" name="DBGC_VBIF_DBG_CNTL"/> 1013 <reg32 offset="0x0622" name="DBGC_DBG_LO_HI_GPIO"/> 1014 <reg32 offset="0x0623" name="DBGC_EXT_TRACE_BUS_CNTL"/> 1015 <reg32 offset="0x0624" name="DBGC_READ_AHB_THROUGH_DBG"/> 1016 <reg32 offset="0x0625" name="DBGC_CFG_DBGBUS_EVENT_LOGIC"/> 1017 <reg32 offset="0x0626" name="DBGC_CFG_DBGBUS_OVER"/> 1018 <reg32 offset="0x0627" name="DBGC_CFG_DBGBUS_COUNT0"/> 1019 <reg32 offset="0x0628" name="DBGC_CFG_DBGBUS_COUNT1"/> 1020 <reg32 offset="0x0629" name="DBGC_CFG_DBGBUS_COUNT2"/> 1021 <reg32 offset="0x062a" name="DBGC_CFG_DBGBUS_COUNT3"/> 1022 <reg32 offset="0x062b" name="DBGC_CFG_DBGBUS_COUNT4"/> 1023 <reg32 offset="0x062c" name="DBGC_CFG_DBGBUS_COUNT5"/> 1024 <reg32 offset="0x062d" name="DBGC_CFG_DBGBUS_TRACE_ADDR"/> 1025 <reg32 offset="0x062e" name="DBGC_CFG_DBGBUS_TRACE_BUF0"/> 1026 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/> 1027 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/> 1028 <reg32 offset="0x0631" name="DBGC_CFG_DBGBUS_TRACE_BUF3"/> 1029 <reg32 offset="0x0632" name="DBGC_CFG_DBGBUS_TRACE_BUF4"/> 1030 <reg32 offset="0x0633" name="DBGC_CFG_DBGBUS_MISR0"/> 1031 <reg32 offset="0x0634" name="DBGC_CFG_DBGBUS_MISR1"/> 1032 <reg32 offset="0x0635" name="DBGC_EVT_CFG"/> 1033 <reg32 offset="0x0636" name="DBGC_EVT_INTF_SEL_0"/> 1034 <reg32 offset="0x0637" name="DBGC_EVT_INTF_SEL_1"/> 1035 <reg32 offset="0x0638" name="DBGC_EVT_SLICE_CFG"/> 1036 <reg32 offset="0x0639" name="DBGC_QDSS_TIMESTAMP_0"/> 1037 <reg32 offset="0x063a" name="DBGC_QDSS_TIMESTAMP_1"/> 1038 <reg32 offset="0x063b" name="DBGC_ECO_CNTL"/> 1039 <reg32 offset="0x063c" name="DBGC_AHB_DBG_CNTL"/> 1040 <reg32 offset="0x063d" name="DBGC_EVT_INTF_SEL_2"/> 1041 <reg32 offset="0x0640" name="DBGC_CFG_DBGBUS_PONG_SEL_A"/> 1042 <reg32 offset="0x0641" name="DBGC_CFG_DBGBUS_PONG_SEL_B"/> 1043 <reg32 offset="0x0642" name="DBGC_CFG_DBGBUS_PONG_SEL_C"/> 1044 <reg32 offset="0x0643" name="DBGC_CFG_DBGBUS_PONG_SEL_D"/> 1045 <reg32 offset="0x0644" name="DBGC_CFG_DBGBUS_MISC_MODE"/> 1046 <reg32 offset="0x0650" name="DBGC_EVT_INTF_SEL_3_0"/> 1047 <reg32 offset="0x0651" name="DBGC_EVT_INTF_SEL_3_1"/> 1048 <reg32 offset="0x0652" name="DBGC_EVT_INTF_SEL_3_2"/> 1049 <reg32 offset="0x0653" name="DBGC_EVT_INTF_SEL_3_3"/> 1050 <reg32 offset="0x0654" name="DBGC_EVT_INTF_SEL_3_4"/> 1051 <reg32 offset="0x0655" name="DBGC_EVT_INTF_SEL_3_5"/> 1052 <reg32 offset="0x0660" name="DBGC_TRACE_BUFFER_STATUS"/> 1053 <reg32 offset="0x0661" name="DBGC_TRACE_BUFFER_CMD"/> 1054 <reg32 offset="0x0662" name="DBGC_DBG_TRACE_BUFFER_RD_ADDR"/> 1055 <reg32 offset="0x0663" name="DBGC_DBG_TRACE_BUFFER_RD_DATA"/> 1056 <reg32 offset="0x0664" name="DBGC_TRACE_BUFFER_ATB_RD_STATUS"/> 1057 <reg32 offset="0x0665" name="DBGC_SMMU_FAULT_BLOCK_HALT_CFG"/> 1058 <reg32 offset="0x0666" name="DBGC_DBG_LOPC_SB_RD_ADDR"/> 1059 <reg32 offset="0x0667" name="DBGC_DBG_LOPC_SB_RD_DATA"/> 1060 <reg32 offset="0x0668" name="DBGC_DBG_LOPC_SB_WR_ADDR"/> 1061 <reg32 offset="0x0669" name="DBGC_DBG_LOPC_SB_WR_DATA"/> 1062 <reg32 offset="0x066a" name="DBGC_INTERRUPT_STATUS"/> 1063 <reg64 offset="0x0680" name="DBGC_GBIF_DBG_BASE"/> 1064 <reg32 offset="0x0682" name="DBGC_GBIF_DBG_BUFF_SIZE"/> 1065 <reg32 offset="0x0683" name="DBGC_GBIF_DBG_CNTL"/> 1066 <reg32 offset="0x0684" name="DBGC_GBIF_DBG_CMD"/> 1067 <reg32 offset="0x0685" name="DBGC_GBIF_DBG_STATUS"/> 1068 1069 <reg32 offset="0x0700" name="DBGC_SCOPE_PERF_COUNTER_CFG_US" variants="A8XX-"/> 1070 <reg32 offset="0x0701" name="DBGC_CFG_PERF_TRIG_CLUSTER_FE_US" variants="A8XX-"/> 1071 <reg32 offset="0x0702" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_US" variants="A8XX-"/> 1072 <reg32 offset="0x0703" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS_US" variants="A8XX-"/> 1073 <reg32 offset="0x0704" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS_US" variants="A8XX-"/> 1074 <reg32 offset="0x0707" name="DBGC_CFG_PERF_TRIG_CLUSTER_NONE_US" variants="A8XX-"/> 1075 <reg32 offset="0x0708" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_US" variants="A8XX-"/> 1076 <reg32 offset="0x0709" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_US" variants="A8XX-"/> 1077 <reg32 offset="0x070a" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS_US" variants="A8XX-"/> 1078 <reg32 offset="0x070f" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_NONE_US" variants="A8XX-"/> 1079 <reg32 offset="0x0710" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US" variants="A8XX-"/> 1080 <reg32 offset="0x0711" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US_1" variants="A8XX-"/> 1081 <reg32 offset="0x0712" name="DBGC_CFG_PERF_COUNTER_SEL_FE_US_2" variants="A8XX-"/> 1082 <reg32 offset="0x0713" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_US" variants="A8XX-"/> 1083 <reg32 offset="0x0714" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_US_1" variants="A8XX-"/> 1084 <reg32 offset="0x0715" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_US" variants="A8XX-"/> 1085 <reg32 offset="0x0716" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_US" variants="A8XX-"/> 1086 <reg32 offset="0x0720" name="DBGC_CFG_PERF_COUNTER_SEL_NONE_US" variants="A8XX-"/> 1087 <reg32 offset="0x0721" name="DBGC_CFG_PERF_COUNTER_SEL_NONE_US_1" variants="A8XX-"/> 1088 <reg32 offset="0x0722" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US" variants="A8XX-"/> 1089 <reg32 offset="0x0723" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_1" variants="A8XX-"/> 1090 <reg32 offset="0x0724" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_US_2" variants="A8XX-"/> 1091 <reg32 offset="0x0730" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US" variants="A8XX-"/> 1092 <reg32 offset="0x0731" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_US_1" variants="A8XX-"/> 1093 <reg32 offset="0x0732" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_US" variants="A8XX-"/> 1094 <reg32 offset="0x0740" name="DBGC_CFG_BV_PERF_COUNTER_SEL_NONE_US" variants="A8XX-"/> 1095 <reg32 offset="0x0742" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_US" variants="A8XX-"/> 1096 <reg32 offset="0x0743" name="DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_US" variants="A8XX-"/> 1097 <reg64 offset="0x0744" name="DBGC_CFG_GBIF_BR_PERF_CNTR_BASE" variants="A8XX-"/> 1098 <reg32 offset="0x0746" name="DBGC_CFG_GBIF_BR_BUFFER_SIZE" variants="A8XX-"/> 1099 <reg64 offset="0x0747" name="DBGC_CFG_GBIF_BV_PERF_CNTR_BASE" variants="A8XX-"/> 1100 <reg32 offset="0x0749" name="DBGC_CFG_GBIF_BV_BUFFER_SIZE" variants="A8XX-"/> 1101 <reg32 offset="0x074a" name="DBGC_CFG_GBIF_QOS_CTRL" variants="A8XX-"/> 1102 <reg32 offset="0x0750" name="DBGC_GBIF_BR_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/> 1103 <reg32 offset="0x0751" name="DBGC_GBIF_BV_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/> 1104 <reg32 offset="0x0752" name="DBGC_PERF_COUNTER_FE_LOCAL_BATCH_ID" variants="A8XX-"/> 1105 <reg32 offset="0x0753" name="DBGC_CFG_PERF_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/> 1106 <reg32 offset="0x0754" name="DBGC_PERF_COUNTER_SCOPING_CMD_US" variants="A8XX-"/> 1107 <reg32 offset="0x0755" name="DBGC_PERF_SKEW_BUFFER_INIT_CMD" variants="A8XX-"/> 1108 <reg32 offset="0x0759" name="DBGC_LOPC_INTERRUPT_STATUS" variants="A8XX-"/> 1109 <reg32 offset="0x075a" name="DBGC_LOPC_BUFFER_PTR_STATUS" variants="A8XX-"/> 1110 <reg32 offset="0x075b" name="DBGC_PERF_SCOPING_STATUS" variants="A8XX-"/> 1111 <reg32 offset="0x075c" name="DBGC_PERF_COUNTER_PKT_STATUS" variants="A8XX-"/> 1112 <reg32 offset="0x0760" name="DBGC_GC_LIVE_MBX_PKT_STATUS" variants="A8XX-"/> 1113 <reg32 offset="0x0761" name="DBGC_GC_ALW_MBX_PKT_STATUS" variants="A8XX-"/> 1114 <reg32 offset="0x0762" name="DBGC_AO_CNTR_LO_STATUS" variants="A8XX-"/> 1115 <reg32 offset="0x0763" name="DBGC_AO_CNTR_HI_STATUS" variants="A8XX-"/> 1116 <reg32 offset="0x0770" name="DBGC_LOPC_GC_SB_DEPTH_STATUS" variants="A8XX-"/> 1117 <reg32 offset="0x0780" name="DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_US" variants="A8XX-"/> 1118 <reg32 offset="0x0781" name="DBGC_CFG_PERF_TRIG_LPAC_US" variants="A8XX-"/> 1119 <reg32 offset="0x0782" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US" variants="A8XX-"/> 1120 <reg32 offset="0x0783" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_1" variants="A8XX-"/> 1121 <reg32 offset="0x0784" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_US_2" variants="A8XX-"/> 1122 <reg32 offset="0x0785" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_US" variants="A8XX-"/> 1123 <reg64 offset="0x0786" name="DBGC_CFG_GBIF_LPAC_PERF_CNTR_BASE" variants="A8XX-"/> 1124 <reg32 offset="0x0788" name="DBGC_CFG_GBIF_LPAC_BUFFER_SIZE" variants="A8XX-"/> 1125 <reg32 offset="0x0789" name="DBGC_GBIF_LPAC_PERF_CNTR_WRITE_POINTER" variants="A8XX-"/> 1126 <reg32 offset="0x078a" name="DBGC_CFG_LPAC_PERF_WAIT_IDLE_CLOCKS_CNTL" variants="A8XX-"/> 1127 <reg32 offset="0x078b" name="DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_US" variants="A8XX-"/> 1128 <reg32 offset="0x078c" name="DBGC_LPAC_MBX_PKT_STATUS" variants="A8XX-"/> 1129 <reg32 offset="0x078d" name="DBGC_LPAC_PERF_SCOPING_STATUS" variants="A8XX-"/> 1130 <reg32 offset="0x0790" name="DBGC_LOPC_LPAC_SB_DEPTH_STATUS" variants="A8XX-"/> 1131 <reg32 offset="0x07a0" name="DBGC_SCOPE_PERF_COUNTER_CFG_S" variants="A8XX-"/> 1132 <reg32 offset="0x07a1" name="DBGC_CFG_PERF_TRIG_CLUSTER_FE_S" variants="A8XX-"/> 1133 <reg32 offset="0x07a2" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_VS" variants="A8XX-"/> 1134 <reg32 offset="0x07a3" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_VS" variants="A8XX-"/> 1135 <reg32 offset="0x07a4" name="DBGC_CFG_PERF_TRIG_CLUSTER_GRAS" variants="A8XX-"/> 1136 <reg32 offset="0x07a5" name="DBGC_CFG_PERF_TRIG_CLUSTER_SP_PS" variants="A8XX-"/> 1137 <reg32 offset="0x07a6" name="DBGC_CFG_PERF_TRIG_CLUSTER_VPC_PS" variants="A8XX-"/> 1138 <reg32 offset="0x07a7" name="DBGC_CFG_PERF_TRIG_CLUSTER_PS" variants="A8XX-"/> 1139 <reg32 offset="0x07a8" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_FE_S" variants="A8XX-"/> 1140 <reg32 offset="0x07a9" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_SP_VS" variants="A8XX-"/> 1141 <reg32 offset="0x07aa" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_VS" variants="A8XX-"/> 1142 <reg32 offset="0x07ab" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_GRAS" variants="A8XX-"/> 1143 <reg32 offset="0x07ac" name="DBGC_CFG_BV_PERF_TRIG_CLUSTER_VPC_PS" variants="A8XX-"/> 1144 <reg32 offset="0x07ad" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S" variants="A8XX-"/> 1145 <reg32 offset="0x07ae" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_1" variants="A8XX-"/> 1146 <reg32 offset="0x07af" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_2" variants="A8XX-"/> 1147 <reg32 offset="0x07b0" name="DBGC_CFG_PERF_COUNTER_SEL_FE_S_3" variants="A8XX-"/> 1148 <reg32 offset="0x07b1" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS" variants="A8XX-"/> 1149 <reg32 offset="0x07b2" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_1" variants="A8XX-"/> 1150 <reg32 offset="0x07b3" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_2" variants="A8XX-"/> 1151 <reg32 offset="0x07b4" name="DBGC_CFG_PERF_COUNTER_SEL_SP_VS_3" variants="A8XX-"/> 1152 <reg32 offset="0x07b5" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_VS" variants="A8XX-"/> 1153 <reg32 offset="0x07b6" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_VS_1" variants="A8XX-"/> 1154 <reg32 offset="0x07b7" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS" variants="A8XX-"/> 1155 <reg32 offset="0x07b8" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS_1" variants="A8XX-"/> 1156 <reg32 offset="0x07b9" name="DBGC_CFG_PERF_COUNTER_SEL_GRAS_2" variants="A8XX-"/> 1157 <reg32 offset="0x07ba" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS" variants="A8XX-"/> 1158 <reg32 offset="0x07bb" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_1" variants="A8XX-"/> 1159 <reg32 offset="0x07bc" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_2" variants="A8XX-"/> 1160 <reg32 offset="0x07bd" name="DBGC_CFG_PERF_COUNTER_SEL_SP_PS_3" variants="A8XX-"/> 1161 <reg32 offset="0x07be" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_PS" variants="A8XX-"/> 1162 <reg32 offset="0x07bf" name="DBGC_CFG_PERF_COUNTER_SEL_VPC_PS_1" variants="A8XX-"/> 1163 <reg32 offset="0x07c0" name="DBGC_CFG_PERF_COUNTER_SEL_PS" variants="A8XX-"/> 1164 <reg32 offset="0x07c1" name="DBGC_CFG_PERF_COUNTER_SEL_PS_1" variants="A8XX-"/> 1165 <reg32 offset="0x07c2" name="DBGC_CFG_PERF_COUNTER_SEL_PS_2" variants="A8XX-"/> 1166 <reg32 offset="0x07c3" name="DBGC_CFG_PERF_COUNTER_SEL_PS_3" variants="A8XX-"/> 1167 <reg32 offset="0x07c4" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_S" variants="A8XX-"/> 1168 <reg32 offset="0x07c5" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S" variants="A8XX-"/> 1169 <reg32 offset="0x07c6" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_1" variants="A8XX-"/> 1170 <reg32 offset="0x07c7" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_2" variants="A8XX-"/> 1171 <reg32 offset="0x07c8" name="DBGC_CFG_BV_PERF_COUNTER_SEL_FE_S_3" variants="A8XX-"/> 1172 <reg32 offset="0x07c9" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS" variants="A8XX-"/> 1173 <reg32 offset="0x07ca" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_1" variants="A8XX-"/> 1174 <reg32 offset="0x07cb" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_2" variants="A8XX-"/> 1175 <reg32 offset="0x07cc" name="DBGC_CFG_BV_PERF_COUNTER_SEL_SP_VS_3" variants="A8XX-"/> 1176 <reg32 offset="0x07cd" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS" variants="A8XX-"/> 1177 <reg32 offset="0x07ce" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_VS_1" variants="A8XX-"/> 1178 <reg32 offset="0x07cf" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS" variants="A8XX-"/> 1179 <reg32 offset="0x07d0" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_1" variants="A8XX-"/> 1180 <reg32 offset="0x07d1" name="DBGC_CFG_BV_PERF_COUNTER_SEL_GRAS_2" variants="A8XX-"/> 1181 <reg32 offset="0x07d2" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS" variants="A8XX-"/> 1182 <reg32 offset="0x07d3" name="DBGC_CFG_BV_PERF_COUNTER_SEL_VPC_PS_1" variants="A8XX-"/> 1183 <reg32 offset="0x07d4" name="DBGC_CFG_BV_PERF_TIMESTAMP_TRIG_SEL_S" variants="A8XX-"/> 1184 <reg32 offset="0x07d5" name="DBGC_PERF_COUNTER_SCOPING_CMD_S" variants="A8XX-"/> 1185 <reg32 offset="0x07e0" name="DBGC_LPAC_SCOPE_PERF_COUNTER_CFG_S" variants="A8XX-"/> 1186 <reg32 offset="0x07e1" name="DBGC_CFG_PERF_TRIG_LPAC_S" variants="A8XX-"/> 1187 <reg32 offset="0x07e2" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S" variants="A8XX-"/> 1188 <reg32 offset="0x07e3" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_1" variants="A8XX-"/> 1189 <reg32 offset="0x07e4" name="DBGC_CFG_PERF_COUNTER_SEL_LPAC_S_2" variants="A8XX-"/> 1190 <reg32 offset="0x07e5" name="DBGC_CFG_PERF_TIMESTAMP_TRIG_SEL_LPAC_S" variants="A8XX-"/> 1191 <reg32 offset="0x07e6" name="DBGC_LPAC_PERF_COUNTER_SCOPING_CMD_S" variants="A8XX-"/> 1192 1193 <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/> 1194 <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/> 1195 <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/> 1196 <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 1197 <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/> 1198 <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX" variants="A6XX"/> 1199 <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE" variants="A6XX-A7XX"/> 1200 <reg64 offset="0x0E06" name="UCHE_WRITE_THRU_BASE" variants="A8XX-"/> 1201 <reg64 offset="0x0E09" name="UCHE_TRAP_BASE" variants="A6XX-A7XX"/> 1202 <reg64 offset="0x0E08" name="UCHE_TRAP_BASE" variants="A8XX-"/> 1203 <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN" variants="A6XX-A7XX"/> 1204 <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX" variants="A6XX-A7XX"/> 1205 <reg32 offset="0x0e17" name="UCHE_CACHE_WAYS" variants="A6XX-A7XX" usage="init"/> 1206 <reg32 offset="0x0e04" name="UCHE_CACHE_WAYS" variants="A8XX-"/> 1207 <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/> 1208 <reg32 offset="0x0e19" name="UCHE_CLIENT_PF" variants="A6XX-A7XX" usage="init"> 1209 <bitfield high="7" low="0" name="PERFSEL"/> 1210 </reg32> 1211 <array offset="0x0e1c" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12" variants="A6XX-A7XX"/> 1212 <array offset="0x0e20" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="24" variants="A8XX-"/> 1213 <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG" variants="A6XX-A7XX"/> 1214 <reg32 offset="0x0e12" name="UCHE_GBIF_GX_CONFIG" variants="A8XX-"/> 1215 <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG" variants="A6XX-A7XX"/> 1216 1217 <reg32 offset="0x0f01" name="UCHE_CCHE_MODE_CNTL" variants="A8XX-"/> 1218 <reg32 offset="0x0f02" name="UCHE_CCHE_CACHE_WAYS" variants="A8XX-"/> 1219 <reg64 offset="0x0f04" name="UCHE_CCHE_WRITE_THRU_BASE" variants="A8XX-"/> 1220 <reg64 offset="0x0f06" name="UCHE_CCHE_TRAP_BASE" variants="A8XX-"/> 1221 <reg64 offset="0x0f08" name="UCHE_CCHE_GC_GMEM_RANGE_MIN" variants="A8XX-"/> 1222 <reg64 offset="0x0f0a" name="UCHE_CCHE_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/> 1223 <reg32 offset="0x0f0c" name="UCHE_CCHE_HW_DBG_CNTL" variants="A8XX-"/> 1224 1225 <!-- VBIF only existed on early a6xx, and was later replaced with GBIF --> 1226 1227 <reg32 offset="0x3000" name="VBIF_VERSION" variants="A6XX"/> 1228 <reg32 offset="0x3001" name="VBIF_CLKON" variants="A6XX"> 1229 <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/> 1230 </reg32> 1231 <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN" variants="A6XX"/> 1232 <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0" variants="A6XX"/> 1233 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1" variants="A6XX"/> 1234 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL" variants="A6XX"/> 1235 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0" variants="A6XX"/> 1236 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1" variants="A6XX"> 1237 <bitfield low="0" high="3" name="DATA_SEL"/> 1238 </reg32> 1239 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0" variants="A6XX"/> 1240 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1" variants="A6XX"> 1241 <bitfield low="0" high="8" name="DATA_SEL"/> 1242 </reg32> 1243 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT" variants="A6XX"/> 1244 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" variants="A6XX"/> 1245 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" variants="A6XX"/> 1246 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" variants="A6XX"/> 1247 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" variants="A6XX"/> 1248 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0" variants="A6XX"/> 1249 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1" variants="A6XX"/> 1250 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2" variants="A6XX"/> 1251 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3" variants="A6XX"/> 1252 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0" variants="A6XX"/> 1253 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1" variants="A6XX"/> 1254 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2" variants="A6XX"/> 1255 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3" variants="A6XX"/> 1256 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0" variants="A6XX"/> 1257 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1" variants="A6XX"/> 1258 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2" variants="A6XX"/> 1259 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0" variants="A6XX"/> 1260 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1" variants="A6XX"/> 1261 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2" variants="A6XX"/> 1262 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0" variants="A6XX"/> 1263 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1" variants="A6XX"/> 1264 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2" variants="A6XX"/> 1265 1266 <reg32 offset="0x3c00" name="GBIF_CX_CONFIG" variants="A8XX-"/> 1267 <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/> 1268 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/> 1269 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/> 1270 <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/> 1271 <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/> 1272 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/> 1273 <reg32 offset="0x3c45" name="GBIF_HALT"/> 1274 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/> 1275 <reg32 offset="0x3c49" name="GBIF_REINIT_ENABLE" variants="A8XX-"/> 1276 <reg32 offset="0x3c4a" name="GBIF_REINIT_DONE" variants="A8XX-"/> 1277 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/> 1278 <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/> 1279 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/> 1280 <reg32 offset="0x3cc3" name="GBIF_PERF_CNT_SEL_1" variants="A8XX-"/> 1281 1282 <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL" variants="A6XX-A7XX"/> 1283 <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0" variants="A6XX-A7XX"/> 1284 <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1" variants="A6XX-A7XX"/> 1285 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2" variants="A6XX-A7XX"/> 1286 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3" variants="A6XX-A7XX"/> 1287 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0" variants="A6XX-A7XX"/> 1288 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1" variants="A6XX-A7XX"/> 1289 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2" variants="A6XX-A7XX"/> 1290 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3" variants="A6XX-A7XX"/> 1291 <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0" variants="A6XX-A7XX"/> 1292 <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1" variants="A6XX-A7XX"/> 1293 <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2" variants="A6XX-A7XX"/> 1294 <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0" variants="A6XX-A7XX"/> 1295 <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1" variants="A6XX-A7XX"/> 1296 <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2" variants="A6XX-A7XX"/> 1297 1298 <reg32 offset="0x3cc4" name="GBIF_PWR_CNT_SEL" variants="A8XX"/> 1299 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LO_0" variants="A8XX"/> 1300 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_HI_0" variants="A8XX"/> 1301 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_LO_1" variants="A8XX"/> 1302 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HI_1" variants="A8XX"/> 1303 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_LO_2" variants="A8XX"/> 1304 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HI_2" variants="A8XX"/> 1305 <reg32 offset="0x3ccc" name="GBIF_PERF_CNT_LO_3" variants="A8XX"/> 1306 <reg32 offset="0x3ccd" name="GBIF_PERF_CNT_HI_3" variants="A8XX"/> 1307 <reg32 offset="0x3cce" name="GBIF_PERF_CNT_LO_4" variants="A8XX"/> 1308 <reg32 offset="0x3ccf" name="GBIF_PERF_CNT_HI_4" variants="A8XX"/> 1309 <reg32 offset="0x3cd0" name="GBIF_PERF_CNT_LO_5" variants="A8XX"/> 1310 <reg32 offset="0x3cd1" name="GBIF_PERF_CNT_HI_5" variants="A8XX"/> 1311 <reg32 offset="0x3cd2" name="GBIF_PERF_CNT_LO_6" variants="A8XX"/> 1312 <reg32 offset="0x3cd3" name="GBIF_PERF_CNT_HI_6" variants="A8XX"/> 1313 <reg32 offset="0x3cd4" name="GBIF_PERF_CNT_LO_7" variants="A8XX"/> 1314 <reg32 offset="0x3cd5" name="GBIF_PERF_CNT_HI_7" variants="A8XX"/> 1315 <reg32 offset="0x3ce0" name="GBIF_PWR_CNT_LO_0" variants="A8XX"/> 1316 <reg32 offset="0x3ce1" name="GBIF_PWR_CNT_LO_1" variants="A8XX"/> 1317 <reg32 offset="0x3ce2" name="GBIF_PWR_CNT_LO_2" variants="A8XX"/> 1318 <reg32 offset="0x3ce3" name="GBIF_PWR_CNT_HI_0" variants="A8XX"/> 1319 <reg32 offset="0x3ce4" name="GBIF_PWR_CNT_HI_1" variants="A8XX"/> 1320 <reg32 offset="0x3ce5" name="GBIF_PWR_CNT_HI_2" variants="A8XX"/> 1321 1322 <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/> 1323 <reg32 offset="0x0df0" name="VSC_KMD_DBG_ECO_CNTL" variants="A8XX-"/> 1324 <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit" variants="A6XX-A7XX"> 1325 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/> 1326 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/> 1327 </reg32> 1328 1329 <bitset name="a8xx_bin_size" inline="yes"> 1330 <bitfield name="BINW" low="0" high="9" shr="5" type="uint"/> 1331 <bitfield name="BINH" low="16" high="26" shr="4" type="uint"/> 1332 </bitset> 1333 1334 <reg32 offset="0x0c02" name="VSC_BIN_SIZE" type="a8xx_bin_size" usage="rp_blit" variants="A8XX"/> 1335 <reg64 offset="0x0c03" name="VSC_SIZE_BASE" type="waddress" usage="cmd"/> 1336 <reg32 offset="0x0c06" name="VSC_EXPANDED_BIN_CNTL" usage="rp_blit"> 1337 <bitfield name="NX" low="1" high="10" type="uint"/> 1338 <bitfield name="NY" low="11" high="20" type="uint"/> 1339 </reg32> 1340 <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="rp_blit"> 1341 <reg32 offset="0x0" name="REG"> 1342 <doc> 1343 Configures the mapping between VSC_PIPE buffer and 1344 bin, X/Y specify the bin index in the horiz/vert 1345 direction (0,0 is upper left, 0,1 is leftmost bin 1346 on second row, and so on). W/H specify the number 1347 of bins assigned to this VSC_PIPE in the horiz/vert 1348 dimension. 1349 </doc> 1350 <bitfield name="X" low="0" high="9" type="uint"/> 1351 <bitfield name="Y" low="10" high="19" type="uint"/> 1352 <bitfield name="W" low="20" high="25" type="uint"/> 1353 <bitfield name="H" low="26" high="31" type="uint"/> 1354 </reg32> 1355 </array> 1356 <!-- 1357 HW binning primitive & draw streams, which enable draws and primitives 1358 within a draw to be skipped in the main tile pass. See: 1359 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format 1360 1361 Compared to a5xx and earlier, we just program the address of the first 1362 stream and hw adds (pipe_num * VSC_*_STRM_PITCH) 1363 1364 LIMIT is set to PITCH - 64, to make room for a bit of overflow 1365 --> 1366 <reg64 offset="0x0c30" name="VSC_PIPE_DATA_PRIM_BASE" type="waddress" usage="cmd"/> 1367 <reg32 offset="0x0c32" name="VSC_PIPE_DATA_PRIM_STRIDE" usage="cmd"/> 1368 <reg32 offset="0x0c33" name="VSC_PIPE_DATA_PRIM_LENGTH" usage="cmd"/> 1369 <reg64 offset="0x0c34" name="VSC_PIPE_DATA_DRAW_BASE" type="waddress" usage="cmd"/> 1370 <reg32 offset="0x0c36" name="VSC_PIPE_DATA_DRAW_STRIDE" usage="cmd"/> 1371 <reg32 offset="0x0c37" name="VSC_PIPE_DATA_DRAW_LENGTH" usage="cmd"/> 1372 1373 <array offset="0x0c38" name="VSC_CHANNEL_VISIBILITY" stride="1" length="32" usage="rp_blit"> 1374 <doc> 1375 Seems to be a bitmap of which tiles mapped to the VSC 1376 pipe contain geometry. 1377 1378 I suppose we can connect a maximum of 32 tiles to a 1379 single VSC pipe. 1380 </doc> 1381 <reg32 offset="0x0" name="REG"/> 1382 </array> 1383 1384 <array offset="0x0c58" name="VSC_PIPE_DATA_PRIM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 1385 <doc> 1386 Has the size of data written to corresponding VSC_PRIM_STRM 1387 buffer. 1388 </doc> 1389 <reg32 offset="0x0" name="REG"/> 1390 </array> 1391 1392 <array offset="0x0c78" name="VSC_PIPE_DATA_DRAW_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 1393 <doc> 1394 Has the size of data written to corresponding VSC pipe, ie. 1395 same thing that is written out to VSC_SIZE_BASE 1396 </doc> 1397 <reg32 offset="0x0" name="REG"/> 1398 </array> 1399 1400 <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/> 1401 1402 <reg32 offset="0x0e10" name="UCHE_UNKNOWN_0E10" variants="A7XX" usage="init"/> 1403 <reg32 offset="0x0e10" name="UCHE_VARB_IDLE_TIMEOUT" variants="A8XX-"/> 1404 <reg32 offset="0x0e11" name="UCHE_UNKNOWN_0E11" variants="A7XX" usage="init"/> 1405 <reg32 offset="0x0e11" name="UCHE_CLIENT_PF" variants="A8XX-"/> 1406 <!-- always 0x03200000 ? --> 1407 <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" variants="A6XX-A7XX" usage="init"/> 1408 <reg32 offset="0x0e15" name="UCHE_DBG_ECO_CNTL_0" variants="A8XX-"/> 1409 <reg32 offset="0x0e16" name="UCHE_HW_DBG_CNTL" variants="A8XX-"/> 1410 1411 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 --> 1412 <bitset name="a6xx_reg_xy" inline="yes"> 1413 <bitfield name="X" low="0" high="13" type="uint"/> 1414 <bitfield name="Y" low="16" high="29" type="uint"/> 1415 </bitset> 1416 1417 <bitset name="a6xx_gras_cl_cntl" inline="yes"> 1418 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/> 1419 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/> 1420 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/> 1421 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> 1422 <!-- controls near z clip behavior (set for vulkan) --> 1423 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/> 1424 <!-- guess based on a3xx and meaning of bits 8 and 9 1425 if the guess is right then this is related to point sprite clipping --> 1426 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/> 1427 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/> 1428 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/> 1429 </bitset> 1430 1431 <reg32 offset="0x8000" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1432 <reg32 offset="0x8200" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A8XX-" usage="rp_blit"/> 1433 1434 <bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes"> 1435 <bitfield name="CLIP_MASK" low="0" high="7"/> 1436 <bitfield name="CULL_MASK" low="8" high="15"/> 1437 </bitset> 1438 <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 1439 <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 1440 <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 1441 <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit" variants="A6XX-A7XX" /> 1442 1443 <reg32 offset="0x8201" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" /> 1444 <reg32 offset="0x8202" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" /> 1445 <reg32 offset="0x8203" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A8XX" /> 1446 <reg32 offset="0x8204" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit" variants="A8XX" /> 1447 1448 <reg32 offset="0x8228" name="GRAS_UNKNOWN_8228" variants="A8XX-"/> 1449 <reg32 offset="0x8229" name="GRAS_UNKNOWN_8229" variants="A8XX-"/> 1450 <reg32 offset="0x822a" name="GRAS_UNKNOWN_822A" variants="A8XX-"/> 1451 <reg32 offset="0x822b" name="GRAS_UNKNOWN_822B" variants="A8XX-"/> 1452 <reg32 offset="0x822c" name="GRAS_UNKNOWN_822C" variants="A8XX-"/> 1453 <reg32 offset="0x822d" name="GRAS_UNKNOWN_822D" variants="A8XX-"/> 1454 1455 <bitset name="a6xx_gras_cl_interp_cntl" inline="yes"> 1456 <!-- see also RB_INTERP_CNTL --> 1457 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 1458 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 1459 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 1460 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 1461 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 1462 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 1463 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 1464 <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/> 1465 <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/> 1466 </bitset> 1467 1468 <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1469 <reg32 offset="0x8080" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A8XX-" usage="rp_blit"/> 1470 1471 <bitset name="a6xx_gras_cl_guardband_clip_adj" inline="true"> 1472 <bitfield name="HORZ" low="0" high="8" type="uint"/> 1473 <bitfield name="VERT" low="10" high="18" type="uint"/> 1474 </bitset> 1475 1476 <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A6XX-A7XX" usage="rp_blit"/> 1477 <reg32 offset="0x8205" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A8XX-" usage="rp_blit"/> 1478 1479 <!-- the scale/offset is per view, with up to 6 views --> 1480 <bitset name="a6xx_gras_bin_foveat" inline="yes"> 1481 <bitfield name="BINSCALEEN" pos="6" type="boolean"/> 1482 <enum name="a7xx_bin_scale"> 1483 <value value="0" name="NOSCALE"/> 1484 <value value="1" name="SCALE2X"/> 1485 <value value="2" name="SCALE4X"/> 1486 </enum> 1487 <bitfield name="XSCALE_0" low="8" high="9" type="a7xx_bin_scale"/> 1488 <bitfield name="YSCALE_0" low="10" high="11" type="a7xx_bin_scale"/> 1489 <bitfield name="XSCALE_1" low="12" high="13" type="a7xx_bin_scale"/> 1490 <bitfield name="YSCALE_1" low="14" high="15" type="a7xx_bin_scale"/> 1491 <bitfield name="XSCALE_2" low="16" high="17" type="a7xx_bin_scale"/> 1492 <bitfield name="YSCALE_2" low="18" high="19" type="a7xx_bin_scale"/> 1493 <bitfield name="XSCALE_3" low="20" high="21" type="a7xx_bin_scale"/> 1494 <bitfield name="YSCALE_3" low="22" high="23" type="a7xx_bin_scale"/> 1495 <bitfield name="XSCALE_4" low="24" high="25" type="a7xx_bin_scale"/> 1496 <bitfield name="YSCALE_4" low="26" high="27" type="a7xx_bin_scale"/> 1497 <bitfield name="XSCALE_5" low="28" high="29" type="a7xx_bin_scale"/> 1498 <bitfield name="YSCALE_5" low="30" high="31" type="a7xx_bin_scale"/> 1499 </bitset> 1500 1501 <reg32 offset="0x8008" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A7XX" usage="cmd"/> 1502 <reg32 offset="0x8206" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A8XX-" usage="cmd"/> 1503 1504 <reg32 offset="0x8009" name="GRAS_BIN_FOVEAT_OFFSET_0" variants="A7XX-" usage="cmd"> 1505 <bitfield name="XOFFSET_0" low="0" high="9" shr="2" type="uint"/> 1506 <bitfield name="XOFFSET_1" low="10" high="19" shr="2" type="uint"/> 1507 <bitfield name="XOFFSET_2" low="20" high="29" shr="2" type="uint"/> 1508 </reg32> 1509 <reg32 offset="0x800a" name="GRAS_BIN_FOVEAT_OFFSET_1" variants="A7XX-" usage="cmd"> 1510 <bitfield name="XOFFSET_3" low="0" high="9" shr="2" type="uint"/> 1511 <bitfield name="XOFFSET_4" low="10" high="19" shr="2" type="uint"/> 1512 <bitfield name="XOFFSET_5" low="20" high="29" shr="2" type="uint"/> 1513 </reg32> 1514 <reg32 offset="0x800b" name="GRAS_BIN_FOVEAT_OFFSET_2" variants="A7XX-" usage="cmd"> 1515 <bitfield name="YOFFSET_0" low="0" high="9" shr="2" type="uint"/> 1516 <bitfield name="YOFFSET_1" low="10" high="19" shr="2" type="uint"/> 1517 <bitfield name="YOFFSET_2" low="20" high="29" shr="2" type="uint"/> 1518 </reg32> 1519 <reg32 offset="0x800c" name="GRAS_BIN_FOVEAT_OFFSET_3" variants="A7XX-" usage="cmd"> 1520 <bitfield name="YOFFSET_3" low="0" high="9" shr="2" type="uint"/> 1521 <bitfield name="YOFFSET_4" low="10" high="19" shr="2" type="uint"/> 1522 <bitfield name="YOFFSET_5" low="20" high="29" shr="2" type="uint"/> 1523 </reg32> 1524 1525 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> --> 1526 1527 <!-- 0x8006-0x800f invalid --> 1528 <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" variants="A6XX-A7XX" usage="rp_blit"> 1529 <reg32 offset="0" name="XOFFSET" type="float"/> 1530 <reg32 offset="1" name="XSCALE" type="float"/> 1531 <reg32 offset="2" name="YOFFSET" type="float"/> 1532 <reg32 offset="3" name="YSCALE" type="float"/> 1533 <reg32 offset="4" name="ZOFFSET" type="float"/> 1534 <reg32 offset="5" name="ZSCALE" type="float"/> 1535 </array> 1536 1537 <array offset="0x82d0" name="GRAS_CL_VIEWPORT" stride="6" length="16" variants="A8XX-" usage="rp_blit"> 1538 <reg32 offset="0" name="XOFFSET" type="float"/> 1539 <reg32 offset="1" name="XSCALE" type="float"/> 1540 <reg32 offset="2" name="YOFFSET" type="float"/> 1541 <reg32 offset="3" name="YSCALE" type="float"/> 1542 <reg32 offset="4" name="ZOFFSET" type="float"/> 1543 <reg32 offset="5" name="ZSCALE" type="float"/> 1544 </array> 1545 1546 <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 1547 <reg32 offset="0" name="MIN" type="float"/> 1548 <reg32 offset="1" name="MAX" type="float"/> 1549 </array> 1550 <array offset="0x80c0" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A8XX-" usage="rp_blit"> 1551 <reg32 offset="0" name="MIN" type="float"/> 1552 <reg32 offset="1" name="MAX" type="float"/> 1553 </array> 1554 1555 <bitset name="a6xx_gras_su_cntl" varset="chip"> 1556 <bitfield name="CULL_FRONT" pos="0" type="boolean"/> 1557 <bitfield name="CULL_BACK" pos="1" type="boolean"/> 1558 <bitfield name="FRONT_CW" pos="2" type="boolean"/> 1559 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/> 1560 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/> 1561 <bitfield name="UNK12" pos="12"/> 1562 <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/> 1563 <bitfield name="UNK15" low="15" high="16"/> 1564 <!-- 1565 On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have 1566 the ability to add the view index to either the RT array 1567 index or the viewport index, and it seems that 1568 MULTIVIEW_ENABLE doesn't do anything, instead we need to 1569 set at least one of RENDERTARGETINDEXINCR or 1570 VIEWPORTINDEXINCR to enable multiview. The blob still 1571 sets MULTIVIEW_ENABLE regardless. 1572 TODO: what about gen2 (a640)? 1573 --> 1574 <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/> 1575 <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean" variants="A6XX-A7XX"/> 1576 <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean" variants="A6XX-A7XX"/> 1577 <bitfield name="UNK20" low="20" high="22" variants="A6XX-A7XX"/> 1578 </bitset> 1579 <reg32 offset="0x8090" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1580 <reg32 offset="0x8209" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A8XX-" usage="rp_blit"/> 1581 1582 <!-- Fields moved from GRAS_SU_CNTL on earlier gens: --> 1583 <reg32 offset="0x820c" name="GRAS_SU_STEREO_CNTL" variants="A8XX-" usage="rp_blit"> 1584 <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/> 1585 <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/> 1586 </reg32> 1587 1588 <bitset name="a6xx_gras_su_point_minmax" inline="yes"> 1589 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> 1590 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> 1591 </bitset> 1592 1593 <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A6XX-A7XX" usage="rp_blit"/> 1594 <reg32 offset="0x820a" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A8XX-" usage="rp_blit"/> 1595 1596 <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A6XX-A7XX" usage="rp_blit"/> 1597 <reg32 offset="0x820b" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A8XX-" usage="rp_blit"/> 1598 1599 <bitset name="a6xx_gras_su_depth_cntl" inline="yes"> 1600 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 1601 </bitset> 1602 1603 <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" variants="A6XX-A7XX" type="a6xx_gras_su_depth_cntl" usage="rp_blit"/> 1604 <reg32 offset="0x8086" name="GRAS_SU_DEPTH_CNTL" variants="A8XX-" type="a6xx_gras_su_depth_cntl" usage="rp_blit"/> 1605 1606 <bitset name="a6xx_gras_su_stencil_cntl" inline="yes"> 1607 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 1608 </bitset> 1609 1610 <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1611 <reg32 offset="0x8087" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A8XX-" usage="rp_blit"/> 1612 1613 <bitset name="a6xx_gras_su_render_cntl" inline="yes"> 1614 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1615 </bitset> 1616 1617 <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A7XX" usage="rp_blit"/> 1618 <reg32 offset="0x8088" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A8XX-" usage="rp_blit"/> 1619 1620 <!-- 0x8093 invalid --> 1621 <bitset name="a6xx_depth_plane_cntl" inline="yes"> 1622 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 1623 </bitset> 1624 1625 <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1626 <reg32 offset="0x8089" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A8XX-" usage="rp_blit"/> 1627 1628 <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 1629 <reg32 offset="0x808a" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A8XX-" usage="rp_blit"/> 1630 1631 <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 1632 <reg32 offset="0x808b" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A8XX-" usage="rp_blit"/> 1633 1634 <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 1635 <reg32 offset="0x808c" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A8XX-" usage="rp_blit"/> 1636 1637 <bitset name="a6xx_depth_buffer_info" inline="yes"> 1638 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1639 <bitfield name="READ_ONLY" pos="3" type="boolean"/> 1640 </bitset> 1641 1642 <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 1643 <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A6XX-A7XX" usage="rp_blit"/> 1644 <reg32 offset="0x808d" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A8XX-" usage="rp_blit"/> 1645 1646 <bitset name="a6xx_gras_su_conservative_ras_cntl" inline="yes"> 1647 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 1648 <enum name="a6xx_shift_amount"> 1649 <value value="0" name="NO_SHIFT"/> 1650 <value value="1" name="HALF_PIXEL_SHIFT"/> 1651 <value value="2" name="FULL_PIXEL_SHIFT"/> 1652 </enum> 1653 <bitfield name="SHIFTAMOUNT" low="1" high="2" type="a6xx_shift_amount"/> 1654 <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/> 1655 <bitfield name="UNK4" low="4" high="5"/> 1656 </bitset> 1657 1658 <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A6XX-A7XX" usage="cmd"/> 1659 <reg32 offset="0x820d" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A8XX-" usage="cmd"/> 1660 1661 <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL"> 1662 <bitfield name="UNK0" pos="0" type="boolean"/> 1663 <bitfield name="LINELENGTHEN" pos="1" type="boolean"/> 1664 </reg32> 1665 1666 <bitset name="a6xx_gras_us_xs_siv_cntl" inline="yes"> 1667 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/> 1668 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/> 1669 </bitset> 1670 <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1671 <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1672 <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1673 1674 <reg32 offset="0x820e" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="rp_blit"/> 1675 <reg32 offset="0x820f" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="rp_blit"/> 1676 <reg32 offset="0x8210" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A8XX" usage="rp_blit"/> 1677 1678 <bitset name="a6xx_rast_cntl" inline="yes"> 1679 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 1680 </bitset> 1681 1682 <reg32 offset="0x8211" name="GRAS_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="rp_blit"/> 1683 1684 <enum name="a6xx_sequenced_thread_dist"> 1685 <value value="0x0" name="DIST_SCREEN_COORD"/> 1686 <value value="0x1" name="DIST_ALL_TO_RB0"/> 1687 </enum> 1688 1689 <enum name="a6xx_single_prim_mode"> 1690 <value value="0x0" name="NO_FLUSH"/> 1691 <doc> 1692 In addition to FLUSH_PER_OVERLAP, guarantee that UCHE 1693 and CCU don't get out of sync when fetching the previous 1694 value for the current pixel. With NO_FLUSH, there's the 1695 possibility that the flags for the current pixel are 1696 flushed before the data or vice-versa, leading to 1697 texture fetches via UCHE getting out of sync values. 1698 This mode should eliminate that. It's used in bypass 1699 mode for coherent blending 1700 (GL_KHR_blend_equation_advanced_coherent) as well as 1701 non-coherent blending. 1702 </doc> 1703 <value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/> 1704 <doc> 1705 Invalidate UCHE and wait for any pending work to finish 1706 if there was possibly an overlapping primitive prior to 1707 the current one. This is similar to a combination of 1708 GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and 1709 WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for 1710 coherent blending 1711 (GL_KHR_blend_equation_advanced_coherent). 1712 </doc> 1713 <value value="0x3" name="FLUSH_PER_OVERLAP"/> 1714 </enum> 1715 1716 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE --> 1717 <enum name="a6xx_raster_mode"> 1718 <value value="0x0" name="TYPE_TILED"/> 1719 <value value="0x1" name="TYPE_WRITER"/> 1720 </enum> 1721 1722 <!-- I'm guessing this is the same as a3xx --> 1723 <enum name="a6xx_raster_direction"> 1724 <value value="0x0" name="LR_TB"/> 1725 <value value="0x1" name="RL_TB"/> 1726 <value value="0x2" name="LR_BT"/> 1727 <value value="0x3" name="RB_BT"/> 1728 </enum> 1729 1730 <bitset name="a6xx_gras_sc_cntl" inline="yes"> 1731 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/> 1732 <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/> 1733 <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/> 1734 <bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/> 1735 <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set --> 1736 <bitfield name="UNK9" pos="9" type="boolean"/> 1737 <bitfield name="ROTATION" low="10" high="11" type="uint"/> 1738 <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/> 1739 </bitset> 1740 1741 <reg32 offset="0x80a0" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A6XX-A7XX" usage="rp_blit"> 1742 <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2" variants="A6XX-A7XX"/> 1743 </reg32> 1744 <reg32 offset="0x8230" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A8XX-" usage="rp_blit"/> 1745 1746 <enum name="a6xx_render_mode"> 1747 <value value="0x0" name="RENDERING_PASS"/> 1748 <value value="0x1" name="BINNING_PASS"/> 1749 </enum> 1750 1751 <enum name="a6xx_buffers_location"> 1752 <value value="0" name="BUFFERS_IN_GMEM"/> 1753 <value value="3" name="BUFFERS_IN_SYSMEM"/> 1754 </enum> 1755 1756 <enum name="a6xx_lrz_feedback_mask"> 1757 <value value="0x0" name="LRZ_FEEDBACK_NONE"/> 1758 <value value="0x1" name="LRZ_FEEDBACK_EARLY_Z"/> 1759 <value value="0x2" name="LRZ_FEEDBACK_EARLY_Z_LATE_Z"/> 1760 <!-- We don't have a flag type and this flags combination is often used --> 1761 <value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z"/> 1762 <value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/> 1763 </enum> 1764 1765 <bitset name="a6xx_bin_cntl" inline="yes"> 1766 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1767 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1768 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1769 <doc>Disable LRZ feedback writes</doc> 1770 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1771 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/> 1772 <doc> 1773 Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have 1774 GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. 1775 In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. 1776 </doc> 1777 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1778 <bitfield name="FORCE_LRZ_DIS" pos="27" type="boolean"/> 1779 </bitset> 1780 1781 <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" type="a6xx_bin_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1782 1783 <!-- Common fields for RB_CNTL and GRAS_SC_BIN_CNTL --> 1784 <bitset name="a8xx_bin_cntl" inline="yes"> 1785 <bitfield name="BINW" low="0" high="9" shr="5" type="uint"/> 1786 <bitfield name="BINH" low="16" high="26" shr="4" type="uint"/> 1787 <bitfield name="RENDER_MODE" low="11" high="13" type="a6xx_render_mode"/> 1788 <doc> 1789 Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have 1790 GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. 1791 In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. 1792 </doc> 1793 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="28" high="30" type="a6xx_lrz_feedback_mask"/> 1794 <doc>Disable LRZ feedback writes</doc> 1795 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="31" type="boolean"/> 1796 </bitset> 1797 1798 <reg32 offset="0x8231" name="GRAS_SC_BIN_CNTL" type="a8xx_bin_cntl" variants="A8XX-" usage="rp_blit"> 1799 <bitfield name="CONS_VIS_IN_BINNING" pos="10" type="boolean"/> 1800 <bitfield name="FORCE_BI_DIR_LRZ_DISABLE" pos="14" type="boolean"/> 1801 <bitfield name="FORCE_LRZ_DIS" pos="15" type="boolean"/> 1802 <bitfield name="BIN_VRS_DIS" pos="27" type="boolean"/> 1803 </reg32> 1804 1805 <bitset name="a6xx_gras_sc_ras_msaa_cntl" inline="yes"> 1806 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1807 <bitfield name="UNK2" pos="2"/> 1808 <bitfield name="UNK3" pos="3"/> 1809 </bitset> 1810 1811 <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1812 <reg32 offset="0x8232" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A8XX-" usage="rp_blit"/> 1813 1814 <bitset name="a6xx_gras_sc_dest_msaa_cntl" inline="yes"> 1815 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1816 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1817 </bitset> 1818 1819 <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1820 <reg32 offset="0x8233" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A8XX-" usage="rp_blit"/> 1821 1822 <bitset name="a6xx_msaa_sample_pos_cntl" inline="yes"> 1823 <bitfield name="UNK0" pos="0"/> 1824 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/> 1825 </bitset> 1826 1827 <bitset name="a6xx_programmable_msaa_pos" inline="yes"> 1828 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/> 1829 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/> 1830 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/> 1831 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/> 1832 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/> 1833 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/> 1834 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/> 1835 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/> 1836 </bitset> 1837 1838 <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1839 <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/> 1840 <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/> 1841 1842 <reg32 offset="0x8237" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A8XX-" usage="rp_blit"/> 1843 <reg32 offset="0x8238" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/> 1844 <reg32 offset="0x8239" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/> 1845 <reg32 offset="0x823a" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_2" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/> 1846 <reg32 offset="0x823b" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_3" type="a6xx_programmable_msaa_pos" variants="A8XX-" usage="rp_blit"/> 1847 1848 <reg32 offset="0x80a7" name="GRAS_ROTATION_CNTL" variants="A7XX" usage="cmd"/> 1849 <reg32 offset="0x8207" name="GRAS_ROTATION_CNTL" variants="A8XX-" usage="cmd"/> 1850 1851 <bitset name="a6xx_screen_scissor_cntl" inline="yes"> 1852 <bitfield name="SCISSOR_DISABLE" pos="0" type="boolean"/> 1853 </bitset> 1854 1855 <reg32 offset="0x80af" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A6XX-A7XX" pos="0" usage="cmd"/> 1856 <reg32 offset="0x8234" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A8XX-" pos="0" usage="cmd"/> 1857 1858 <bitset name="a6xx_scissor_xy" inline="yes"> 1859 <bitfield name="X" low="0" high="15" type="uint"/> 1860 <bitfield name="Y" low="16" high="31" type="uint"/> 1861 </bitset> 1862 1863 <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 1864 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1865 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1866 </array> 1867 1868 <array offset="0x8240" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" variants="A8XX-" usage="rp_blit"> 1869 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1870 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1871 </array> 1872 1873 <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 1874 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1875 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1876 </array> 1877 <array offset="0x8270" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A8XX-" usage="rp_blit"> 1878 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1879 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1880 </array> 1881 1882 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1883 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1884 1885 <reg32 offset="0x8235" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 1886 <reg32 offset="0x8236" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 1887 1888 <enum name="a6xx_fsr_combiner"> 1889 <value value="0" name="FSR_COMBINER_OP_KEEP"/> 1890 <value value="1" name="FSR_COMBINER_OP_REPLACE"/> 1891 <value value="2" name="FSR_COMBINER_OP_MIN"/> 1892 <value value="3" name="FSR_COMBINER_OP_MAX"/> 1893 <value value="4" name="FSR_COMBINER_OP_MUL"/> 1894 </enum> 1895 1896 <bitset name="a6xx_gras_vrs_config"> 1897 <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 1898 <bitfield name="FRAG_SIZE_X" low="1" high="2" type="uint"/> 1899 <bitfield name="FRAG_SIZE_Y" low="3" high="4" type="uint"/> 1900 <bitfield name="COMBINER_OP_1" low="5" high="7" type="a6xx_fsr_combiner"/> 1901 <bitfield name="COMBINER_OP_2" low="8" high="10" type="a6xx_fsr_combiner"/> 1902 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="13" type="boolean"/> 1903 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="20" type="boolean"/> 1904 </bitset> 1905 1906 <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A7XX" usage="rp_blit"/> 1907 <reg32 offset="0x8208" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A8XX-" usage="rp_blit"/> 1908 1909 <bitset name="a6xx_gras_quality_buffer_info" inline="yes"> 1910 <bitfield name="LAYERED" pos="0" type="boolean"/> 1911 <bitfield name="TILE_MODE" low="1" high="2" type="a6xx_tile_mode"/> 1912 </bitset> 1913 1914 <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A7XX" usage="rp_blit"/> 1915 <reg32 offset="0x808e" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A8XX-" usage="rp_blit"/> 1916 1917 <bitset name="a6xx_gras_quality_buffer_dimension" inline="yes"> 1918 <bitfield name="WIDTH" low="0" high="15" type="uint"/> 1919 <bitfield name="HEIGHT" low="16" high="31" type="uint"/> 1920 </bitset> 1921 1922 <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A7XX" usage="rp_blit"/> 1923 <reg32 offset="0x808f" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A8XX-" usage="rp_blit"/> 1924 1925 <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX" type="waddress" usage="rp_blit"/> 1926 <reg64 offset="0x8090" name="GRAS_QUALITY_BUFFER_BASE" variants="A8XX-" type="waddress" usage="rp_blit"/> 1927 1928 <bitset name="a6xx_gras_quality_buffer_pitch" inline="yes"> 1929 <bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/> 1930 <bitfield name="ARRAY_PITCH" shr="6" low="10" high="28" type="uint"/> 1931 </bitset> 1932 1933 <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A7XX" usage="rp_blit"/> 1934 <reg32 offset="0x8092" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A8XX-" usage="rp_blit"/> 1935 1936 <enum name="a6xx_lrz_dir_status"> 1937 <value value="0x1" name="LRZ_DIR_LE"/> 1938 <value value="0x2" name="LRZ_DIR_GE"/> 1939 <value value="0x3" name="LRZ_DIR_INVALID"/> 1940 </enum> 1941 1942 <bitset name="a6xx_gras_lrz_cntl" inline="yes"> 1943 <bitfield name="ENABLE" pos="0" type="boolean"/> 1944 <doc>LRZ write also disabled for blend/etc.</doc> 1945 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> 1946 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc> 1947 <bitfield name="GREATER" pos="2" type="boolean"/> 1948 <doc> 1949 Clears the LRZ block being touched to: 1950 - 0.0 if GREATER 1951 - 1.0 if LESS 1952 </doc> 1953 <!-- set when depth-test + depth-write enabled --> 1954 <bitfield name="Z_WRITE_ENABLE" pos="4" type="boolean"/> 1955 <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/> 1956 <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/> 1957 <doc> 1958 If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into 1959 buffer, in case of mismatched direction writes 0 (disables LRZ). 1960 </doc> 1961 <bitfield name="DIR_WRITE" pos="8" type="boolean"/> 1962 <doc> 1963 Disable LRZ based on previous direction and the current one. 1964 If DIR_WRITE is not enabled - there is no write to direction buffer. 1965 </doc> 1966 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/> 1967 </bitset> 1968 1969 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A6XX"> 1970 <bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/> 1971 <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/> 1972 </reg32> 1973 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A7XX"/> 1974 <reg32 offset="0x8212" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A8XX-"/> 1975 1976 <reg32 offset="0x8007" name="GRAS_LRZ_CB_CNTL" variants="A7XX" usage="rp_blit"> 1977 <doc> 1978 The total size of the LRZ image array (not including 1979 fast clear buffer), used as a stride for double 1980 buffering used with concurrent binning. 1981 </doc> 1982 <bitfield name="DOUBLE_BUFFER_STRIDE" low="8" high="31" shr="8"/> 1983 </reg32> 1984 <reg32 offset="0x8101" name="GRAS_LRZ_CB_CNTL" usage="rp_blit" variants="A8XX-"> 1985 <bitfield name="DOUBLE_BUFFER_PITCH" low="8" high="31" shr="8"/> 1986 </reg32> 1987 1988 <enum name="a6xx_fragcoord_sample_mode"> 1989 <value value="0" name="FRAGCOORD_CENTER"/> 1990 <value value="3" name="FRAGCOORD_SAMPLE"/> 1991 </enum> 1992 1993 <bitset name="a6xx_gras_lrz_ps_input_cntl" inline="yes"> 1994 <bitfield name="SAMPLEID" pos="0" type="boolean"/> 1995 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/> 1996 </bitset> 1997 1998 <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="rp_blit" variants="A6XX-A7XX"/> 1999 <reg32 offset="0x8102" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="rp_blit" variants="A8XX-"/> 2000 2001 <bitset name="a6xx_gras_lrz_mrt_buffer_info_0" inline="yes"> 2002 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2003 </bitset> 2004 2005 <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="rp_blit" variants="A6XX-A7XX"/> 2006 <reg32 offset="0x8103" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="rp_blit" variants="A8XX-"/> 2007 2008 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit" variants="A6XX-A7XX"/> 2009 <reg64 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit" variants="A8XX-"/> 2010 2011 <bitset name="a6xx_gras_lrz_buffer_pitch" inline="yes"> 2012 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/> 2013 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="8" type="uint"/> 2014 </bitset> 2015 2016 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="rp_blit" variants="A6XX-A7XX"/> 2017 <reg32 offset="0x8108" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="rp_blit" variants="A8XX-"/> 2018 2019 <reg32 offset="0x810e" name="GRAS_LRZ_BUFFER_STRIDE" usage="rp_blit" low="0" high="16" shr="12" variants="A8XX-"/> 2020 2021 <!-- 2022 The LRZ "fast clear" buffer is initialized to zero's by blob, and 2023 read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears 2024 to store 1b/block. It appears that '0' means block has original 2025 depth clear value, and '1' means that the corresponding block in 2026 LRZ has been modified. Ignoring alignment/padding, the size is 2027 given by the formula: 2028 2029 // calculate LRZ size from depth size: 2030 if (nr_samples == 4) { 2031 width *= 2; 2032 height *= 2; 2033 } else if (nr_samples == 2) { 2034 height *= 2; 2035 } 2036 2037 lrz_width = div_round_up(width, 8); 2038 lrz_heigh = div_round_up(height, 8); 2039 2040 // calculate # of blocks: 2041 nblocksx = div_round_up(lrz_width, 16); 2042 nblocksy = div_round_up(lrz_height, 4); 2043 2044 // fast-clear buffer is 1bit/block: 2045 fc_sz = div_round_up(nblocksx * nblocksy, 8); 2046 2047 In practice the blob seems to switch off FC_ENABLE once the size 2048 increases beyond 1 page. Not sure if that is an actual limit or 2049 not. 2050 --> 2051 <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/> 2052 <reg32 offset="0x8109" name="GRAS_LRZ_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> 2053 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 2054 </reg32> 2055 <!-- 2056 LRZ buffer represents a single array layer + mip level, and there is 2057 a single buffer per depth image. Thus to reuse LRZ between renderpasses 2058 it is necessary to track the depth view used in the past renderpass, which 2059 GRAS_LRZ_VIEW_INFO is for. 2060 GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_VIEW_INFO is equal to 2061 the value stored in the LRZ buffer, if not - LRZ is disabled. 2062 --> 2063 <reg32 offset="0x810a" name="GRAS_LRZ_VIEW_INFO" usage="cmd"> 2064 <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/> 2065 <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/> 2066 <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/> 2067 </reg32> 2068 2069 <reg32 offset="0x810b" name="GRAS_LRZ_CNTL2" variants="A7XX-" usage="rp_blit"> 2070 <bitfield name="DISABLE_ON_WRONG_DIR" pos="0" type="boolean"/> 2071 <bitfield name="FC_ENABLE" pos="1" type="boolean"/> 2072 </reg32> 2073 2074 <!-- 0x810c-0x810f invalid --> 2075 2076 <reg32 offset="0x8110" name="GRAS_LRZ_BUFFER_SLICE_PITCH" low="0" high="31" shr="8" type="uint" variants="A8XX-"/> 2077 2078 <reg32 offset="0x8110" name="GRAS_MODE_CNTL" low="0" high="1" variants="A6XX-A7XX" usage="cmd"/> 2079 <reg32 offset="0x8213" name="GRAS_MODE_CNTL" low="0" high="1" variants="A8XX-" usage="cmd"/> 2080 2081 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR --> 2082 <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX"/> 2083 <reg32 offset="0x810d" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A8XX-"/> 2084 2085 <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A7XX" usage="rp_blit"/> 2086 <reg32 offset="0x810f" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A8XX" usage="rp_blit"/> 2087 2088 <doc>LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values.</doc> 2089 <array offset="0x8120" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A7XX" stride="1" length="2"/> 2090 <array offset="0x8130" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A8XX-" stride="1" length="2"/> 2091 2092 <reg32 offset="0x810c" name="GRAS_LRZ_COLOR_COMP_MASK" variants="A8XX-"> 2093 <bitfield name="MRT0" low="0" high="3"/> 2094 <bitfield name="MRT1" low="4" high="7"/> 2095 <bitfield name="MRT2" low="8" high="11"/> 2096 <bitfield name="MRT3" low="12" high="15"/> 2097 <bitfield name="MRT4" low="16" high="19"/> 2098 <bitfield name="MRT5" low="20" high="23"/> 2099 <bitfield name="MRT6" low="24" high="27"/> 2100 <bitfield name="MRT7" low="28" high="31"/> 2101 </reg32> 2102 2103 <enum name="a6xx_rotation"> 2104 <value value="0x0" name="ROTATE_0"/> 2105 <value value="0x1" name="ROTATE_90"/> 2106 <value value="0x2" name="ROTATE_180"/> 2107 <value value="0x3" name="ROTATE_270"/> 2108 <value value="0x4" name="ROTATE_HFLIP"/> 2109 <value value="0x5" name="ROTATE_VFLIP"/> 2110 </enum> 2111 2112 <bitset name="a6xx_a2d_blt_cntl" inline="yes"> 2113 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/> 2114 <bitfield name="OVERWRITEEN" pos="3" type="boolean"/> 2115 <bitfield name="UNK4" low="4" high="6"/> 2116 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/> 2117 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/> 2118 <bitfield name="SCISSOR" pos="16" type="boolean"/> 2119 <bitfield name="UNK17" low="17" high="18"/> 2120 <!-- required when blitting D24S8/D24X8 --> 2121 <bitfield name="D24S8" pos="19" type="boolean"/> 2122 <!-- some sort of channel mask, disabled channels are set to zero ? --> 2123 <bitfield name="MASK" low="20" high="23"/> 2124 <bitfield name="IFMT" low="24" high="26" type="a6xx_2d_ifmt"/> 2125 <bitfield name="UNK27" pos="27" type="boolean"/> 2126 <bitfield name="UNK28" pos="28" type="boolean"/> 2127 <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/> 2128 <bitfield name="COPY" pos="30" type="boolean" variants="A7XX-"/> 2129 </bitset> 2130 2131 <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2132 <!-- note: the low 8 bits for src coords are valid, probably fixed point 2133 it would be a bit weird though, since we subtract 1 from BR coords 2134 apparently signed, gallium driver uses negative coords and it works? 2135 --> 2136 <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 2137 <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 2138 <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 2139 <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 2140 <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 2141 <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 2142 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/> 2143 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/> 2144 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/> 2145 <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 2146 <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 2147 2148 <reg32 offset="0x8500" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" variants="A8XX-" usage="rp_blit"/> 2149 <reg32 offset="0x8501" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/> 2150 <reg32 offset="0x8502" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/> 2151 <reg32 offset="0x8503" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/> 2152 <reg32 offset="0x8504" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" variants="A8XX-" usage="rp_blit"/> 2153 <reg32 offset="0x8505" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 2154 <reg32 offset="0x8506" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 2155 <reg32 offset="0x8507" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 2156 <reg32 offset="0x8508" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 2157 2158 <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> 2159 <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="init" variants="A6XX-A7XX"> 2160 <bitfield name="UNK7" pos="7" type="boolean"/> 2161 <bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/> 2162 </reg32> 2163 <reg32 offset="0x8600" name="GRAS_TSEFE_DBG_ECO_CNTL" variants="A8XX-"/> 2164 <reg32 offset="0x8702" name="GRAS_DBG_ECO_CNTL" variants="A8XX"/> 2165 <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/> 2166 <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX"/> 2167 <reg32 offset="0x8700" name="GRAS_NC_MODE_CNTL" variants="A8XX-"/> 2168 <array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 2169 <array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 2170 <array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 2171 2172 <array offset="0x8610" name="GRAS_PERFCTR_TSEFE_SEL" stride="1" length="6" variants="A8XX-"/> 2173 <array offset="0x8710" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="6" variants="A8XX-"/> 2174 <array offset="0x8720" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4" variants="A8XX-"/> 2175 <array offset="0x8730" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="6" variants="A8XX-"/> 2176 2177 2178 <!-- note 0x8620-0x87ff are not all invalid 2179 (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords) 2180 --> 2181 2182 <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> 2183 <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX-A7XX" type="a6xx_bin_cntl" usage="rp_blit"/> 2184 <reg32 offset="0x8800" name="RB_CNTL" variants="A8XX-" type="a8xx_bin_cntl" usage="rp_blit"/> 2185 2186 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit"> 2187 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> 2188 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 2189 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 2190 <bitfield name="UNK8" low="8" high="10"/> 2191 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 2192 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 2193 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 2194 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 2195 <!-- bit seems to be set whenever depth buffer enabled: --> 2196 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/> 2197 <!-- bitmask of MRTs using UBWC flag buffer: --> 2198 <bitfield name="FLAG_MRTS" low="16" high="23"/> 2199 </reg32> 2200 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 2201 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 2202 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 2203 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 2204 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 2205 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 2206 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 2207 </reg32> 2208 2209 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit"> 2210 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 2211 <bitfield name="UNK2" pos="2"/> 2212 <bitfield name="UNK3" pos="3"/> 2213 </reg32> 2214 <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL" usage="rp_blit"> 2215 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 2216 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 2217 </reg32> 2218 2219 <reg32 offset="0x8804" name="RB_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 2220 <reg32 offset="0x8805" name="RB_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 2221 <reg32 offset="0x8806" name="RB_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 2222 <reg32 offset="0x8807" name="RB_PROGRAMMABLE_MSAA_POS_2" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A8XX-"/> 2223 <reg32 offset="0x8808" name="RB_PROGRAMMABLE_MSAA_POS_3" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A8XX-"/> 2224 <!-- 2225 note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL 2226 name comes from kernel and is probably right) 2227 --> 2228 <reg32 offset="0x8809" name="RB_INTERP_CNTL" usage="rp_blit"> 2229 <!-- see also GRAS_CL_INTERP_CNTL --> 2230 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 2231 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 2232 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 2233 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 2234 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 2235 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 2236 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 2237 <bitfield name="INTERP_EN" pos="10" type="boolean"/> 2238 </reg32> 2239 <reg32 offset="0x880a" name="RB_PS_INPUT_CNTL" usage="rp_blit"> 2240 <!-- enable bits for various FS sysvalue regs: --> 2241 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/> 2242 <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/> 2243 <bitfield name="FACENESS" pos="2" type="boolean"/> 2244 <bitfield name="SAMPLEID" pos="3" type="boolean"/> 2245 <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/> 2246 <bitfield name="CENTERRHW" pos="6" type="boolean"/> 2247 <bitfield name="LINELENGTHEN" pos="7" type="boolean"/> 2248 <bitfield name="FOVEATION" pos="8" type="boolean"/> 2249 </reg32> 2250 2251 <reg32 offset="0x880b" name="RB_PS_OUTPUT_CNTL" usage="rp_blit"> 2252 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 2253 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/> 2254 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/> 2255 <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/> 2256 </reg32> 2257 <reg32 offset="0x880c" name="RB_PS_MRT_CNTL" usage="rp_blit"> 2258 <bitfield name="MRT" low="0" high="3" type="uint"/> 2259 </reg32> 2260 <reg32 offset="0x880d" name="RB_PS_OUTPUT_MASK" usage="rp_blit"> 2261 <bitfield name="RT0" low="0" high="3"/> 2262 <bitfield name="RT1" low="4" high="7"/> 2263 <bitfield name="RT2" low="8" high="11"/> 2264 <bitfield name="RT3" low="12" high="15"/> 2265 <bitfield name="RT4" low="16" high="19"/> 2266 <bitfield name="RT5" low="20" high="23"/> 2267 <bitfield name="RT6" low="24" high="27"/> 2268 <bitfield name="RT7" low="28" high="31"/> 2269 </reg32> 2270 <reg32 offset="0x880e" name="RB_DITHER_CNTL" usage="cmd"> 2271 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> 2272 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> 2273 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> 2274 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> 2275 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> 2276 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> 2277 <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/> 2278 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> 2279 </reg32> 2280 <reg32 offset="0x880f" name="RB_SRGB_CNTL" usage="rp_blit"> 2281 <!-- Same as SP_SRGB_CNTL --> 2282 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 2283 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 2284 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 2285 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 2286 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 2287 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 2288 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 2289 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 2290 </reg32> 2291 2292 <reg32 offset="0x8810" name="RB_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> 2293 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 2294 </reg32> 2295 <reg32 offset="0x8811" name="RB_MODE_CNTL" low="4" high="6" usage="cmd"/> 2296 <reg32 offset="0x8812" name="RB_BUFFER_CNTL" variants="A7XX-" usage="rp_blit"> 2297 <bitfield name="Z_SYSMEM" pos="0" type="boolean"/> 2298 <bitfield name="S_SYSMEM" pos="1" type="boolean"/> 2299 <bitfield name="RT0_SYSMEM" pos="2" type="boolean"/> 2300 <bitfield name="RT1_SYSMEM" pos="3" type="boolean"/> 2301 <bitfield name="RT2_SYSMEM" pos="4" type="boolean"/> 2302 <bitfield name="RT3_SYSMEM" pos="5" type="boolean"/> 2303 <bitfield name="RT4_SYSMEM" pos="6" type="boolean"/> 2304 <bitfield name="RT5_SYSMEM" pos="7" type="boolean"/> 2305 <bitfield name="RT6_SYSMEM" pos="8" type="boolean"/> 2306 <bitfield name="RT7_SYSMEM" pos="9" type="boolean"/> 2307 <bitfield name="Z_FULL_IN_GMEM" pos="10" type="boolean" variants="A8XX-"/> 2308 <bitfield name="S_FULL_IN_GMEM" pos="11" type="boolean" variants="A8XX-"/> 2309 <bitfield name="RT0_FULL_IN_GMEM" pos="12" type="boolean" variants="A8XX-"/> 2310 <bitfield name="RT1_FULL_IN_GMEM" pos="13" type="boolean" variants="A8XX-"/> 2311 <bitfield name="RT2_FULL_IN_GMEM" pos="14" type="boolean" variants="A8XX-"/> 2312 <bitfield name="RT3_FULL_IN_GMEM" pos="15" type="boolean" variants="A8XX-"/> 2313 <bitfield name="RT4_FULL_IN_GMEM" pos="16" type="boolean" variants="A8XX-"/> 2314 <bitfield name="RT5_FULL_IN_GMEM" pos="17" type="boolean" variants="A8XX-"/> 2315 <bitfield name="RT6_FULL_IN_GMEM" pos="18" type="boolean" variants="A8XX-"/> 2316 <bitfield name="RT7_FULL_IN_GMEM" pos="19" type="boolean" variants="A8XX-"/> 2317 </reg32> 2318 2319 <reg32 offset="0x8816" name="RB_RESOLVE_CR_CNTL" variants="A8XX-" usage="rp_blit"/> 2320 2321 <!-- 0x8813-0x8817 invalid --> 2322 <!-- always 0x0 ? --> 2323 <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/> 2324 <!-- 0x8819-0x881e all 32 bits --> 2325 <reg32 offset="0x8819" name="RB_UNKNOWN_8819" usage="cmd"/> 2326 <reg32 offset="0x881a" name="RB_UNKNOWN_881A" usage="cmd"/> 2327 <reg32 offset="0x881b" name="RB_UNKNOWN_881B" usage="cmd"/> 2328 <reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/> 2329 <reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/> 2330 <reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/> 2331 2332 <!-- Duplicates fields from SP_PS_CNTL_0 --> 2333 <reg32 offset="0x881f" name="RB_PS_CNTL" variants="A8XX-" usage="rp_blit"> 2334 <bitfield name="PIXLODENABLE" pos="0" type="boolean"/> 2335 <bitfield name="LODPIXMASK" pos="1" type="boolean"/> 2336 </reg32> 2337 2338 <array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit"> 2339 <reg32 offset="0x0" name="CONTROL"> 2340 <bitfield name="COLOR_BLEND_EN" pos="0" type="boolean"/> 2341 <bitfield name="ALPHA_BLEND_EN" pos="1" type="boolean"/> 2342 <bitfield name="ROP_ENABLE" pos="2" type="boolean"/> 2343 <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/> 2344 <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/> 2345 </reg32> 2346 <reg32 offset="0x1" name="BLEND_CONTROL"> 2347 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/> 2348 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/> 2349 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/> 2350 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/> 2351 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/> 2352 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/> 2353 </reg32> 2354 <reg32 offset="0x2" name="BUF_INFO" variants="A6XX"> 2355 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2356 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2357 <bitfield name="UNK10" pos="10"/> 2358 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> 2359 </reg32> 2360 <reg32 offset="0x2" name="BUF_INFO" variants="A7XX-"> 2361 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2362 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2363 <bitfield name="UNK10" pos="10"/> 2364 <bitfield name="LOSSLESSCOMPEN" pos="11" type="boolean"/> 2365 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> 2366 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/> 2367 </reg32> 2368 <!-- 2369 at least in gmem, things seem to be aligned to pitch of 64.. 2370 maybe an artifact of tiled format used in gmem? 2371 --> 2372 <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/> 2373 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/> 2374 <!-- 2375 Compared to a5xx and before, we configure both a GMEM base and 2376 external base. Not sure if this is to facilitate GMEM save/ 2377 restore for context switch, or just to simplify state setup to 2378 not have to care about GMEM vs BYPASS mode. 2379 --> 2380 <!-- maybe something in low bits since alignment of 1 doesn't make sense? --> 2381 <reg64 offset="0x5" name="BASE" type="waddress" align="1"/> 2382 2383 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/> 2384 </array> 2385 2386 <reg32 offset="0x8860" name="RB_BLEND_CONSTANT_RED_FP32" type="float" usage="rp_blit"/> 2387 <reg32 offset="0x8861" name="RB_BLEND_CONSTANT_GREEN_FP32" type="float" usage="rp_blit"/> 2388 <reg32 offset="0x8862" name="RB_BLEND_CONSTANT_BLUE_FP32" type="float" usage="rp_blit"/> 2389 <reg32 offset="0x8863" name="RB_BLEND_CONSTANT_ALPHA_FP32" type="float" usage="rp_blit"/> 2390 <reg32 offset="0x8864" name="RB_ALPHA_TEST_CNTL" usage="cmd"> 2391 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> 2392 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> 2393 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> 2394 </reg32> 2395 <reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit"> 2396 <!-- per-mrt enable bit --> 2397 <bitfield name="BLEND_READS_DEST" low="0" high="7"/> 2398 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> 2399 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 2400 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 2401 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/> 2402 <bitfield name="SAMPLE_MASK" low="16" high="31"/> 2403 </reg32> 2404 <reg32 offset="0x8866" name="RB_LB_PARAM_LIMIT" variants="A8XX-" usage="rp_blit"> 2405 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 2406 </reg32> 2407 <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" usage="rp_blit"/> 2408 2409 <reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit"> 2410 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 2411 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/> 2412 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/> 2413 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> 2414 <doc> 2415 Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER 2416 also set when Z_BOUNDS_ENABLE is set 2417 </doc> 2418 <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/> 2419 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/> 2420 <!-- clamp shader depth out to [0, 1] (instead of RB_VIEWPORT_ZCLAMP_MIN/MAX)--> 2421 <bitfield name="O_DEPTH_01_CLAMP_EN" pos="8" type="boolean" variants="A8XX-"/> 2422 </reg32> 2423 2424 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: --> 2425 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" type="a6xx_depth_buffer_info" usage="rp_blit"/> 2426 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO --> 2427 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A7XX-" usage="rp_blit"> 2428 <bitfield name="PRT" low="3" high="4"/> 2429 <bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/> 2430 <bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/> 2431 </reg32> 2432 2433 <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="rp_blit"/> 2434 <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="rp_blit"/> 2435 <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2436 <reg32 offset="0x8877" name="RB_DEPTH_GMEM_BASE" low="12" high="31" shr="12" usage="rp_blit"/> 2437 2438 <reg32 offset="0x8878" name="RB_DEPTH_BOUND_MIN" type="float" usage="rp_blit"/> 2439 <reg32 offset="0x8879" name="RB_DEPTH_BOUND_MAX" type="float" usage="rp_blit"/> 2440 <!-- 0x887a-0x887f invalid --> 2441 <reg32 offset="0x8880" name="RB_STENCIL_CNTL" usage="rp_blit"> 2442 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 2443 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> 2444 <!-- 2445 set for stencil operations that require read from stencil 2446 buffer, but not for example for stencil clear (which does 2447 not require read).. so guessing this is analogous to 2448 READ_DEST_ENABLE for color buffer.. 2449 --> 2450 <bitfield name="STENCIL_READ" pos="2" type="boolean"/> 2451 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/> 2452 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/> 2453 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/> 2454 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/> 2455 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/> 2456 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/> 2457 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> 2458 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> 2459 </reg32> 2460 2461 <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A6XX" usage="rp_blit"> 2462 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 2463 <bitfield name="UNK1" pos="1" type="boolean"/> 2464 </reg32> 2465 <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 2466 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 2467 <bitfield name="UNK1" pos="1" type="boolean"/> 2468 <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/> 2469 </reg32> 2470 <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="rp_blit"/> 2471 <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="rp_blit"/> 2472 <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2473 <reg32 offset="0x8886" name="RB_STENCIL_GMEM_BASE" low="12" high="31" shr="12" usage="rp_blit"/> 2474 <reg32 offset="0x8887" name="RB_STENCIL_REF_CNTL" usage="rp_blit"> 2475 <bitfield name="REF" low="0" high="7"/> 2476 <bitfield name="BFREF" low="8" high="15"/> 2477 </reg32> 2478 <reg32 offset="0x8888" name="RB_STENCIL_MASK" usage="rp_blit"> 2479 <bitfield name="MASK" low="0" high="7"/> 2480 <bitfield name="BFMASK" low="8" high="15"/> 2481 </reg32> 2482 <reg32 offset="0x8889" name="RB_STENCIL_WRITE_MASK" usage="rp_blit"> 2483 <bitfield name="WRMASK" low="0" high="7"/> 2484 <bitfield name="BFWRMASK" low="8" high="15"/> 2485 </reg32> 2486 <!-- 0x888a-0x888f invalid --> 2487 <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 2488 <reg32 offset="0x8891" name="RB_SAMPLE_COUNTER_CNTL" usage="cmd"> 2489 <bitfield name="DISABLE" pos="0" type="boolean"/> 2490 <bitfield name="COPY" pos="1" type="boolean"/> 2491 </reg32> 2492 <!-- 0x8892-0x8897 invalid --> 2493 <reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit"> 2494 <bitfield name="ENABLE" pos="0" type="boolean"/> 2495 </reg32> 2496 <reg32 offset="0x8899" name="RB_LRZ_CNTL2" variants="A7XX-" usage="cmd"> 2497 <bitfield name="ENABLE_BIDIRECTIONAL_LRZ" pos="0" type="boolean"/> 2498 </reg32> 2499 <!-- 0x8899-0x88bf invalid --> 2500 <!-- clamps depth value for depth test/write --> 2501 <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit" variants="A6XX-A7XX"/> 2502 <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit" variants="A6XX-A7XX"/> 2503 2504<!-- todo allow type="float" on an <array/> --> 2505 <array offset="0x88b0" name="RB_VIEWPORT_ZCLAMP_MIN" stride="1" length="16" usage="rp_blit" variants="A8XX-"> 2506 <reg32 offset="0" name="REG" type="float"/> 2507 </array> 2508 <array offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MAX" stride="1" length="16" usage="rp_blit" variants="A8XX-"> 2509 <reg32 offset="0" name="REG" type="float"/> 2510 </array> 2511 2512 <!-- 0x88c2-0x88cf invalid--> 2513 <reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="rp_blit"> 2514 <bitfield name="UNK0" low="0" high="12"/> 2515 <bitfield name="UNK16" low="16" high="26"/> 2516 </reg32> 2517 <reg32 offset="0x88d1" name="RB_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/> 2518 <reg32 offset="0x88d2" name="RB_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/> 2519 <!-- weird to duplicate other regs from same block?? --> 2520 <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" variants="A6XX-A7XX" usage="rp_blit"> 2521 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 2522 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 2523 </reg32> 2524 2525 <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/> 2526 <reg32 offset="0x88f0" name="RB_RESOLVE_CNTL_4" variants="A8XX-" usage="rp_blit"/> 2527 <reg32 offset="0x88f1" name="RB_RESOLVE_CNTL_5" variants="A8XX-" usage="rp_blit"/> 2528 2529 <reg32 offset="0x88d4" name="RB_RESOLVE_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 2530 <reg32 offset="0x88d5" name="RB_RESOLVE_GMEM_BUFFER_INFO" usage="rp_blit"> 2531 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 2532 </reg32> 2533 <reg32 offset="0x88d6" name="RB_RESOLVE_GMEM_BUFFER_BASE" low="12" high="31" shr="12" usage="rp_blit"/> 2534 <!-- s/DST_FORMAT/DST_INFO/ probably: --> 2535 <reg32 offset="0x88d7" name="RB_RESOLVE_SYSTEM_BUFFER_INFO" usage="rp_blit"> 2536 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 2537 <bitfield name="FLAGS" pos="2" type="boolean"/> 2538 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 2539 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/> 2540 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/> 2541 <bitfield name="UNK15" pos="15" type="boolean"/> 2542 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/> 2543 </reg32> 2544 <reg64 offset="0x88d8" name="RB_RESOLVE_SYSTEM_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2545 <reg32 offset="0x88da" name="RB_RESOLVE_SYSTEM_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 2546 <!-- array-pitch is size of layer --> 2547 <reg32 offset="0x88db" name="RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/> 2548 <reg64 offset="0x88dc" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2549 2550 <bitset name="a6xx_flag_buffer_pitch" inline="yes"> 2551 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 2552 <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/> 2553 </bitset> 2554 2555 <reg32 offset="0x88de" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" usage="rp_blit"/> 2556 2557 <reg32 offset="0x88df" name="RB_RESOLVE_CLEAR_COLOR_DW0" usage="rp_blit"/> 2558 <reg32 offset="0x88e0" name="RB_RESOLVE_CLEAR_COLOR_DW1" usage="rp_blit"/> 2559 <reg32 offset="0x88e1" name="RB_RESOLVE_CLEAR_COLOR_DW2" usage="rp_blit"/> 2560 <reg32 offset="0x88e2" name="RB_RESOLVE_CLEAR_COLOR_DW3" usage="rp_blit"/> 2561 2562 <enum name="a6xx_blit_event_type"> 2563 <value value="0x0" name="BLIT_EVENT_STORE"/> 2564 <value value="0x1" name="BLIT_EVENT_STORE_AND_CLEAR"/> 2565 <value value="0x2" name="BLIT_EVENT_CLEAR"/> 2566 <value value="0x3" name="BLIT_EVENT_LOAD"/> 2567 </enum> 2568 2569 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: --> 2570 <reg32 offset="0x88e3" name="RB_RESOLVE_OPERATION" usage="rp_blit"> 2571 <bitfield name="TYPE" low="0" high="1" type="a6xx_blit_event_type"/> 2572 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging --> 2573 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? --> 2574 <doc> 2575 For clearing depth/stencil 2576 1 - depth 2577 2 - stencil 2578 3 - depth+stencil 2579 For clearing color buffer: 2580 then probably a component mask, I always see 0xf 2581 </doc> 2582 <bitfield name="CLEAR_MASK" low="4" high="7"/> 2583 <!-- set when this is the last resolve on a650+ --> 2584 <bitfield name="LAST" low="8" high="9"/> 2585 <!-- 2586 a618 GLES: color render target number being resolved for CCU_RESOLVE, 0x8 for depth, 0x9 for separate stencil. 2587 a618 VK: 0x8 for depth CCU_RESOLVE, 0x9 for separate stencil, 0 otherwise. 2588 a7xx VK: 0x8 for depth, 0x9 for separate stencil, 0x0 to 0x7 used for concurrent resolves of color render 2589 targets inside a given resolve group. 2590 --> 2591 <bitfield name="BUFFER_ID" low="12" high="15"/> 2592 </reg32> 2593 2594 <enum name="a7xx_blit_clear_mode"> 2595 <value value="0x0" name="CLEAR_MODE_SYSMEM"/> 2596 <value value="0x1" name="CLEAR_MODE_GMEM"/> 2597 </enum> 2598 <reg32 offset="0x88e4" name="RB_CLEAR_TARGET" variants="A7XX-" usage="rp_blit"> 2599 <bitfield name="CLEAR_MODE" pos="0" type="a7xx_blit_clear_mode"/> 2600 </reg32> 2601 2602 <enum name="a6xx_ccu_cache_size"> 2603 <value value="0x0" name="CCU_CACHE_SIZE_FULL"/> 2604 <value value="0x1" name="CCU_CACHE_SIZE_HALF"/> 2605 <value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/> 2606 <value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/> 2607 <!-- for DEPTH_CACHE_SIZE 3 == THREE_QUARTER from KNP --> 2608 <value value="0x3" name="CCU_CACHE_SIZE_THREE_QUARTER"/> 2609 </enum> 2610 <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A7XX" usage="cmd"> 2611 <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/> 2612 <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/> 2613 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> 2614 <!-- GMEM offset of CCU depth cache --> 2615 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/> 2616 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/> 2617 <!-- GMEM offset of CCU color cache 2618 for GMEM rendering, we set it to GMEM size minus the minimum 2619 CCU color cache size. CCU color cache will be needed in some 2620 resolve cases, and in those cases we need to reserve the end 2621 of GMEM for color cache. 2622 --> 2623 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 2624 </reg32> 2625 2626 <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A8XX-" usage="cmd"> 2627 <!-- 2628 For color cache, full is 128KB per CCU. For depth cache, 2629 full is 256KB per CCU. 2630 2631 For attr/pos caches (see VPC_{ATTR,POS,BV_POS}_BUF_GMEM_SIZE), 2632 the sizes are per CCU 2633 --> 2634 <bitfield name="COLOR_OFFSET" low="0" high="13" shr="12" type="hex"/> 2635 <bitfield name="COLOR_CACHE_SIZE" low="14" high="15" type="a6xx_ccu_cache_size"/> 2636 <bitfield name="DEPTH_OFFSET" low="16" high="29" shr="12" type="hex"/> 2637 <bitfield name="DEPTH_CACHE_SIZE" low="30" high="31" type="a6xx_ccu_cache_size"/> 2638 </reg32> 2639 2640 <reg32 offset="0x88e6" name="RB_RESOLVE_GMEM_BUFFER_CNTL" variants="A8XX-"> 2641 <bitfield name="FULL_IN_GMEM" pos="0" type="boolean"/> 2642 </reg32> 2643 2644 <!-- always 0x0 ? --> 2645 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" variants="A6XX" usage="cmd"/> 2646 <!-- could be for separate stencil? (or may not be a flag buffer at all) --> 2647 <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64" variants="A6XX"/> 2648 <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" variants="A6XX"/> 2649 2650 <reg32 offset="0x88f4" name="RB_VRS_CONFIG" usage="rp_blit"> 2651 <bitfield name="UNK2" pos="2" type="boolean"/> 2652 <bitfield name="PIPELINE_FSR_ENABLE" pos="4" type="boolean"/> 2653 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="5" type="boolean"/> 2654 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="18" type="boolean"/> 2655 </reg32> 2656 <reg32 offset="0x88f5" name="RB_BIN_FOVEAT" variants="A7XX-" usage="cmd"> 2657 <bitfield name="BINSCALEEN" pos="6" type="boolean"/> 2658 </reg32> 2659 <!-- 0x88f6-0x88ff invalid --> 2660 <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2661 <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit"> 2662 <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/> 2663 <!-- TODO: actually part of array pitch --> 2664 <bitfield name="UNK8" low="8" high="10"/> 2665 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 2666 </reg32> 2667 2668 <array offset="0x8903" name="RB_COLOR_FLAG_BUFFER" stride="3" length="8" usage="rp_blit"> 2669 <reg64 offset="0" name="ADDR" type="waddress" align="64"/> 2670 <reg32 offset="2" name="PITCH" type="a6xx_flag_buffer_pitch"/> 2671 </array> 2672 <!-- 0x891b-0x8926 invalid --> 2673 <doc> 2674 RB_SAMPLE_COUNTER_BASE register is used up to (and including) a730. After that 2675 the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. 2676 </doc> 2677 <reg64 offset="0x8927" name="RB_SAMPLE_COUNTER_BASE" type="waddress" align="16" usage="cmd"/> 2678 2679 <bitset name="a8xx_gmem_dimension" inline="yes"> 2680 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 2681 <bitfield name="HEIGHT" low="16" high="30" type="uint"/> 2682 </bitset> 2683 2684 <reg32 offset="0x8813" name="RB_DEPTH_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/> 2685 <reg32 offset="0x8814" name="RB_STENCIL_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/> 2686 <reg32 offset="0x8815" name="RB_RESOLVE_GMEM_DIMENSION" type="a8xx_gmem_dimension" variants="A8XX-"/> 2687 2688 <array offset="0x8930" name="RB_MRT_GMEM_DIMENSION" variants="A8XX-" stride="1" length="8"> 2689 <reg32 offset="0" name="REG" type="a8xx_gmem_dimension"/> 2690 </array> 2691 2692 <!-- 2693 These show up in a6xx gen3+ but so far haven't found an example of 2694 blob writing non-zero: 2695 --> 2696 <reg32 offset="0x8a00" name="RB_UNKNOWN_8A00" variants="A6XX" usage="rp_blit"/> 2697 <reg32 offset="0x8a10" name="RB_UNKNOWN_8A10" variants="A6XX" usage="rp_blit"/> 2698 <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/> 2699 <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/> 2700 2701 <reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_blt_cntl" usage="rp_blit"/> 2702 <reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="rp_blit"/> 2703 2704 <bitset name="a6xx_a2d_src_texture_info" inline="yes"> 2705 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2706 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2707 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> 2708 <bitfield name="FLAGS" pos="12" type="boolean"/> 2709 <bitfield name="SRGB" pos="13" type="boolean"/> 2710 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> 2711 <bitfield name="FILTER" pos="16" type="boolean"/> 2712 <bitfield name="UNK17" pos="17" type="boolean"/> 2713 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/> 2714 <bitfield name="UNK19" pos="19" type="boolean"/> 2715 <bitfield name="UNK20" pos="20" type="boolean"/> 2716 <bitfield name="UNK21" pos="21" type="boolean"/> 2717 <bitfield name="UNK22" pos="22" type="boolean"/> 2718 <bitfield name="UNK23" low="23" high="26"/> 2719 <bitfield name="UNK28" pos="28" type="boolean"/> 2720 <bitfield name="MUTABLEEN" pos="29" type="boolean" variants="A7XX-"/> 2721 </bitset> 2722 2723 <bitset name="a6xx_a2d_dest_buffer_info" inline="yes"> 2724 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2725 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2726 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> 2727 <bitfield name="FLAGS" pos="12" type="boolean"/> 2728 <bitfield name="SRGB" pos="13" type="boolean"/> 2729 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> 2730 <bitfield name="MUTABLEEN" pos="17" type="boolean" variants="A7XX-"/> 2731 </bitset> 2732 2733 <!-- 0x8c02-0x8c16 invalid --> 2734 <reg32 offset="0x8c17" name="RB_A2D_DEST_BUFFER_INFO" type="a6xx_a2d_dest_buffer_info" usage="rp_blit"/> 2735 <reg64 offset="0x8c18" name="RB_A2D_DEST_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2736 <reg32 offset="0x8c1a" name="RB_A2D_DEST_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 2737 <!-- this is a guess but seems likely (for NV12/IYUV): --> 2738 <reg64 offset="0x8c1b" name="RB_A2D_DEST_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> 2739 <reg32 offset="0x8c1d" name="RB_A2D_DEST_BUFFER_PITCH_1" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 2740 <reg64 offset="0x8c1e" name="RB_A2D_DEST_BUFFER_BASE_2" type="waddress" align="64" usage="rp_blit"/> 2741 2742 <reg64 offset="0x8c20" name="RB_A2D_DEST_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2743 <reg32 offset="0x8c22" name="RB_A2D_DEST_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" usage="rp_blit"/> 2744 <!-- this is a guess but seems likely (for NV12 with UBWC): --> 2745 <reg64 offset="0x8c23" name="RB_A2D_DEST_FLAG_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> 2746 <reg32 offset="0x8c25" name="RB_A2D_DEST_FLAG_BUFFER_PITCH_1" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 2747 2748 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers --> 2749 <!-- unlike a5xx, these are per channel values rather than packed --> 2750 <reg32 offset="0x8c2c" name="RB_A2D_CLEAR_COLOR_DW0" usage="rp_blit"/> 2751 <reg32 offset="0x8c2d" name="RB_A2D_CLEAR_COLOR_DW1" usage="rp_blit"/> 2752 <reg32 offset="0x8c2e" name="RB_A2D_CLEAR_COLOR_DW2" usage="rp_blit"/> 2753 <reg32 offset="0x8c2f" name="RB_A2D_CLEAR_COLOR_DW3" usage="rp_blit"/> 2754 2755 <reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/> 2756 2757 <!-- 0x8c35-0x8dff invalid --> 2758 2759 <!-- always 0x1 ? either doesn't exist for a650 or write-only: --> 2760 <reg32 offset="0x8e01" name="RB_RBP_CNTL" usage="cmd"/> 2761 <!-- 0x8e00-0x8e03 invalid --> 2762 <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff --> 2763 <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/> 2764 <!-- 0x02080000 in GMEM, zero otherwise? --> 2765 <reg32 offset="0x8e06" name="RB_CCU_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 2766 2767 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX"> 2768 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> 2769 <!-- concurrent resolves are apparently a 2-bit enum on a650+ --> 2770 <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/> 2771 <bitfield name="DEPTH_OFFSET_HI" pos="7" type="hex"/> 2772 <bitfield name="COLOR_OFFSET_HI" pos="9" type="hex"/> 2773 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> 2774 <!-- GMEM offset of CCU depth cache --> 2775 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/> 2776 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/> 2777 <!-- GMEM offset of CCU color cache 2778 for GMEM rendering, we set it to GMEM size minus the minimum 2779 CCU color cache size. CCU color cache will be needed in some 2780 resolve cases, and in those cases we need to reserve the end 2781 of GMEM for color cache. 2782 --> 2783 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 2784 <!--TODO: valid mask 0xfffffc1f --> 2785 </reg32> 2786 <enum name="a7xx_concurrent_resolve_mode"> 2787 <value value="0x0" name="CONCURRENT_RESOLVE_MODE_DISABLED"/> 2788 <value value="0x1" name="CONCURRENT_RESOLVE_MODE_1"/> 2789 <value value="0x2" name="CONCURRENT_RESOLVE_MODE_2"/> 2790 </enum> 2791 <enum name="a7xx_concurrent_unresolve_mode"> 2792 <value value="0x0" name="CONCURRENT_UNRESOLVE_MODE_DISABLED"/> 2793 <value value="0x1" name="CONCURRENT_UNRESOLVE_MODE_PARTIAL"/> 2794 <value value="0x3" name="CONCURRENT_UNRESOLVE_MODE_FULL"/> 2795 </enum> 2796 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-"> 2797 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> 2798 <bitfield name="CONCURRENT_RESOLVE_MODE" low="2" high="3" type="a7xx_concurrent_resolve_mode"/> 2799 <bitfield name="CONCURRENT_UNRESOLVE_MODE" low="5" high="6" type="a7xx_concurrent_unresolve_mode"/> 2800 <!-- rest of the bits were moved to RB_CCU_CACHE_CNTL --> 2801 </reg32> 2802 <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL" variants="A6XX-A7XX"> 2803 <bitfield name="MODE" pos="0" type="boolean"/> 2804 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 2805 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 2806 <bitfield name="AMSBC" pos="4" type="boolean"/> 2807 <bitfield name="UPPER_BIT" pos="10" type="uint"/> 2808 <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/> 2809 <bitfield name="UNK12" low="12" high="13"/> 2810 </reg32> 2811 <reg32 offset="0x8e08" name="RB_CCU_NC_MODE_CNTL" variants="A8XX-"/> 2812 2813 <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX" usage="cmd"/> 2814 <reg32 offset="0x8e09" name="RB_GC_GMEM_PROTECT" variants="A8XX-"/> 2815 <reg32 offset="0x8e0a" name="RB_LPAC_GMEM_PROTECT" variants="A8XX-"/> 2816 <!-- 0x8e09-0x8e0f invalid --> 2817 <array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/> 2818 <array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/> 2819 <!-- 0x8e1d-0x8e1f invalid --> 2820 <!-- 0x8e20-0x8e25 more perfcntr sel? --> 2821 <!-- 0x8e26-0x8e27 invalid --> 2822 2823 <reg32 offset="0x8f00" name="RB_CMP_NC_MODE_CNTL" variants="A8XX-"/> 2824 <reg32 offset="0x8f01" name="RB_RESOLVE_PREFETCH_CNTL" variants="A8XX-"/> 2825 <reg32 offset="0x8f02" name="RB_CMP_DBG_ECO_CNTL" variants="A8XX-"/> 2826 2827 <reg32 offset="0x8f03" name="RB_UNSLICE_STATUS" variants="A8XX-"/> 2828 <reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL" variants="A6XX-A7XX"/> 2829 <!-- 0x8e29-0x8e2b invalid --> 2830 <array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4" variants="A6XX-A7XX"/> 2831 <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX"/> 2832 <array offset="0x8f04" name="RB_PERFCTR_CMP_SEL" stride="1" length="4" variants="A8XX-"/> 2833 <array offset="0x8f10" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A8XX-"/> 2834 <reg32 offset="0x8e3b" name="RB_SUB_BLOCK_SEL_CNTL_HOST"/> 2835 <reg32 offset="0x8e3d" name="RB_SUB_BLOCK_SEL_CNTL_CD"/> 2836 <reg32 offset="0x8f29" name="RB_UFC_DBG_CNTL" variants="A8XX-"/> 2837 <!-- 0x8e3e-0x8e4f invalid --> 2838 <!-- GMEM save/restore for preemption: --> 2839 <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE" pos="0" type="boolean"/> 2840 <!-- address for GMEM save/restore? --> 2841 <reg32 offset="0x8e51" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR" type="waddress" align="1"/> 2842 <reg32 offset="0x8e77" name="RB_SLICE_UFC_PREFETCH_CNTL" variants="A8XX-"/> 2843 <reg32 offset="0x8e78" name="RB_SLICE_UFC_DBG_CNTL" variants="A8XX-"/> 2844 <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX" usage="init"/> 2845 <!-- 0x8e80-0x8e83 are valid --> 2846 <!-- 0x8e84-0x90ff invalid --> 2847 2848 <!-- 0x9000-0x90ff invalid --> 2849 2850 <reg32 offset="0x9100" name="VPC_GS_PARAM" variants="A6XX" usage="rp_blit"> 2851 <bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/> 2852 </reg32> 2853 2854 <bitset name="a6xx_vpc_xs_clip_cntl" inline="yes"> 2855 <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/> 2856 <!-- there can be up to 8 total clip/cull distance outputs, 2857 but apparenly VPC can only deal with vec4, so when there are 2858 more than 4 outputs a second location needs to be programmed 2859 --> 2860 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/> 2861 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/> 2862 </bitset> 2863 <reg32 offset="0x9101" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2864 <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2865 <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2866 2867 <reg32 offset="0x9307" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="rp_blit"/> 2868 <reg32 offset="0x9308" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="rp_blit"/> 2869 <reg32 offset="0x9309" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A8XX" usage="rp_blit"/> 2870 2871 <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2872 <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2873 <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2874 2875 <bitset name="a6xx_vpc_xs_siv_cntl" inline="yes"> 2876 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> 2877 <bitfield name="VIEWLOC" low="8" high="15" type="uint"/> 2878 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/> 2879 </bitset> 2880 2881 <reg32 offset="0x9104" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2882 <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2883 <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2884 2885 <reg32 offset="0x930a" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="rp_blit"/> 2886 <reg32 offset="0x930b" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="rp_blit"/> 2887 <reg32 offset="0x930c" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A8XX-" usage="rp_blit"/> 2888 2889 <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2890 <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2891 <reg32 offset="0x9316" name="VPC_DS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2892 2893 <bitset name="a6xx_vpc_rast_stream_cntl" inline="yes"> 2894 <!-- which stream to send to GRAS --> 2895 <bitfield name="STREAM" low="0" high="1" type="uint"/> 2896 <!-- discard primitives before rasterization --> 2897 <bitfield name="DISCARD" pos="2" type="boolean"/> 2898 </bitset> 2899 2900 <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A6XX" usage="rp_blit"/> 2901 <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/> 2902 <reg32 offset="0x930d" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A8XX-" usage="rp_blit"/> 2903 <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/> 2904 2905 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit"> 2906 <!-- this mirrors VPC_RAST_STREAM_CNTL::DISCARD, although it seems it's unused --> 2907 <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> 2908 <bitfield name="UNK2" pos="2" type="boolean"/> 2909 </reg32> 2910 2911 <reg32 offset="0x9108" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2912 <reg32 offset="0x930e" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="rp_blit"/> 2913 <bitset name="a6xx_pc_cntl" inline="yes"> 2914 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> 2915 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> 2916 <bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean"> 2917 <doc> 2918 Swaps TESS_CW_TRIS/TESS_CCW_TRIS, and also makes 2919 triangle fans and triangle strips use the D3D 2920 order instead of the OpenGL order. 2921 </doc> 2922 </bitfield> 2923 <bitfield name="UNK3" pos="3" type="boolean"/> 2924 </bitset> 2925 2926 <bitset name="a6xx_gs_param_0" inline="yes"> 2927 <doc> 2928 geometry shader 2929 </doc> 2930 <!-- TODO: first 16 bits are valid so something is wrong or missing here --> 2931 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/> 2932 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/> 2933 <bitfield name="LINELENGTHEN" pos="15" type="boolean"/> 2934 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/> 2935 <bitfield name="UNK18" pos="18"/> 2936 </bitset> 2937 2938 <bitset name="a6xx_stereo_rendering_cntl" inline="yes"> 2939 <bitfield name="ENABLE" pos="0" type="boolean"/> 2940 <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean"> 2941 <doc> 2942 Multi-position output lets the last geometry 2943 stage shader write multiple copies of 2944 gl_Position. If disabled then the VS is run once 2945 for each view, and ViewID is passed as a 2946 register to the VS. 2947 </doc> 2948 </bitfield> 2949 <bitfield name="VIEWS" low="2" high="6" type="uint"/> 2950 </bitset> 2951 2952 <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX" usage="rp_blit"/> 2953 <reg32 offset="0x930f" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A8XX-" usage="rp_blit"/> 2954 <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX" usage="rp_blit"/> 2955 <reg32 offset="0x90c0" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A8XX-" usage="rp_blit"/> 2956 <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX" usage="rp_blit"/> 2957 <reg32 offset="0x90c1" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A8XX-" usage="rp_blit"/> 2958 <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX" usage="rp_blit"/> 2959 <reg32 offset="0x931a" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A8XX-" usage="rp_blit"/> 2960 2961 <enum name="a6xx_varying_interp_mode"> 2962 <value value="0" name="INTERP_SMOOTH"/> 2963 <value value="1" name="INTERP_FLAT"/> 2964 <value value="2" name="INTERP_ZERO"/> 2965 <value value="3" name="INTERP_ONE"/> 2966 </enum> 2967 2968 <enum name="a6xx_varying_ps_repl_mode"> 2969 <value value="0" name="PS_REPL_NONE"/> 2970 <value value="1" name="PS_REPL_S"/> 2971 <value value="2" name="PS_REPL_T"/> 2972 <value value="3" name="PS_REPL_ONE_MINUS_T"/> 2973 </enum> 2974 2975 <!-- 0x9109-0x91ff invalid --> 2976 <array offset="0x9200" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" variants="A6XX-A7XX" usage="rp_blit"> 2977 <doc>Packed array of a6xx_varying_interp_mode</doc> 2978 <reg32 offset="0x0" name="MODE"/> 2979 </array> 2980 <array offset="0x9208" name="VPC_VARYING_REPLACE_MODE" stride="1" length="8" variants="A6XX-A7XX" usage="rp_blit"> 2981 <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 2982 <reg32 offset="0x0" name="MODE"/> 2983 </array> 2984 2985 <array offset="0x9240" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" variants="A8XX-" usage="rp_blit"> 2986 <doc>Packed array of a6xx_varying_interp_mode</doc> 2987 <reg32 offset="0x0" name="MODE"/> 2988 </array> 2989 <array offset="0x9248" name="VPC_VARYING_REPLACE_MODE" stride="1" length="8" variants="A8XX-" usage="rp_blit"> 2990 <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 2991 <reg32 offset="0x0" name="MODE"/> 2992 </array> 2993 2994 <!-- always 0x0 --> 2995 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/> 2996 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/> 2997 2998 <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A6XX-A7XX" usage="rp_blit"> 2999 <!-- one bit per varying component: --> 3000 <reg32 offset="0" name="DISABLE"/> 3001 </array> 3002 3003 <array offset="0x9252" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A8XX-" usage="rp_blit"> 3004 <!-- one bit per varying component: --> 3005 <reg32 offset="0" name="DISABLE"/> 3006 </array> 3007 3008 <bitset name="a6xx_vpc_so_mapping_wptr" inline="yes"> 3009 <!-- 3010 Choose which DWORD to write to. There is an array of 3011 (4 * 64) DWORD's, dumped in the devcoredump at 3012 HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a 3013 (VPC location, stream) pair like so: 3014 3015 location 0, stream 0 3016 location 2, stream 0 3017 ... 3018 location 126, stream 0 3019 location 0, stream 1 3020 location 2, stream 1 3021 ... 3022 location 126, stream 1 3023 location 0, stream 2 3024 ... 3025 3026 When EmitStreamVertex(N) happens, the HW goes to DWORD 3027 64 * N and then "executes" the next 64 DWORD's. 3028 3029 This field is auto-incremented when VPC_SO_MAPPING_PORT is 3030 written to. 3031 --> 3032 <bitfield name="ADDR" low="0" high="7" type="hex"/> 3033 <!-- clear all A_EN and B_EN bits for all DWORD's --> 3034 <bitfield name="RESET" pos="16" type="boolean"/> 3035 </bitset> 3036 3037 <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A6XX-A7XX" usage="rp_blit"/> 3038 <reg32 offset="0x9180" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A8XX-" usage="rp_blit"/> 3039 3040 <bitset name="a6xx_vpc_so_mapping_port" inline="yes"> 3041 <bitfield name="A_BUF" low="0" high="1" type="uint"/> 3042 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> 3043 <bitfield name="A_EN" pos="11" type="boolean"/> 3044 <bitfield name="B_BUF" low="12" high="13" type="uint"/> 3045 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> 3046 <bitfield name="B_EN" pos="23" type="boolean"/> 3047 </bitset> 3048 3049 <!-- special register, write multiple times to load SO program (not readable) --> 3050 <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A6XX-A7XX" usage="rp_blit"/> 3051 <reg32 offset="0x9181" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A8XX-" usage="rp_blit"/> 3052 3053 <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A6XX-A7XX" usage="cmd"/> 3054 <reg64 offset="0x9182" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A8XX-" usage="cmd"/> 3055 3056 <array offset="0x921a" name="VPC_SO" stride="7" length="4" variants="A6XX-A7XX" usage="cmd"> 3057 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 3058 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 3059 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> 3060 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/> 3061 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 3062 </array> 3063 3064 <array offset="0x9184" name="VPC_SO" stride="7" length="4" variants="A8XX-" usage="cmd"> 3065 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 3066 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 3067 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> 3068 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/> 3069 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 3070 </array> 3071 3072 <bitset name="a6xx_vpc_replace_mode_cntl" inline="yes"> 3073 <bitfield name="INVERT" pos="0" type="boolean"/> 3074 </bitset> 3075 3076 <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A6XX-A7XX" usage="cmd"/> 3077 <reg32 offset="0x9310" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A8XX-" usage="cmd"/> 3078 3079 <reg32 offset="0x9300" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A6XX-A7XX" usage="cmd"/> 3080 <reg32 offset="0x9312" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A8XX-" usage="cmd"/> 3081 3082 <bitset name="a6xx_vpc_xs_cntl" inline="yes"> 3083 <doc> 3084 num of varyings plus four for gl_Position (plus one if gl_PointSize) 3085 plus # of transform-feedback (streamout) varyings if using the 3086 hw streamout (rather than stg instructions in shader) 3087 </doc> 3088 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 3089 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/> 3090 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/> 3091 <bitfield name="EXTRAPOS" low="24" high="27" type="uint"> 3092 <doc> 3093 The number of extra copies of POSITION, i.e. 3094 number of views minus one when multi-position 3095 output is enabled, otherwise 0. 3096 </doc> 3097 </bitfield> 3098 </bitset> 3099 3100 <reg32 offset="0x9301" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3101 <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3102 <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3103 3104 <reg32 offset="0x9300" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 3105 <reg32 offset="0x9301" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 3106 <reg32 offset="0x9302" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 3107 3108 <bitset name="a6xx_vpc_ps_cntl" inline="yes"> 3109 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> 3110 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> 3111 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/> 3112 <bitfield name="VARYING" pos="16" type="boolean"/> 3113 <bitfield name="VIEWIDLOC" low="24" high="31" type="uint"> 3114 <doc> 3115 This VPC location will be overwritten with 3116 ViewID when multiview is enabled. It's used when 3117 fragment shaders read ViewID. It's only 3118 strictly required for multi-position output, 3119 where the same VS invocation is used for all the 3120 views at once, but it can be used when multi-pos 3121 output is disabled too, to avoid having to pass 3122 ViewID through the VS. 3123 </doc> 3124 </bitfield> 3125 </bitset> 3126 3127 <reg32 offset="0x9304" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3128 <reg32 offset="0x9303" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A8XX-" usage="rp_blit"/> 3129 3130 <bitset name="a6xx_vpc_so_cntl" inline="yes"> 3131 <!-- 3132 It's offset by 1, and 0 means "disabled" 3133 --> 3134 <bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/> 3135 <bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/> 3136 <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/> 3137 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/> 3138 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 3139 </bitset> 3140 3141 <reg32 offset="0x9305" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3142 <reg32 offset="0x9304" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A8XX-" usage="rp_blit"/> 3143 3144 <bitset name="a6xx_so_override" inline="yes"> 3145 <bitfield name="DISABLE" pos="0" type="boolean"/> 3146 </bitset> 3147 3148 <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A6XX-A7XX" usage="rp_blit"/> 3149 <reg32 offset="0x9305" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A8XX-" usage="rp_blit"/> 3150 3151 <reg32 offset="0x9807" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A7XX" usage="rp_blit"/> 3152 <reg32 offset="0x9b0a" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A8XX-" usage="rp_blit"/> 3153 3154 <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3155 <reg32 offset="0x9306" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX-" usage="rp_blit"/> 3156 3157 <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="cmd"/> 3158 <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX" type="hex" usage="cmd"/> 3159 3160 <reg32 offset="0x9314" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3161 <reg32 offset="0x9315" name="VPC_ATTR_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/> 3162 3163 <reg32 offset="0x9316" name="VPC_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3164 <reg32 offset="0x9317" name="VPC_POS_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/> 3165 3166 <reg32 offset="0x9318" name="VPC_BV_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3167 <reg32 offset="0x9319" name="VPC_BV_POS_BUF_GMEM_BASE" variants="A8XX-" type="hex" usage="cmd"/> 3168 3169 <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="cmd"/> 3170 <reg32 offset="0x9b16" name="PC_ATTR_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3171 3172 <reg32 offset="0x9b17" name="PC_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3173 <reg32 offset="0x9b18" name="PC_BV_POS_BUF_GMEM_SIZE" variants="A8XX-" type="uint" usage="cmd"/> 3174 3175 <reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX"/> 3176 3177 <reg32 offset="0x9313" name="VPC_UNKNOWN_9313" variants="A8XX-"/> 3178 <reg32 offset="0x9e17" name="PC_UNKNOWN_9E17" variants="A8XX-"/> 3179 3180 <reg32 offset="0x960a" name="VPC_FLATSHADE_MODE_CNTL" variants="A7XX"/> 3181 <reg32 offset="0x9741" name="VPC_FLATSHADE_MODE_CNTL" variants="A8XX-"/> 3182 3183 <!-- 0x9307-0x95ff invalid --> 3184 3185 <!-- TODO: 0x9600-0x97ff range --> 3186 <reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" variants="A6XX-A7XX" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask --> 3187 <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd" variants="A6XX"/> 3188 <reg32 offset="0x9680" name="VPC_DBG_ECO_CNTL" variants="A8XX-"/> 3189 <reg32 offset="0x9604" name="VPC_DBG_ECO_CNTL_2" variants="A8XX-"/> 3190 <reg32 offset="0x9742" name="VPC_DBG_ECO_CNTL_1" variants="A8XX-"/> 3191 <reg32 offset="0x9745" name="VPC_DBG_ECO_CNTL_3" variants="A8XX-"/> 3192 <reg32 offset="0x9602" name="VPC_LB_MODE_CNTL" pos="0" variants="A6XX-A7XX" usage="init"/> <!-- always 0x0 ? --> 3193 <reg32 offset="0x9740" name="VPC_LB_MODE_CNTL" pos="0" variants="A8XX-"/> 3194 <reg32 offset="0x9603" name="VPC_STATUS" low="0" high="26" variants="A6XX-A7XX"/> 3195 <reg32 offset="0x9600" name="VPC_STATUS" low="0" high="26" variants="A8XX-"/> 3196 <array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/> 3197 <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX"/> 3198 <array offset="0x9670" name="VPC_PERFCTR_VPC_SEL_2" stride="1" length="12" variants="A8XX-"/> 3199 <array offset="0x9690" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A8XX-"/> 3200 <array offset="0x9750" name="VPC_PERFCTR_VPC_SEL_1" stride="1" length="12" variants="A8XX-"/> 3201 3202 <reg64 offset="0x9634" name="VPC_CONTEXT_SWITCH_SO_SAVE_ADDR" type="waddress" variants="A6XX-A7XX"/> 3203 <reg64 offset="0x9602" name="VPC_CONTEXT_SWITCH_SO_SAVE_ADDR" type="waddress" variants="A8XX-"/> 3204 3205 <reg32 offset="0x980b" name="PC_UNKNOWN_980B" variants="A8XX-"/> 3206 3207 <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A6XX-A7XX" usage="rp_blit"/> 3208 <reg32 offset="0x9b10" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A8XX-" usage="rp_blit"/> 3209 3210 <bitset name="a6xx_pc_hs_param_1" inline="yes"> 3211 <bitfield name="SIZE" low="0" high="10" type="uint"/> 3212 <bitfield name="UNK13" pos="13"/> 3213 </bitset> 3214 3215 <reg32 offset="0x9801" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A6XX-A7XX" usage="rp_blit"/> 3216 <reg32 offset="0x9b11" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A8XX-" usage="rp_blit"/> 3217 3218 <bitset name="a6xx_pc_ds_param" inline="yes"> 3219 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> 3220 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> 3221 </bitset> 3222 3223 <reg32 offset="0x9802" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A6XX-A7XX" usage="rp_blit"/> 3224 <reg32 offset="0x9b12" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A8XX-" usage="rp_blit"/> 3225 3226 <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A6XX-A7XX" usage="rp_blit"/> 3227 <reg32 offset="0x9b15" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A8XX-" usage="rp_blit"/> 3228 3229 <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" variants="A6XX-A7XX" usage="rp_blit"/> 3230 <reg32 offset="0x9b00" name="PC_MODE_CNTL" low="0" high="14" variants="A8XX" usage="rp_blit"/> 3231 3232 <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 3233 3234 <bitset name="a6xx_pc_ps_cntl" inline="yes"> 3235 <bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/> 3236 </bitset> 3237 3238 <reg32 offset="0x9806" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3239 <reg32 offset="0x9b06" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A8XX-" usage="rp_blit"/> 3240 3241 <bitset name="a6xx_pc_dgen_so_cntl" inline="yes"> 3242 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 3243 </bitset> 3244 3245 <!-- New in a6xx gen3+ --> 3246 <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3247 <reg32 offset="0x9b0b" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A8XX-" usage="rp_blit"/> 3248 3249 <bitset name="a6xx_pc_dgen_su_conservative_ras_cntl" inline="yes"> 3250 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 3251 </bitset> 3252 3253 <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A6XX-A7XX"/> 3254 <reg32 offset="0x9b08" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A8XX-"/> 3255 3256 <reg32 offset="0x9b0c" name="PC_VS_INPUT_CNTL" variants="A8XX-" usage="rp_blit"> 3257 <bitfield name="INSTR_CNT" low="0" high="5" type="uint"/> 3258 <bitfield name="SIDEBAND_CNT" low="6" high="8" type="uint"/> 3259 </reg32> 3260 3261 <!-- 0x9840 - 0x9842 are not readable --> 3262 <bitset name="a6xx_draw_initiator" inline="yes"> 3263 <bitfield name="STATE_ID" low="0" high="7"/> 3264 </bitset> 3265 3266 <reg32 offset="0x9840" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 3267 <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 3268 3269 <reg32 offset="0x9800" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A8XX-"/> 3270 <reg32 offset="0x9801" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A8XX-"/> 3271 3272 <bitset name="a6xx_event_initiator" inline="yes"> 3273 <!-- I think only the low bit is actually used? --> 3274 <bitfield name="STATE_ID" low="16" high="23"/> 3275 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3276 </bitset> 3277 3278 <reg32 offset="0x9842" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A6XX-A7XX"/> 3279 <reg32 offset="0x9802" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A8XX-"/> 3280 3281 <!-- 3282 0x9880 written in a lot of places by SQE, same value gets written 3283 to control reg 0x12a. Set by CP_SET_MARKER, so lets name it after 3284 that 3285 --> 3286 <reg32 offset="0x9880" name="PC_MARKER"/> 3287 3288 <!-- 0x9843-0x997f invalid --> 3289 3290 <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX" usage="rp_blit"/> 3291 <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A7XX" usage="rp_blit"/> 3292 <reg32 offset="0x9812" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A8XX" usage="rp_blit"/> 3293 3294 <!-- Both are a750+. 3295 Probably needed to correctly overlap execution of several draws. 3296 --> 3297 <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 3298 <reg32 offset="0x9814" name="PC_HS_BUFFER_SIZE" variants="A8XX-" usage="cmd"/> 3299 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of 3300 this additional space is not known. 3301 --> 3302 <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 3303 <reg32 offset="0x9815" name="PC_TF_BUFFER_SIZE" variants="A8XX-" usage="cmd"/> 3304 3305 <!-- 0x9982-0x9aff invalid --> 3306 3307 <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3308 <reg32 offset="0x9b01" name="PC_CNTL" type="a6xx_pc_cntl" variants="A8XX-" usage="rp_blit"/> 3309 3310 <bitset name="a6xx_pc_xs_cntl" inline="yes"> 3311 <doc> 3312 num of varyings plus four for gl_Position (plus one if gl_PointSize) 3313 plus # of transform-feedback (streamout) varyings if using the 3314 hw streamout (rather than stg instructions in shader) 3315 </doc> 3316 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 3317 <bitfield name="PSIZE" pos="8" type="boolean"/> 3318 <bitfield name="LAYER" pos="9" type="boolean"/> 3319 <bitfield name="VIEW" pos="10" type="boolean"/> 3320 <!-- note: PC_VS_CNTL doesn't have the PRIMITIVE_ID bit --> 3321 <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 3322 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> 3323 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/> 3324 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/> 3325 </bitset> 3326 3327 <reg32 offset="0x9b01" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3328 <reg32 offset="0x9b02" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3329 <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3330 <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3331 3332 <reg32 offset="0x9b02" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 3333 <reg32 offset="0x9b03" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 3334 <reg32 offset="0x9b04" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 3335 <reg32 offset="0x9b05" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A8XX-" usage="rp_blit"/> 3336 3337 <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A6XX-A7XX" usage="rp_blit"/> 3338 <reg32 offset="0x9b13" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A8XX-" usage="rp_blit"/> 3339 3340 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit"> 3341 <doc> 3342 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC 3343 </doc> 3344 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/> 3345 </reg32> 3346 3347 <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3348 <reg32 offset="0x9b09" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A8XX-" usage="rp_blit"/> 3349 <!-- mask of enabled views, doesn't exist on A630 --> 3350 <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A6XX-A7XX" usage="rp_blit"/> 3351 <reg32 offset="0x9b0d" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A8XX-" usage="rp_blit"/> 3352 <!-- 0x9b09-0x9bff invalid --> 3353 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> 3354 <!-- special register (but note first 8 bits can be written/read) --> 3355 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3356 <bitfield name="STATE_ID" low="8" high="15"/> 3357 </reg32> 3358 3359 <reg32 offset="0x9e50" name="PC_CHICKEN_BITS_1" variants="A8XX-"/> 3360 <reg32 offset="0x9f20" name="PC_CHICKEN_BITS_2" variants="A8XX-"/> 3361 <reg32 offset="0x9e22" name="PC_CHICKEN_BITS_3" variants="A8XX-"/> 3362 <reg32 offset="0x9e23" name="PC_CHICKEN_BITS_4" variants="A8XX-"/> 3363 <reg32 offset="0x9f23" name="PC_CHICKEN_BITS_5" variants="A8XX-"/> 3364 3365 <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL" variants="A6XX-A7XX"/> 3366 <reg32 offset="0x9e53" name="PC_DBG_ECO_CNTL" variants="A8XX-"/> 3367 <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 3368 <reg64 offset="0x9e04" name="PC_DMA_BASE" type="address" variants="A6XX-A7XX"/> 3369 <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint" variants="A6XX-A7XX"/> 3370 <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint" variants="A6XX-A7XX"/> 3371 3372 <reg64 offset="0x9e06" name="PC_DMA_BASE" type="address" variants="A8XX-"/> 3373 <reg32 offset="0x9e08" name="PC_DMA_OFFSET" type="uint" variants="A8XX-"/> 3374 <reg32 offset="0x9e09" name="PC_DMA_SIZE" type="uint" variants="A8XX-"/> 3375 3376 <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> 3377 <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX" type="waddress" align="32" usage="cmd"/> 3378 <reg64 offset="0x9816" name="PC_TESS_BASE" variants="A8XX-" type="waddress" align="32" usage="cmd"/> 3379 3380 <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A6XX-A7XX"> 3381 <doc> 3382 Possibly not really "initiating" the draw but the layout is similar 3383 to VGT_DRAW_INITIATOR on older gens 3384 </doc> 3385 </reg32> 3386 <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A6XX-A7XX"/> 3387 <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint" variants="A6XX-A7XX"/> 3388 3389 <reg32 offset="0x9e00" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A8XX-"/> 3390 <reg32 offset="0x9e01" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A8XX-"/> 3391 <reg32 offset="0x9e02" name="PC_DRAWCALL_SIZE" type="uint" variants="A8XX-"/> 3392 3393 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> 3394 <bitset name="a6xx_pc_vis_stream_cntl" inline="yes"> 3395 <bitfield name="UNK0" low="0" high="15"/> 3396 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 3397 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 3398 </bitset> 3399 3400 <reg32 offset="0x9e11" name="PC_VIS_STREAM_CNTL" type="a6xx_pc_vis_stream_cntl" variants="A6XX-A7XX"/> 3401 <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 3402 <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 3403 3404 <reg32 offset="0x9e0a" name="PC_AUTO_VERTEX_STRIDE"/> 3405 <reg32 offset="0x9e0d" name="PC_VIS_STREAM_CNTL" type="a6xx_pc_vis_stream_cntl" variants="A8XX-"/> 3406 <reg64 offset="0x9e0e" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/> 3407 <reg64 offset="0x9e10" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A8XX-"/> 3408 3409 <bitset name="a6xx_pc_drawcall_cntl_override" inline="yes"> 3410 <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> 3411 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 3412 </bitset> 3413 3414 <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A6XX-A7XX"/> 3415 <reg32 offset="0x9e04" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A8XX-"/> 3416 3417 <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="init"/> 3418 3419 <array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/> 3420 <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX"/> 3421 <array offset="0x9e30" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A8XX-"/> 3422 <array offset="0x9f00" name="PC_SLICE_PERFCTR_PC_SEL" stride="1" length="16" variants="A8XX-"/> 3423 3424 <!-- always 0x0 --> 3425 <reg32 offset="0x9e72" name="PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE" variants="A6XX-A7XX" usage="init"/> 3426 <reg32 offset="0x9e63" name="PC_CONTEXT_SWITCH_GFX_PREEMPTION_MODE" variants="A8XX-"/> 3427 <reg32 offset="0x9e64" name="PC_CONTEXT_SWITCH_STABILIZE_CNTL_1" variants="A8XX-"/> 3428 3429 <reg32 offset="0xa000" name="VFD_CNTL_0" usage="rp_blit"> 3430 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/> 3431 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/> 3432 </reg32> 3433 <reg32 offset="0xa001" name="VFD_CNTL_1" usage="rp_blit"> 3434 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/> 3435 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/> 3436 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/> 3437 <!-- only used for VS in non-multi-position-output case --> 3438 <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/> 3439 </reg32> 3440 <reg32 offset="0xa002" name="VFD_CNTL_2" usage="rp_blit"> 3441 <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid"> 3442 <doc> 3443 This is the ID of the current patch within the 3444 subdraw, used to calculate the offset of the 3445 patch within the HS->DS buffers. When a draw is 3446 split into multiple subdraws then this differs 3447 from gl_PrimitiveID on the second, third, etc. 3448 subdraws. 3449 </doc> 3450 </bitfield> 3451 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/> 3452 </reg32> 3453 <reg32 offset="0xa003" name="VFD_CNTL_3" usage="rp_blit"> 3454 <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/> 3455 <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/> 3456 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> 3457 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> 3458 </reg32> 3459 <reg32 offset="0xa004" name="VFD_CNTL_4" usage="rp_blit"> 3460 <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/> 3461 </reg32> 3462 <reg32 offset="0xa005" name="VFD_CNTL_5" usage="rp_blit"> 3463 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/> 3464 <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/> 3465 </reg32> 3466 <reg32 offset="0xa006" name="VFD_CNTL_6" usage="rp_blit"> 3467 <!-- 3468 True if gl_PrimitiveID is read via the FS 3469 --> 3470 <bitfield name="PRIMID4PSEN" pos="0" type="boolean"/> 3471 </reg32> 3472 3473 <reg32 offset="0xa007" name="VFD_RENDER_MODE" usage="cmd"> 3474 <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/> 3475 </reg32> 3476 3477 <reg32 offset="0xa008" name="VFD_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="rp_blit"/> 3478 <reg32 offset="0xa009" name="VFD_MODE_CNTL" usage="cmd"> 3479 <!-- add VFD_INDEX_OFFSET to REGID4VTX --> 3480 <bitfield name="VERTEX" pos="0" type="boolean"/> 3481 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST --> 3482 <bitfield name="INSTANCE" pos="1" type="boolean"/> 3483 </reg32> 3484 3485 <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/> 3486 <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/> 3487 <array offset="0xa010" name="VFD_VERTEX_BUFFER" stride="4" length="32" usage="rp_blit"> 3488 <reg64 offset="0x0" name="BASE" type="address" align="1"/> 3489 <reg32 offset="0x2" name="SIZE" type="uint"/> 3490 <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/> 3491 </array> 3492 <array offset="0xa090" name="VFD_FETCH_INSTR" stride="2" length="32" usage="rp_blit"> 3493 <reg32 offset="0x0" name="INSTR"> 3494 <!-- IDX and byte OFFSET into VFD_VERTEX_BUFFER --> 3495 <bitfield name="IDX" low="0" high="4" type="uint"/> 3496 <bitfield name="OFFSET" low="5" high="16"/> 3497 <bitfield name="INSTANCED" pos="17" type="boolean"/> 3498 <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/> 3499 <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/> 3500 <bitfield name="UNK30" pos="30" type="boolean"/> 3501 <bitfield name="FLOAT" pos="31" type="boolean"/> 3502 </reg32> 3503 <reg32 offset="0x1" name="STEP_RATE" type="uint"/> 3504 </array> 3505 <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32" usage="rp_blit"> 3506 <reg32 offset="0x0" name="INSTR"> 3507 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/> 3508 <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/> 3509 </reg32> 3510 </array> 3511 3512 <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 3513 3514 <reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="init"/> 3515 3516 <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 3517 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/> 3518 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/> 3519 <reg32 offset="0xa639" name="VFD_CB_BV_THRESHOLD" variants="A8XX-"/> 3520 <reg32 offset="0xa63a" name="VFD_CB_BR_THRESHOLD" variants="A8XX-"/> 3521 <reg32 offset="0xa63b" name="VFD_CB_BUSY_REQ_CNT" variants="A8XX-"/> 3522 <reg32 offset="0xa63c" name="VFD_CB_LP_REQ_CNT" variants="A8XX-"/> 3523 3524 <!-- 3525 Note: this seems to always be paired with another bit in another 3526 block. 3527 --> 3528 <enum name="a6xx_threadsize"> 3529 <value value="0" name="THREAD64"/> 3530 <value value="1" name="THREAD128"/> 3531 </enum> 3532 3533 <bitset name="a6xx_sp_xs_cntl_0" inline="yes"> 3534 <!-- if set to SINGLE, only use 1 concurrent wave on each SP --> 3535 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> 3536 <!-- 3537 When b31 set we just see FULLREGFOOTPRINT set. The pattern of 3538 used registers is a bit odd too: 3539 - used (half): 0-15 68-179 (cnt=128, max=179) 3540 - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127> 3541 whereas we usually see a (mostly) contiguous range of regs used. But if 3542 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)), 3543 then: 3544 - used (merged): 0-191 (cnt=192, max=191) 3545 So I think if b31 is set, then the half precision registers overlap 3546 the full precision registers. (Which seems like a pretty sensible 3547 feature, actually I'm not sure when you *wouldn't* want to use that, 3548 since it gives register allocation more flexibility) 3549 --> 3550 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/> 3551 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/> 3552 <!-- could it be a low bit of branchstack? --> 3553 <bitfield name="UNK13" pos="13" type="boolean"/> 3554 <!-- seems to be nesting level for flow control:.. --> 3555 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/> 3556 </bitset> 3557 3558 <bitset name="a6xx_sp_xs_config" inline="yes"> 3559 <!-- 3560 Each of these are set if the given resource type is used 3561 with the Vulkan/bindless binding model. 3562 --> 3563 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/> 3564 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/> 3565 <bitfield name="BINDLESS_UAV" pos="2" type="boolean"/> 3566 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/> 3567 3568 <bitfield name="ENABLED" pos="8" type="boolean"/> 3569 <!-- 3570 number of textures and samplers.. these might be swapped, with GL I 3571 always see the same value for both. 3572 --> 3573 <bitfield name="NTEX" low="9" high="16" type="uint"/> 3574 <bitfield name="NSAMP" low="17" high="21" type="uint"/> 3575 <bitfield name="NUAV" low="22" high="28" type="uint"/> 3576 </bitset> 3577 3578 <bitset name="a6xx_sp_xs_output_cntl" inline="yes"> 3579 <!-- # of VS outputs including pos/psize --> 3580 <bitfield name="OUT" low="0" high="5" type="uint"/> 3581 </bitset> 3582 3583 <reg32 offset="0xa800" name="SP_VS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 3584 <!-- 3585 This field actually controls all geometry stages. TCS, TES, and 3586 GS must have the same mergedregs setting as VS. 3587 --> 3588 <bitfield name="MERGEDREGS" pos="20" type="boolean"/> 3589 <!-- 3590 Creates a separate preamble-only thread? 3591 3592 Early preamble has the following limitations: 3593 - Only shared, a1, and consts regs could be used 3594 (accessing other regs would result in GPU fault); 3595 - No cat5/cat6, only stc/ldc variants are working; 3596 - Values writen to shared regs are not accessible by the rest 3597 of the shader; 3598 - Instructions before shps are also considered to be a part of 3599 early preamble; 3600 3601 Note, for all shaders from d3d11 games blob produced preambles 3602 compatible with early preamble mode. 3603 --> 3604 <bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/> 3605 </reg32> 3606 <!-- bitmask of true/false conditions for VS brac.N instructions, 3607 bit N corresponds to brac.N --> 3608 <reg32 offset="0xa801" name="SP_VS_BOOLEAN_CF_MASK" type="hex"/> 3609 <!-- # of VS outputs including pos/psize --> 3610 <reg32 offset="0xa802" name="SP_VS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> 3611 <array offset="0xa803" name="SP_VS_OUTPUT" stride="1" length="16" usage="rp_blit"> 3612 <reg32 offset="0x0" name="REG"> 3613 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3614 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3615 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3616 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3617 </reg32> 3618 </array> 3619 <!-- 3620 Starting with a5xx, position/psize outputs from shader end up in the 3621 SP_VS_OUTPUT map, with highest OUTLOCn position. (Generally they are 3622 the last entries too, except when gl_PointCoord is used, blob inserts 3623 an extra varying after, but with a lower OUTLOC position. If present, 3624 psize is last, preceded by position. 3625 --> 3626 <array offset="0xa813" name="SP_VS_VPC_DEST" stride="1" length="8" usage="rp_blit"> 3627 <reg32 offset="0x0" name="REG"> 3628 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3629 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3630 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3631 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3632 </reg32> 3633 </array> 3634 3635 <bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes"> 3636 <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9"> 3637 <doc>The size of memory that ldp/stp can address.</doc> 3638 </bitfield> 3639 <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31"> 3640 <doc> 3641 Seems to be the same as a3xx. The maximum stack 3642 size in units of 4 calls, so a call depth of 7 3643 would result in a value of 2. 3644 TODO: What's the actual size per call, i.e. the 3645 size of the PC? a3xx docs say it's 16 bits 3646 there, but the length register now takes 28 bits 3647 so it's probably been bumped to 32 bits. 3648 </doc> 3649 </bitfield> 3650 </bitset> 3651 3652 <bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes"> 3653 <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/> 3654 <bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean"> 3655 <doc> 3656 There are four indices used to compute the 3657 private memory location for an access: 3658 3659 - stp/ldp offset 3660 - fiber id 3661 - wavefront id (a swizzled version of what "getwid" returns) 3662 - SP ID (the same as what "getspid" returns) 3663 3664 The stride for the SP ID is always set by 3665 TOTALPVTMEMSIZE. In the per-wave layout, the 3666 indices are used in this order: 3667 3668 - offset % 4 (offset within dword) 3669 - fiber id 3670 - offset / 4 3671 - wavefront id 3672 - SP ID 3673 3674 and the stride for the wavefront ID is 3675 MEMSIZEPERITEM, multiplied by 128 (fibers per 3676 wavefront). In the per-fiber layout, the indices 3677 are used in this order: 3678 3679 - offset 3680 - fiber id % 4 3681 - wavefront id 3682 - fiber id / 4 3683 - SP ID 3684 3685 and the stride for the fiber id/wavefront id 3686 combo is MEMSIZEPERITEM. 3687 3688 Note: Accesses of more than 1 dword do not work 3689 with per-fiber layout. The blob will fall back 3690 to per-wave instead. 3691 </doc> 3692 </bitfield> 3693 </bitset> 3694 3695 <bitset name="a6xx_sp_xs_pvt_mem_stack_offset" inline="yes"> 3696 <doc> 3697 This seems to be be the equivalent of HWSTACKOFFSET in 3698 a3xx. The ldp/stp offset formula above isn't affected by 3699 HWSTACKSIZEPERTHREAD at all, so the HW return address 3700 stack seems to be after all the normal per-SP private 3701 memory. 3702 </doc> 3703 <bitfield name="OFFSET" low="0" high="18" shr="11"/> 3704 </bitset> 3705 3706 <bitset name="a6xx_sp_xs_hysteresis" inline="yes"> 3707 <doc>Same on a6xx/a7xx, UMD should not need to write this</doc> 3708 </bitset> 3709 3710 <bitset name="a8xx_sp_xs_hysteresis" inline="yes"> 3711 <doc>UMD needs to write in some cases</doc> 3712 <!-- seen 0x400, 0xc00, 0x1000, 0x1c00, 0x1000, 0x2000, 0x3000 --> 3713 </bitset> 3714 3715 <reg32 offset="0xa81b" name="SP_VS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 3716 <reg64 offset="0xa81c" name="SP_VS_BASE" type="address" align="32" usage="rp_blit"/> 3717 <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3718 <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 3719 <reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3720 <reg32 offset="0xa822" name="SP_VS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 3721 <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3722 <reg32 offset="0xa824" name="SP_VS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3723 <reg32 offset="0xa825" name="SP_VS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 3724 <reg32 offset="0xa826" name="SP_VS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 3725 <reg32 offset="0xa826" name="SP_VS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3726 <reg32 offset="0xa82d" name="SP_VS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3727 3728 <reg32 offset="0xa830" name="SP_HS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 3729 <!-- There is no mergedregs bit, that comes from the VS. --> 3730 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3731 </reg32> 3732 <!-- 3733 Total size of local storage in dwords divided by the wave size. 3734 The maximum value is 64. With the wave size being always 64 for HS, 3735 the maximum size of local storage should be: 3736 64 (wavesize) * 64 (SP_HS_CNTL_1) * 4 = 16k 3737 --> 3738 <reg32 offset="0xa831" name="SP_HS_CNTL_1" low="0" high="7" type="uint" usage="rp_blit"/> 3739 <reg32 offset="0xa832" name="SP_HS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/> 3740 3741 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3742 <reg32 offset="0xa833" name="SP_HS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 3743 <reg64 offset="0xa834" name="SP_HS_BASE" type="address" align="32" usage="rp_blit"/> 3744 <reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3745 <reg64 offset="0xa837" name="SP_HS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 3746 <reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3747 <reg32 offset="0xa83a" name="SP_HS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 3748 <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3749 <reg32 offset="0xa83c" name="SP_HS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3750 <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 3751 <reg32 offset="0xa83e" name="SP_HS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 3752 <reg32 offset="0xa83e" name="SP_HS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3753 <reg32 offset="0xa82f" name="SP_HS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3754 3755 <reg32 offset="0xa840" name="SP_DS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 3756 <!-- There is no mergedregs bit, that comes from the VS. --> 3757 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3758 </reg32> 3759 <reg32 offset="0xa841" name="SP_DS_BOOLEAN_CF_MASK" type="hex"/> 3760 3761 <!-- TODO: exact same layout as 0xa802-0xa81a --> 3762 <reg32 offset="0xa842" name="SP_DS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> 3763 <array offset="0xa843" name="SP_DS_OUTPUT" stride="1" length="16" usage="rp_blit"> 3764 <reg32 offset="0x0" name="REG"> 3765 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3766 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3767 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3768 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3769 </reg32> 3770 </array> 3771 <array offset="0xa853" name="SP_DS_VPC_DEST" stride="1" length="8" usage="rp_blit"> 3772 <reg32 offset="0x0" name="REG"> 3773 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3774 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3775 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3776 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3777 </reg32> 3778 </array> 3779 3780 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3781 <reg32 offset="0xa85b" name="SP_DS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 3782 <reg64 offset="0xa85c" name="SP_DS_BASE" type="address" align="32" usage="rp_blit"/> 3783 <reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3784 <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 3785 <reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3786 <reg32 offset="0xa862" name="SP_DS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 3787 <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3788 <reg32 offset="0xa864" name="SP_DS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3789 <reg32 offset="0xa865" name="SP_DS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 3790 <reg32 offset="0xa866" name="SP_DS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 3791 <reg32 offset="0xa866" name="SP_DS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3792 <reg32 offset="0xa868" name="SP_DS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3793 3794 <reg32 offset="0xa870" name="SP_GS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 3795 <!-- There is no mergedregs bit, that comes from the VS. --> 3796 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3797 </reg32> 3798 <reg32 offset="0xa871" name="SP_GS_CNTL_1" low="0" high="7" type="uint" usage="rp_blit"> 3799 <doc> 3800 Normally the size of the output of the last stage in 3801 dwords. It should be programmed as follows: 3802 3803 size less than 63 - size 3804 size of 63 (?) or 64 - 63 3805 size greater than 64 - 64 3806 3807 What to program when the size is 61-63 is a guess, but 3808 both the blob and ir3 align the size to 4 dword's so it 3809 doesn't matter in practice. 3810 </doc> 3811 </reg32> 3812 <reg32 offset="0xa872" name="SP_GS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/> 3813 3814 <!-- TODO: exact same layout as 0xa802-0xa81a --> 3815 <reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"> 3816 <!-- FLAGS_REGID only for GS --> 3817 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> 3818 </reg32> 3819 <array offset="0xa874" name="SP_GS_OUTPUT" stride="1" length="16" usage="rp_blit"> 3820 <reg32 offset="0x0" name="REG"> 3821 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3822 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3823 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3824 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3825 </reg32> 3826 </array> 3827 3828 <array offset="0xa884" name="SP_GS_VPC_DEST" stride="1" length="8" usage="rp_blit"> 3829 <reg32 offset="0x0" name="REG"> 3830 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3831 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3832 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3833 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3834 </reg32> 3835 </array> 3836 3837 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3838 <reg32 offset="0xa88c" name="SP_GS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 3839 <reg64 offset="0xa88d" name="SP_GS_BASE" type="address" align="32" usage="rp_blit"/> 3840 <reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3841 <reg64 offset="0xa890" name="SP_GS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 3842 <reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3843 <reg32 offset="0xa893" name="SP_GS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 3844 <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3845 <reg32 offset="0xa895" name="SP_GS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3846 <reg32 offset="0xa896" name="SP_GS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 3847 <reg32 offset="0xa897" name="SP_GS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 3848 <reg32 offset="0xa897" name="SP_GS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 3849 <reg32 offset="0xa899" name="SP_GS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 3850 3851 <reg64 offset="0xa8a0" name="SP_VS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 3852 <reg64 offset="0xa8a2" name="SP_HS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 3853 <reg64 offset="0xa8a4" name="SP_DS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 3854 <reg64 offset="0xa8a6" name="SP_GS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 3855 <reg64 offset="0xa8a8" name="SP_VS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 3856 <reg64 offset="0xa8aa" name="SP_HS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 3857 <reg64 offset="0xa8ac" name="SP_DS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 3858 <reg64 offset="0xa8ae" name="SP_GS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 3859 3860 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 --> 3861 3862 <reg32 offset="0xa980" name="SP_PS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 3863 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 3864 <bitfield name="UNK21" pos="21" type="boolean"/> 3865 <bitfield name="VARYING" pos="22" type="boolean"/> 3866 <bitfield name="LODPIXMASK" pos="23" type="boolean"> 3867 <doc> 3868 Enable ALL helper invocations in a quad. Necessary for 3869 fine derivatives and quad subgroup ops. 3870 </doc> 3871 </bitfield> 3872 <bitfield name="INOUTREGOVERLAP" pos="24" type="boolean"/> 3873 <bitfield name="UNK25" pos="25" type="boolean"/> 3874 <bitfield name="PIXLODENABLE" pos="26" type="boolean"> 3875 <doc> 3876 Enable helper invocations. Enables 3 out of 4 fragments, 3877 because the coarse derivatives only use half of the quad 3878 and so one pixel's value is always unused. 3879 </doc> 3880 </bitfield> 3881 <bitfield name="UNK27" pos="27" type="boolean"/> 3882 <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/> 3883 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 3884 </reg32> 3885 <reg32 offset="0xa981" name="SP_PS_BOOLEAN_CF_MASK" type="hex"/> 3886 <reg32 offset="0xa982" name="SP_PS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 3887 <reg64 offset="0xa983" name="SP_PS_BASE" type="address" align="32" usage="rp_blit"/> 3888 <reg32 offset="0xa985" name="SP_PS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3889 <reg64 offset="0xa986" name="SP_PS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 3890 <reg32 offset="0xa988" name="SP_PS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3891 3892 <bitset name="a6xx_sp_blend_cntl" inline="yes"> 3893 <!-- per-mrt enable bit --> 3894 <bitfield name="ENABLE_BLEND" low="0" high="7"/> 3895 <bitfield name="INDEPENDENT_BLEND_EN" pos="8" type="boolean"/> 3896 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 3897 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 3898 </bitset> 3899 3900 <reg32 offset="0xa989" name="SP_BLEND_CNTL" type="a6xx_sp_blend_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3901 <reg32 offset="0xa989" name="SP_BLEND_CNTL" type="a6xx_sp_blend_cntl" variants="A8XX-" usage="rp_blit"> 3902 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean" variants="A8XX-"/> 3903 </reg32> 3904 3905 <reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit"> 3906 <!-- Same as RB_SRGB_CNTL --> 3907 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 3908 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 3909 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 3910 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 3911 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 3912 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 3913 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 3914 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 3915 </reg32> 3916 <reg32 offset="0xa98b" name="SP_PS_OUTPUT_MASK" usage="rp_blit"> 3917 <bitfield name="RT0" low="0" high="3"/> 3918 <bitfield name="RT1" low="4" high="7"/> 3919 <bitfield name="RT2" low="8" high="11"/> 3920 <bitfield name="RT3" low="12" high="15"/> 3921 <bitfield name="RT4" low="16" high="19"/> 3922 <bitfield name="RT5" low="20" high="23"/> 3923 <bitfield name="RT6" low="24" high="27"/> 3924 <bitfield name="RT7" low="28" high="31"/> 3925 </reg32> 3926 <reg32 offset="0xa98c" name="SP_PS_OUTPUT_CNTL" usage="rp_blit"> 3927 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 3928 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> 3929 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/> 3930 <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/> 3931 </reg32> 3932 <reg32 offset="0xa98d" name="SP_PS_MRT_CNTL" usage="rp_blit"> 3933 <bitfield name="MRT" low="0" high="3" type="uint"/> 3934 </reg32> 3935 3936 <array offset="0xa98e" name="SP_PS_OUTPUT" stride="1" length="8" usage="rp_blit"> 3937 <doc>per MRT</doc> 3938 <reg32 offset="0x0" name="REG"> 3939 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> 3940 <bitfield name="HALF_PRECISION" pos="8" type="boolean"/> 3941 </reg32> 3942 </array> 3943 3944 <array offset="0xa996" name="SP_PS_MRT" stride="1" length="8" usage="rp_blit"> 3945 <reg32 offset="0" name="REG"> 3946 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 3947 <bitfield name="COLOR_SINT" pos="8" type="boolean"/> 3948 <bitfield name="COLOR_UINT" pos="9" type="boolean"/> 3949 <bitfield name="UNK10" pos="10" type="boolean"/> 3950 </reg32> 3951 </array> 3952 3953 <reg32 offset="0xa99e" name="SP_PS_INITIAL_TEX_LOAD_CNTL" usage="rp_blit"> 3954 <bitfield name="COUNT" low="0" high="2" type="uint"/> 3955 <bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/> 3956 <doc> 3957 Similar to "(eq)" flag but disables helper invocations 3958 after the texture prefetch. 3959 </doc> 3960 <bitfield name="ENDOFQUAD" pos="4" type="boolean" /> 3961 <doc> 3962 Bypass writing to regs and overwrite output with color from 3963 CONSTSLOTID const regs. 3964 </doc> 3965 <bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/> 3966 <bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/> 3967 <!-- Blob never uses it --> 3968 <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/> 3969 </reg32> 3970 <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A6XX" usage="rp_blit"> 3971 <reg32 offset="0" name="CMD" variants="A6XX"> 3972 <bitfield name="SRC" low="0" high="6" type="uint"/> 3973 <bitfield name="SAMP_ID" low="7" high="10" type="uint"/> 3974 <bitfield name="TEX_ID" low="11" high="15" type="uint"/> 3975 <bitfield name="DST" low="16" high="21" type="a3xx_regid"/> 3976 <bitfield name="WRMASK" low="22" high="25" type="hex"/> 3977 <bitfield name="HALF" pos="26" type="boolean"/> 3978 <doc>Results in color being zero</doc> 3979 <bitfield name="UNK27" pos="27" type="boolean"/> 3980 <bitfield name="BINDLESS" pos="28" type="boolean"/> 3981 <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/> 3982 </reg32> 3983 </array> 3984 <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A7XX-" usage="rp_blit"> 3985 <reg32 offset="0" name="CMD" variants="A7XX-"> 3986 <bitfield name="SRC" low="0" high="6" type="uint"/> 3987 <bitfield name="SAMP_ID" low="7" high="9" type="uint"/> 3988 <bitfield name="TEX_ID" low="10" high="12" type="uint"/> 3989 <bitfield name="DST" low="13" high="18" type="a3xx_regid"/> 3990 <bitfield name="WRMASK" low="19" high="22" type="hex"/> 3991 <bitfield name="HALF" pos="23" type="boolean"/> 3992 <bitfield name="BINDLESS" pos="25" type="boolean"/> 3993 <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/> 3994 </reg32> 3995 </array> 3996 <array offset="0xa9a3" name="SP_PS_INITIAL_TEX_INDEX" stride="1" length="4" usage="rp_blit"> 3997 <reg32 offset="0" name="CMD"> 3998 <bitfield name="SAMP_ID" low="0" high="15" type="uint"/> 3999 <bitfield name="TEX_ID" low="16" high="31" type="uint"/> 4000 </reg32> 4001 </array> 4002 <reg32 offset="0xa9a7" name="SP_PS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 4003 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? --> 4004 <reg32 offset="0xa9a9" name="SP_PS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 4005 <reg32 offset="0xa9ab" name="SP_PS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 4006 <reg32 offset="0xa9ab" name="SP_PS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 4007 4008 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS --> 4009 4010 <reg32 offset="0xa9b0" name="SP_CS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="cmd"> 4011 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 4012 <!-- seems to make SP use less concurrent threads when possible? --> 4013 <bitfield name="UNK21" pos="21" type="boolean"/> 4014 <!-- has a small impact on performance, not clear what it does --> 4015 <bitfield name="UNK22" pos="22" type="boolean"/> 4016 <bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/> 4017 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 4018 </reg32> 4019 4020 <enum name="a6xx_const_ram_mode"> 4021 <value value="0x0" name="CONSTLEN_128"/> 4022 <value value="0x1" name="CONSTLEN_192"/> 4023 <value value="0x2" name="CONSTLEN_256"/> 4024 <value value="0x3" name="CONSTLEN_512"/> <!-- a7xx only --> 4025 </enum> 4026 4027 <!-- set for compute shaders --> 4028 <reg32 offset="0xa9b1" name="SP_CS_CNTL_1" usage="cmd"> 4029 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"> 4030 <doc> 4031 If 0 - all 32k of shared storage is enabled, otherwise 4032 (SHARED_SIZE + 1) * 1k is enabled. 4033 The ldl/stl offset seems to be rewritten to 0 when it is beyond 4034 this limit. This is different from ldlw/stlw, which wraps at 4035 64k (and has 36k of storage on A640 - reads between 36k-64k 4036 always return 0) 4037 </doc> 4038 </bitfield> 4039 <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"> 4040 <doc> 4041 This defines the split between consts and local 4042 memory in the Local Buffer. The programmed value 4043 must be at least the actual CONSTLEN. 4044 </doc> 4045 </bitfield> 4046 <bitfield name="ALT_LM_ENCODE" pos="26" type="boolean"/> 4047 </reg32> 4048 <reg32 offset="0xa9b2" name="SP_CS_BOOLEAN_CF_MASK" type="hex" usage="cmd"/> 4049 <reg32 offset="0xa9b3" name="SP_CS_PROGRAM_COUNTER_OFFSET" type="uint" usage="cmd"/> 4050 <reg64 offset="0xa9b4" name="SP_CS_BASE" type="address" align="32" usage="cmd"/> 4051 <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/> 4052 <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_BASE" type="waddress" align="32" usage="cmd"/> 4053 <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/> 4054 <reg32 offset="0xa9ba" name="SP_CS_TSIZE" low="0" high="7" type="uint" usage="cmd"/> 4055 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/> 4056 <reg32 offset="0xa9bc" name="SP_CS_INSTR_SIZE" low="0" high="27" type="uint" usage="cmd"/> 4057 <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="cmd"/> 4058 <reg32 offset="0xa9be" name="SP_CS_HYSTERESIS" type="a6xx_sp_xs_hysteresis" variants="A6XX-A7XX"/> 4059 <reg32 offset="0xa9be" name="SP_CS_HYSTERESIS" type="a8xx_sp_xs_hysteresis" variants="A8XX-"/> 4060 <reg32 offset="0xa9c5" name="SP_CS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 4061 4062 <!-- new in a6xx gen4, matches SP_CS_CONST_CONFIG_0 --> 4063 <reg32 offset="0xa9c2" name="SP_CS_WIE_CNTL_0" usage="cmd"> 4064 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 4065 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 4066 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 4067 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 4068 </reg32> 4069 <!-- new in a6xx gen4, matches SP_CS_WGE_CNTL --> 4070 <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A6XX" usage="cmd"> 4071 <!-- gl_LocalInvocationIndex --> 4072 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4073 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 4074 one of those 6 "SP cores" --> 4075 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 4076 <!-- Must match SP_CS_CTRL --> 4077 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 4078 <!-- 1 thread per wave (ignored if bit9 set) --> 4079 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 4080 </reg32> 4081 4082 <enum name="a7xx_workitem_rast_order"> 4083 <value value="0x0" name="WORKITEMRASTORDER_LINEAR"/> 4084 <doc> 4085 This is a fixed tiling, with 4x4 invocation outer tiles 4086 containing 2x2 invocation inner tiles. The intent is to 4087 improve cache locality with textures and images accessed 4088 using gl_LocalInvocationID. 4089 </doc> 4090 <value value="0x1" name="WORKITEMRASTORDER_TILED"/> 4091 </enum> 4092 4093 <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A7XX-" usage="cmd"> 4094 <!-- gl_LocalInvocationIndex --> 4095 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4096 <!-- Must match SP_CS_CTRL --> 4097 <bitfield name="THREADSIZE" pos="8" type="a6xx_threadsize"/> 4098 <!-- 1 thread per wave (would hang if THREAD128 is also set) --> 4099 <bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/> 4100 4101 <doc>How invocations/fibers within a workgroup are tiled.</doc> 4102 <bitfield name="WORKITEMRASTORDER" pos="15" type="a7xx_workitem_rast_order"/> 4103 </reg32> 4104 4105 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 --> 4106 4107 <reg64 offset="0xa9e0" name="SP_PS_SAMPLER_BASE" type="address" align="16" usage="rp_blit"/> 4108 <reg64 offset="0xa9e2" name="SP_CS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 4109 <reg64 offset="0xa9e4" name="SP_PS_TEXMEMOBJ_BASE" type="address" align="64" usage="rp_blit"/> 4110 <reg64 offset="0xa9e6" name="SP_CS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 4111 4112 <enum name="a6xx_bindless_descriptor_size"> 4113 <doc> 4114 This can alternatively be interpreted as a pitch shift, ie, the 4115 descriptor size is 2 << N dwords 4116 </doc> 4117 <value value="1" name="BINDLESS_DESCRIPTOR_16B"/> 4118 <value value="3" name="BINDLESS_DESCRIPTOR_64B"/> 4119 </enum> 4120 4121 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd"> 4122 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> 4123 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4124 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4125 </reg64> 4126 </array> 4127 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cmd"> 4128 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> 4129 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4130 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4131 </reg64> 4132 </array> 4133 4134 <!-- 4135 UAV state for compute shader: 4136 --> 4137 <reg64 offset="0xa9f2" name="SP_CS_UAV_BASE" type="address" align="16" variants="A6XX"/> 4138 <reg64 offset="0xa9f8" name="SP_CS_UAV_BASE" type="address" align="16" variants="A7XX-"/> 4139 <reg32 offset="0xaa00" name="SP_CS_USIZE" low="0" high="6" type="uint"/> 4140 4141 <!-- Correlated with avgs/uvgs usage in FS --> 4142 <reg32 offset="0xaa01" name="SP_PS_VGS_CNTL" type="uint" variants="A7XX-" usage="cmd"/> 4143 4144 <reg32 offset="0xaa02" name="SP_PS_OUTPUT_CONST_CNTL" variants="A7XX-" usage="cmd"> 4145 <bitfield name="ENABLED" pos="0" type="boolean"/> 4146 </reg32> 4147 <reg32 offset="0xaa03" name="SP_PS_OUTPUT_CONST_MASK" variants="A7XX-" usage="cmd"> 4148 <doc> 4149 Specify for which components the output color should be read 4150 from alias, e.g. for: 4151 4152 alias.1.b32.0 r3.x, c8.x 4153 alias.1.b32.0 r2.x, c4.x 4154 alias.1.b32.0 r1.x, c4.x 4155 alias.1.b32.0 r0.x, c0.x 4156 4157 the SP_PS_OUTPUT_CONST_MASK would be 0x00001111 4158 </doc> 4159 4160 <bitfield name="RT0" low="0" high="3"/> 4161 <bitfield name="RT1" low="4" high="7"/> 4162 <bitfield name="RT2" low="8" high="11"/> 4163 <bitfield name="RT3" low="12" high="15"/> 4164 <bitfield name="RT4" low="16" high="19"/> 4165 <bitfield name="RT5" low="20" high="23"/> 4166 <bitfield name="RT6" low="24" high="27"/> 4167 <bitfield name="RT7" low="28" high="31"/> 4168 </reg32> 4169 4170 <array offset="0xaa04" name="SP_MRT_BLEND_CNTL" stride="1" length="8" variants="A8XX-"> 4171 <reg32 offset="0" name="REG"> 4172 <bitfield name="COLOR_BLEND_EN" pos="0" type="boolean"/> 4173 <bitfield name="ALPHA_BLEND_EN" pos="1" type="boolean"/> 4174 <bitfield name="COMPONENT_WRITE_MASK" low="7" high="10"/> 4175 </reg32> 4176 </array> 4177 4178 <reg32 offset="0xaa0c" name="SP_ALPHA_TEST_CNTL" variants="A8XX-"> 4179 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> 4180 </reg32> 4181 4182 <reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/> 4183 4184 <!-- 4185 This enum is probably similar in purpose to SNORMMODE on a3xx, 4186 minus the snorm stuff, i.e. it controls what happens with an 4187 out-of-bounds isam/isamm. GL and Vulkan robustness require us to 4188 return 0 on out-of-bound textureFetch(). 4189 --> 4190 <enum name="a6xx_isam_mode"> 4191 <value value="0x1" name="ISAMMODE_CL"/> 4192 <value value="0x2" name="ISAMMODE_GL"/> 4193 </enum> 4194 4195 <reg32 offset="0xab00" name="SP_MODE_CNTL" usage="rp_blit"> 4196 <!-- 4197 When set, half register loads from the constant file will 4198 load a 32-bit value (so hc0.y loads the same value as c0.y) 4199 and implicitly convert it to 16b (f2f16, or u2u16, based on 4200 operand type). When unset, half register loads from the 4201 constant file will load 16 bits from the packed constant 4202 file (so hc0.y loads the top 16 bits of the value of c0.x) 4203 --> 4204 <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/> 4205 <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/> 4206 <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see SP_SHARED_CONSTANT --> 4207 </reg32> 4208 4209 <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/> 4210 <reg32 offset="0xab02" name="SP_HLSQ_MODE_CNTL" variants="A7XX-" usage="cmd"> 4211 <bitfield name="SHARED_CONSTS_ENABLE" pos="0" type="boolean"/> <!-- see SP_SHARED_CONSTANT --> 4212 </reg32> 4213 4214 <reg32 offset="0xab04" name="SP_PS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 4215 <reg32 offset="0xab05" name="SP_PS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 4216 4217 <reg32 offset="0xab06" name="SP_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/> 4218 4219 <array offset="0xab10" name="SP_GFX_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> 4220 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> 4221 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4222 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4223 </reg64> 4224 </array> 4225 <array offset="0xab0a" name="SP_GFX_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit"> 4226 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> 4227 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4228 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4229 </reg64> 4230 </array> 4231 4232 <!-- 4233 Combined UAV state for 3d pipe, used for Image and SSBO write/atomic 4234 instructions VS/HS/DS/GS/FS. See SP_CS_UAV_BASE_* for compute shaders. 4235 --> 4236 <reg64 offset="0xab1a" name="SP_GFX_UAV_BASE" type="address" align="16" usage="cmd"/> 4237 <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A6XX-A7XX" usage="cmd"/> 4238 <reg32 offset="0xab09" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A8XX-" usage="cmd"/> 4239 4240 <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX" usage="cmd"/> 4241 4242 <reg32 offset="0xab23" name="SP_UNKNOWN_AB23" variants="A8XX-"/> 4243 4244 <enum name="a6xx_sp_a2d_output_ifmt_type"> 4245 <value name="OUTPUT_IFMT_2D_FLOAT" value="0"/> 4246 <value name="OUTPUT_IFMT_2D_SINT" value="1"/> 4247 <value name="OUTPUT_IFMT_2D_UINT" value="2"/> 4248 </enum> 4249 4250 <bitset name="a6xx_sp_a2d_output_info" inline="yes"> 4251 <bitfield name="HALF_PRECISION" pos="0" type="boolean"/> 4252 <bitfield name="IFMT_TYPE" low="1" high="2" type="a6xx_sp_a2d_output_ifmt_type"/> 4253 <!-- looks like HW only cares about the base type of this format, 4254 which matches the ifmt? --> 4255 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/> 4256 <!-- set when ifmt is R2D_UNORM8_SRGB --> 4257 <bitfield name="SRGB" pos="11" type="boolean"/> 4258 <!-- some sort of channel mask, not sure what it is for --> 4259 <bitfield name="MASK" low="12" high="15"/> 4260 </bitset> 4261 4262 <reg32 offset="0xacc0" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A6XX" usage="rp_blit"/> 4263 <reg32 offset="0xa9bf" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A7XX-" usage="rp_blit"/> 4264 4265 <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="init"/> 4266 <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" variants="A6XX"/> 4267 <reg32 offset="0xae01" name="SP_SHADER_PROFILING" variants="A8XX-"/> 4268 <reg32 offset="0xae02" name="SP_NC_MODE_CNTL"> 4269 <!-- TODO: valid bits 0x3c3f, see kernel --> 4270 </reg32> 4271 <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="init"/> 4272 <reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="init"> 4273 <bitfield name="F16_NO_INF" pos="3" type="boolean"/> 4274 </reg32> 4275 4276 <reg32 offset="0xae05" name="SP_SS_CHICKEN_BITS_0" variants="A8XX-"/> 4277 <reg32 offset="0xae06" name="SP_ISDB_CNTL" variants="A7XX-" usage="init"/> 4278 <reg32 offset="0xae07" name="SP_PERFCTR_CNTL"/> 4279 <reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="init"/> 4280 <reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="init"/> 4281 <reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="init"/> 4282 <reg32 offset="0xae0b" name="SP_CHICKEN_BITS_4" variants="A8XX-"/> 4283 <reg32 offset="0xae0c" name="SP_STATUS"/> 4284 4285 <reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="init"> 4286 <!-- some perfcntrs are affected by a per-stage enable bit 4287 (PERF_SP_ALU_WORKING_CYCLES for example) 4288 TODO: verify position of HS/DS/GS bits --> 4289 <bitfield name="VS" pos="0" type="boolean"/> 4290 <bitfield name="HS" pos="1" type="boolean"/> 4291 <bitfield name="DS" pos="2" type="boolean"/> 4292 <bitfield name="GS" pos="3" type="boolean"/> 4293 <bitfield name="FS" pos="4" type="boolean"/> 4294 <bitfield name="CS" pos="5" type="boolean"/> 4295 </reg32> 4296 <array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24" variants="A6XX"/> 4297 <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/> 4298 <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="init"/> 4299 <reg32 offset="0xae6b" name="SP_HLSQ_TIMEOUT_THRESHOLD_DP" variants="A7XX-" usage="init"/> 4300 <reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="init"/> 4301 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-"> 4302 <bitfield name="CONTEXT" low="26" high="30"/> 4303 <bitfield name="SLICE" low="21" high="25"/> 4304 <bitfield name="LOCATION" low="18" high="20" type="a7xx_state_location"/> 4305 <bitfield name="PIPE" low="16" high="17" type="adreno_pipe"/> 4306 <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/> 4307 <bitfield name="USPTP" low="4" high="7"/> 4308 <bitfield name="SPTP" low="0" high="3"/> 4309 </reg32> 4310 <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/> 4311 <reg32 offset="0xae73" name="SP_HLSQ_DBG_ECO_CNTL_1" variants="A7XX-"/> 4312 <reg32 offset="0xae74" name="SP_HLSQ_DBG_ECO_CNTL_2" variants="A7XX-"/> 4313 <reg32 offset="0xae76" name="SP_HLSQ_DBG_ECO_CNTL_3" variants="A8XX-"/> 4314 <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/> 4315 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) --> 4316 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range --> 4317 <reg32 offset="0xae52" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 4318 4319 <reg64 offset="0xae10" name="SP_HLSQ_GC_GMEM_RANGE_MIN" variants="A8XX-"/> 4320 <reg64 offset="0xae12" name="SP_HLSQ_LPAC_GMEM_RANGE_MIN" variants="A8XX-"/> 4321 <reg32 offset="0xae15" name="SP_LPAC_CPI_STATUS" variants="A8XX-"/> 4322 <reg32 offset="0xae16" name="SP_LPAC_DBG_STATUS" variants="A8XX-"/> 4323 <reg32 offset="0xae17" name="SP_LPAC_ISDB_BATCH_COUNT" variants="A8XX-"/> 4324 <reg32 offset="0xae18" name="SP_LPAC_ISDB_BATCH_COUNT_INCR_EN" variants="A8XX-"/> 4325 <reg32 offset="0xae19" name="SP_LPAC_ISDB_BATCH_COUNT_SHADERS" variants="A8XX-"/> 4326 <reg32 offset="0xae30" name="SP_ISDB_BATCH_COUNT" variants="A7XX-"/> 4327 <reg32 offset="0xae31" name="SP_ISDB_BATCH_COUNT_INCR_EN" variants="A7XX-"/> 4328 <reg32 offset="0xae32" name="SP_ISDB_BATCH_COUNT_SHADERS" variants="A7XX-"/> 4329 <reg32 offset="0xae35" name="SP_ISDB_DEBUG_CONFIG" variants="A7XX-"/> 4330 4331 <reg32 offset="0xae3a" name="SP_SELF_THROTTLE_CONTROL" variants="A7XX-"/> 4332 <reg32 offset="0xae3b" name="SP_DISPATCH_CNTL" variants="A7XX-"/> 4333 <reg64 offset="0xae3c" name="SP_SW_DEBUG_ADDR" variants="A7XX-"/> 4334 <reg64 offset="0xae3e" name="SP_ISDB_DEBUG_ADDR" variants="A7XX-"/> 4335 4336 <array offset="0xaec0" name="SP_PERFCTR_HLSQ_SEL_2_0" stride="1" length="6" variants="A7XX-"/> 4337 4338 <!-- 4339 The downstream kernel calls the debug cluster of registers 4340 "a6xx_sp_ps_tp_cluster" but this actually specifies the border 4341 color base for compute shaders. 4342 --> 4343 <reg64 offset="0xb180" name="TPL1_CS_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 4344 <reg32 offset="0xb182" name="TPL1_PS_ROTATION_CNTL" low="0" high="2" usage="cmd"/> 4345 <reg32 offset="0xb183" name="TPL1_PS_SWIZZLE_CNTL" low="0" high="23" usage="cmd"/> 4346 4347 <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/> 4348 <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/> 4349 4350 <reg32 offset="0xb2d6" name="TPL1_A2D_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/> 4351 <reg32 offset="0xb2d7" name="TPL1_A2D_FILTER_CNTL" variants="A8XX-" usage="rp_blit"/> 4352 4353 <reg32 offset="0xb300" name="TPL1_RAS_MSAA_CNTL" usage="rp_blit"> 4354 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 4355 <bitfield name="UNK2" low="2" high="3"/> 4356 </reg32> 4357 <reg32 offset="0xb301" name="TPL1_DEST_MSAA_CNTL" usage="rp_blit"> 4358 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 4359 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 4360 </reg32> 4361 4362 <!-- looks to work in the same way as a5xx: --> 4363 <reg64 offset="0xb302" name="TPL1_GFX_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 4364 <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 4365 <reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A6XX-A7XX" /> 4366 <reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit" variants="A6XX-A7XX" /> 4367 <reg32 offset="0xb307" name="TPL1_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 4368 4369 <reg32 offset="0xb304" name="TPL1_BIN_SIZE" type="a8xx_bin_size" variants="A8XX-" usage="rp_blit"/> 4370 4371 <enum name="a6xx_coord_round"> 4372 <value value="0" name="COORD_TRUNCATE"/> 4373 <value value="1" name="COORD_ROUND_NEAREST_EVEN"/> 4374 </enum> 4375 4376 <enum name="a6xx_nearest_mode"> 4377 <value value="0" name="ROUND_CLAMP_TRUNCATE"/> 4378 <value value="1" name="CLAMP_ROUND_TRUNCATE"/> 4379 <value value="2" name="ROUND_FLOAT_TO_INT"/> <!-- only ARRAYCOORDROUNDMODE --> 4380 </enum> 4381 4382 <reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd"> 4383 <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/> 4384 <bitfield name="TEXCOORDROUNDMODE" pos="2" type="a6xx_coord_round"/> 4385 <bitfield name="ARRAYCOORDROUNDMODE" low="3" high="4" type="a6xx_coord_round"/> 4386 <bitfield name="NEARESTMIPSNAP" pos="5" type="a6xx_nearest_mode"/> 4387 <bitfield name="SAMPLEREPLICATE" pos="6" type="boolean"/> 4388 <bitfield name="DESTDATATYPEOVERRIDE" pos="7" type="boolean"/> 4389 <bitfield name="PACK_SAMP_REDUCED_PRECISION" pos="8" type="boolean"/> 4390 </reg32> 4391 <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/> 4392 4393 <!-- 4394 Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either 4395 badly named or the functionality moved in a6xx. But downstream kernel 4396 calls this "a6xx_sp_ps_tp_2d_cluster" 4397 --> 4398 <reg32 offset="0xb4c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A6XX" usage="rp_blit"/> 4399 <reg32 offset="0xb4c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A6XX" usage="rp_blit"> 4400 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 4401 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 4402 </reg32> 4403 <reg64 offset="0xb4c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A6XX" usage="rp_blit"/> 4404 <reg32 offset="0xb4c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A6XX" usage="rp_blit"> 4405 <bitfield name="UNK0" low="0" high="8"/> 4406 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> 4407 </reg32> 4408 4409 <reg32 offset="0xb2c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A7XX-" usage="rp_blit"/> 4410 <reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX-"> 4411 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 4412 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 4413 </reg32> 4414 <reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 4415 <reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX-"> 4416 <!-- 4417 Bits from 3..9 must be zero unless 'TPL1_A2D_BLT_CNTL::TYPE' 4418 is A6XX_TEX_IMG_BUFFER, which allows for lower alignment. 4419 --> 4420 <bitfield name="PITCH" low="3" high="23" type="uint"/> 4421 </reg32> 4422 4423 <!-- planes for NV12, etc. (TODO: not tested) --> 4424 <reg64 offset="0xb4c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A6XX"/> 4425 <reg32 offset="0xb4c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A6XX"/> 4426 <reg64 offset="0xb4c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A6XX"/> 4427 4428 <reg64 offset="0xb2c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A7XX-"/> 4429 <reg32 offset="0xb2c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A7XX-"/> 4430 <reg64 offset="0xb2c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A7XX-"/> 4431 4432 <reg64 offset="0xb4ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A6XX" usage="rp_blit"/> 4433 <reg32 offset="0xb4cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/> 4434 4435 <reg64 offset="0xb2ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 4436 <reg32 offset="0xb2cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/> 4437 4438 <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/> 4439 <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/> 4440 <reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/> 4441 <reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/> 4442 <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="rp_blit"/> 4443 4444 <reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/> 4445 <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/> 4446 <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/> 4447 <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/> 4448 <reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-"/> 4449 <reg32 offset="0xb2d2" name="TPL1_A2D_BLT_CNTL" variants="A7XX-" usage="rp_blit"> 4450 <bitfield name="RAW_COPY" pos="0" type="boolean"/> 4451 <bitfield name="START_OFFSET_TEXELS" low="16" high="21"/> 4452 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 4453 </reg32> 4454 <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX" usage="rp_blit"/> 4455 <reg32 offset="0xab07" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A8XX-" usage="rp_blit"/> 4456 4457 <!-- always 0x100000 or 0x1000000? --> 4458 <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="init"/> 4459 <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 4460 <reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="init"> 4461 <!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set 4462 and if other blit is done without it - UBWC image may be copied incorrectly. 4463 --> 4464 <bitfield name="TP_UBWC_FLAG_HINT" pos="18" type="boolean"/> 4465 </reg32> 4466 <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL"> 4467 <bitfield name="MODE" pos="0" type="boolean"/> 4468 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 4469 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 4470 <bitfield name="UPPER_BIT" pos="4" type="uint"/> 4471 <bitfield name="UNK6" low="6" high="7"/> 4472 </reg32> 4473 <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="init"/> <!-- always 0x0 or 0x44 ? --> 4474 4475 <array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A6XX"> 4476 <reg32 offset="0" name="REG" low="0" high="29"/> 4477 </array> 4478 4479 <array offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="5" variants="A7XX"> 4480 <reg32 offset="0" name="REG" low="0" high="29" usage="cmd"/> 4481 </array> 4482 4483 <array offset="0xb606" name="TPL1_BICUBIC_WEIGHTS_TABLE" stride="1" length="25" variants="A8XX"> 4484 <reg32 offset="0" name="REG" low="0" high="29"/> 4485 </array> 4486 4487 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/> 4488 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/> 4489 <array offset="0xb620" name="TPL1_PERFCTR_TP_SEL" stride="1" length="20" variants="A8XX"/> 4490 4491 <!-- TODO: 4 more perfcntr sel at 0xb620 ? --> 4492 4493 <bitset name="a6xx_xs_const_config" inline="yes"> 4494 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/> 4495 <bitfield name="ENABLED" pos="8" type="boolean"/> 4496 <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/> 4497 </bitset> 4498 4499 <reg32 offset="0xb800" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 4500 <reg32 offset="0xb801" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 4501 <reg32 offset="0xb802" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 4502 <reg32 offset="0xb803" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 4503 4504 <reg32 offset="0xa827" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 4505 <reg32 offset="0xa83f" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 4506 <reg32 offset="0xa867" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 4507 <reg32 offset="0xa898" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 4508 4509 <reg32 offset="0xa9aa" name="SP_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 4510 <bitfield name="FS_DISABLE" pos="0" type="boolean"/> 4511 </reg32> 4512 4513 <reg32 offset="0xa9ac" name="SP_DITHER_CNTL" variants="A7XX-" usage="cmd"> 4514 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> 4515 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> 4516 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> 4517 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> 4518 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> 4519 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> 4520 <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/> 4521 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> 4522 </reg32> 4523 4524 <reg32 offset="0xa9ad" name="SP_VRS_CONFIG" variants="A7XX-" usage="rp_blit"> 4525 <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 4526 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="1" type="boolean"/> 4527 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="3" type="boolean"/> 4528 </reg32> 4529 4530 <reg32 offset="0xa9ae" name="SP_PS_CNTL_1" variants="A7XX-" usage="rp_blit"> 4531 <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/> 4532 <bitfield name="DEFER_WAVE_ALLOC_DIS" pos="8" type="boolean"/> 4533 <bitfield name="EVICT_BUF_MODE" low="9" high="10"/> 4534 </reg32> 4535 4536 <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/> 4537 <reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/> 4538 <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/> 4539 4540 4541 <bitset name="a6xx_sp_ps_wave_cntl" inline="yes"> 4542 <!-- must match SP_FS_CTRL --> 4543 <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/> 4544 <bitfield name="VARYINGS" pos="1" type="boolean"/> 4545 <bitfield name="UNK2" low="2" high="11"/> 4546 </bitset> 4547 <bitset name="a6xx_sp_reg_prog_id_1" inline="yes"> 4548 <!-- register loaded with position (bary.f) --> 4549 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/> 4550 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/> 4551 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/> 4552 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/> 4553 </bitset> 4554 <bitset name="a6xx_sp_reg_prog_id_2" inline="yes"> 4555 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/> 4556 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/> 4557 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/> 4558 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> 4559 </bitset> 4560 <bitset name="a6xx_sp_reg_prog_id_3" inline="yes"> 4561 <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/> 4562 <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/> 4563 </bitset> 4564 4565 <reg32 offset="0xb980" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A6XX" usage="rp_blit"/> 4566 <reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob --> 4567 <reg32 offset="0xb982" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A6XX" usage="rp_blit"> 4568 <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the 4569 A3xx field, except that it's not necessary to set it to anything but the maximum, since 4570 the hardware will simply emit smaller waves when it runs out of space. --> 4571 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 4572 </reg32> 4573 <reg32 offset="0xb983" name="SP_REG_PROG_ID_0" variants="A6XX" usage="rp_blit"> 4574 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 4575 <!-- SAMPLEID is loaded into a half-precision register: --> 4576 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 4577 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 4578 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 4579 </reg32> 4580 <reg32 offset="0xb984" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A6XX" usage="rp_blit"/> 4581 <reg32 offset="0xb985" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A6XX" usage="rp_blit"/> 4582 <reg32 offset="0xb986" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A6XX" usage="rp_blit"/> 4583 <reg32 offset="0xb987" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="cmd"/> 4584 <reg32 offset="0xa9c6" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A7XX" usage="rp_blit"/> 4585 <reg32 offset="0xa9c6" name="SP_PS_WAVE_CNTL" variants="A8XX-" usage="rp_blit"> 4586 <bitfield name="VARYINGS" pos="1" type="boolean"/> 4587 </reg32> 4588 <reg32 offset="0xa9c7" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A7XX-" usage="rp_blit"> 4589 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 4590 </reg32> 4591 <reg32 offset="0xa9c8" name="SP_REG_PROG_ID_0" variants="A7XX-" usage="rp_blit"> 4592 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 4593 <!-- SAMPLEID is loaded into a half-precision register: --> 4594 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 4595 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 4596 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 4597 </reg32> 4598 <reg32 offset="0xa9c9" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A7XX-" usage="rp_blit"/> 4599 <reg32 offset="0xa9ca" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A7XX-" usage="rp_blit"/> 4600 <reg32 offset="0xa9cb" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A7XX-" usage="rp_blit"/> 4601 <reg32 offset="0xa9cd" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="cmd"/> 4602 4603 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 4604 <reg32 offset="0xb990" name="SP_CS_NDRANGE_0" variants="A6XX" usage="rp_blit"> 4605 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 4606 <!-- localsize is value minus one: --> 4607 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 4608 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 4609 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 4610 </reg32> 4611 <reg32 offset="0xb991" name="SP_CS_NDRANGE_1" variants="A6XX" usage="rp_blit"> 4612 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 4613 </reg32> 4614 <reg32 offset="0xb992" name="SP_CS_NDRANGE_2" variants="A6XX" usage="rp_blit"> 4615 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 4616 </reg32> 4617 <reg32 offset="0xb993" name="SP_CS_NDRANGE_3" variants="A6XX" usage="rp_blit"> 4618 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 4619 </reg32> 4620 <reg32 offset="0xb994" name="SP_CS_NDRANGE_4" variants="A6XX" usage="rp_blit"> 4621 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 4622 </reg32> 4623 <reg32 offset="0xb995" name="SP_CS_NDRANGE_5" variants="A6XX" usage="rp_blit"> 4624 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 4625 </reg32> 4626 <reg32 offset="0xb996" name="SP_CS_NDRANGE_6" variants="A6XX" usage="rp_blit"> 4627 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 4628 </reg32> 4629 <reg32 offset="0xb997" name="SP_CS_CONST_CONFIG_0" variants="A6XX" usage="rp_blit"> 4630 <!-- these are all vec3. first 3 need to be high regs 4631 WGSIZECONSTID is the local size (from SP_CS_NDRANGE_0) 4632 WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID 4633 --> 4634 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 4635 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 4636 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 4637 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 4638 </reg32> 4639 <reg32 offset="0xb998" name="SP_CS_WGE_CNTL" variants="A6XX" usage="rp_blit"> 4640 <!-- gl_LocalInvocationIndex --> 4641 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4642 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 4643 one of those 6 "SP cores" --> 4644 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 4645 <!-- Must match SP_CS_CTRL --> 4646 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 4647 <!-- 1 thread per wave (ignored if bit9 set) --> 4648 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 4649 </reg32> 4650 <!--note: vulkan blob doesn't use these --> 4651 <reg32 offset="0xb999" name="SP_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/> 4652 <reg32 offset="0xb99a" name="SP_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/> 4653 <reg32 offset="0xb99b" name="SP_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/> 4654 4655 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 4656 <reg32 offset="0xa9d4" name="SP_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit"> 4657 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 4658 <!-- localsize is value minus one: --> 4659 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 4660 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 4661 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 4662 </reg32> 4663 <reg32 offset="0xa9d5" name="SP_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit"> 4664 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 4665 </reg32> 4666 <reg32 offset="0xa9d6" name="SP_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit"> 4667 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 4668 </reg32> 4669 <reg32 offset="0xa9d7" name="SP_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit"> 4670 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 4671 </reg32> 4672 <reg32 offset="0xa9d8" name="SP_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit"> 4673 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 4674 </reg32> 4675 <reg32 offset="0xa9d9" name="SP_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit"> 4676 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 4677 </reg32> 4678 <reg32 offset="0xa9da" name="SP_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit"> 4679 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 4680 </reg32> 4681 <!--note: vulkan blob doesn't use these --> 4682 <reg32 offset="0xa9dc" name="SP_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/> 4683 <reg32 offset="0xa9dd" name="SP_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/> 4684 <reg32 offset="0xa9de" name="SP_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/> 4685 4686 <enum name="a7xx_cs_yalign"> 4687 <value name="CS_YALIGN_1" value="8"/> 4688 <value name="CS_YALIGN_2" value="4"/> 4689 <value name="CS_YALIGN_4" value="2"/> 4690 <value name="CS_YALIGN_8" value="1"/> 4691 </enum> 4692 4693 <reg32 offset="0xa9db" name="SP_CS_WGE_CNTL" variants="A7XX-" usage="rp_blit"> 4694 <!-- gl_LocalInvocationIndex --> 4695 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4696 <!-- Must match SP_CS_CTRL --> 4697 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 4698 <doc> 4699 When this bit is enabled, the dispatch order interleaves 4700 the z coordinate instead of launching all workgroups 4701 with z=0, then all with z=1 and so on. 4702 </doc> 4703 <bitfield name="WORKGROUPRASTORDERZFIRSTEN" pos="11" type="boolean"/> 4704 <doc> 4705 When both fields are non-0 then the dispatcher uses 4706 these tile sizes to launch workgroups in a tiled manner 4707 when the x and y workgroup counts are 4708 both more than 1. 4709 </doc> 4710 <bitfield name="WGTILEWIDTH" low="20" high="25"/> 4711 <bitfield name="WGTILEHEIGHT" low="26" high="31"/> 4712 </reg32> 4713 4714 <reg32 offset="0xa9df" name="SP_CS_NDRANGE_7" variants="A7XX-" usage="cmd"> 4715 <!-- The size of the last workgroup. localsize is value minus one: --> 4716 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 4717 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 4718 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 4719 </reg32> 4720 4721 <reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/> 4722 <reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/> 4723 <reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/> 4724 4725 <!-- mirror of SP_CS_BINDLESS_BASE --> 4726 <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> 4727 <reg64 offset="0" name="DESCRIPTOR"> 4728 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4729 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4730 </reg64> 4731 </array> 4732 4733 <!-- new in a6xx gen4, mirror of SP_CS_CNTL_1? --> 4734 <reg32 offset="0xb9d0" name="HLSQ_CS_CTRL_REG1" variants="A6XX" usage="cmd"> 4735 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/> 4736 <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"/> 4737 </reg32> 4738 4739 <reg32 offset="0xbb00" name="SP_DRAW_INITIATOR" variants="A6XX"> 4740 <bitfield name="STATE_ID" low="0" high="7"/> 4741 </reg32> 4742 4743 <reg32 offset="0xbb01" name="SP_KERNEL_INITIATOR" variants="A6XX"> 4744 <bitfield name="STATE_ID" low="0" high="7"/> 4745 </reg32> 4746 4747 <reg32 offset="0xbb02" name="SP_EVENT_INITIATOR" variants="A6XX"> 4748 <!-- I think only the low bit is actually used? --> 4749 <bitfield name="STATE_ID" low="16" high="23"/> 4750 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4751 </reg32> 4752 4753 <reg32 offset="0xbb08" name="SP_UPDATE_CNTL" variants="A6XX" usage="cmd"> 4754 <doc> 4755 This register clears pending loads queued up by 4756 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 4757 CP_LOAD_STATE6. 4758 </doc> 4759 4760 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 4761 <bitfield name="VS_STATE" pos="0" type="boolean"/> 4762 <bitfield name="HS_STATE" pos="1" type="boolean"/> 4763 <bitfield name="DS_STATE" pos="2" type="boolean"/> 4764 <bitfield name="GS_STATE" pos="3" type="boolean"/> 4765 <bitfield name="FS_STATE" pos="4" type="boolean"/> 4766 <bitfield name="CS_STATE" pos="5" type="boolean"/> 4767 4768 <bitfield name="CS_UAV" pos="6" type="boolean"/> 4769 <bitfield name="GFX_UAV" pos="7" type="boolean"/> 4770 4771 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 --> 4772 <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/> 4773 <bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/> 4774 4775 <!-- SS6_BINDLESS: one bit per bindless base --> 4776 <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/> 4777 <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/> 4778 </reg32> 4779 4780 <reg32 offset="0xab1c" name="SP_DRAW_INITIATOR" variants="A7XX-"> 4781 <bitfield name="STATE_ID" low="0" high="7"/> 4782 </reg32> 4783 4784 <reg32 offset="0xab1d" name="SP_KERNEL_INITIATOR" variants="A7XX-"> 4785 <bitfield name="STATE_ID" low="0" high="7"/> 4786 </reg32> 4787 4788 <reg32 offset="0xab1e" name="SP_EVENT_INITIATOR" variants="A7XX-"> 4789 <bitfield name="STATE_ID" low="16" high="23"/> 4790 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4791 </reg32> 4792 4793 <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A7XX" usage="cmd"> 4794 <doc> 4795 This register clears pending loads queued up by 4796 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 4797 CP_LOAD_STATE6. 4798 </doc> 4799 4800 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 4801 <bitfield name="VS_STATE" pos="0" type="boolean"/> 4802 <bitfield name="HS_STATE" pos="1" type="boolean"/> 4803 <bitfield name="DS_STATE" pos="2" type="boolean"/> 4804 <bitfield name="GS_STATE" pos="3" type="boolean"/> 4805 <bitfield name="FS_STATE" pos="4" type="boolean"/> 4806 <bitfield name="CS_STATE" pos="5" type="boolean"/> 4807 4808 <bitfield name="CS_UAV" pos="6" type="boolean"/> 4809 <bitfield name="GFX_UAV" pos="7" type="boolean"/> 4810 4811 <!-- SS6_BINDLESS: one bit per bindless base --> 4812 <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/> 4813 <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/> 4814 </reg32> 4815 4816 <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A8XX" usage="cmd"> 4817 <doc> 4818 This register clears pending loads queued up by 4819 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 4820 CP_LOAD_STATE6. 4821 </doc> 4822 4823 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 4824 <bitfield name="VS_STATE" pos="0" type="boolean"/> 4825 <bitfield name="HS_STATE" pos="1" type="boolean"/> 4826 <bitfield name="DS_STATE" pos="2" type="boolean"/> 4827 <bitfield name="GS_STATE" pos="3" type="boolean"/> 4828 <bitfield name="FS_STATE" pos="4" type="boolean"/> 4829 <bitfield name="CS_STATE" pos="5" type="boolean"/> 4830 </reg32> 4831 4832 <reg32 offset="0xa9c0" name="SP_CS_BINDLESS_INVALIDATE"/> 4833 <reg32 offset="0xab08" name="SP_GFX_BINDLESS_INVALIDATE"/> 4834 4835 <reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 4836 <reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 4837 4838 <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX" stride="1" length="64" variants="A7XX"/> 4839 <array offset="0xab30" name="SP_SHARED_CONSTANT_GFX" stride="1" length="128" variants="A8XX-"/> 4840 4841 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd"> 4842 <doc> 4843 Shared constants are intended to be used for Vulkan push 4844 constants. When enabled, 8 vec4's are reserved in the FS 4845 const pool and 16 in the geometry const pool although 4846 only 8 are actually used (why?) and they are mapped to 4847 c504-c511 in each stage. Both VS and FS shared consts 4848 are written using ST6_CONSTANTS/SB6_UAV, so that both 4849 the geometry and FS shared consts can be written at once 4850 by using CP_LOAD_STATE6 rather than 4851 CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition 4852 DST_OFF and NUM_UNIT are in units of dwords instead of 4853 vec4's. 4854 4855 There is also a separate shared constant pool for CS, 4856 which is loaded through CP_LOAD_STATE6_FRAG with 4857 ST6_UBO/ST6_UAV. However the only real difference for CS 4858 is the dword units. 4859 </doc> 4860 <bitfield name="ENABLE" pos="0" type="boolean"/> 4861 </reg32> 4862 4863 <!-- mirror of SP_GFX_BINDLESS_BASE --> 4864 <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd"> 4865 <reg64 offset="0" name="DESCRIPTOR"> 4866 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4867 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4868 </reg64> 4869 </array> 4870 4871 <reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD"> 4872 <bitfield name="STATE_ID" low="8" high="15"/> 4873 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4874 </reg32> 4875 4876 <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="init"/> <!-- all bits valid except bit 29 --> 4877 <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="init"/> 4878 <reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="init"/> 4879 <reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode" variants="A6XX"/> 4880 <reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/> 4881 <array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/> 4882 4883 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 --> 4884 <reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE" variants="A6XX"/> 4885 4886 <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/> 4887 4888 <!-- Don't know if these are SP, always 0 --> 4889 <reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/> 4890 <reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/> 4891 <reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/> 4892 4893 <!-- 4894 These special registers signal the beginning/end of an event 4895 sequence. The sequence used internally for an event looks like: 4896 - write EVENT_CMD pipe register 4897 - write CP_EVENT_START 4898 - write SP_EVENT_INITIATOR with event or SP_DRAW_INITIATOR 4899 - write PC_EVENT_INITIATOR with event or PC_DRAW_INITIATOR 4900 - write SP_EVENT_INITIATOR(CONTEXT_DONE) 4901 - write PC_EVENT_INITIATOR(CONTEXT_DONE) 4902 - write CP_EVENT_END 4903 Writing to CP_EVENT_END seems to actually trigger the context roll 4904 --> 4905 <reg32 offset="0xd600" name="CP_EVENT_START"> 4906 <bitfield name="STATE_ID" low="0" high="7"/> 4907 </reg32> 4908 <reg32 offset="0xd601" name="CP_EVENT_END"> 4909 <bitfield name="STATE_ID" low="0" high="7"/> 4910 </reg32> 4911 <reg32 offset="0xd700" name="CP_2D_EVENT_START"> 4912 <bitfield name="STATE_ID" low="0" high="7"/> 4913 </reg32> 4914 <reg32 offset="0xd701" name="CP_2D_EVENT_END"> 4915 <bitfield name="STATE_ID" low="0" high="7"/> 4916 </reg32> 4917</domain> 4918 4919<domain name="A6XX_PDC" width="32"> 4920 <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/> 4921 <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/> 4922 <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/> 4923 <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/> 4924 <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/> 4925 <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/> 4926 <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/> 4927 <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/> 4928 <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/> 4929 <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/> 4930 <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/> 4931 <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/> 4932 <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/> 4933 <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/> 4934 <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/> 4935 <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/> 4936 <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/> 4937 <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/> 4938 <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/> 4939 <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/> 4940 <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/> 4941 <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/> 4942 <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/> 4943 <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/> 4944 <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/> 4945 <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/> 4946</domain> 4947 4948<domain name="A6XX_PDC_GPU_SEQ" width="32"> 4949 <reg32 offset="0x0" name="MEM_0"/> 4950</domain> 4951 4952<domain name="A6XX_CX_DBGC" width="32"> 4953 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A"> 4954 <bitfield high="7" low="0" name="PING_INDEX"/> 4955 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 4956 </reg32> 4957 <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/> 4958 <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/> 4959 <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/> 4960 <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT"> 4961 <bitfield high="5" low="0" name="TRACEEN"/> 4962 <bitfield high="14" low="12" name="GRANU"/> 4963 <bitfield high="31" low="28" name="SEGT"/> 4964 </reg32> 4965 <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM"> 4966 <bitfield high="27" low="24" name="ENABLE"/> 4967 </reg32> 4968 <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/> 4969 <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/> 4970 <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/> 4971 <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/> 4972 <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/> 4973 <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/> 4974 <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/> 4975 <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/> 4976 <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0"> 4977 <bitfield high="3" low="0" name="BYTEL0"/> 4978 <bitfield high="7" low="4" name="BYTEL1"/> 4979 <bitfield high="11" low="8" name="BYTEL2"/> 4980 <bitfield high="15" low="12" name="BYTEL3"/> 4981 <bitfield high="19" low="16" name="BYTEL4"/> 4982 <bitfield high="23" low="20" name="BYTEL5"/> 4983 <bitfield high="27" low="24" name="BYTEL6"/> 4984 <bitfield high="31" low="28" name="BYTEL7"/> 4985 </reg32> 4986 <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1"> 4987 <bitfield high="3" low="0" name="BYTEL8"/> 4988 <bitfield high="7" low="4" name="BYTEL9"/> 4989 <bitfield high="11" low="8" name="BYTEL10"/> 4990 <bitfield high="15" low="12" name="BYTEL11"/> 4991 <bitfield high="19" low="16" name="BYTEL12"/> 4992 <bitfield high="23" low="20" name="BYTEL13"/> 4993 <bitfield high="27" low="24" name="BYTEL14"/> 4994 <bitfield high="31" low="28" name="BYTEL15"/> 4995 </reg32> 4996 4997 <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/> 4998 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> 4999</domain> 5000 5001<domain name="A7XX_CX_DBGC" width="32" varset="chip"> 5002 <!-- Bitfields shifted, but otherwise the same: --> 5003 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A" variants="A7XX-"> 5004 <bitfield high="7" low="0" name="PING_INDEX"/> 5005 <bitfield high="24" low="16" name="PING_BLK_SEL"/> 5006 </reg32> 5007</domain> 5008 5009<domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip"> 5010 <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/> 5011 <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/> 5012 <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/> 5013 <reg32 offset="0x0087" name="CX_MISC_SLICE_ENABLE_FINAL" variants="A8XX"/> 5014 <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-"> 5015 <bitfield pos="0" name="FASTBLEND" type="boolean"/> 5016 <bitfield pos="1" name="LPAC" type="boolean"/> 5017 <bitfield pos="2" name="RAYTRACING" type="boolean"/> 5018 </reg32> 5019 <reg32 offset="0x0405" name="CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS" variants="A8XX-"> 5020 <bitfield high="8" low="0" name="FINALFREQLIMIT"/> 5021 <bitfield pos="24" name="SOFTSKUDISABLED" type="boolean"/> 5022 </reg32> 5023</domain> 5024 5025</database> 5026