1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7<import file="adreno/adreno_pm4.xml"/> 8 9<!-- 10Each register that is actually being used by driver should have "usage" defined, 11currently there are following usages: 12- "cmd" - the register is used outside of renderpass and blits, 13 roughly corresponds to registers used in ib1 for Freedreno 14- "rp_blit" - the register is used inside renderpass or blits 15 (ib2 for Freedreno) 16 17It is expected that register with "cmd" usage may be written into only at 18the start of the command buffer (ib1), while "rp_blit" usage indicates that register 19is either overwritten by renderpass/blit (ib2) or not used if not overwritten 20by a particular renderpass/blit. 21--> 22 23<!-- these might be same as a5xx --> 24<enum name="a6xx_tile_mode"> 25 <value name="TILE6_LINEAR" value="0"/> 26 <value name="TILE6_2" value="2"/> 27 <value name="TILE6_3" value="3"/> 28</enum> 29 30<enum name="a6xx_format"> 31 <value value="0x02" name="FMT6_A8_UNORM"/> 32 <value value="0x03" name="FMT6_8_UNORM"/> 33 <value value="0x04" name="FMT6_8_SNORM"/> 34 <value value="0x05" name="FMT6_8_UINT"/> 35 <value value="0x06" name="FMT6_8_SINT"/> 36 37 <value value="0x08" name="FMT6_4_4_4_4_UNORM"/> 38 <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/> 39 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only --> 40 <value value="0x0e" name="FMT6_5_6_5_UNORM"/> 41 42 <value value="0x0f" name="FMT6_8_8_UNORM"/> 43 <value value="0x10" name="FMT6_8_8_SNORM"/> 44 <value value="0x11" name="FMT6_8_8_UINT"/> 45 <value value="0x12" name="FMT6_8_8_SINT"/> 46 <value value="0x13" name="FMT6_L8_A8_UNORM"/> 47 48 <value value="0x15" name="FMT6_16_UNORM"/> 49 <value value="0x16" name="FMT6_16_SNORM"/> 50 <value value="0x17" name="FMT6_16_FLOAT"/> 51 <value value="0x18" name="FMT6_16_UINT"/> 52 <value value="0x19" name="FMT6_16_SINT"/> 53 54 <value value="0x21" name="FMT6_8_8_8_UNORM"/> 55 <value value="0x22" name="FMT6_8_8_8_SNORM"/> 56 <value value="0x23" name="FMT6_8_8_8_UINT"/> 57 <value value="0x24" name="FMT6_8_8_8_SINT"/> 58 59 <value value="0x30" name="FMT6_8_8_8_8_UNORM"/> 60 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha --> 61 <value value="0x32" name="FMT6_8_8_8_8_SNORM"/> 62 <value value="0x33" name="FMT6_8_8_8_8_UINT"/> 63 <value value="0x34" name="FMT6_8_8_8_8_SINT"/> 64 65 <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/> 66 67 <value value="0x36" name="FMT6_10_10_10_2_UNORM"/> 68 <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/> 69 <value value="0x39" name="FMT6_10_10_10_2_SNORM"/> 70 <value value="0x3a" name="FMT6_10_10_10_2_UINT"/> 71 <value value="0x3b" name="FMT6_10_10_10_2_SINT"/> 72 73 <value value="0x42" name="FMT6_11_11_10_FLOAT"/> 74 75 <value value="0x43" name="FMT6_16_16_UNORM"/> 76 <value value="0x44" name="FMT6_16_16_SNORM"/> 77 <value value="0x45" name="FMT6_16_16_FLOAT"/> 78 <value value="0x46" name="FMT6_16_16_UINT"/> 79 <value value="0x47" name="FMT6_16_16_SINT"/> 80 81 <value value="0x48" name="FMT6_32_UNORM"/> 82 <value value="0x49" name="FMT6_32_SNORM"/> 83 <value value="0x4a" name="FMT6_32_FLOAT"/> 84 <value value="0x4b" name="FMT6_32_UINT"/> 85 <value value="0x4c" name="FMT6_32_SINT"/> 86 <value value="0x4d" name="FMT6_32_FIXED"/> 87 88 <value value="0x58" name="FMT6_16_16_16_UNORM"/> 89 <value value="0x59" name="FMT6_16_16_16_SNORM"/> 90 <value value="0x5a" name="FMT6_16_16_16_FLOAT"/> 91 <value value="0x5b" name="FMT6_16_16_16_UINT"/> 92 <value value="0x5c" name="FMT6_16_16_16_SINT"/> 93 94 <value value="0x60" name="FMT6_16_16_16_16_UNORM"/> 95 <value value="0x61" name="FMT6_16_16_16_16_SNORM"/> 96 <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/> 97 <value value="0x63" name="FMT6_16_16_16_16_UINT"/> 98 <value value="0x64" name="FMT6_16_16_16_16_SINT"/> 99 100 <value value="0x65" name="FMT6_32_32_UNORM"/> 101 <value value="0x66" name="FMT6_32_32_SNORM"/> 102 <value value="0x67" name="FMT6_32_32_FLOAT"/> 103 <value value="0x68" name="FMT6_32_32_UINT"/> 104 <value value="0x69" name="FMT6_32_32_SINT"/> 105 <value value="0x6a" name="FMT6_32_32_FIXED"/> 106 107 <value value="0x70" name="FMT6_32_32_32_UNORM"/> 108 <value value="0x71" name="FMT6_32_32_32_SNORM"/> 109 <value value="0x72" name="FMT6_32_32_32_UINT"/> 110 <value value="0x73" name="FMT6_32_32_32_SINT"/> 111 <value value="0x74" name="FMT6_32_32_32_FLOAT"/> 112 <value value="0x75" name="FMT6_32_32_32_FIXED"/> 113 114 <value value="0x80" name="FMT6_32_32_32_32_UNORM"/> 115 <value value="0x81" name="FMT6_32_32_32_32_SNORM"/> 116 <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/> 117 <value value="0x83" name="FMT6_32_32_32_32_UINT"/> 118 <value value="0x84" name="FMT6_32_32_32_32_SINT"/> 119 <value value="0x85" name="FMT6_32_32_32_32_FIXED"/> 120 121 <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/> <!-- UYVY --> 122 <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/> <!-- YUYV --> 123 <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/> <!-- NV12 --> 124 <value value="0x8f" name="FMT6_NV21"/> 125 <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/> <!-- YV12 --> 126 127 <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/> 128 129 <!-- Note: tiling/UBWC for these may be different from equivalent formats 130 For example FMT6_NV12_Y is not compatible with FMT6_8_UNORM 131 --> 132 <value value="0x94" name="FMT6_NV12_Y"/> 133 <value value="0x95" name="FMT6_NV12_UV"/> 134 <value value="0x96" name="FMT6_NV12_VU"/> 135 <value value="0x97" name="FMT6_NV12_4R"/> 136 <value value="0x98" name="FMT6_NV12_4R_Y"/> 137 <value value="0x99" name="FMT6_NV12_4R_UV"/> 138 <value value="0x9a" name="FMT6_P010"/> 139 <value value="0x9b" name="FMT6_P010_Y"/> 140 <value value="0x9c" name="FMT6_P010_UV"/> 141 <value value="0x9d" name="FMT6_TP10"/> 142 <value value="0x9e" name="FMT6_TP10_Y"/> 143 <value value="0x9f" name="FMT6_TP10_UV"/> 144 145 <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/> 146 147 <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/> 148 <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/> 149 <value value="0xad" name="FMT6_ETC2_R11_UNORM"/> 150 <value value="0xae" name="FMT6_ETC2_R11_SNORM"/> 151 <value value="0xaf" name="FMT6_ETC1"/> 152 <value value="0xb0" name="FMT6_ETC2_RGB8"/> 153 <value value="0xb1" name="FMT6_ETC2_RGBA8"/> 154 <value value="0xb2" name="FMT6_ETC2_RGB8A1"/> 155 <value value="0xb3" name="FMT6_DXT1"/> 156 <value value="0xb4" name="FMT6_DXT3"/> 157 <value value="0xb5" name="FMT6_DXT5"/> 158 <value value="0xb7" name="FMT6_RGTC1_UNORM"/> 159 <value value="0xb8" name="FMT6_RGTC1_SNORM"/> 160 <value value="0xbb" name="FMT6_RGTC2_UNORM"/> 161 <value value="0xbc" name="FMT6_RGTC2_SNORM"/> 162 <value value="0xbe" name="FMT6_BPTC_UFLOAT"/> 163 <value value="0xbf" name="FMT6_BPTC_FLOAT"/> 164 <value value="0xc0" name="FMT6_BPTC"/> 165 <value value="0xc1" name="FMT6_ASTC_4x4"/> 166 <value value="0xc2" name="FMT6_ASTC_5x4"/> 167 <value value="0xc3" name="FMT6_ASTC_5x5"/> 168 <value value="0xc4" name="FMT6_ASTC_6x5"/> 169 <value value="0xc5" name="FMT6_ASTC_6x6"/> 170 <value value="0xc6" name="FMT6_ASTC_8x5"/> 171 <value value="0xc7" name="FMT6_ASTC_8x6"/> 172 <value value="0xc8" name="FMT6_ASTC_8x8"/> 173 <value value="0xc9" name="FMT6_ASTC_10x5"/> 174 <value value="0xca" name="FMT6_ASTC_10x6"/> 175 <value value="0xcb" name="FMT6_ASTC_10x8"/> 176 <value value="0xcc" name="FMT6_ASTC_10x10"/> 177 <value value="0xcd" name="FMT6_ASTC_12x10"/> 178 <value value="0xce" name="FMT6_ASTC_12x12"/> 179 180 <!-- for sampling stencil (integer, 2nd channel), not available on a630 --> 181 <value value="0xea" name="FMT6_Z24_UINT_S8_UINT"/> 182 183 <!-- Not a hw enum, used internally in driver --> 184 <value value="0xff" name="FMT6_NONE"/> 185 186</enum> 187 188<!-- probably same as a5xx --> 189<enum name="a6xx_polygon_mode"> 190 <value name="POLYMODE6_POINTS" value="1"/> 191 <value name="POLYMODE6_LINES" value="2"/> 192 <value name="POLYMODE6_TRIANGLES" value="3"/> 193</enum> 194 195<enum name="a6xx_depth_format"> 196 <value name="DEPTH6_NONE" value="0"/> 197 <value name="DEPTH6_16" value="1"/> 198 <value name="DEPTH6_24_8" value="2"/> 199 <value name="DEPTH6_32" value="4"/> 200</enum> 201 202<bitset name="a6x_cp_protect" inline="yes"> 203 <bitfield name="BASE_ADDR" low="0" high="17"/> 204 <bitfield name="MASK_LEN" low="18" high="30"/> 205 <bitfield name="READ" pos="31" type="boolean"/> 206</bitset> 207 208<enum name="a6xx_shader_id"> 209 <value value="0x9" name="A6XX_TP0_TMO_DATA"/> 210 <value value="0xa" name="A6XX_TP0_SMO_DATA"/> 211 <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/> 212 <value value="0x19" name="A6XX_TP1_TMO_DATA"/> 213 <value value="0x1a" name="A6XX_TP1_SMO_DATA"/> 214 <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/> 215 <value value="0x29" name="A6XX_SP_INST_DATA"/> 216 <value value="0x2a" name="A6XX_SP_LB_0_DATA"/> 217 <value value="0x2b" name="A6XX_SP_LB_1_DATA"/> 218 <value value="0x2c" name="A6XX_SP_LB_2_DATA"/> 219 <value value="0x2d" name="A6XX_SP_LB_3_DATA"/> 220 <value value="0x2e" name="A6XX_SP_LB_4_DATA"/> 221 <value value="0x2f" name="A6XX_SP_LB_5_DATA"/> 222 <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/> 223 <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/> 224 <value value="0x32" name="A6XX_SP_UAV_DATA"/> 225 <value value="0x33" name="A6XX_SP_INST_TAG"/> 226 <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/> 227 <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/> 228 <value value="0x36" name="A6XX_SP_SMO_TAG"/> 229 <value value="0x37" name="A6XX_SP_STATE_DATA"/> 230 <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/> 231 <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/> 232 <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/> 233 <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/> 234 <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> 235 <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> 236 <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/> 237 <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/> 238 <value value="0x52" name="A6XX_HLSQ_INST_RAM"/> 239 <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/> 240 <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/> 241 <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/> 242 <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/> 243 <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/> 244 <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> 245 <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> 246 <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/> 247 <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/> 248 <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/> 249 <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/> 250 <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/> 251 <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/> 252 <value value="0x70" name="A6XX_SP_LB_6_DATA"/> 253 <value value="0x71" name="A6XX_SP_LB_7_DATA"/> 254 <value value="0x73" name="A6XX_HLSQ_INST_RAM_1"/> 255</enum> 256 257<enum name="a7xx_statetype_id"> 258 <value value="0" name="A7XX_TP0_NCTX_REG"/> 259 <value value="1" name="A7XX_TP0_CTX0_3D_CVS_REG"/> 260 <value value="2" name="A7XX_TP0_CTX0_3D_CPS_REG"/> 261 <value value="3" name="A7XX_TP0_CTX1_3D_CVS_REG"/> 262 <value value="4" name="A7XX_TP0_CTX1_3D_CPS_REG"/> 263 <value value="5" name="A7XX_TP0_CTX2_3D_CPS_REG"/> 264 <value value="6" name="A7XX_TP0_CTX3_3D_CPS_REG"/> 265 <value value="9" name="A7XX_TP0_TMO_DATA"/> 266 <value value="10" name="A7XX_TP0_SMO_DATA"/> 267 <value value="11" name="A7XX_TP0_MIPMAP_BASE_DATA"/> 268 <value value="32" name="A7XX_SP_NCTX_REG"/> 269 <value value="33" name="A7XX_SP_CTX0_3D_CVS_REG"/> 270 <value value="34" name="A7XX_SP_CTX0_3D_CPS_REG"/> 271 <value value="35" name="A7XX_SP_CTX1_3D_CVS_REG"/> 272 <value value="36" name="A7XX_SP_CTX1_3D_CPS_REG"/> 273 <value value="37" name="A7XX_SP_CTX2_3D_CPS_REG"/> 274 <value value="38" name="A7XX_SP_CTX3_3D_CPS_REG"/> 275 <value value="39" name="A7XX_SP_INST_DATA"/> 276 <value value="40" name="A7XX_SP_INST_DATA_1"/> 277 <value value="41" name="A7XX_SP_LB_0_DATA"/> 278 <value value="42" name="A7XX_SP_LB_1_DATA"/> 279 <value value="43" name="A7XX_SP_LB_2_DATA"/> 280 <value value="44" name="A7XX_SP_LB_3_DATA"/> 281 <value value="45" name="A7XX_SP_LB_4_DATA"/> 282 <value value="46" name="A7XX_SP_LB_5_DATA"/> 283 <value value="47" name="A7XX_SP_LB_6_DATA"/> 284 <value value="48" name="A7XX_SP_LB_7_DATA"/> 285 <value value="49" name="A7XX_SP_CB_RAM"/> 286 <value value="50" name="A7XX_SP_LB_13_DATA"/> 287 <value value="51" name="A7XX_SP_LB_14_DATA"/> 288 <value value="52" name="A7XX_SP_INST_TAG"/> 289 <value value="53" name="A7XX_SP_INST_DATA_2"/> 290 <value value="54" name="A7XX_SP_TMO_TAG"/> 291 <value value="55" name="A7XX_SP_SMO_TAG"/> 292 <value value="56" name="A7XX_SP_STATE_DATA"/> 293 <value value="57" name="A7XX_SP_HWAVE_RAM"/> 294 <value value="58" name="A7XX_SP_L0_INST_BUF"/> 295 <value value="59" name="A7XX_SP_LB_8_DATA"/> 296 <value value="60" name="A7XX_SP_LB_9_DATA"/> 297 <value value="61" name="A7XX_SP_LB_10_DATA"/> 298 <value value="62" name="A7XX_SP_LB_11_DATA"/> 299 <value value="63" name="A7XX_SP_LB_12_DATA"/> 300 <value value="64" name="A7XX_HLSQ_DATAPATH_DSTR_META"/> 301 <value value="67" name="A7XX_HLSQ_L2STC_TAG_RAM"/> 302 <value value="68" name="A7XX_HLSQ_L2STC_INFO_CMD"/> 303 <value value="69" name="A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG"/> 304 <value value="70" name="A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG"/> 305 <value value="71" name="A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM"/> 306 <value value="72" name="A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM"/> 307 <value value="73" name="A7XX_HLSQ_CHUNK_CVS_RAM"/> 308 <value value="74" name="A7XX_HLSQ_CHUNK_CPS_RAM"/> 309 <value value="75" name="A7XX_HLSQ_CHUNK_CVS_RAM_TAG"/> 310 <value value="76" name="A7XX_HLSQ_CHUNK_CPS_RAM_TAG"/> 311 <value value="77" name="A7XX_HLSQ_ICB_CVS_CB_BASE_TAG"/> 312 <value value="78" name="A7XX_HLSQ_ICB_CPS_CB_BASE_TAG"/> 313 <value value="79" name="A7XX_HLSQ_CVS_MISC_RAM"/> 314 <value value="80" name="A7XX_HLSQ_CPS_MISC_RAM"/> 315 <value value="81" name="A7XX_HLSQ_CPS_MISC_RAM_1"/> 316 <value value="82" name="A7XX_HLSQ_INST_RAM"/> 317 <value value="83" name="A7XX_HLSQ_GFX_CVS_CONST_RAM"/> 318 <value value="84" name="A7XX_HLSQ_GFX_CPS_CONST_RAM"/> 319 <value value="85" name="A7XX_HLSQ_CVS_MISC_RAM_TAG"/> 320 <value value="86" name="A7XX_HLSQ_CPS_MISC_RAM_TAG"/> 321 <value value="87" name="A7XX_HLSQ_INST_RAM_TAG"/> 322 <value value="88" name="A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/> 323 <value value="89" name="A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/> 324 <value value="90" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM"/> 325 <value value="91" name="A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG"/> 326 <value value="92" name="A7XX_HLSQ_INST_RAM_1"/> 327 <value value="93" name="A7XX_HLSQ_STPROC_META"/> 328 <value value="94" name="A7XX_HLSQ_BV_BE_META"/> 329 <value value="95" name="A7XX_HLSQ_INST_RAM_2"/> 330 <value value="96" name="A7XX_HLSQ_DATAPATH_META"/> 331 <value value="97" name="A7XX_HLSQ_FRONTEND_META"/> 332 <value value="98" name="A7XX_HLSQ_INDIRECT_META"/> 333 <value value="99" name="A7XX_HLSQ_BACKEND_META"/> 334</enum> 335 336<enum name="a6xx_debugbus_id"> 337 <value value="0x1" name="A6XX_DBGBUS_CP"/> 338 <value value="0x2" name="A6XX_DBGBUS_RBBM"/> 339 <value value="0x3" name="A6XX_DBGBUS_VBIF"/> 340 <value value="0x4" name="A6XX_DBGBUS_HLSQ"/> 341 <value value="0x5" name="A6XX_DBGBUS_UCHE"/> 342 <value value="0x6" name="A6XX_DBGBUS_DPM"/> 343 <value value="0x7" name="A6XX_DBGBUS_TESS"/> 344 <value value="0x8" name="A6XX_DBGBUS_PC"/> 345 <value value="0x9" name="A6XX_DBGBUS_VFDP"/> 346 <value value="0xa" name="A6XX_DBGBUS_VPC"/> 347 <value value="0xb" name="A6XX_DBGBUS_TSE"/> 348 <value value="0xc" name="A6XX_DBGBUS_RAS"/> 349 <value value="0xd" name="A6XX_DBGBUS_VSC"/> 350 <value value="0xe" name="A6XX_DBGBUS_COM"/> 351 <value value="0x10" name="A6XX_DBGBUS_LRZ"/> 352 <value value="0x11" name="A6XX_DBGBUS_A2D"/> 353 <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/> 354 <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/> 355 <value value="0x14" name="A6XX_DBGBUS_RBP"/> 356 <value value="0x15" name="A6XX_DBGBUS_DCS"/> 357 <value value="0x16" name="A6XX_DBGBUS_DBGC"/> 358 <value value="0x17" name="A6XX_DBGBUS_CX"/> 359 <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/> 360 <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/> 361 <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/> 362 <value value="0x1d" name="A6XX_DBGBUS_GPC"/> 363 <value value="0x1e" name="A6XX_DBGBUS_LARC"/> 364 <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/> 365 <value value="0x20" name="A6XX_DBGBUS_RB_0"/> 366 <value value="0x21" name="A6XX_DBGBUS_RB_1"/> 367 <value value="0x22" name="A6XX_DBGBUS_RB_2"/> 368 <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/> 369 <value value="0x28" name="A6XX_DBGBUS_CCU_0"/> 370 <value value="0x29" name="A6XX_DBGBUS_CCU_1"/> 371 <value value="0x2a" name="A6XX_DBGBUS_CCU_2"/> 372 <value value="0x38" name="A6XX_DBGBUS_VFD_0"/> 373 <value value="0x39" name="A6XX_DBGBUS_VFD_1"/> 374 <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/> 375 <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/> 376 <value value="0x3c" name="A6XX_DBGBUS_VFD_4"/> 377 <value value="0x3d" name="A6XX_DBGBUS_VFD_5"/> 378 <value value="0x40" name="A6XX_DBGBUS_SP_0"/> 379 <value value="0x41" name="A6XX_DBGBUS_SP_1"/> 380 <value value="0x42" name="A6XX_DBGBUS_SP_2"/> 381 <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/> 382 <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/> 383 <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/> 384 <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/> 385 <value value="0x4c" name="A6XX_DBGBUS_TPL1_4"/> 386 <value value="0x4d" name="A6XX_DBGBUS_TPL1_5"/> 387 <value value="0x58" name="A6XX_DBGBUS_SPTP_0"/> 388 <value value="0x59" name="A6XX_DBGBUS_SPTP_1"/> 389 <value value="0x5a" name="A6XX_DBGBUS_SPTP_2"/> 390 <value value="0x5b" name="A6XX_DBGBUS_SPTP_3"/> 391 <value value="0x5c" name="A6XX_DBGBUS_SPTP_4"/> 392 <value value="0x5d" name="A6XX_DBGBUS_SPTP_5"/> 393</enum> 394 395<enum name="a7xx_state_location"> 396 <value value="0" name="A7XX_HLSQ_STATE"/> 397 <value value="1" name="A7XX_HLSQ_DP"/> 398 <value value="2" name="A7XX_SP_TOP"/> 399 <value value="3" name="A7XX_USPTP"/> 400 <value value="4" name="A7XX_HLSQ_DP_STR"/> 401</enum> 402 403<enum name="a7xx_pipe"> 404 <value value="0" name="A7XX_PIPE_NONE"/> 405 <value value="1" name="A7XX_PIPE_BR"/> 406 <value value="2" name="A7XX_PIPE_BV"/> 407 <value value="3" name="A7XX_PIPE_LPAC"/> 408</enum> 409 410<enum name="a7xx_cluster"> 411 <value value="0" name="A7XX_CLUSTER_NONE"/> 412 <value value="1" name="A7XX_CLUSTER_FE"/> 413 <value value="2" name="A7XX_CLUSTER_SP_VS"/> 414 <value value="3" name="A7XX_CLUSTER_PC_VS"/> 415 <value value="4" name="A7XX_CLUSTER_GRAS"/> 416 <value value="5" name="A7XX_CLUSTER_SP_PS"/> 417 <value value="6" name="A7XX_CLUSTER_VPC_PS"/> 418 <value value="7" name="A7XX_CLUSTER_PS"/> 419</enum> 420 421<enum name="a7xx_debugbus_id"> 422 <value value="1" name="A7XX_DBGBUS_CP_0_0"/> 423 <value value="2" name="A7XX_DBGBUS_CP_0_1"/> 424 <value value="3" name="A7XX_DBGBUS_RBBM"/> 425 <value value="5" name="A7XX_DBGBUS_GBIF_GX"/> 426 <value value="6" name="A7XX_DBGBUS_GBIF_CX"/> 427 <value value="7" name="A7XX_DBGBUS_HLSQ"/> 428 <value value="9" name="A7XX_DBGBUS_UCHE_0"/> 429 <value value="10" name="A7XX_DBGBUS_UCHE_1"/> 430 <value value="13" name="A7XX_DBGBUS_TESS_BR"/> 431 <value value="14" name="A7XX_DBGBUS_TESS_BV"/> 432 <value value="17" name="A7XX_DBGBUS_PC_BR"/> 433 <value value="18" name="A7XX_DBGBUS_PC_BV"/> 434 <value value="21" name="A7XX_DBGBUS_VFDP_BR"/> 435 <value value="22" name="A7XX_DBGBUS_VFDP_BV"/> 436 <value value="25" name="A7XX_DBGBUS_VPC_BR"/> 437 <value value="26" name="A7XX_DBGBUS_VPC_BV"/> 438 <value value="29" name="A7XX_DBGBUS_TSE_BR"/> 439 <value value="30" name="A7XX_DBGBUS_TSE_BV"/> 440 <value value="33" name="A7XX_DBGBUS_RAS_BR"/> 441 <value value="34" name="A7XX_DBGBUS_RAS_BV"/> 442 <value value="37" name="A7XX_DBGBUS_VSC"/> 443 <value value="39" name="A7XX_DBGBUS_COM_0"/> 444 <value value="43" name="A7XX_DBGBUS_LRZ_BR"/> 445 <value value="44" name="A7XX_DBGBUS_LRZ_BV"/> 446 <value value="47" name="A7XX_DBGBUS_UFC_0"/> 447 <value value="48" name="A7XX_DBGBUS_UFC_1"/> 448 <value value="55" name="A7XX_DBGBUS_GMU_GX"/> 449 <value value="59" name="A7XX_DBGBUS_DBGC"/> 450 <value value="60" name="A7XX_DBGBUS_CX"/> 451 <value value="61" name="A7XX_DBGBUS_GMU_CX"/> 452 <value value="62" name="A7XX_DBGBUS_GPC_BR"/> 453 <value value="63" name="A7XX_DBGBUS_GPC_BV"/> 454 <value value="66" name="A7XX_DBGBUS_LARC"/> 455 <value value="68" name="A7XX_DBGBUS_HLSQ_SPTP"/> 456 <value value="70" name="A7XX_DBGBUS_RB_0"/> 457 <value value="71" name="A7XX_DBGBUS_RB_1"/> 458 <value value="72" name="A7XX_DBGBUS_RB_2"/> 459 <value value="73" name="A7XX_DBGBUS_RB_3"/> 460 <value value="74" name="A7XX_DBGBUS_RB_4"/> 461 <value value="75" name="A7XX_DBGBUS_RB_5"/> 462 <value value="102" name="A7XX_DBGBUS_UCHE_WRAPPER"/> 463 <value value="106" name="A7XX_DBGBUS_CCU_0"/> 464 <value value="107" name="A7XX_DBGBUS_CCU_1"/> 465 <value value="108" name="A7XX_DBGBUS_CCU_2"/> 466 <value value="109" name="A7XX_DBGBUS_CCU_3"/> 467 <value value="110" name="A7XX_DBGBUS_CCU_4"/> 468 <value value="111" name="A7XX_DBGBUS_CCU_5"/> 469 <value value="138" name="A7XX_DBGBUS_VFD_BR_0"/> 470 <value value="139" name="A7XX_DBGBUS_VFD_BR_1"/> 471 <value value="140" name="A7XX_DBGBUS_VFD_BR_2"/> 472 <value value="141" name="A7XX_DBGBUS_VFD_BR_3"/> 473 <value value="142" name="A7XX_DBGBUS_VFD_BR_4"/> 474 <value value="143" name="A7XX_DBGBUS_VFD_BR_5"/> 475 <value value="144" name="A7XX_DBGBUS_VFD_BR_6"/> 476 <value value="145" name="A7XX_DBGBUS_VFD_BR_7"/> 477 <value value="202" name="A7XX_DBGBUS_VFD_BV_0"/> 478 <value value="203" name="A7XX_DBGBUS_VFD_BV_1"/> 479 <value value="204" name="A7XX_DBGBUS_VFD_BV_2"/> 480 <value value="205" name="A7XX_DBGBUS_VFD_BV_3"/> 481 <value value="234" name="A7XX_DBGBUS_USP_0"/> 482 <value value="235" name="A7XX_DBGBUS_USP_1"/> 483 <value value="236" name="A7XX_DBGBUS_USP_2"/> 484 <value value="237" name="A7XX_DBGBUS_USP_3"/> 485 <value value="238" name="A7XX_DBGBUS_USP_4"/> 486 <value value="239" name="A7XX_DBGBUS_USP_5"/> 487 <value value="266" name="A7XX_DBGBUS_TP_0"/> 488 <value value="267" name="A7XX_DBGBUS_TP_1"/> 489 <value value="268" name="A7XX_DBGBUS_TP_2"/> 490 <value value="269" name="A7XX_DBGBUS_TP_3"/> 491 <value value="270" name="A7XX_DBGBUS_TP_4"/> 492 <value value="271" name="A7XX_DBGBUS_TP_5"/> 493 <value value="272" name="A7XX_DBGBUS_TP_6"/> 494 <value value="273" name="A7XX_DBGBUS_TP_7"/> 495 <value value="274" name="A7XX_DBGBUS_TP_8"/> 496 <value value="275" name="A7XX_DBGBUS_TP_9"/> 497 <value value="276" name="A7XX_DBGBUS_TP_10"/> 498 <value value="277" name="A7XX_DBGBUS_TP_11"/> 499 <value value="330" name="A7XX_DBGBUS_USPTP_0"/> 500 <value value="331" name="A7XX_DBGBUS_USPTP_1"/> 501 <value value="332" name="A7XX_DBGBUS_USPTP_2"/> 502 <value value="333" name="A7XX_DBGBUS_USPTP_3"/> 503 <value value="334" name="A7XX_DBGBUS_USPTP_4"/> 504 <value value="335" name="A7XX_DBGBUS_USPTP_5"/> 505 <value value="336" name="A7XX_DBGBUS_USPTP_6"/> 506 <value value="337" name="A7XX_DBGBUS_USPTP_7"/> 507 <value value="338" name="A7XX_DBGBUS_USPTP_8"/> 508 <value value="339" name="A7XX_DBGBUS_USPTP_9"/> 509 <value value="340" name="A7XX_DBGBUS_USPTP_10"/> 510 <value value="341" name="A7XX_DBGBUS_USPTP_11"/> 511 <value value="396" name="A7XX_DBGBUS_CCHE_0"/> 512 <value value="397" name="A7XX_DBGBUS_CCHE_1"/> 513 <value value="398" name="A7XX_DBGBUS_CCHE_2"/> 514 <value value="408" name="A7XX_DBGBUS_VPC_DSTR_0"/> 515 <value value="409" name="A7XX_DBGBUS_VPC_DSTR_1"/> 516 <value value="410" name="A7XX_DBGBUS_VPC_DSTR_2"/> 517 <value value="411" name="A7XX_DBGBUS_HLSQ_DP_STR_0"/> 518 <value value="412" name="A7XX_DBGBUS_HLSQ_DP_STR_1"/> 519 <value value="413" name="A7XX_DBGBUS_HLSQ_DP_STR_2"/> 520 <value value="414" name="A7XX_DBGBUS_HLSQ_DP_STR_3"/> 521 <value value="415" name="A7XX_DBGBUS_HLSQ_DP_STR_4"/> 522 <value value="416" name="A7XX_DBGBUS_HLSQ_DP_STR_5"/> 523 <value value="443" name="A7XX_DBGBUS_UFC_DSTR_0"/> 524 <value value="444" name="A7XX_DBGBUS_UFC_DSTR_1"/> 525 <value value="445" name="A7XX_DBGBUS_UFC_DSTR_2"/> 526 <value value="446" name="A7XX_DBGBUS_CGC_SUBCORE"/> 527 <value value="447" name="A7XX_DBGBUS_CGC_CORE"/> 528</enum> 529 530<enum name="a6xx_cp_perfcounter_select"> 531 <value value="0" name="PERF_CP_ALWAYS_COUNT"/> 532 <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> 533 <value value="2" name="PERF_CP_BUSY_CYCLES"/> 534 <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/> 535 <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> 536 <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> 537 <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> 538 <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> 539 <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/> 540 <value value="9" name="PERF_CP_MODE_SWITCH"/> 541 <value value="10" name="PERF_CP_ZPASS_DONE"/> 542 <value value="11" name="PERF_CP_CONTEXT_DONE"/> 543 <value value="12" name="PERF_CP_CACHE_FLUSH"/> 544 <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/> 545 <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/> 546 <value value="15" name="PERF_CP_SQE_IDLE"/> 547 <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/> 548 <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/> 549 <value value="18" name="PERF_CP_SQE_MRB_STARVE"/> 550 <value value="19" name="PERF_CP_SQE_RRB_STARVE"/> 551 <value value="20" name="PERF_CP_SQE_VSD_STARVE"/> 552 <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/> 553 <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/> 554 <value value="23" name="PERF_CP_SQE_SYNC_STALL"/> 555 <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/> 556 <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/> 557 <value value="26" name="PERF_CP_SQE_T4_EXEC"/> 558 <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/> 559 <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/> 560 <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/> 561 <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> 562 <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/> 563 <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/> 564 <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/> 565 <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> 566 <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> 567 <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/> 568 <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/> 569 <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/> 570 <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/> 571 <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/> 572 <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/> 573 <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/> 574 <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/> 575 <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/> 576 <value value="45" name="PERF_CP_PM4_DATA"/> 577 <value value="46" name="PERF_CP_PM4_HEADERS"/> 578 <value value="47" name="PERF_CP_VBIF_READ_BEATS"/> 579 <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/> 580 <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/> 581</enum> 582 583<enum name="a6xx_rbbm_perfcounter_select"> 584 <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/> 585 <value value="1" name="PERF_RBBM_ALWAYS_ON"/> 586 <value value="2" name="PERF_RBBM_TSE_BUSY"/> 587 <value value="3" name="PERF_RBBM_RAS_BUSY"/> 588 <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/> 589 <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/> 590 <value value="6" name="PERF_RBBM_STATUS_MASKED"/> 591 <value value="7" name="PERF_RBBM_COM_BUSY"/> 592 <value value="8" name="PERF_RBBM_DCOM_BUSY"/> 593 <value value="9" name="PERF_RBBM_VBIF_BUSY"/> 594 <value value="10" name="PERF_RBBM_VSC_BUSY"/> 595 <value value="11" name="PERF_RBBM_TESS_BUSY"/> 596 <value value="12" name="PERF_RBBM_UCHE_BUSY"/> 597 <value value="13" name="PERF_RBBM_HLSQ_BUSY"/> 598</enum> 599 600<enum name="a6xx_pc_perfcounter_select"> 601 <value value="0" name="PERF_PC_BUSY_CYCLES"/> 602 <value value="1" name="PERF_PC_WORKING_CYCLES"/> 603 <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/> 604 <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/> 605 <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/> 606 <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/> 607 <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/> 608 <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/> 609 <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/> 610 <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/> 611 <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/> 612 <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> 613 <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> 614 <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/> 615 <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/> 616 <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/> 617 <value value="16" name="PERF_PC_INSTANCES"/> 618 <value value="17" name="PERF_PC_VPC_PRIMITIVES"/> 619 <value value="18" name="PERF_PC_DEAD_PRIM"/> 620 <value value="19" name="PERF_PC_LIVE_PRIM"/> 621 <value value="20" name="PERF_PC_VERTEX_HITS"/> 622 <value value="21" name="PERF_PC_IA_VERTICES"/> 623 <value value="22" name="PERF_PC_IA_PRIMITIVES"/> 624 <value value="23" name="PERF_PC_GS_PRIMITIVES"/> 625 <value value="24" name="PERF_PC_HS_INVOCATIONS"/> 626 <value value="25" name="PERF_PC_DS_INVOCATIONS"/> 627 <value value="26" name="PERF_PC_VS_INVOCATIONS"/> 628 <value value="27" name="PERF_PC_GS_INVOCATIONS"/> 629 <value value="28" name="PERF_PC_DS_PRIMITIVES"/> 630 <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/> 631 <value value="30" name="PERF_PC_3D_DRAWCALLS"/> 632 <value value="31" name="PERF_PC_2D_DRAWCALLS"/> 633 <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> 634 <value value="33" name="PERF_TESS_BUSY_CYCLES"/> 635 <value value="34" name="PERF_TESS_WORKING_CYCLES"/> 636 <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/> 637 <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/> 638 <value value="37" name="PERF_PC_TSE_TRANSACTION"/> 639 <value value="38" name="PERF_PC_TSE_VERTEX"/> 640 <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/> 641 <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/> 642 <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/> 643</enum> 644 645<enum name="a6xx_vfd_perfcounter_select"> 646 <value value="0" name="PERF_VFD_BUSY_CYCLES"/> 647 <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/> 648 <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> 649 <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/> 650 <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/> 651 <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/> 652 <value value="6" name="PERF_VFD_RBUFFER_FULL"/> 653 <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/> 654 <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> 655 <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/> 656 <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/> 657 <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/> 658 <value value="12" name="PERF_VFD_MODE_0_FIBERS"/> 659 <value value="13" name="PERF_VFD_MODE_1_FIBERS"/> 660 <value value="14" name="PERF_VFD_MODE_2_FIBERS"/> 661 <value value="15" name="PERF_VFD_MODE_3_FIBERS"/> 662 <value value="16" name="PERF_VFD_MODE_4_FIBERS"/> 663 <value value="17" name="PERF_VFD_TOTAL_VERTICES"/> 664 <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/> 665 <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> 666 <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/> 667 <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/> 668 <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/> 669</enum> 670 671<enum name="a6xx_hlsq_perfcounter_select"> 672 <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/> 673 <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/> 674 <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/> 675 <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> 676 <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/> 677 <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/> 678 <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/> 679 <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/> 680 <value value="8" name="PERF_HLSQ_QUADS"/> 681 <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/> 682 <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/> 683 <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> 684 <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> 685 <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> 686 <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> 687 <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> 688 <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> 689 <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> 690 <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/> 691 <value value="19" name="PERF_HLSQ_PIXELS"/> 692 <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> 693</enum> 694 695<enum name="a6xx_vpc_perfcounter_select"> 696 <value value="0" name="PERF_VPC_BUSY_CYCLES"/> 697 <value value="1" name="PERF_VPC_WORKING_CYCLES"/> 698 <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/> 699 <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/> 700 <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> 701 <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/> 702 <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/> 703 <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/> 704 <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/> 705 <value value="9" name="PERF_VPC_PC_PRIMITIVES"/> 706 <value value="10" name="PERF_VPC_SP_COMPONENTS"/> 707 <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> 708 <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> 709 <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/> 710 <value value="14" name="PERF_VPC_LM_TRANSACTION"/> 711 <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/> 712 <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/> 713 <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/> 714 <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/> 715 <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/> 716 <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/> 717 <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/> 718 <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/> 719 <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/> 720 <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> 721 <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/> 722 <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/> 723 <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/> 724</enum> 725 726<enum name="a6xx_tse_perfcounter_select"> 727 <value value="0" name="PERF_TSE_BUSY_CYCLES"/> 728 <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/> 729 <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/> 730 <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> 731 <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> 732 <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/> 733 <value value="6" name="PERF_TSE_INPUT_PRIM"/> 734 <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/> 735 <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/> 736 <value value="9" name="PERF_TSE_CLIPPED_PRIM"/> 737 <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/> 738 <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/> 739 <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/> 740 <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/> 741 <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/> 742 <value value="15" name="PERF_TSE_CINVOCATION"/> 743 <value value="16" name="PERF_TSE_CPRIMITIVES"/> 744 <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/> 745 <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/> 746 <value value="19" name="PERF_TSE_CLIP_PLANES"/> 747</enum> 748 749<enum name="a6xx_ras_perfcounter_select"> 750 <value value="0" name="PERF_RAS_BUSY_CYCLES"/> 751 <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> 752 <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/> 753 <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/> 754 <value value="4" name="PERF_RAS_SUPER_TILES"/> 755 <value value="5" name="PERF_RAS_8X4_TILES"/> 756 <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/> 757 <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/> 758 <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/> 759 <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/> 760 <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> 761 <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> 762 <value value="12" name="PERF_RAS_BLOCKS"/> 763</enum> 764 765<enum name="a6xx_uche_perfcounter_select"> 766 <value value="0" name="PERF_UCHE_BUSY_CYCLES"/> 767 <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/> 768 <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/> 769 <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/> 770 <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/> 771 <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/> 772 <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> 773 <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/> 774 <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/> 775 <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/> 776 <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/> 777 <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/> 778 <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/> 779 <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/> 780 <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/> 781 <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/> 782 <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/> 783 <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/> 784 <value value="18" name="PERF_UCHE_EVICTS"/> 785 <value value="19" name="PERF_UCHE_BANK_REQ0"/> 786 <value value="20" name="PERF_UCHE_BANK_REQ1"/> 787 <value value="21" name="PERF_UCHE_BANK_REQ2"/> 788 <value value="22" name="PERF_UCHE_BANK_REQ3"/> 789 <value value="23" name="PERF_UCHE_BANK_REQ4"/> 790 <value value="24" name="PERF_UCHE_BANK_REQ5"/> 791 <value value="25" name="PERF_UCHE_BANK_REQ6"/> 792 <value value="26" name="PERF_UCHE_BANK_REQ7"/> 793 <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/> 794 <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/> 795 <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/> 796 <value value="30" name="PERF_UCHE_TPH_REF_FULL"/> 797 <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/> 798 <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/> 799 <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/> 800 <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/> 801 <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/> 802 <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/> 803 <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/> 804 <value value="38" name="PERF_UCHE_RAM_READ_REQ"/> 805 <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/> 806</enum> 807 808<enum name="a6xx_tp_perfcounter_select"> 809 <value value="0" name="PERF_TP_BUSY_CYCLES"/> 810 <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/> 811 <value value="2" name="PERF_TP_LATENCY_CYCLES"/> 812 <value value="3" name="PERF_TP_LATENCY_TRANS"/> 813 <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/> 814 <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/> 815 <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/> 816 <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/> 817 <value value="8" name="PERF_TP_SP_TP_TRANS"/> 818 <value value="9" name="PERF_TP_TP_SP_TRANS"/> 819 <value value="10" name="PERF_TP_OUTPUT_PIXELS"/> 820 <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/> 821 <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/> 822 <value value="13" name="PERF_TP_QUADS_RECEIVED"/> 823 <value value="14" name="PERF_TP_QUADS_OFFSET"/> 824 <value value="15" name="PERF_TP_QUADS_SHADOW"/> 825 <value value="16" name="PERF_TP_QUADS_ARRAY"/> 826 <value value="17" name="PERF_TP_QUADS_GRADIENT"/> 827 <value value="18" name="PERF_TP_QUADS_1D"/> 828 <value value="19" name="PERF_TP_QUADS_2D"/> 829 <value value="20" name="PERF_TP_QUADS_BUFFER"/> 830 <value value="21" name="PERF_TP_QUADS_3D"/> 831 <value value="22" name="PERF_TP_QUADS_CUBE"/> 832 <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/> 833 <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/> 834 <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/> 835 <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/> 836 <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/> 837 <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/> 838 <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> 839 <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/> 840 <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/> 841 <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/> 842 <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/> 843 <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/> 844 <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> 845 <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> 846 <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> 847 <value value="38" name="PERF_TP_TPA2TPC_TRANS"/> 848 <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/> 849 <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/> 850 <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/> 851 <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/> 852 <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/> 853 <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/> 854 <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> 855 <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/> 856 <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> 857 <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/> 858 <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/> 859 <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> 860 <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> 861 <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/> 862 <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/> 863 <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> 864 <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/> 865 <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/> 866</enum> 867 868<enum name="a6xx_sp_perfcounter_select"> 869 <value value="0" name="PERF_SP_BUSY_CYCLES"/> 870 <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/> 871 <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/> 872 <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/> 873 <value value="4" name="PERF_SP_STALL_CYCLES_TP"/> 874 <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/> 875 <value value="6" name="PERF_SP_STALL_CYCLES_RB"/> 876 <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/> 877 <value value="8" name="PERF_SP_WAVE_CONTEXTS"/> 878 <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/> 879 <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/> 880 <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/> 881 <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/> 882 <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/> 883 <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/> 884 <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/> 885 <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/> 886 <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/> 887 <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/> 888 <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/> 889 <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/> 890 <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/> 891 <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/> 892 <value value="23" name="PERF_SP_WAVE_END_CYCLES"/> 893 <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/> 894 <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> 895 <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/> 896 <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/> 897 <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/> 898 <value value="29" name="PERF_SP_LM_ATOMICS"/> 899 <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/> 900 <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/> 901 <value value="32" name="PERF_SP_GM_ATOMICS"/> 902 <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> 903 <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> 904 <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> 905 <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> 906 <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> 907 <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> 908 <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> 909 <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> 910 <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> 911 <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> 912 <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/> 913 <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/> 914 <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/> 915 <value value="46" name="PERF_SP_UCHE_READ_TRANS"/> 916 <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/> 917 <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/> 918 <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/> 919 <value value="50" name="PERF_SP_PIXELS_KILLED"/> 920 <value value="51" name="PERF_SP_ICL1_REQUESTS"/> 921 <value value="52" name="PERF_SP_ICL1_MISSES"/> 922 <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/> 923 <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/> 924 <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/> 925 <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/> 926 <value value="57" name="PERF_SP_GPR_READ"/> 927 <value value="58" name="PERF_SP_GPR_WRITE"/> 928 <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> 929 <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> 930 <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/> 931 <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> 932 <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> 933 <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> 934 <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/> 935 <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/> 936 <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/> 937 <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> 938 <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/> 939 <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/> 940 <value value="71" name="PERF_SP_WORKING_EU"/> 941 <value value="72" name="PERF_SP_ANY_EU_WORKING"/> 942 <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/> 943 <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/> 944 <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/> 945 <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/> 946 <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/> 947 <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/> 948 <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/> 949 <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/> 950 <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/> 951 <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/> 952 <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> 953 <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/> 954</enum> 955 956<enum name="a6xx_rb_perfcounter_select"> 957 <value value="0" name="PERF_RB_BUSY_CYCLES"/> 958 <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/> 959 <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/> 960 <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/> 961 <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/> 962 <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/> 963 <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/> 964 <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/> 965 <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/> 966 <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/> 967 <value value="10" name="PERF_RB_Z_WORKLOAD"/> 968 <value value="11" name="PERF_RB_HLSQ_ACTIVE"/> 969 <value value="12" name="PERF_RB_Z_READ"/> 970 <value value="13" name="PERF_RB_Z_WRITE"/> 971 <value value="14" name="PERF_RB_C_READ"/> 972 <value value="15" name="PERF_RB_C_WRITE"/> 973 <value value="16" name="PERF_RB_TOTAL_PASS"/> 974 <value value="17" name="PERF_RB_Z_PASS"/> 975 <value value="18" name="PERF_RB_Z_FAIL"/> 976 <value value="19" name="PERF_RB_S_FAIL"/> 977 <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/> 978 <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/> 979 <value value="22" name="PERF_RB_PS_INVOCATIONS"/> 980 <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/> 981 <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/> 982 <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/> 983 <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/> 984 <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/> 985 <value value="28" name="PERF_RB_2D_VALID_PIXELS"/> 986 <value value="29" name="PERF_RB_3D_PIXELS"/> 987 <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/> 988 <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/> 989 <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/> 990 <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/> 991 <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> 992 <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> 993 <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> 994 <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> 995 <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/> 996 <value value="39" name="PERF_RB_2D_INPUT_TRANS"/> 997 <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> 998 <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> 999 <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/> 1000 <value value="43" name="PERF_RB_COLOR_PIX_TILES"/> 1001 <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/> 1002 <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/> 1003 <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/> 1004 <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/> 1005</enum> 1006 1007<enum name="a6xx_vsc_perfcounter_select"> 1008 <value value="0" name="PERF_VSC_BUSY_CYCLES"/> 1009 <value value="1" name="PERF_VSC_WORKING_CYCLES"/> 1010 <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/> 1011 <value value="3" name="PERF_VSC_EOT_NUM"/> 1012 <value value="4" name="PERF_VSC_INPUT_TILES"/> 1013</enum> 1014 1015<enum name="a6xx_ccu_perfcounter_select"> 1016 <value value="0" name="PERF_CCU_BUSY_CYCLES"/> 1017 <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> 1018 <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> 1019 <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/> 1020 <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/> 1021 <value value="5" name="PERF_CCU_COLOR_BLOCKS"/> 1022 <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/> 1023 <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/> 1024 <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/> 1025 <value value="9" name="PERF_CCU_GMEM_READ"/> 1026 <value value="10" name="PERF_CCU_GMEM_WRITE"/> 1027 <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/> 1028 <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/> 1029 <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/> 1030 <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/> 1031 <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/> 1032 <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/> 1033 <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/> 1034 <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/> 1035 <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/> 1036 <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/> 1037 <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/> 1038 <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/> 1039 <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/> 1040 <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/> 1041 <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/> 1042 <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/> 1043 <value value="27" name="PERF_CCU_2D_RD_REQ"/> 1044 <value value="28" name="PERF_CCU_2D_WR_REQ"/> 1045</enum> 1046 1047<enum name="a6xx_lrz_perfcounter_select"> 1048 <value value="0" name="PERF_LRZ_BUSY_CYCLES"/> 1049 <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/> 1050 <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/> 1051 <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/> 1052 <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/> 1053 <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> 1054 <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/> 1055 <value value="7" name="PERF_LRZ_LRZ_READ"/> 1056 <value value="8" name="PERF_LRZ_LRZ_WRITE"/> 1057 <value value="9" name="PERF_LRZ_READ_LATENCY"/> 1058 <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/> 1059 <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> 1060 <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/> 1061 <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> 1062 <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/> 1063 <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/> 1064 <value value="16" name="PERF_LRZ_TILE_KILLED"/> 1065 <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/> 1066 <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> 1067 <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/> 1068 <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/> 1069 <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/> 1070 <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/> 1071 <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/> 1072 <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> 1073 <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> 1074 <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/> 1075 <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/> 1076</enum> 1077 1078<enum name="a6xx_cmp_perfcounter_select"> 1079 <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/> 1080 <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> 1081 <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> 1082 <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> 1083 <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> 1084 <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/> 1085 <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> 1086 <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/> 1087 <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/> 1088 <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/> 1089 <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/> 1090 <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> 1091 <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> 1092 <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> 1093 <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> 1094 <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> 1095 <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> 1096 <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> 1097 <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> 1098 <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> 1099 <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> 1100 <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> 1101 <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> 1102 <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> 1103 <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> 1104 <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/> 1105 <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/> 1106 <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/> 1107 <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/> 1108 <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/> 1109 <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> 1110 <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> 1111 <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/> 1112 <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> 1113 <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> 1114 <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> 1115 <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> 1116 <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/> 1117 <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/> 1118 <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/> 1119</enum> 1120 1121<!-- 1122Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the 1123component type/size, so I think it relates to internal format used for 1124blending? The one exception is that 16b unorm and 32b float use the 1125same value... maybe 16b unorm is uncommon enough that it was just easier 1126to upconvert to 32b float internally? 1127 1128 8b unorm: 10 (sometimes 0, is the high bit part of something else?) 112916b unorm: 4 1130 113132b int: 7 113216b int: 6 1133 8b int: 5 1134 113532b float: 4 113616b float: 3 1137 --> 1138<enum name="a6xx_2d_ifmt"> 1139 <value value="0x10" name="R2D_UNORM8"/> 1140 <value value="0x7" name="R2D_INT32"/> 1141 <value value="0x6" name="R2D_INT16"/> 1142 <value value="0x5" name="R2D_INT8"/> 1143 <value value="0x4" name="R2D_FLOAT32"/> 1144 <value value="0x3" name="R2D_FLOAT16"/> 1145 <value value="0x1" name="R2D_UNORM8_SRGB"/> 1146 <value value="0x0" name="R2D_RAW"/> 1147</enum> 1148 1149<enum name="a6xx_ztest_mode"> 1150 <doc>Allow early z-test and early-lrz (if applicable)</doc> 1151 <value value="0x0" name="A6XX_EARLY_Z"/> 1152 <doc>Disable early z-test and early-lrz test (if applicable)</doc> 1153 <value value="0x1" name="A6XX_LATE_Z"/> 1154 <doc> 1155 A special mode that allows early-lrz test but disables 1156 early-z test. Which might sound a bit funny, since 1157 lrz-test happens before z-test. But as long as a couple 1158 conditions are maintained this allows using lrz-test in 1159 cases where fragment shader has kill/discard: 1160 1161 1) Disable lrz-write in cases where it is uncertain during 1162 binning pass that a fragment will pass. Ie. if frag 1163 shader has-kill, writes-z, or alpha/stencil test is 1164 enabled. (For correctness, lrz-write must be disabled 1165 when blend is enabled.) This is analogous to how a 1166 z-prepass works. 1167 1168 2) Disable lrz-write and test if a depth-test direction 1169 reversal is detected. Due to condition (1), the contents 1170 of the lrz buffer are a conservative estimation of the 1171 depth buffer during the draw pass. Meaning that geometry 1172 that we know for certain will not be visible will not pass 1173 lrz-test. But geometry which may be (or contributes to 1174 blend) will pass the lrz-test. 1175 1176 This allows us to keep early-lrz-test in cases where the frag 1177 shader does not write-z (ie. we know the z-value before FS) 1178 and does not have side-effects (image/ssbo writes, etc), but 1179 does have kill/discard. Which turns out to be a common 1180 enough case that it is useful to keep early-lrz test against 1181 the conservative lrz buffer to discard fragments that we 1182 know will definitely not be visible. 1183 </doc> 1184 <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/> 1185 <doc>Not a real hw value, used internally by mesa</doc> 1186 <value value="0x3" name="A6XX_INVALID_ZTEST"/> 1187</enum> 1188 1189<enum name="a6xx_tess_spacing"> 1190 <value value="0x0" name="TESS_EQUAL"/> 1191 <value value="0x2" name="TESS_FRACTIONAL_ODD"/> 1192 <value value="0x3" name="TESS_FRACTIONAL_EVEN"/> 1193</enum> 1194<enum name="a6xx_tess_output"> 1195 <value value="0x0" name="TESS_POINTS"/> 1196 <value value="0x1" name="TESS_LINES"/> 1197 <value value="0x2" name="TESS_CW_TRIS"/> 1198 <value value="0x3" name="TESS_CCW_TRIS"/> 1199</enum> 1200 1201<domain name="A6XX" width="32" prefix="variant" varset="chip"> 1202 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip"> 1203 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/> 1204 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/> 1205 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/> 1206 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/> 1207 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/> 1208 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/> 1209 <bitfield name="CP_SW" pos="8" type="boolean"/> 1210 <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/> 1211 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/> 1212 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/> 1213 <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/> 1214 <bitfield name="CP_IB2" pos="13" type="boolean"/> 1215 <bitfield name="CP_IB1" pos="14" type="boolean"/> 1216 <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/> 1217 <!-- Same as above but different name??: --> 1218 <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/> 1219 <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/> 1220 <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/> 1221 <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/> 1222 <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/> 1223 <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/> 1224 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/> 1225 <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/> 1226 <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/> 1227 <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/> 1228 <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/> 1229 <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/> 1230 <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/> 1231 <bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/> 1232 <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/> 1233 <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/> 1234 </bitset> 1235 1236 <!-- 1237 Note the _LPAC bits probably *actually* first appeared in a660, but the 1238 _BV bits are new in a7xx 1239 --> 1240 <bitset name="A6XX_CP_INT" varset="chip"> 1241 <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/> 1242 <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/> 1243 <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/> 1244 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/> 1245 <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/> 1246 <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/> 1247 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/> 1248 <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/> 1249 <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/> 1250 <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/> 1251 <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/> 1252 <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/> 1253 <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/> 1254 <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/> 1255 <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/> 1256 <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/> 1257 <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/> 1258 </bitset> 1259 1260 <reg64 offset="0x0800" name="CP_RB_BASE"/> 1261 <reg32 offset="0x0802" name="CP_RB_CNTL"/> 1262 <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/> 1263 <reg32 offset="0x0806" name="CP_RB_RPTR"/> 1264 <reg32 offset="0x0807" name="CP_RB_WPTR"/> 1265 <reg32 offset="0x0808" name="CP_SQE_CNTL"/> 1266 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS"> 1267 <bitfield name="IFPC" pos="0" type="boolean"/> 1268 </reg32> 1269 <reg32 offset="0x0821" name="CP_HW_FAULT"/> 1270 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/> 1271 <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/> 1272 <reg32 offset="0x0825" name="CP_STATUS_1"/> 1273 <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/> 1274 <reg32 offset="0x0840" name="CP_MISC_CNTL"/> 1275 <reg32 offset="0x0844" name="CP_APRIV_CNTL"> 1276 <!-- Crashdumper writes --> 1277 <bitfield pos="6" name="CDWRITE" type="boolean"/> 1278 <!-- Crashdumper reads --> 1279 <bitfield pos="5" name="CDREAD" type="boolean"/> 1280 1281 <!-- 4 is unknown --> 1282 1283 <!-- RPTR shadow writes --> 1284 <bitfield pos="3" name="RBRPWB" type="boolean"/> 1285 <!-- Memory accesses from PM4 packets in the ringbuffer --> 1286 <bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/> 1287 <!-- Ringbuffer reads --> 1288 <bitfield pos="1" name="RBFETCH" type="boolean"/> 1289 <!-- Instruction cache fetches --> 1290 <bitfield pos="0" name="ICACHE" type="boolean"/> 1291 </reg32> 1292 <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: --> 1293 <reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/> 1294 <!-- all the threshold values seem to be in units of quad-dwords: --> 1295 <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1"> 1296 <doc> 1297 b0..7 identifies where MRB data starts (and RB data ends) 1298 b8.15 identifies where VSD data starts (and MRB data ends) 1299 b16..23 identifies where IB1 data starts (and RB data ends) 1300 b24..31 identifies where IB2 data starts (and IB1 data ends) 1301 </doc> 1302 <bitfield name="MRB_START" low="0" high="7" shr="2"/> 1303 <bitfield name="VSD_START" low="8" high="15" shr="2"/> 1304 <bitfield name="IB1_START" low="16" high="23" shr="2"/> 1305 <bitfield name="IB2_START" low="24" high="31" shr="2"/> 1306 </reg32> 1307 <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2"> 1308 <doc> 1309 low bits identify where CP_SET_DRAW_STATE stateobj 1310 processing starts (and IB2 data ends). I'm guessing 1311 b8 is part of this since (from downstream kgsl): 1312 1313 /* ROQ sizes are twice as big on a640/a680 than on a630 */ 1314 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) { 1315 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 1316 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C); 1317 } ... 1318 </doc> 1319 <bitfield name="SDS_START" low="0" high="8" shr="2"/> 1320 <!-- total ROQ size: --> 1321 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/> 1322 </reg32> 1323 <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/> 1324 <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/> 1325 <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 1326 <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/> 1327 <reg32 offset="0x084F" name="CP_PROTECT_CNTL"> 1328 <bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/> 1329 <bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/> 1330 <bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/> 1331 </reg32> 1332 1333 <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8"> 1334 <reg32 offset="0x0" name="REG" type="uint"/> 1335 </array> 1336 <array offset="0x0850" name="CP_PROTECT" stride="1" length="32"> 1337 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 1338 </array> 1339 1340 <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/> 1341 <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/> 1342 <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/> 1343 <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/> 1344 <reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/> 1345 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/> 1346 <array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/> 1347 <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/> 1348 <reg64 offset="0x0900" name="CP_CRASH_SCRIPT_BASE"/> 1349 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/> 1350 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/> 1351 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/> 1352 <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/> 1353 <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/> 1354 <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/> 1355 <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/> 1356 <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/> 1357 <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/> 1358 <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/> 1359 <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/> 1360 <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/> 1361 <reg64 offset="0x0928" name="CP_IB1_BASE"/> 1362 <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/> 1363 <reg64 offset="0x092B" name="CP_IB2_BASE"/> 1364 <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/> 1365 <!-- SDS == CP_SET_DRAW_STATE: --> 1366 <reg64 offset="0x092e" name="CP_SDS_BASE"/> 1367 <reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/> 1368 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware --> 1369 <reg64 offset="0x0931" name="CP_MRB_BASE"/> 1370 <reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/> 1371 <!-- 1372 VSD == Visibility Stream Decode 1373 This is used by CP to read the draw stream and skip empty draws 1374 --> 1375 <reg64 offset="0x0934" name="CP_VSD_BASE"/> 1376 1377 <bitset name="a6xx_roq_stat" inline="yes"> 1378 <bitfield name="RPTR" low="0" high="9"/> 1379 <bitfield name="WPTR" low="16" high="25"/> 1380 </bitset> 1381 <reg32 offset="0x0939" name="CP_ROQ_RB_STAT" type="a6xx_roq_stat"/> 1382 <reg32 offset="0x093a" name="CP_ROQ_IB1_STAT" type="a6xx_roq_stat"/> 1383 <reg32 offset="0x093b" name="CP_ROQ_IB2_STAT" type="a6xx_roq_stat"/> 1384 <reg32 offset="0x093c" name="CP_ROQ_SDS_STAT" type="a6xx_roq_stat"/> 1385 <reg32 offset="0x093d" name="CP_ROQ_MRB_STAT" type="a6xx_roq_stat"/> 1386 <reg32 offset="0x093e" name="CP_ROQ_VSD_STAT" type="a6xx_roq_stat"/> 1387 1388 <reg32 offset="0x0943" name="CP_IB1_DWORDS"/> 1389 <reg32 offset="0x0944" name="CP_IB2_DWORDS"/> 1390 <reg32 offset="0x0945" name="CP_SDS_DWORDS"/> 1391 <reg32 offset="0x0946" name="CP_MRB_DWORDS"/> 1392 <reg32 offset="0x0947" name="CP_VSD_DWORDS"/> 1393 1394 <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB"> 1395 <doc>number of remaining dwords incl current dword being consumed?</doc> 1396 <bitfield name="REM" low="16" high="31"/> 1397 </reg32> 1398 <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1"> 1399 <doc>number of remaining dwords incl current dword being consumed?</doc> 1400 <bitfield name="REM" low="16" high="31"/> 1401 </reg32> 1402 <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2"> 1403 <doc>number of remaining dwords incl current dword being consumed?</doc> 1404 <bitfield name="REM" low="16" high="31"/> 1405 </reg32> 1406 <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS"> 1407 <doc>number of remaining dwords incl current dword being consumed?</doc> 1408 <bitfield name="REM" low="16" high="31"/> 1409 </reg32> 1410 <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB"> 1411 <doc>number of dwords that have already been read but haven't been consumed by $addr</doc> 1412 <bitfield name="REM" low="16" high="31"/> 1413 </reg32> 1414 <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD"> 1415 <doc>number of remaining dwords incl current dword being consumed?</doc> 1416 <bitfield name="REM" low="16" high="31"/> 1417 </reg32> 1418 1419 <bitset name="a7xx_aperture_cntl" inline="yes"> 1420 <bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/> 1421 <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/> 1422 <bitfield name="CONTEXT" low="4" high="5"/> 1423 </bitset> 1424 <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/> 1425 <reg32 offset="0x098D" name="CP_AHB_CNTL"/> 1426 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/> 1427 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/> 1428 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/> 1429 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/> 1430 1431 <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/> 1432 <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/> 1433 <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/> 1434 <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/> 1435 <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/> 1436 <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/> 1437 <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/> 1438 <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/> 1439 <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/> 1440 <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/> 1441 <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/> 1442 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/> 1443 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/> 1444 1445 <reg32 offset="0x0a9a" name="CP_RESOURCE_TBL_DBG_ADDR" variants="A7XX-"/> 1446 <reg32 offset="0x0a9b" name="CP_RESOURCE_TBL_DBG_DATA" variants="A7XX-"/> 1447 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/> 1448 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/> 1449 1450 <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/> 1451 <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/> 1452 <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/> 1453 <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/> 1454 <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/> 1455 <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/> 1456 <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/> 1457 1458 <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/> 1459 <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/> 1460 <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/> 1461 <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/> 1462 <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/> 1463 <reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/> 1464 <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/> 1465 1466 <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/> 1467 <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/> 1468 <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/> 1469 1470 <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/> 1471 <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/> 1472 <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/> 1473 <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/> 1474 <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/> 1475 <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/> 1476 <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/> 1477 <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/> 1478 <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/> 1479 <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/> 1480 <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/> 1481 <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/> 1482 1483 <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 1484 <reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/> 1485 <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/> 1486 <reg32 offset="0x0210" name="RBBM_STATUS"> 1487 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/> 1488 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/> 1489 <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/> 1490 <bitfield pos="20" name="VSC_BUSY" type="boolean"/> 1491 <bitfield pos="19" name="TPL1_BUSY" type="boolean"/> 1492 <bitfield pos="18" name="SP_BUSY" type="boolean"/> 1493 <bitfield pos="17" name="UCHE_BUSY" type="boolean"/> 1494 <bitfield pos="16" name="VPC_BUSY" type="boolean"/> 1495 <bitfield pos="15" name="VFD_BUSY" type="boolean"/> 1496 <bitfield pos="14" name="TESS_BUSY" type="boolean"/> 1497 <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/> 1498 <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/> 1499 <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/> 1500 <bitfield pos="10" name="LRZ_BUSY" type="boolean"/> 1501 <bitfield pos="9" name="A2D_BUSY" type="boolean"/> 1502 <bitfield pos="8" name="CCU_BUSY" type="boolean"/> 1503 <bitfield pos="7" name="RB_BUSY" type="boolean"/> 1504 <bitfield pos="6" name="RAS_BUSY" type="boolean"/> 1505 <bitfield pos="5" name="TSE_BUSY" type="boolean"/> 1506 <bitfield pos="4" name="VBIF_BUSY" type="boolean"/> 1507 <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/> 1508 <bitfield pos="2" name="CP_BUSY" type="boolean"/> 1509 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/> 1510 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/> 1511 </reg32> 1512 <reg32 offset="0x0211" name="RBBM_STATUS1"/> 1513 <reg32 offset="0x0212" name="RBBM_STATUS2"/> 1514 <reg32 offset="0x0213" name="RBBM_STATUS3"> 1515 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/> 1516 </reg32> 1517 <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/> 1518 1519 <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/> 1520 <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/> 1521 <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/> 1522 <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/> 1523 <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/> 1524 <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/> 1525 1526 <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/> 1527 <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/> 1528 1529 <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/> 1530 <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/> 1531 <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/> 1532 <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/> 1533 <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/> 1534 <array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/> 1535 <array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/> 1536 <array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/> 1537 <array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/> 1538 <array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/> 1539 <array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/> 1540 <array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/> 1541 <array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/> 1542 <array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/> 1543 <array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/> 1544 <array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/> 1545 1546 <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/> 1547 <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/> 1548 <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/> 1549 <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/> 1550 <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/> 1551 <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/> 1552 <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/> 1553 <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/> 1554 <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/> 1555 <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/> 1556 <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/> 1557 <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/> 1558 <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/> 1559 <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/> 1560 <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/> 1561 <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/> 1562 <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/> 1563 <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/> 1564 <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/> 1565 <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/> 1566 <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/> 1567 <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/> 1568 <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/> 1569 <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/> 1570 <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/> 1571 <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/> 1572 <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/> 1573 <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/> 1574 1575 <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/> 1576 <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/> 1577 <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/> 1578 <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/> 1579 <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/> 1580 <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/> 1581 <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/> 1582 <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/> 1583 <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/> 1584 <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/> 1585 <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/> 1586 <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/> 1587 <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL" variants="A7XX-"/> 1588 <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/> 1589 1590 <!--- 1591 This block of registers aren't tied to perf counters. They 1592 count various geometry stats, for example number of 1593 vertices in, number of primnitives assembled etc. 1594 --> 1595 1596 <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in --> 1597 <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/> 1598 <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out --> 1599 <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/> 1600 <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in --> 1601 <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/> 1602 <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out --> 1603 <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/> 1604 <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in --> 1605 <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/> 1606 <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out --> 1607 <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/> 1608 <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in --> 1609 <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/> 1610 <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out --> 1611 <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/> 1612 <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out --> 1613 <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/> 1614 <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in --> 1615 <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/> 1616 <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/> 1617 <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/> 1618 1619 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> 1620 <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/> 1621 <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/> 1622 <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/> 1623 <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 1624 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/> 1625 <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/> 1626 <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/> 1627 <reg32 offset="0x00016" name="RBBM_GBIF_HALT"/> 1628 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/> 1629 <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD"> 1630 <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/> 1631 </reg32> 1632 1633 <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/> 1634 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/> 1635 <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> 1636 <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/> 1637 <reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/> 1638 <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/> 1639 <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/> 1640 <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/> 1641 <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/> 1642 <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/> 1643 <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/> 1644 <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/> 1645 <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/> 1646 <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/> 1647 <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/> 1648 <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/> 1649 <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/> 1650 <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/> 1651 <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/> 1652 <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/> 1653 <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/> 1654 <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/> 1655 <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/> 1656 <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/> 1657 <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/> 1658 <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/> 1659 <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/> 1660 <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/> 1661 <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/> 1662 <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/> 1663 <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/> 1664 <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/> 1665 <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/> 1666 <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/> 1667 <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/> 1668 <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/> 1669 <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/> 1670 <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/> 1671 <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/> 1672 <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/> 1673 <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/> 1674 <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/> 1675 <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/> 1676 <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/> 1677 <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/> 1678 <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/> 1679 <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/> 1680 <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/> 1681 <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/> 1682 <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/> 1683 <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/> 1684 <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/> 1685 <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/> 1686 <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/> 1687 <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/> 1688 <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/> 1689 <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/> 1690 <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/> 1691 <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/> 1692 <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/> 1693 <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/> 1694 <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/> 1695 <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/> 1696 <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/> 1697 <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/> 1698 <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/> 1699 <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/> 1700 <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/> 1701 <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/> 1702 <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/> 1703 <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/> 1704 <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/> 1705 <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/> 1706 <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/> 1707 <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/> 1708 <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/> 1709 <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/> 1710 <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/> 1711 <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/> 1712 <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/> 1713 <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/> 1714 <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/> 1715 <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/> 1716 <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/> 1717 <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/> 1718 <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/> 1719 <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/> 1720 <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/> 1721 <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/> 1722 <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/> 1723 <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/> 1724 <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/> 1725 <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/> 1726 <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/> 1727 <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/> 1728 <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/> 1729 <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/> 1730 <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/> 1731 <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/> 1732 <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/> 1733 <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/> 1734 <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/> 1735 <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/> 1736 <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/> 1737 <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/> 1738 <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/> 1739 <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/> 1740 <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/> 1741 <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/> 1742 <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/> 1743 <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/> 1744 <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/> 1745 <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/> 1746 <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/> 1747 <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/> 1748 <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/> 1749 <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/> 1750 <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/> 1751 <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/> 1752 <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/> 1753 <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/> 1754 <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/> 1755 <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/> 1756 <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/> 1757 <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-"> 1758 <bitfield name="TXDONE" pos="0" type="boolean"/> 1759 </reg32> 1760 <reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/> 1761 <reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/> 1762 <reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/> 1763 <reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/> 1764 <reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/> 1765 <reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/> 1766 <reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/> 1767 <reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/> 1768 <reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/> 1769 <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/> 1770 <reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/> 1771 1772 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/> 1773 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/> 1774 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/> 1775 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D"> 1776 <bitfield high="7" low="0" name="PING_INDEX"/> 1777 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 1778 </reg32> 1779 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT"> 1780 <bitfield high="5" low="0" name="TRACEEN"/> 1781 <bitfield high="14" low="12" name="GRANU"/> 1782 <bitfield high="31" low="28" name="SEGT"/> 1783 </reg32> 1784 <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM"> 1785 <bitfield high="27" low="24" name="ENABLE"/> 1786 </reg32> 1787 <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/> 1788 <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/> 1789 <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/> 1790 <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/> 1791 <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/> 1792 <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/> 1793 <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/> 1794 <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/> 1795 <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0"> 1796 <bitfield high="3" low="0" name="BYTEL0"/> 1797 <bitfield high="7" low="4" name="BYTEL1"/> 1798 <bitfield high="11" low="8" name="BYTEL2"/> 1799 <bitfield high="15" low="12" name="BYTEL3"/> 1800 <bitfield high="19" low="16" name="BYTEL4"/> 1801 <bitfield high="23" low="20" name="BYTEL5"/> 1802 <bitfield high="27" low="24" name="BYTEL6"/> 1803 <bitfield high="31" low="28" name="BYTEL7"/> 1804 </reg32> 1805 <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1"> 1806 <bitfield high="3" low="0" name="BYTEL8"/> 1807 <bitfield high="7" low="4" name="BYTEL9"/> 1808 <bitfield high="11" low="8" name="BYTEL10"/> 1809 <bitfield high="15" low="12" name="BYTEL11"/> 1810 <bitfield high="19" low="16" name="BYTEL12"/> 1811 <bitfield high="23" low="20" name="BYTEL13"/> 1812 <bitfield high="27" low="24" name="BYTEL14"/> 1813 <bitfield high="31" low="28" name="BYTEL15"/> 1814 </reg32> 1815 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/> 1816 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/> 1817 <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2"/> 1818 <reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX"> 1819 <doc> 1820 Set to true when binning, isn't changed afterwards 1821 </doc> 1822 <bitfield name="BINNING" pos="0" type="boolean"/> 1823 </reg32> 1824 <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/> 1825 <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/> 1826 <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 1827 <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/> 1828 <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/> 1829 <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/> 1830 <reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/> 1831 <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/> 1832 <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/> 1833 <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/> 1834 <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/> 1835 <reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd"> 1836 <bitfield high="7" low="0" name="PERFSEL"/> 1837 </reg32> 1838 <array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/> 1839 <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/> 1840 <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/> 1841 1842 <reg32 offset="0x3000" name="VBIF_VERSION"/> 1843 <reg32 offset="0x3001" name="VBIF_CLKON"> 1844 <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/> 1845 </reg32> 1846 <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/> 1847 <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/> 1848 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/> 1849 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/> 1850 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/> 1851 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"> 1852 <bitfield low="0" high="3" name="DATA_SEL"/> 1853 </reg32> 1854 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/> 1855 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"> 1856 <bitfield low="0" high="8" name="DATA_SEL"/> 1857 </reg32> 1858 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/> 1859 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/> 1860 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/> 1861 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/> 1862 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/> 1863 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/> 1864 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/> 1865 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/> 1866 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/> 1867 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/> 1868 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/> 1869 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/> 1870 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/> 1871 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/> 1872 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/> 1873 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/> 1874 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/> 1875 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/> 1876 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/> 1877 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/> 1878 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/> 1879 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/> 1880 1881 <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/> 1882 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/> 1883 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/> 1884 <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/> 1885 <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/> 1886 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/> 1887 <reg32 offset="0x3c45" name="GBIF_HALT"/> 1888 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/> 1889 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/> 1890 <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/> 1891 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/> 1892 <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/> 1893 <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/> 1894 <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/> 1895 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/> 1896 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/> 1897 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/> 1898 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/> 1899 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/> 1900 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/> 1901 <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/> 1902 <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/> 1903 <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/> 1904 <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/> 1905 <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/> 1906 <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/> 1907 1908 <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/> 1909 <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit"> 1910 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/> 1911 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/> 1912 </reg32> 1913 <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress" usage="cmd"/> 1914 <reg32 offset="0x0c06" name="VSC_BIN_COUNT" usage="rp_blit"> 1915 <bitfield name="NX" low="1" high="10" type="uint"/> 1916 <bitfield name="NY" low="11" high="20" type="uint"/> 1917 </reg32> 1918 <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="rp_blit"> 1919 <reg32 offset="0x0" name="REG"> 1920 <doc> 1921 Configures the mapping between VSC_PIPE buffer and 1922 bin, X/Y specify the bin index in the horiz/vert 1923 direction (0,0 is upper left, 0,1 is leftmost bin 1924 on second row, and so on). W/H specify the number 1925 of bins assigned to this VSC_PIPE in the horiz/vert 1926 dimension. 1927 </doc> 1928 <bitfield name="X" low="0" high="9" type="uint"/> 1929 <bitfield name="Y" low="10" high="19" type="uint"/> 1930 <bitfield name="W" low="20" high="25" type="uint"/> 1931 <bitfield name="H" low="26" high="31" type="uint"/> 1932 </reg32> 1933 </array> 1934 <!-- 1935 HW binning primitive & draw streams, which enable draws and primitives 1936 within a draw to be skipped in the main tile pass. See: 1937 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format 1938 1939 Compared to a5xx and earlier, we just program the address of the first 1940 stream and hw adds (pipe_num * VSC_*_STRM_PITCH) 1941 1942 LIMIT is set to PITCH - 64, to make room for a bit of overflow 1943 --> 1944 <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress" usage="cmd"/> 1945 <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH" usage="cmd"/> 1946 <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT" usage="cmd"/> 1947 <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress" usage="cmd"/> 1948 <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH" usage="cmd"/> 1949 <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT" usage="cmd"/> 1950 1951 <array offset="0x0c38" name="VSC_STATE" stride="1" length="32" usage="rp_blit"> 1952 <doc> 1953 Seems to be a bitmap of which tiles mapped to the VSC 1954 pipe contain geometry. 1955 1956 I suppose we can connect a maximum of 32 tiles to a 1957 single VSC pipe. 1958 </doc> 1959 <reg32 offset="0x0" name="REG"/> 1960 </array> 1961 1962 <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 1963 <doc> 1964 Has the size of data written to corresponding VSC_PRIM_STRM 1965 buffer. 1966 </doc> 1967 <reg32 offset="0x0" name="REG"/> 1968 </array> 1969 1970 <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 1971 <doc> 1972 Has the size of data written to corresponding VSC pipe, ie. 1973 same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI 1974 </doc> 1975 <reg32 offset="0x0" name="REG"/> 1976 </array> 1977 1978 <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/> 1979 1980 <reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/> 1981 <reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/> 1982 <!-- always 0x03200000 ? --> 1983 <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" usage="cmd"/> 1984 1985 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 --> 1986 <bitset name="a6xx_reg_xy" inline="yes"> 1987 <bitfield name="X" low="0" high="13" type="uint"/> 1988 <bitfield name="Y" low="16" high="29" type="uint"/> 1989 </bitset> 1990 1991 <reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit"> 1992 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/> 1993 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/> 1994 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/> 1995 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> 1996 <!-- controls near z clip behavior (set for vulkan) --> 1997 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/> 1998 <!-- guess based on a3xx and meaning of bits 8 and 9 1999 if the guess is right then this is related to point sprite clipping --> 2000 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/> 2001 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/> 2002 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/> 2003 </reg32> 2004 2005 <bitset name="a6xx_gras_xs_cl_cntl" inline="yes"> 2006 <bitfield name="CLIP_MASK" low="0" high="7"/> 2007 <bitfield name="CULL_MASK" low="8" high="15"/> 2008 </bitset> 2009 <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/> 2010 <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/> 2011 <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl" usage="rp_blit"/> 2012 <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint" usage="rp_blit"/> 2013 2014 <reg32 offset="0x8005" name="GRAS_CNTL" usage="rp_blit"> 2015 <!-- see also RB_RENDER_CONTROL0 --> 2016 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 2017 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 2018 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 2019 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 2020 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 2021 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 2022 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 2023 <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/> 2024 <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/> 2025 </reg32> 2026 <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit"> 2027 <bitfield name="HORZ" low="0" high="8" type="uint"/> 2028 <bitfield name="VERT" low="10" high="18" type="uint"/> 2029 </reg32> 2030 2031 <!-- Something connected to depth-stencil attachment size --> 2032 <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/> 2033 2034 <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/> 2035 2036 <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/> 2037 <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/> 2038 <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/> 2039 <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/> 2040 2041 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> --> 2042 2043 <!-- 0x8006-0x800f invalid --> 2044 <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16" usage="rp_blit"> 2045 <reg32 offset="0" name="XOFFSET" type="float"/> 2046 <reg32 offset="1" name="XSCALE" type="float"/> 2047 <reg32 offset="2" name="YOFFSET" type="float"/> 2048 <reg32 offset="3" name="YSCALE" type="float"/> 2049 <reg32 offset="4" name="ZOFFSET" type="float"/> 2050 <reg32 offset="5" name="ZSCALE" type="float"/> 2051 </array> 2052 <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16" usage="rp_blit"> 2053 <reg32 offset="0" name="MIN" type="float"/> 2054 <reg32 offset="1" name="MAX" type="float"/> 2055 </array> 2056 2057 <reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit"> 2058 <bitfield name="CULL_FRONT" pos="0" type="boolean"/> 2059 <bitfield name="CULL_BACK" pos="1" type="boolean"/> 2060 <bitfield name="FRONT_CW" pos="2" type="boolean"/> 2061 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/> 2062 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/> 2063 <bitfield name="UNK12" pos="12"/> 2064 <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/> 2065 <bitfield name="UNK15" low="15" high="16"/> 2066 <!-- 2067 On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have 2068 the ability to add the view index to either the RT array 2069 index or the viewport index, and it seems that 2070 MULTIVIEW_ENABLE doesn't do anything, instead we need to 2071 set at least one of RENDERTARGETINDEXINCR or 2072 VIEWPORTINDEXINCR to enable multiview. The blob still 2073 sets MULTIVIEW_ENABLE regardless. 2074 TODO: what about gen2 (a640)? 2075 --> 2076 <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/> 2077 <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/> 2078 <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/> 2079 <bitfield name="UNK20" low="20" high="22"/> 2080 </reg32> 2081 <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit"> 2082 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> 2083 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> 2084 </reg32> 2085 <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="rp_blit"/> 2086 <!-- 0x8093 invalid --> 2087 <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit"> 2088 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 2089 </reg32> 2090 <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/> 2091 <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/> 2092 <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/> 2093 <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 2094 <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit"> 2095 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 2096 <bitfield name="UNK3" pos="3"/> 2097 </reg32> 2098 2099 <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd"> 2100 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 2101 <bitfield name="SHIFTAMOUNT" low="1" high="2"/> 2102 <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/> 2103 <bitfield name="UNK4" low="4" high="5"/> 2104 </reg32> 2105 <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL"> 2106 <bitfield name="UNK0" pos="0" type="boolean"/> 2107 <bitfield name="LINELENGTHEN" pos="1" type="boolean"/> 2108 </reg32> 2109 2110 <bitset name="a6xx_gras_layer_cntl" inline="yes"> 2111 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/> 2112 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/> 2113 </bitset> 2114 <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/> 2115 <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/> 2116 <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl" usage="rp_blit"/> 2117 <!-- 0x809e/0x809f invalid --> 2118 2119 <enum name="a6xx_sequenced_thread_dist"> 2120 <value value="0x0" name="DIST_SCREEN_COORD"/> 2121 <value value="0x1" name="DIST_ALL_TO_RB0"/> 2122 </enum> 2123 2124 <enum name="a6xx_single_prim_mode"> 2125 <value value="0x0" name="NO_FLUSH"/> 2126 <doc> 2127 In addition to FLUSH_PER_OVERLAP, guarantee that UCHE 2128 and CCU don't get out of sync when fetching the previous 2129 value for the current pixel. With NO_FLUSH, there's the 2130 possibility that the flags for the current pixel are 2131 flushed before the data or vice-versa, leading to 2132 texture fetches via UCHE getting out of sync values. 2133 This mode should eliminate that. It's used in bypass 2134 mode for coherent blending 2135 (GL_KHR_blend_equation_advanced_coherent) as well as 2136 non-coherent blending. 2137 </doc> 2138 <value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/> 2139 <doc> 2140 Invalidate UCHE and wait for any pending work to finish 2141 if there was possibly an overlapping primitive prior to 2142 the current one. This is similar to a combination of 2143 GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and 2144 WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for 2145 coherent blending 2146 (GL_KHR_blend_equation_advanced_coherent). 2147 </doc> 2148 <value value="0x3" name="FLUSH_PER_OVERLAP"/> 2149 </enum> 2150 2151 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE --> 2152 <enum name="a6xx_raster_mode"> 2153 <value value="0x0" name="TYPE_TILED"/> 2154 <value value="0x1" name="TYPE_WRITER"/> 2155 </enum> 2156 2157 <!-- I'm guessing this is the same as a3xx --> 2158 <enum name="a6xx_raster_direction"> 2159 <value value="0x0" name="LR_TB"/> 2160 <value value="0x1" name="RL_TB"/> 2161 <value value="0x2" name="LR_BT"/> 2162 <value value="0x3" name="RB_BT"/> 2163 </enum> 2164 2165 <reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit"> 2166 <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/> 2167 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/> 2168 <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/> 2169 <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/> 2170 <bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/> 2171 <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set --> 2172 <bitfield name="UNK9" pos="9" type="boolean"/> 2173 <bitfield name="ROTATION" low="10" high="11" type="uint"/> 2174 <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/> 2175 </reg32> 2176 2177 <enum name="a6xx_render_mode"> 2178 <value value="0x0" name="RENDERING_PASS"/> 2179 <value value="0x1" name="BINNING_PASS"/> 2180 </enum> 2181 2182 <enum name="a6xx_buffers_location"> 2183 <value value="0" name="BUFFERS_IN_GMEM"/> 2184 <value value="3" name="BUFFERS_IN_SYSMEM"/> 2185 </enum> 2186 2187 <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL" usage="rp_blit"> 2188 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 2189 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 2190 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 2191 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 2192 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/> 2193 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/> 2194 <bitfield name="UNK27" pos="27"/> 2195 </reg32> 2196 2197 <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL" usage="rp_blit"> 2198 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 2199 <bitfield name="UNK2" pos="2"/> 2200 <bitfield name="UNK3" pos="3"/> 2201 </reg32> 2202 <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL" usage="rp_blit"> 2203 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 2204 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 2205 </reg32> 2206 2207 <bitset name="a6xx_sample_config" inline="yes"> 2208 <bitfield name="UNK0" pos="0"/> 2209 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/> 2210 </bitset> 2211 2212 <bitset name="a6xx_sample_locations" inline="yes"> 2213 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/> 2214 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/> 2215 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/> 2216 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/> 2217 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/> 2218 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/> 2219 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/> 2220 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/> 2221 </bitset> 2222 2223 <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/> 2224 <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/> 2225 <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/> 2226 2227 <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/> 2228 2229 <!-- 0x80a7-0x80ae invalid --> 2230 <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/> 2231 2232 <bitset name="a6xx_scissor_xy" inline="yes"> 2233 <bitfield name="X" low="0" high="15" type="uint"/> 2234 <bitfield name="Y" low="16" high="31" type="uint"/> 2235 </bitset> 2236 <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit"> 2237 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 2238 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 2239 </array> 2240 <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit"> 2241 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 2242 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 2243 </array> 2244 2245 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 2246 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 2247 2248 <!-- 0x80f4 - 0x80fa are used for VK_KHR_fragment_shading_rate --> 2249 <reg64 offset="0x80f4" name="GRAS_UNKNOWN_80F4" variants="A7XX-" usage="cmd"/> 2250 <reg64 offset="0x80f5" name="GRAS_UNKNOWN_80F5" variants="A7XX-" usage="cmd"/> 2251 <reg64 offset="0x80f6" name="GRAS_UNKNOWN_80F6" variants="A7XX-" usage="cmd"/> 2252 <reg64 offset="0x80f8" name="GRAS_UNKNOWN_80F8" variants="A7XX-" usage="cmd"/> 2253 <reg64 offset="0x80f9" name="GRAS_UNKNOWN_80F9" variants="A7XX-" usage="cmd"/> 2254 <reg64 offset="0x80fa" name="GRAS_UNKNOWN_80FA" variants="A7XX-" usage="cmd"/> 2255 2256 <enum name="a6xx_lrz_dir_status"> 2257 <value value="0x1" name="LRZ_DIR_LE"/> 2258 <value value="0x2" name="LRZ_DIR_GE"/> 2259 <value value="0x3" name="LRZ_DIR_INVALID"/> 2260 </enum> 2261 2262 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit"> 2263 <bitfield name="ENABLE" pos="0" type="boolean"/> 2264 <doc>LRZ write also disabled for blend/etc.</doc> 2265 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> 2266 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc> 2267 <bitfield name="GREATER" pos="2" type="boolean"/> 2268 <doc> 2269 Clears the LRZ block being touched to: 2270 - 0.0 if GREATER 2271 - 1.0 if LESS 2272 </doc> 2273 <bitfield name="FC_ENABLE" pos="3" type="boolean"/> 2274 <!-- set when depth-test + depth-write enabled --> 2275 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/> 2276 <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/> 2277 <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/> 2278 <doc> 2279 If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into 2280 buffer, in case of mismatched direction writes 0 (disables LRZ). 2281 </doc> 2282 <bitfield name="DIR_WRITE" pos="8" type="boolean"/> 2283 <doc> 2284 Disable LRZ based on previous direction and the current one. 2285 If DIR_WRITE is not enabled - there is no write to direction buffer. 2286 </doc> 2287 <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean"/> 2288 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/> 2289 </reg32> 2290 2291 <enum name="a6xx_fragcoord_sample_mode"> 2292 <value value="0" name="FRAGCOORD_CENTER"/> 2293 <value value="3" name="FRAGCOORD_SAMPLE"/> 2294 </enum> 2295 2296 <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit"> 2297 <bitfield name="SAMPLEID" pos="0" type="boolean"/> 2298 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/> 2299 </reg32> 2300 2301 <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUF_INFO_0" usage="rp_blit"> 2302 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2303 </reg32> 2304 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/> 2305 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit"> 2306 <!-- TODO: fix the shr fields --> 2307 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/> 2308 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/> 2309 </reg32> 2310 2311 <!-- 2312 The LRZ "fast clear" buffer is initialized to zero's by blob, and 2313 read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears 2314 to store 1b/block. It appears that '0' means block has original 2315 depth clear value, and '1' means that the corresponding block in 2316 LRZ has been modified. Ignoring alignment/padding, the size is 2317 given by the formula: 2318 2319 // calculate LRZ size from depth size: 2320 if (nr_samples == 4) { 2321 width *= 2; 2322 height *= 2; 2323 } else if (nr_samples == 2) { 2324 height *= 2; 2325 } 2326 2327 lrz_width = div_round_up(width, 8); 2328 lrz_heigh = div_round_up(height, 8); 2329 2330 // calculate # of blocks: 2331 nblocksx = div_round_up(lrz_width, 16); 2332 nblocksy = div_round_up(lrz_height, 4); 2333 2334 // fast-clear buffer is 1bit/block: 2335 fc_sz = div_round_up(nblocksx * nblocksy, 8); 2336 2337 In practice the blob seems to switch off FC_ENABLE once the size 2338 increases beyond 1 page. Not sure if that is an actual limit or 2339 not. 2340 --> 2341 <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/> 2342 <!-- 0x8108 invalid --> 2343 <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL" usage="rp_blit"> 2344 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 2345 </reg32> 2346 <!-- 2347 LRZ buffer represents a single array layer + mip level, and there is 2348 a single buffer per depth image. Thus to reuse LRZ between renderpasses 2349 it is necessary to track the depth view used in the past renderpass, which 2350 GRAS_LRZ_DEPTH_VIEW is for. 2351 GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_DEPTH_VIEW is equal to 2352 the value stored in the LRZ buffer, if not - LRZ is disabled. 2353 --> 2354 <reg32 offset="0x810a" name="GRAS_LRZ_DEPTH_VIEW" usage="cmd"> 2355 <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/> 2356 <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/> 2357 <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/> 2358 </reg32> 2359 2360 <reg32 offset="0x810b" name="GRAS_UNKNOWN_810B" variants="A7XX-" usage="cmd"/> 2361 2362 <!-- 0x810c-0x810f invalid --> 2363 2364 <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/> 2365 2366 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR --> 2367 <reg32 offset="0x8111" name="GRAS_LRZ_CLEAR_DEPTH_F32" type="float" variants="A7XX-"/> 2368 2369 <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"/> 2370 2371 <!-- Always written together and always equal 09510840 00000a62 --> 2372 <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/> 2373 <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/> 2374 2375 <!-- 0x8112-0x83ff invalid --> 2376 2377 <enum name="a6xx_rotation"> 2378 <value value="0x0" name="ROTATE_0"/> 2379 <value value="0x1" name="ROTATE_90"/> 2380 <value value="0x2" name="ROTATE_180"/> 2381 <value value="0x3" name="ROTATE_270"/> 2382 <value value="0x4" name="ROTATE_HFLIP"/> 2383 <value value="0x5" name="ROTATE_VFLIP"/> 2384 </enum> 2385 2386 <bitset name="a6xx_2d_blit_cntl" inline="yes"> 2387 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/> 2388 <bitfield name="OVERWRITEEN" pos="3" type="boolean"/> 2389 <bitfield name="UNK4" low="4" high="6"/> 2390 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/> 2391 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/> 2392 <bitfield name="SCISSOR" pos="16" type="boolean"/> 2393 <bitfield name="UNK17" low="17" high="18"/> 2394 <!-- required when blitting D24S8/D24X8 --> 2395 <bitfield name="D24S8" pos="19" type="boolean"/> 2396 <!-- some sort of channel mask, disabled channels are set to zero ? --> 2397 <bitfield name="MASK" low="20" high="23"/> 2398 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/> 2399 <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/> 2400 <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/> 2401 </bitset> 2402 2403 <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/> 2404 <!-- note: the low 8 bits for src coords are valid, probably fixed point 2405 it would be a bit weird though, since we subtract 1 from BR coords 2406 apparently signed, gallium driver uses negative coords and it works? 2407 --> 2408 <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int" usage="rp_blit"/> 2409 <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int" usage="rp_blit"/> 2410 <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int" usage="rp_blit"/> 2411 <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int" usage="rp_blit"/> 2412 <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy" usage="rp_blit"/> 2413 <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy" usage="rp_blit"/> 2414 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/> 2415 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/> 2416 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/> 2417 <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/> 2418 <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/> 2419 <!-- 0x840c-0x85ff invalid --> 2420 2421 <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> 2422 <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd"> 2423 <bitfield name="UNK7" pos="7" type="boolean"/> 2424 <bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/> 2425 </reg32> 2426 <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 2427 <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/> 2428 <array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/> 2429 <array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/> 2430 <array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/> 2431 2432 <!-- note 0x8620-0x87ff are not all invalid 2433 (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords) 2434 --> 2435 2436 <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> 2437 <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A6XX" usage="rp_blit"> 2438 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 2439 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 2440 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 2441 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 2442 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/> 2443 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/> 2444 </reg32> 2445 2446 <reg32 offset="0x8800" name="RB_BIN_CONTROL" variants="A7XX-" usage="rp_blit"> 2447 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 2448 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 2449 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 2450 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 2451 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26"/> 2452 </reg32> 2453 2454 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit"> 2455 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> 2456 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 2457 <!-- set during binning pass: --> 2458 <bitfield name="BINNING" pos="7" type="boolean"/> 2459 <bitfield name="UNK8" low="8" high="10"/> 2460 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 2461 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 2462 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 2463 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 2464 <!-- bit seems to be set whenever depth buffer enabled: --> 2465 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/> 2466 <!-- bitmask of MRTs using UBWC flag buffer: --> 2467 <bitfield name="FLAG_MRTS" low="16" high="23"/> 2468 </reg32> 2469 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 2470 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 2471 <!-- set during binning pass: --> 2472 <bitfield name="BINNING" pos="7" type="boolean"/> 2473 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 2474 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 2475 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 2476 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 2477 </reg32> 2478 <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 2479 <bitfield name="BINNING" pos="7" type="boolean"/> 2480 </reg32> 2481 2482 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit"> 2483 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 2484 <bitfield name="UNK2" pos="2"/> 2485 <bitfield name="UNK3" pos="3"/> 2486 </reg32> 2487 <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL" usage="rp_blit"> 2488 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 2489 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 2490 </reg32> 2491 2492 <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/> 2493 <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/> 2494 <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/> 2495 <!-- 0x8807-0x8808 invalid --> 2496 <!-- 2497 note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL 2498 name comes from kernel and is probably right) 2499 --> 2500 <reg32 offset="0x8809" name="RB_RENDER_CONTROL0" usage="rp_blit"> 2501 <!-- see also GRAS_CNTL --> 2502 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 2503 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 2504 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 2505 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 2506 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 2507 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 2508 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 2509 <bitfield name="UNK10" pos="10" type="boolean"/> 2510 </reg32> 2511 <reg32 offset="0x880a" name="RB_RENDER_CONTROL1" usage="rp_blit"> 2512 <!-- enable bits for various FS sysvalue regs: --> 2513 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/> 2514 <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/> 2515 <bitfield name="FACENESS" pos="2" type="boolean"/> 2516 <bitfield name="SAMPLEID" pos="3" type="boolean"/> 2517 <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/> 2518 <bitfield name="CENTERRHW" pos="6" type="boolean"/> 2519 <bitfield name="LINELENGTHEN" pos="7" type="boolean"/> 2520 <bitfield name="FOVEATION" pos="8" type="boolean"/> 2521 </reg32> 2522 2523 <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0" usage="rp_blit"> 2524 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 2525 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/> 2526 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/> 2527 <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/> 2528 </reg32> 2529 <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1" usage="rp_blit"> 2530 <bitfield name="MRT" low="0" high="3" type="uint"/> 2531 </reg32> 2532 <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS" usage="rp_blit"> 2533 <bitfield name="RT0" low="0" high="3"/> 2534 <bitfield name="RT1" low="4" high="7"/> 2535 <bitfield name="RT2" low="8" high="11"/> 2536 <bitfield name="RT3" low="12" high="15"/> 2537 <bitfield name="RT4" low="16" high="19"/> 2538 <bitfield name="RT5" low="20" high="23"/> 2539 <bitfield name="RT6" low="24" high="27"/> 2540 <bitfield name="RT7" low="28" high="31"/> 2541 </reg32> 2542 <reg32 offset="0x880e" name="RB_DITHER_CNTL" usage="cmd"> 2543 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> 2544 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> 2545 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> 2546 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> 2547 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> 2548 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> 2549 <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/> 2550 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> 2551 </reg32> 2552 <reg32 offset="0x880f" name="RB_SRGB_CNTL" usage="rp_blit"> 2553 <!-- Same as SP_SRGB_CNTL --> 2554 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 2555 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 2556 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 2557 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 2558 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 2559 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 2560 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 2561 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 2562 </reg32> 2563 2564 <reg32 offset="0x8810" name="RB_SAMPLE_CNTL" usage="rp_blit"> 2565 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 2566 </reg32> 2567 <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/> 2568 <reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/> 2569 <!-- 0x8813-0x8817 invalid --> 2570 <!-- always 0x0 ? --> 2571 <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/> 2572 <!-- 0x8819-0x881e all 32 bits --> 2573 <reg32 offset="0x8819" name="RB_UNKNOWN_8819" usage="cmd"/> 2574 <reg32 offset="0x881a" name="RB_UNKNOWN_881A" usage="cmd"/> 2575 <reg32 offset="0x881b" name="RB_UNKNOWN_881B" usage="cmd"/> 2576 <reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/> 2577 <reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/> 2578 <reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/> 2579 <!-- 0x881f invalid --> 2580 <array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit"> 2581 <reg32 offset="0x0" name="CONTROL"> 2582 <bitfield name="BLEND" pos="0" type="boolean"/> 2583 <bitfield name="BLEND2" pos="1" type="boolean"/> 2584 <bitfield name="ROP_ENABLE" pos="2" type="boolean"/> 2585 <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/> 2586 <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/> 2587 </reg32> 2588 <reg32 offset="0x1" name="BLEND_CONTROL"> 2589 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/> 2590 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/> 2591 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/> 2592 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/> 2593 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/> 2594 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/> 2595 </reg32> 2596 <reg32 offset="0x2" name="BUF_INFO" variants="A6XX"> 2597 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2598 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2599 <bitfield name="UNK10" pos="10"/> 2600 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> 2601 </reg32> 2602 <reg32 offset="0x2" name="BUF_INFO" variants="A7XX-"> 2603 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2604 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2605 <bitfield name="UNK10" pos="10"/> 2606 <bitfield name="LOSSLESSCOMPEN" pos="11" type="boolean"/> 2607 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> 2608 </reg32> 2609 <!-- 2610 at least in gmem, things seem to be aligned to pitch of 64.. 2611 maybe an artifact of tiled format used in gmem? 2612 --> 2613 <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/> 2614 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/> 2615 <!-- 2616 Compared to a5xx and before, we configure both a GMEM base and 2617 external base. Not sure if this is to facilitate GMEM save/ 2618 restore for context switch, or just to simplify state setup to 2619 not have to care about GMEM vs BYPASS mode. 2620 --> 2621 <!-- maybe something in low bits since alignment of 1 doesn't make sense? --> 2622 <reg64 offset="0x5" name="BASE" type="waddress" align="1"/> 2623 2624 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/> 2625 </array> 2626 2627 <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float" usage="rp_blit"/> 2628 <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float" usage="rp_blit"/> 2629 <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float" usage="rp_blit"/> 2630 <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float" usage="rp_blit"/> 2631 <reg32 offset="0x8864" name="RB_ALPHA_CONTROL" usage="cmd"> 2632 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> 2633 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> 2634 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> 2635 </reg32> 2636 <reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit"> 2637 <!-- per-mrt enable bit --> 2638 <bitfield name="ENABLE_BLEND" low="0" high="7"/> 2639 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> 2640 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 2641 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 2642 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/> 2643 <bitfield name="SAMPLE_MASK" low="16" high="31"/> 2644 </reg32> 2645 <!-- 0x8866-0x886f invalid --> 2646 <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" usage="rp_blit"> 2647 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 2648 </reg32> 2649 2650 <reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit"> 2651 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 2652 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/> 2653 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/> 2654 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> 2655 <doc> 2656 Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER 2657 also set when Z_BOUNDS_ENABLE is set 2658 </doc> 2659 <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/> 2660 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/> 2661 </reg32> 2662 <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" usage="rp_blit"> 2663 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 2664 </reg32> 2665 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: --> 2666 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" usage="rp_blit"> 2667 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 2668 <bitfield name="UNK3" low="3" high="4"/> 2669 </reg32> 2670 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO --> 2671 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 2672 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 2673 <bitfield name="UNK3" low="3" high="4"/> 2674 <bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/> 2675 <bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/> 2676 </reg32> 2677 2678 <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="rp_blit"/> 2679 <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="rp_blit"/> 2680 <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2681 <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/> 2682 2683 <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float" usage="rp_blit"/> 2684 <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float" usage="rp_blit"/> 2685 <!-- 0x887a-0x887f invalid --> 2686 <reg32 offset="0x8880" name="RB_STENCIL_CONTROL" usage="rp_blit"> 2687 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 2688 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> 2689 <!-- 2690 set for stencil operations that require read from stencil 2691 buffer, but not for example for stencil clear (which does 2692 not require read).. so guessing this is analogous to 2693 READ_DEST_ENABLE for color buffer.. 2694 --> 2695 <bitfield name="STENCIL_READ" pos="2" type="boolean"/> 2696 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/> 2697 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/> 2698 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/> 2699 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/> 2700 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/> 2701 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/> 2702 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> 2703 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> 2704 </reg32> 2705 <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit"> 2706 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 2707 </reg32> 2708 <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A6XX" usage="rp_blit"> 2709 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 2710 <bitfield name="UNK1" pos="1" type="boolean"/> 2711 </reg32> 2712 <reg32 offset="0x8881" name="RB_STENCIL_INFO" variants="A7XX-" usage="rp_blit"> 2713 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 2714 <bitfield name="UNK1" pos="1" type="boolean"/> 2715 <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/> 2716 </reg32> 2717 <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="rp_blit"/> 2718 <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="rp_blit"/> 2719 <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2720 <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/> 2721 <reg32 offset="0x8887" name="RB_STENCILREF" usage="rp_blit"> 2722 <bitfield name="REF" low="0" high="7"/> 2723 <bitfield name="BFREF" low="8" high="15"/> 2724 </reg32> 2725 <reg32 offset="0x8888" name="RB_STENCILMASK" usage="rp_blit"> 2726 <bitfield name="MASK" low="0" high="7"/> 2727 <bitfield name="BFMASK" low="8" high="15"/> 2728 </reg32> 2729 <reg32 offset="0x8889" name="RB_STENCILWRMASK" usage="rp_blit"> 2730 <bitfield name="WRMASK" low="0" high="7"/> 2731 <bitfield name="BFWRMASK" low="8" high="15"/> 2732 </reg32> 2733 <!-- 0x888a-0x888f invalid --> 2734 <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 2735 <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL" usage="cmd"> 2736 <bitfield name="DISABLE" pos="0" type="boolean"/> 2737 <bitfield name="COPY" pos="1" type="boolean"/> 2738 </reg32> 2739 <!-- 0x8892-0x8897 invalid --> 2740 <reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit"> 2741 <bitfield name="ENABLE" pos="0" type="boolean"/> 2742 </reg32> 2743 <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/> 2744 <!-- 0x8899-0x88bf invalid --> 2745 <!-- clamps depth value for depth test/write --> 2746 <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float" usage="rp_blit"/> 2747 <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float" usage="rp_blit"/> 2748 <!-- 0x88c2-0x88cf invalid--> 2749 <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0" usage="rp_blit"> 2750 <bitfield name="UNK0" low="0" high="12"/> 2751 <bitfield name="UNK16" low="16" high="26"/> 2752 </reg32> 2753 <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 2754 <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 2755 <!-- weird to duplicate other regs from same block?? --> 2756 <reg32 offset="0x88d3" name="RB_BIN_CONTROL2" usage="rp_blit"> 2757 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 2758 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 2759 </reg32> 2760 <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy" usage="rp_blit"/> 2761 <reg32 offset="0x88d5" name="RB_BLIT_GMEM_MSAA_CNTL" usage="rp_blit"> 2762 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 2763 </reg32> 2764 <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12" usage="rp_blit"/> 2765 <!-- s/DST_FORMAT/DST_INFO/ probably: --> 2766 <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO" usage="rp_blit"> 2767 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 2768 <bitfield name="FLAGS" pos="2" type="boolean"/> 2769 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 2770 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/> 2771 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/> 2772 <bitfield name="UNK15" pos="15" type="boolean"/> 2773 </reg32> 2774 <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64" usage="rp_blit"/> 2775 <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 2776 <!-- array-pitch is size of layer --> 2777 <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/> 2778 <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64" usage="rp_blit"/> 2779 <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH" usage="rp_blit"> 2780 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 2781 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 2782 </reg32> 2783 2784 <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0" usage="rp_blit"/> 2785 <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1" usage="rp_blit"/> 2786 <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2" usage="rp_blit"/> 2787 <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3" usage="rp_blit"/> 2788 2789 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: --> 2790 <reg32 offset="0x88e3" name="RB_BLIT_INFO" usage="rp_blit"> 2791 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? --> 2792 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? --> 2793 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging --> 2794 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? --> 2795 <doc> 2796 For clearing depth/stencil 2797 1 - depth 2798 2 - stencil 2799 3 - depth+stencil 2800 For clearing color buffer: 2801 then probably a component mask, I always see 0xf 2802 </doc> 2803 <bitfield name="CLEAR_MASK" low="4" high="7"/> 2804 <!-- set when this is the last resolve on a650+ --> 2805 <bitfield name="LAST" low="8" high="9"/> 2806 <!-- 2807 a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil. 2808 a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise. 2809 2810 We believe this is related to concurrent resolves 2811 --> 2812 <bitfield name="BUFFER_ID" low="12" high="15"/> 2813 </reg32> 2814 <reg32 offset="0x88e4" name="RB_UNKNOWN_88E4" variants="A7XX-" usage="rp_blit"> 2815 <!-- Value conditioned based on predicate, changed before blits --> 2816 <bitfield name="UNK0" pos="0" type="boolean"/> 2817 </reg32> 2818 2819 <enum name="a6xx_ccu_cache_size"> 2820 <value value="0x0" name="CCU_CACHE_SIZE_FULL"/> 2821 <value value="0x1" name="CCU_CACHE_SIZE_HALF"/> 2822 <value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/> 2823 <value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/> 2824 </enum> 2825 <reg32 offset="0x88e5" name="RB_CCU_CNTL2" variants="A7XX-" usage="cmd"> 2826 <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/> 2827 <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/> 2828 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> 2829 <!-- GMEM offset of CCU depth cache --> 2830 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/> 2831 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/> 2832 <!-- GMEM offset of CCU color cache 2833 for GMEM rendering, we set it to GMEM size minus the minimum 2834 CCU color cache size. CCU color cache will be needed in some 2835 resolve cases, and in those cases we need to reserve the end 2836 of GMEM for color cache. 2837 --> 2838 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 2839 </reg32> 2840 <!-- 0x88e6-0x88ef invalid --> 2841 <!-- always 0x0 ? --> 2842 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/> 2843 <!-- could be for separate stencil? (or may not be a flag buffer at all) --> 2844 <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/> 2845 <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH"> 2846 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 2847 <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/> 2848 </reg32> 2849 <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/> 2850 <!-- Connected to VK_EXT_fragment_density_map? --> 2851 <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/> 2852 <!-- 0x88f6-0x88ff invalid --> 2853 <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 2854 <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit"> 2855 <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/> 2856 <!-- TODO: actually part of array pitch --> 2857 <bitfield name="UNK8" low="8" high="10"/> 2858 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 2859 </reg32> 2860 <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8" usage="rp_blit"> 2861 <reg64 offset="0" name="ADDR" type="waddress" align="64"/> 2862 <reg32 offset="2" name="PITCH"> 2863 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 2864 <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/> 2865 </reg32> 2866 </array> 2867 <!-- 0x891b-0x8926 invalid --> 2868 <doc> 2869 RB_SAMPLE_COUNT_ADDR register is used up to (and including) a730. After that 2870 the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. 2871 </doc> 2872 <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16" usage="cmd"/> 2873 <!-- 0x8929-0x89ff invalid --> 2874 2875 <!-- TODO: there are some registers in the 0x8a00-0x8bff range --> 2876 2877 <!-- 2878 These show up in a6xx gen3+ but so far haven't found an example of 2879 blob writing non-zero: 2880 --> 2881 <reg32 offset="0x8a00" name="RB_UNKNOWN_8A00" variants="A6XX" usage="rp_blit"/> 2882 <reg32 offset="0x8a10" name="RB_UNKNOWN_8A10" variants="A6XX" usage="rp_blit"/> 2883 <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/> 2884 <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/> 2885 2886 <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl" usage="rp_blit"/> 2887 <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31" usage="rp_blit"/> 2888 2889 <bitset name="a6xx_2d_surf_info" inline="yes"> 2890 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2891 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 2892 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> 2893 <bitfield name="FLAGS" pos="12" type="boolean"/> 2894 <bitfield name="SRGB" pos="13" type="boolean"/> 2895 <!-- the rest is only for src --> 2896 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> 2897 <bitfield name="FILTER" pos="16" type="boolean"/> 2898 <bitfield name="UNK17" pos="17" type="boolean"/> 2899 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/> 2900 <bitfield name="UNK19" pos="19" type="boolean"/> 2901 <bitfield name="UNK20" pos="20" type="boolean"/> 2902 <bitfield name="UNK21" pos="21" type="boolean"/> 2903 <bitfield name="UNK22" pos="22" type="boolean"/> 2904 <bitfield name="UNK23" low="23" high="26"/> 2905 <bitfield name="UNK28" pos="28" type="boolean"/> 2906 </bitset> 2907 2908 <!-- 0x8c02-0x8c16 invalid --> 2909 <!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) --> 2910 <reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info" usage="rp_blit"/> 2911 <reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64" usage="rp_blit"/> 2912 <reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 2913 <!-- this is a guess but seems likely (for NV12/IYUV): --> 2914 <reg64 offset="0x8c1b" name="RB_2D_DST_PLANE1" type="waddress" align="64" usage="rp_blit"/> 2915 <reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 2916 <reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64" usage="rp_blit"/> 2917 2918 <reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64" usage="rp_blit"/> 2919 <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 2920 <!-- this is a guess but seems likely (for NV12 with UBWC): --> 2921 <reg64 offset="0x8c23" name="RB_2D_DST_FLAGS_PLANE" type="waddress" align="64" usage="rp_blit"/> 2922 <reg32 offset="0x8c25" name="RB_2D_DST_FLAGS_PLANE_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 2923 2924 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers --> 2925 <!-- unlike a5xx, these are per channel values rather than packed --> 2926 <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0" usage="rp_blit"/> 2927 <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1" usage="rp_blit"/> 2928 <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2" usage="rp_blit"/> 2929 <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3" usage="rp_blit"/> 2930 <!-- 0x8c34-0x8dff invalid --> 2931 2932 <!-- always 0x1 ? either doesn't exist for a650 or write-only: --> 2933 <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/> 2934 <!-- 0x8e00-0x8e03 invalid --> 2935 <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff --> 2936 <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 2937 <!-- 0x02080000 in GMEM, zero otherwise? --> 2938 <reg32 offset="0x8e06" name="RB_UNKNOWN_8E06" variants="A7XX-" usage="cmd"/> 2939 2940 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX"> 2941 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> 2942 <!-- concurrent resolves are apparently a 2-bit enum on a650+ --> 2943 <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/> 2944 <bitfield name="DEPTH_OFFSET_HI" pos="7" type="hex"/> 2945 <bitfield name="COLOR_OFFSET_HI" pos="9" type="hex"/> 2946 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> 2947 <!-- GMEM offset of CCU depth cache --> 2948 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/> 2949 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/> 2950 <!-- GMEM offset of CCU color cache 2951 for GMEM rendering, we set it to GMEM size minus the minimum 2952 CCU color cache size. CCU color cache will be needed in some 2953 resolve cases, and in those cases we need to reserve the end 2954 of GMEM for color cache. 2955 --> 2956 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 2957 <!--TODO: valid mask 0xfffffc1f --> 2958 </reg32> 2959 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-"> 2960 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> 2961 <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/> 2962 <!-- rest of the bits were moved to RB_CCU_CNTL2 --> 2963 </reg32> 2964 <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL"> 2965 <bitfield name="MODE" pos="0" type="boolean"/> 2966 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 2967 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 2968 <bitfield name="AMSBC" pos="4" type="boolean"/> 2969 <bitfield name="UPPER_BIT" pos="10" type="uint"/> 2970 <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/> 2971 <bitfield name="UNK12" low="12" high="13"/> 2972 </reg32> 2973 <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/> 2974 <!-- 0x8e09-0x8e0f invalid --> 2975 <array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/> 2976 <array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/> 2977 <!-- 0x8e1d-0x8e1f invalid --> 2978 <!-- 0x8e20-0x8e25 more perfcntr sel? --> 2979 <!-- 0x8e26-0x8e27 invalid --> 2980 <reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL"/> 2981 <!-- 0x8e29-0x8e2b invalid --> 2982 <array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/> 2983 <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/> 2984 <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/> 2985 <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/> 2986 <!-- 0x8e3e-0x8e4f invalid --> 2987 <!-- GMEM save/restore for preemption: --> 2988 <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE" pos="0" type="boolean"/> 2989 <!-- address for GMEM save/restore? --> 2990 <reg32 offset="0x8e51" name="RB_UNKNOWN_8E51" type="waddress" align="1"/> 2991 <!-- 0x8e53-0x8e7f invalid --> 2992 <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/> 2993 <!-- 0x8e80-0x8e83 are valid --> 2994 <!-- 0x8e84-0x90ff invalid --> 2995 2996 <!-- 0x9000-0x90ff invalid --> 2997 2998 <reg32 offset="0x9100" name="VPC_GS_PARAM" variants="A6XX" usage="rp_blit"> 2999 <bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/> 3000 </reg32> 3001 3002 <bitset name="a6xx_vpc_xs_clip_cntl" inline="yes"> 3003 <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/> 3004 <!-- there can be up to 8 total clip/cull distance outputs, 3005 but apparenly VPC can only deal with vec4, so when there are 3006 more than 4 outputs a second location needs to be programmed 3007 --> 3008 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/> 3009 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/> 3010 </bitset> 3011 <reg32 offset="0x9101" name="VPC_VS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 3012 <reg32 offset="0x9102" name="VPC_GS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 3013 <reg32 offset="0x9103" name="VPC_DS_CLIP_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 3014 3015 <reg32 offset="0x9311" name="VPC_VS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 3016 <reg32 offset="0x9312" name="VPC_GS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 3017 <reg32 offset="0x9313" name="VPC_DS_CLIP_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 3018 3019 <bitset name="a6xx_vpc_xs_layer_cntl" inline="yes"> 3020 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> 3021 <bitfield name="VIEWLOC" low="8" high="15" type="uint"/> 3022 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/> 3023 </bitset> 3024 3025 <reg32 offset="0x9104" name="VPC_VS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 3026 <reg32 offset="0x9105" name="VPC_GS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 3027 <reg32 offset="0x9106" name="VPC_DS_LAYER_CNTL" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 3028 3029 <reg32 offset="0x9314" name="VPC_VS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 3030 <reg32 offset="0x9315" name="VPC_GS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 3031 <reg32 offset="0x9316" name="VPC_DS_LAYER_CNTL_V2" type="a6xx_vpc_xs_layer_cntl" usage="rp_blit"/> 3032 3033 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit"> 3034 <!-- this mirrors PC_RASTER_CNTL::DISCARD, although it seems it's unused --> 3035 <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> 3036 <bitfield name="UNK2" pos="2" type="boolean"/> 3037 </reg32> 3038 <reg32 offset="0x9108" name="VPC_POLYGON_MODE" usage="rp_blit"> 3039 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 3040 </reg32> 3041 3042 <bitset name="a6xx_primitive_cntl_0" inline="yes"> 3043 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> 3044 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> 3045 <bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean"> 3046 <doc> 3047 Swaps TESS_CW_TRIS/TESS_CCW_TRIS, and also makes 3048 triangle fans and triangle strips use the D3D 3049 order instead of the OpenGL order. 3050 </doc> 3051 </bitfield> 3052 <bitfield name="UNK3" pos="3" type="boolean"/> 3053 </bitset> 3054 3055 <bitset name="a6xx_primitive_cntl_5" inline="yes"> 3056 <doc> 3057 geometry shader 3058 </doc> 3059 <!-- TODO: first 16 bits are valid so something is wrong or missing here --> 3060 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/> 3061 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/> 3062 <bitfield name="LINELENGTHEN" pos="15" type="boolean"/> 3063 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/> 3064 <bitfield name="UNK18" pos="18"/> 3065 </bitset> 3066 3067 <bitset name="a6xx_multiview_cntl" inline="yes"> 3068 <bitfield name="ENABLE" pos="0" type="boolean"/> 3069 <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean"> 3070 <doc> 3071 Multi-position output lets the last geometry 3072 stage shader write multiple copies of 3073 gl_Position. If disabled then the VS is run once 3074 for each view, and ViewID is passed as a 3075 register to the VS. 3076 </doc> 3077 </bitfield> 3078 <bitfield name="VIEWS" low="2" high="6" type="uint"/> 3079 </bitset> 3080 3081 <reg32 offset="0x9109" name="VPC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" variants="A7XX-" usage="rp_blit"/> 3082 <reg32 offset="0x910a" name="VPC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" variants="A7XX-" usage="rp_blit"/> 3083 <reg32 offset="0x910b" name="VPC_MULTIVIEW_MASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/> 3084 <reg32 offset="0x910c" name="VPC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" variants="A7XX-" usage="rp_blit"/> 3085 3086 <enum name="a6xx_varying_interp_mode"> 3087 <value value="0" name="INTERP_SMOOTH"/> 3088 <value value="1" name="INTERP_FLAT"/> 3089 <value value="2" name="INTERP_ZERO"/> 3090 <value value="3" name="INTERP_ONE"/> 3091 </enum> 3092 3093 <enum name="a6xx_varying_ps_repl_mode"> 3094 <value value="0" name="PS_REPL_NONE"/> 3095 <value value="1" name="PS_REPL_S"/> 3096 <value value="2" name="PS_REPL_T"/> 3097 <value value="3" name="PS_REPL_ONE_MINUS_T"/> 3098 </enum> 3099 3100 <!-- 0x9109-0x91ff invalid --> 3101 <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8" usage="rp_blit"> 3102 <doc>Packed array of a6xx_varying_interp_mode</doc> 3103 <reg32 offset="0x0" name="MODE"/> 3104 </array> 3105 <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8" usage="rp_blit"> 3106 <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 3107 <reg32 offset="0x0" name="MODE"/> 3108 </array> 3109 3110 <!-- always 0x0 --> 3111 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/> 3112 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/> 3113 3114 <array offset="0x9212" name="VPC_VAR" stride="1" length="4" usage="rp_blit"> 3115 <!-- one bit per varying component: --> 3116 <reg32 offset="0" name="DISABLE"/> 3117 </array> 3118 3119 <reg32 offset="0x9216" name="VPC_SO_CNTL" usage="rp_blit"> 3120 <!-- 3121 Choose which DWORD to write to. There is an array of 3122 (4 * 64) DWORD's, dumped in the devcoredump at 3123 HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a 3124 (VPC location, stream) pair like so: 3125 3126 location 0, stream 0 3127 location 2, stream 0 3128 ... 3129 location 126, stream 0 3130 location 0, stream 1 3131 location 2, stream 1 3132 ... 3133 location 126, stream 1 3134 location 0, stream 2 3135 ... 3136 3137 When EmitStreamVertex(N) happens, the HW goes to DWORD 3138 64 * N and then "executes" the next 64 DWORD's. 3139 3140 This field is auto-incremented when VPC_SO_PROG is 3141 written to. 3142 --> 3143 <bitfield name="ADDR" low="0" high="7" type="hex"/> 3144 <!-- clear all A_EN and B_EN bits for all DWORD's --> 3145 <bitfield name="RESET" pos="16" type="boolean"/> 3146 </reg32> 3147 <!-- special register, write multiple times to load SO program (not readable) --> 3148 <reg32 offset="0x9217" name="VPC_SO_PROG" usage="rp_blit"> 3149 <bitfield name="A_BUF" low="0" high="1" type="uint"/> 3150 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> 3151 <bitfield name="A_EN" pos="11" type="boolean"/> 3152 <bitfield name="B_BUF" low="12" high="13" type="uint"/> 3153 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> 3154 <bitfield name="B_EN" pos="23" type="boolean"/> 3155 </reg32> 3156 3157 <reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32" usage="cmd"/> 3158 3159 <array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd"> 3160 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 3161 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 3162 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> 3163 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/> 3164 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 3165 </array> 3166 3167 <reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT" usage="cmd"> 3168 <bitfield name="INVERT" pos="0" type="boolean"/> 3169 </reg32> 3170 <!-- 0x9237-0x92ff invalid --> 3171 <!-- always 0x0 ? --> 3172 <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/> 3173 3174 <bitset name="a6xx_vpc_xs_pack" inline="yes"> 3175 <doc> 3176 num of varyings plus four for gl_Position (plus one if gl_PointSize) 3177 plus # of transform-feedback (streamout) varyings if using the 3178 hw streamout (rather than stg instructions in shader) 3179 </doc> 3180 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 3181 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/> 3182 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/> 3183 <bitfield name="EXTRAPOS" low="24" high="27" type="uint"> 3184 <doc> 3185 The number of extra copies of POSITION, i.e. 3186 number of views minus one when multi-position 3187 output is enabled, otherwise 0. 3188 </doc> 3189 </bitfield> 3190 </bitset> 3191 <reg32 offset="0x9301" name="VPC_VS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/> 3192 <reg32 offset="0x9302" name="VPC_GS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/> 3193 <reg32 offset="0x9303" name="VPC_DS_PACK" type="a6xx_vpc_xs_pack" usage="rp_blit"/> 3194 3195 <reg32 offset="0x9304" name="VPC_CNTL_0" usage="rp_blit"> 3196 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> 3197 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> 3198 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/> 3199 <bitfield name="VARYING" pos="16" type="boolean"/> 3200 <bitfield name="VIEWIDLOC" low="24" high="31" type="uint"> 3201 <doc> 3202 This VPC location will be overwritten with 3203 ViewID when multiview is enabled. It's used when 3204 fragment shaders read ViewID. It's only 3205 strictly required for multi-position output, 3206 where the same VS invocation is used for all the 3207 views at once, but it can be used when multi-pos 3208 output is disabled too, to avoid having to pass 3209 ViewID through the VS. 3210 </doc> 3211 </bitfield> 3212 </reg32> 3213 3214 <reg32 offset="0x9305" name="VPC_SO_STREAM_CNTL" usage="rp_blit"> 3215 <!-- 3216 It's offset by 1, and 0 means "disabled" 3217 --> 3218 <bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/> 3219 <bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/> 3220 <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/> 3221 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/> 3222 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 3223 </reg32> 3224 <reg32 offset="0x9306" name="VPC_SO_DISABLE" usage="rp_blit"> 3225 <bitfield name="DISABLE" pos="0" type="boolean"/> 3226 </reg32> 3227 <reg32 offset="0x9307" name="VPC_POLYGON_MODE2" variants="A7XX-" usage="rp_blit"> 3228 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 3229 </reg32> 3230 <reg32 offset="0x9308" name="VPC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit"> 3231 <bitfield name="SIZE_GMEM" low="0" high="31"/> 3232 </reg32> 3233 <reg32 offset="0x9309" name="VPC_ATTR_BUF_BASE_GMEM" variants="A7XX-" usage="rp_blit"> 3234 <bitfield name="BASE_GMEM" low="0" high="31"/> 3235 </reg32> 3236 <reg32 offset="0x9b09" name="PC_ATTR_BUF_SIZE_GMEM" variants="A7XX-" usage="rp_blit"> 3237 <bitfield name="SIZE_GMEM" low="0" high="31"/> 3238 </reg32> 3239 3240 <!-- 0x9307-0x95ff invalid --> 3241 3242 <!-- TODO: 0x9600-0x97ff range --> 3243 <reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask --> 3244 <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd"/> 3245 <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? --> 3246 <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/> 3247 <array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/> 3248 <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/> 3249 <!-- 0x960a-0x9623 invalid --> 3250 <!-- TODO: regs from 0x9624-0x963a --> 3251 <!-- 0x963b-0x97ff invalid --> 3252 3253 <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint" usage="rp_blit"/> 3254 3255 <!-- always 0x0 ? --> 3256 <reg32 offset="0x9801" name="PC_HS_INPUT_SIZE" usage="rp_blit"> 3257 <bitfield name="SIZE" low="0" high="10" type="uint"/> 3258 <bitfield name="UNK13" pos="13"/> 3259 </reg32> 3260 3261 <reg32 offset="0x9802" name="PC_TESS_CNTL" usage="rp_blit"> 3262 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> 3263 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> 3264 </reg32> 3265 3266 <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/> 3267 <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/> 3268 3269 <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 3270 3271 <reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit"> 3272 <bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/> 3273 </reg32> 3274 3275 <!-- New in a6xx gen3+ --> 3276 <reg32 offset="0x9808" name="PC_SO_STREAM_CNTL" usage="rp_blit"> 3277 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 3278 </reg32> 3279 3280 <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL"> 3281 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 3282 </reg32> 3283 <!-- 0x980b-0x983f invalid --> 3284 3285 <!-- 0x9840 - 0x9842 are not readable --> 3286 <reg32 offset="0x9840" name="PC_DRAW_CMD"> 3287 <bitfield name="STATE_ID" low="0" high="7"/> 3288 </reg32> 3289 3290 <reg32 offset="0x9841" name="PC_DISPATCH_CMD"> 3291 <bitfield name="STATE_ID" low="0" high="7"/> 3292 </reg32> 3293 3294 <reg32 offset="0x9842" name="PC_EVENT_CMD"> 3295 <!-- I think only the low bit is actually used? --> 3296 <bitfield name="STATE_ID" low="16" high="23"/> 3297 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3298 </reg32> 3299 3300 <!-- 3301 0x9880 written in a lot of places by SQE, same value gets written 3302 to control reg 0x12a. Set by CP_SET_MARKER, so lets name it after 3303 that 3304 --> 3305 <reg32 offset="0x9880" name="PC_MARKER"/> 3306 3307 <!-- 0x9843-0x997f invalid --> 3308 3309 <reg32 offset="0x9981" name="PC_POLYGON_MODE" variants="A6XX" usage="rp_blit"> 3310 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 3311 </reg32> 3312 <reg32 offset="0x9809" name="PC_POLYGON_MODE" variants="A7XX-" usage="rp_blit"> 3313 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 3314 </reg32> 3315 3316 <reg32 offset="0x9980" name="PC_RASTER_CNTL" variants="A6XX" usage="rp_blit"> 3317 <!-- which stream to send to GRAS --> 3318 <bitfield name="STREAM" low="0" high="1" type="uint"/> 3319 <!-- discard primitives before rasterization --> 3320 <bitfield name="DISCARD" pos="2" type="boolean"/> 3321 </reg32> 3322 <!-- VPC_RASTER_CNTL --> 3323 <reg32 offset="0x9107" name="PC_RASTER_CNTL" variants="A7XX-" usage="rp_blit"> 3324 <!-- which stream to send to GRAS --> 3325 <bitfield name="STREAM" low="0" high="1" type="uint"/> 3326 <!-- discard primitives before rasterization --> 3327 <bitfield name="DISCARD" pos="2" type="boolean"/> 3328 </reg32> 3329 <reg32 offset="0x9317" name="PC_RASTER_CNTL_V2" variants="A7XX-" usage="rp_blit"> 3330 <!-- which stream to send to GRAS --> 3331 <bitfield name="STREAM" low="0" high="1" type="uint"/> 3332 <!-- discard primitives before rasterization --> 3333 <bitfield name="DISCARD" pos="2" type="boolean"/> 3334 </reg32> 3335 3336 <!-- Both are a750+. 3337 Probably needed to correctly overlap execution of several draws. 3338 --> 3339 <reg32 offset="0x9885" name="PC_TESS_PARAM_SIZE" variants="A7XX-" usage="cmd"/> 3340 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of 3341 this additional space is not known. 3342 --> 3343 <reg32 offset="0x9886" name="PC_TESS_FACTOR_SIZE" variants="A7XX-" usage="cmd"/> 3344 3345 <!-- 0x9982-0x9aff invalid --> 3346 3347 <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0" type="a6xx_primitive_cntl_0" usage="rp_blit"/> 3348 3349 <bitset name="a6xx_xs_out_cntl" inline="yes"> 3350 <doc> 3351 num of varyings plus four for gl_Position (plus one if gl_PointSize) 3352 plus # of transform-feedback (streamout) varyings if using the 3353 hw streamout (rather than stg instructions in shader) 3354 </doc> 3355 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 3356 <bitfield name="PSIZE" pos="8" type="boolean"/> 3357 <bitfield name="LAYER" pos="9" type="boolean"/> 3358 <bitfield name="VIEW" pos="10" type="boolean"/> 3359 <!-- note: PC_VS_OUT_CNTL doesn't have the PRIMITIVE_ID bit --> 3360 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> 3361 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/> 3362 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/> 3363 </bitset> 3364 3365 <reg32 offset="0x9b01" name="PC_VS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> 3366 <reg32 offset="0x9b02" name="PC_GS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> 3367 <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 3368 <reg32 offset="0x9b03" name="PC_HS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> 3369 <reg32 offset="0x9b04" name="PC_DS_OUT_CNTL" type="a6xx_xs_out_cntl" usage="rp_blit"/> 3370 3371 <reg32 offset="0x9b05" name="PC_PRIMITIVE_CNTL_5" type="a6xx_primitive_cntl_5" usage="rp_blit"/> 3372 3373 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit"> 3374 <doc> 3375 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC 3376 </doc> 3377 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/> 3378 </reg32> 3379 3380 <reg32 offset="0x9b07" name="PC_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/> 3381 <!-- mask of enabled views, doesn't exist on A630 --> 3382 <reg32 offset="0x9b08" name="PC_MULTIVIEW_MASK" type="hex" low="0" high="15" usage="rp_blit"/> 3383 <!-- 0x9b09-0x9bff invalid --> 3384 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> 3385 <!-- special register (but note first 8 bits can be written/read) --> 3386 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3387 <bitfield name="STATE_ID" low="8" high="15"/> 3388 </reg32> 3389 <!-- 0x9c01-0x9dff invalid --> 3390 <!-- TODO: 0x9e00-0xa000 range incomplete --> 3391 <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/> 3392 <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 3393 <reg64 offset="0x9e04" name="PC_DRAW_INDX_BASE"/> 3394 <reg32 offset="0x9e06" name="PC_DRAW_FIRST_INDX" type="uint"/> 3395 <reg32 offset="0x9e07" name="PC_DRAW_MAX_INDICES" type="uint"/> 3396 <reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" variants="A6XX" type="waddress" align="32" usage="cmd"/> 3397 <reg64 offset="0x9810" name="PC_TESSFACTOR_ADDR" variants="A7XX-" type="waddress" align="32" usage="cmd"/> 3398 3399 <reg32 offset="0x9e0b" name="PC_DRAW_INITIATOR" type="vgt_draw_initiator_a4xx"> 3400 <doc> 3401 Possibly not really "initiating" the draw but the layout is similar 3402 to VGT_DRAW_INITIATOR on older gens 3403 </doc> 3404 </reg32> 3405 <reg32 offset="0x9e0c" name="PC_DRAW_NUM_INSTANCES" type="uint"/> 3406 <reg32 offset="0x9e0d" name="PC_DRAW_NUM_INDICES" type="uint"/> 3407 3408 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> 3409 <reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL"> 3410 <bitfield name="UNK0" low="0" high="15"/> 3411 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 3412 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 3413 </reg32> 3414 <reg64 offset="0x9e12" name="PC_BIN_PRIM_STRM" type="waddress" align="32"/> 3415 <reg64 offset="0x9e14" name="PC_BIN_DRAW_STRM" type="waddress" align="32"/> 3416 3417 <reg32 offset="0x9e1c" name="PC_VISIBILITY_OVERRIDE"> 3418 <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> 3419 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 3420 </reg32> 3421 3422 <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/> 3423 3424 <array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/> 3425 <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/> 3426 3427 <!-- always 0x0 --> 3428 <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/> 3429 3430 <reg32 offset="0xa000" name="VFD_CONTROL_0" usage="rp_blit"> 3431 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/> 3432 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/> 3433 </reg32> 3434 <reg32 offset="0xa001" name="VFD_CONTROL_1" usage="rp_blit"> 3435 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/> 3436 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/> 3437 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/> 3438 <!-- only used for VS in non-multi-position-output case --> 3439 <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/> 3440 </reg32> 3441 <reg32 offset="0xa002" name="VFD_CONTROL_2" usage="rp_blit"> 3442 <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid"> 3443 <doc> 3444 This is the ID of the current patch within the 3445 subdraw, used to calculate the offset of the 3446 patch within the HS->DS buffers. When a draw is 3447 split into multiple subdraws then this differs 3448 from gl_PrimitiveID on the second, third, etc. 3449 subdraws. 3450 </doc> 3451 </bitfield> 3452 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/> 3453 </reg32> 3454 <reg32 offset="0xa003" name="VFD_CONTROL_3" usage="rp_blit"> 3455 <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/> 3456 <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/> 3457 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> 3458 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> 3459 </reg32> 3460 <reg32 offset="0xa004" name="VFD_CONTROL_4" usage="rp_blit"> 3461 <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/> 3462 </reg32> 3463 <reg32 offset="0xa005" name="VFD_CONTROL_5" usage="rp_blit"> 3464 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/> 3465 <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/> 3466 </reg32> 3467 <reg32 offset="0xa006" name="VFD_CONTROL_6" usage="rp_blit"> 3468 <!-- 3469 True if gl_PrimitiveID is read via the FS 3470 --> 3471 <bitfield name="PRIMID4PSEN" pos="0" type="boolean"/> 3472 </reg32> 3473 3474 <reg32 offset="0xa007" name="VFD_MODE_CNTL" usage="cmd"> 3475 <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/> 3476 </reg32> 3477 3478 <reg32 offset="0xa008" name="VFD_MULTIVIEW_CNTL" type="a6xx_multiview_cntl" usage="rp_blit"/> 3479 <reg32 offset="0xa009" name="VFD_ADD_OFFSET" usage="cmd"> 3480 <!-- add VFD_INDEX_OFFSET to REGID4VTX --> 3481 <bitfield name="VERTEX" pos="0" type="boolean"/> 3482 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST --> 3483 <bitfield name="INSTANCE" pos="1" type="boolean"/> 3484 </reg32> 3485 3486 <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/> 3487 <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/> 3488 <array offset="0xa010" name="VFD_FETCH" stride="4" length="32" usage="rp_blit"> 3489 <reg64 offset="0x0" name="BASE" type="address" align="1"/> 3490 <reg32 offset="0x2" name="SIZE" type="uint"/> 3491 <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/> 3492 </array> 3493 <array offset="0xa090" name="VFD_DECODE" stride="2" length="32" usage="rp_blit"> 3494 <reg32 offset="0x0" name="INSTR"> 3495 <!-- IDX and byte OFFSET into VFD_FETCH --> 3496 <bitfield name="IDX" low="0" high="4" type="uint"/> 3497 <bitfield name="OFFSET" low="5" high="16"/> 3498 <bitfield name="INSTANCED" pos="17" type="boolean"/> 3499 <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/> 3500 <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/> 3501 <bitfield name="UNK30" pos="30" type="boolean"/> 3502 <bitfield name="FLOAT" pos="31" type="boolean"/> 3503 </reg32> 3504 <reg32 offset="0x1" name="STEP_RATE" type="uint"/> 3505 </array> 3506 <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32" usage="rp_blit"> 3507 <reg32 offset="0x0" name="INSTR"> 3508 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/> 3509 <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/> 3510 </reg32> 3511 </array> 3512 3513 <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 3514 3515 <reg32 offset="0xa600" name="VFD_UNKNOWN_A600" variants="A7XX-" usage="cmd"/> 3516 3517 <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 3518 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/> 3519 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/> 3520 3521 <!-- 3522 Note: this seems to always be paired with another bit in another 3523 block. 3524 --> 3525 <enum name="a6xx_threadsize"> 3526 <value value="0" name="THREAD64"/> 3527 <value value="1" name="THREAD128"/> 3528 </enum> 3529 3530 <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes"> 3531 <!-- if set to SINGLE, only use 1 concurrent wave on each SP --> 3532 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> 3533 <!-- 3534 When b31 set we just see FULLREGFOOTPRINT set. The pattern of 3535 used registers is a bit odd too: 3536 - used (half): 0-15 68-179 (cnt=128, max=179) 3537 - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127> 3538 whereas we usually see a (mostly) contiguous range of regs used. But if 3539 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)), 3540 then: 3541 - used (merged): 0-191 (cnt=192, max=191) 3542 So I think if b31 is set, then the half precision registers overlap 3543 the full precision registers. (Which seems like a pretty sensible 3544 feature, actually I'm not sure when you *wouldn't* want to use that, 3545 since it gives register allocation more flexibility) 3546 --> 3547 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/> 3548 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/> 3549 <!-- could it be a low bit of branchstack? --> 3550 <bitfield name="UNK13" pos="13" type="boolean"/> 3551 <!-- seems to be nesting level for flow control:.. --> 3552 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/> 3553 </bitset> 3554 3555 <bitset name="a6xx_sp_xs_config" inline="yes"> 3556 <!-- 3557 Each of these are set if the given resource type is used 3558 with the Vulkan/bindless binding model. 3559 --> 3560 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/> 3561 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/> 3562 <bitfield name="BINDLESS_IBO" pos="2" type="boolean"/> 3563 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/> 3564 3565 <bitfield name="ENABLED" pos="8" type="boolean"/> 3566 <!-- 3567 number of textures and samplers.. these might be swapped, with GL I 3568 always see the same value for both. 3569 --> 3570 <bitfield name="NTEX" low="9" high="16" type="uint"/> 3571 <bitfield name="NSAMP" low="17" high="21" type="uint"/> 3572 <bitfield name="NIBO" low="22" high="28" type="uint"/> 3573 </bitset> 3574 3575 <bitset name="a6xx_sp_xs_prim_cntl" inline="yes"> 3576 <!-- # of VS outputs including pos/psize --> 3577 <bitfield name="OUT" low="0" high="5" type="uint"/> 3578 <!-- FLAGS_REGID only for GS --> 3579 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> 3580 </bitset> 3581 3582 <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 3583 <!-- 3584 This field actually controls all geometry stages. TCS, TES, and 3585 GS must have the same mergedregs setting as VS. 3586 --> 3587 <bitfield name="MERGEDREGS" pos="20" type="boolean"/> 3588 <!-- 3589 Creates a separate preamble-only thread? 3590 3591 Early preamble has the following limitations: 3592 - Only shared, a1, and consts regs could be used 3593 (accessing other regs would result in GPU fault); 3594 - No cat5/cat6, only stc/ldc variants are working; 3595 - Values writen to shared regs are not accessible by the rest 3596 of the shader; 3597 - Instructions before shps are also considered to be a part of 3598 early preamble; 3599 3600 Note, for all shaders from d3d11 games blob produced preambles 3601 compatible with early preamble mode. 3602 --> 3603 <bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/> 3604 </reg32> 3605 <!-- bitmask of true/false conditions for VS brac.N instructions, 3606 bit N corresponds to brac.N --> 3607 <reg32 offset="0xa801" name="SP_VS_BRANCH_COND" type="hex"/> 3608 <!-- # of VS outputs including pos/psize --> 3609 <reg32 offset="0xa802" name="SP_VS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/> 3610 <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16" usage="rp_blit"> 3611 <reg32 offset="0x0" name="REG"> 3612 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3613 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3614 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3615 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3616 </reg32> 3617 </array> 3618 <!-- 3619 Starting with a5xx, position/psize outputs from shader end up in the 3620 SP_VS_OUT map, with highest OUTLOCn position. (Generally they are 3621 the last entries too, except when gl_PointCoord is used, blob inserts 3622 an extra varying after, but with a lower OUTLOC position. If present, 3623 psize is last, preceded by position. 3624 --> 3625 <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8" usage="rp_blit"> 3626 <reg32 offset="0x0" name="REG"> 3627 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3628 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3629 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3630 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3631 </reg32> 3632 </array> 3633 3634 <bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes"> 3635 <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9"> 3636 <doc>The size of memory that ldp/stp can address.</doc> 3637 </bitfield> 3638 <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31"> 3639 <doc> 3640 Seems to be the same as a3xx. The maximum stack 3641 size in units of 4 calls, so a call depth of 7 3642 would result in a value of 2. 3643 TODO: What's the actual size per call, i.e. the 3644 size of the PC? a3xx docs say it's 16 bits 3645 there, but the length register now takes 28 bits 3646 so it's probably been bumped to 32 bits. 3647 </doc> 3648 </bitfield> 3649 </bitset> 3650 3651 <bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes"> 3652 <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/> 3653 <bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean"> 3654 <doc> 3655 There are four indices used to compute the 3656 private memory location for an access: 3657 3658 - stp/ldp offset 3659 - fiber id 3660 - wavefront id (a swizzled version of what "getwid" returns) 3661 - SP ID (the same as what "getspid" returns) 3662 3663 The stride for the SP ID is always set by 3664 TOTALPVTMEMSIZE. In the per-wave layout, the 3665 indices are used in this order: 3666 3667 - offset % 4 (offset within dword) 3668 - fiber id 3669 - offset / 4 3670 - wavefront id 3671 - SP ID 3672 3673 and the stride for the wavefront ID is 3674 MEMSIZEPERITEM, multiplied by 128 (fibers per 3675 wavefront). In the per-fiber layout, the indices 3676 are used in this order: 3677 3678 - offset 3679 - fiber id % 4 3680 - wavefront id 3681 - fiber id / 4 3682 - SP ID 3683 3684 and the stride for the fiber id/wavefront id 3685 combo is MEMSIZEPERITEM. 3686 3687 Note: Accesses of more than 1 dword do not work 3688 with per-fiber layout. The blob will fall back 3689 to per-wave instead. 3690 </doc> 3691 </bitfield> 3692 </bitset> 3693 3694 <bitset name="a6xx_sp_xs_pvt_mem_hw_stack_offset" inline="yes"> 3695 <doc> 3696 This seems to be be the equivalent of HWSTACKOFFSET in 3697 a3xx. The ldp/stp offset formula above isn't affected by 3698 HWSTACKSIZEPERTHREAD at all, so the HW return address 3699 stack seems to be after all the normal per-SP private 3700 memory. 3701 </doc> 3702 <bitfield name="OFFSET" low="0" high="18" shr="11"/> 3703 </bitset> 3704 3705 <reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 3706 <reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32" usage="rp_blit"/> 3707 <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3708 <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 3709 <reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3710 <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 3711 <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3712 <reg32 offset="0xa824" name="SP_VS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 3713 <reg32 offset="0xa825" name="SP_VS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 3714 <reg32 offset="0xa82d" name="SP_VS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 3715 3716 <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 3717 <!-- There is no mergedregs bit, that comes from the VS. --> 3718 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3719 </reg32> 3720 <!-- 3721 Total size of local storage in dwords divided by the wave size. 3722 The maximum value is 64. With the wave size being always 64 for HS, 3723 the maximum size of local storage should be: 3724 64 (wavesize) * 64 (SP_HS_WAVE_INPUT_SIZE) * 4 = 16k 3725 --> 3726 <reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint" usage="rp_blit"/> 3727 <reg32 offset="0xa832" name="SP_HS_BRANCH_COND" type="hex" usage="rp_blit"/> 3728 3729 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3730 <reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 3731 <reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32" usage="rp_blit"/> 3732 <reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3733 <reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 3734 <reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3735 <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 3736 <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3737 <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 3738 <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 3739 <reg32 offset="0xa82f" name="SP_HS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 3740 3741 <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 3742 <!-- There is no mergedregs bit, that comes from the VS. --> 3743 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3744 </reg32> 3745 <reg32 offset="0xa841" name="SP_DS_BRANCH_COND" type="hex"/> 3746 3747 <!-- TODO: exact same layout as 0xa802-0xa81a --> 3748 <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/> 3749 <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16" usage="rp_blit"> 3750 <reg32 offset="0x0" name="REG"> 3751 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3752 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3753 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3754 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3755 </reg32> 3756 </array> 3757 <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8" usage="rp_blit"> 3758 <reg32 offset="0x0" name="REG"> 3759 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3760 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3761 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3762 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3763 </reg32> 3764 </array> 3765 3766 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3767 <reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 3768 <reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32" usage="rp_blit"/> 3769 <reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3770 <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 3771 <reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3772 <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 3773 <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3774 <reg32 offset="0xa864" name="SP_DS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 3775 <reg32 offset="0xa865" name="SP_DS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 3776 <reg32 offset="0xa868" name="SP_DS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 3777 3778 <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 3779 <!-- There is no mergedregs bit, that comes from the VS. --> 3780 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 3781 </reg32> 3782 <reg32 offset="0xa871" name="SP_GS_PRIM_SIZE" low="0" high="7" type="uint" usage="rp_blit"> 3783 <doc> 3784 Normally the size of the output of the last stage in 3785 dwords. It should be programmed as follows: 3786 3787 size less than 63 - size 3788 size of 63 (?) or 64 - 63 3789 size greater than 64 - 64 3790 3791 What to program when the size is 61-63 is a guess, but 3792 both the blob and ir3 align the size to 4 dword's so it 3793 doesn't matter in practice. 3794 </doc> 3795 </reg32> 3796 <reg32 offset="0xa872" name="SP_GS_BRANCH_COND" type="hex" usage="rp_blit"/> 3797 3798 <!-- TODO: exact same layout as 0xa802-0xa81a --> 3799 <reg32 offset="0xa873" name="SP_GS_PRIMITIVE_CNTL" type="a6xx_sp_xs_prim_cntl" usage="rp_blit"/> 3800 <array offset="0xa874" name="SP_GS_OUT" stride="1" length="16" usage="rp_blit"> 3801 <reg32 offset="0x0" name="REG"> 3802 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 3803 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 3804 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 3805 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 3806 </reg32> 3807 </array> 3808 3809 <array offset="0xa884" name="SP_GS_VPC_DST" stride="1" length="8" usage="rp_blit"> 3810 <reg32 offset="0x0" name="REG"> 3811 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 3812 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 3813 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 3814 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 3815 </reg32> 3816 </array> 3817 3818 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 3819 <reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 3820 <reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32" usage="rp_blit"/> 3821 <reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3822 <reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 3823 <reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3824 <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 3825 <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3826 <reg32 offset="0xa895" name="SP_GS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 3827 <reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 3828 <reg32 offset="0xa899" name="SP_GS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 3829 3830 <reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16" usage="cmd"/> 3831 <reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16" usage="cmd"/> 3832 <reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16" usage="cmd"/> 3833 <reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16" usage="cmd"/> 3834 <reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64" usage="cmd"/> 3835 <reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64" usage="cmd"/> 3836 <reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64" usage="cmd"/> 3837 <reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64" usage="cmd"/> 3838 3839 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 --> 3840 3841 <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="rp_blit"> 3842 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 3843 <bitfield name="UNK21" pos="21" type="boolean"/> 3844 <bitfield name="VARYING" pos="22" type="boolean"/> 3845 <bitfield name="LODPIXMASK" pos="23" type="boolean"> 3846 <doc> 3847 Enable ALL helper invocations in a quad. Necessary for 3848 fine derivatives and quad subgroup ops. 3849 </doc> 3850 </bitfield> 3851 <!-- note: vk blob uses bit24 --> 3852 <bitfield name="UNK24" pos="24" type="boolean"/> 3853 <bitfield name="UNK25" pos="25" type="boolean"/> 3854 <bitfield name="PIXLODENABLE" pos="26" type="boolean"> 3855 <doc> 3856 Enable helper invocations. Enables 3 out of 4 fragments, 3857 because the coarse derivatives only use half of the quad 3858 and so one pixel's value is always unused. 3859 </doc> 3860 </bitfield> 3861 <bitfield name="UNK27" pos="27" type="boolean"/> 3862 <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/> 3863 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 3864 </reg32> 3865 <reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex"/> 3866 <reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="rp_blit"/> 3867 <reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32" usage="rp_blit"/> 3868 <reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 3869 <reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32" usage="rp_blit"/> 3870 <reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 3871 3872 <reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit"> 3873 <!-- per-mrt enable bit --> 3874 <bitfield name="ENABLE_BLEND" low="0" high="7"/> 3875 <bitfield name="UNK8" pos="8" type="boolean"/> 3876 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 3877 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 3878 </reg32> 3879 <reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit"> 3880 <!-- Same as RB_SRGB_CNTL --> 3881 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 3882 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 3883 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 3884 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 3885 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 3886 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 3887 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 3888 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 3889 </reg32> 3890 <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS" usage="rp_blit"> 3891 <bitfield name="RT0" low="0" high="3"/> 3892 <bitfield name="RT1" low="4" high="7"/> 3893 <bitfield name="RT2" low="8" high="11"/> 3894 <bitfield name="RT3" low="12" high="15"/> 3895 <bitfield name="RT4" low="16" high="19"/> 3896 <bitfield name="RT5" low="20" high="23"/> 3897 <bitfield name="RT6" low="24" high="27"/> 3898 <bitfield name="RT7" low="28" high="31"/> 3899 </reg32> 3900 <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0" usage="rp_blit"> 3901 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 3902 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> 3903 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/> 3904 <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/> 3905 </reg32> 3906 <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1" usage="rp_blit"> 3907 <bitfield name="MRT" low="0" high="3" type="uint"/> 3908 </reg32> 3909 3910 <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8" usage="rp_blit"> 3911 <doc>per MRT</doc> 3912 <reg32 offset="0x0" name="REG"> 3913 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> 3914 <bitfield name="HALF_PRECISION" pos="8" type="boolean"/> 3915 </reg32> 3916 </array> 3917 3918 <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8" usage="rp_blit"> 3919 <reg32 offset="0" name="REG"> 3920 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 3921 <bitfield name="COLOR_SINT" pos="8" type="boolean"/> 3922 <bitfield name="COLOR_UINT" pos="9" type="boolean"/> 3923 <bitfield name="UNK10" pos="10" type="boolean"/> 3924 </reg32> 3925 </array> 3926 3927 <reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL" usage="rp_blit"> 3928 <bitfield name="COUNT" low="0" high="2" type="uint"/> 3929 <bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/> 3930 <doc> 3931 Similar to "(eq)" flag but disables helper invocations 3932 after the texture prefetch. 3933 </doc> 3934 <bitfield name="ENDOFQUAD" pos="4" type="boolean" /> 3935 <doc> 3936 Bypass writing to regs and overwrite output with color from 3937 CONSTSLOTID const regs. 3938 </doc> 3939 <bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/> 3940 <bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/> 3941 <!-- Blob never uses it --> 3942 <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/> 3943 </reg32> 3944 <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A6XX" usage="rp_blit"> 3945 <reg32 offset="0" name="CMD" variants="A6XX"> 3946 <bitfield name="SRC" low="0" high="6" type="uint"/> 3947 <bitfield name="SAMP_ID" low="7" high="10" type="uint"/> 3948 <bitfield name="TEX_ID" low="11" high="15" type="uint"/> 3949 <bitfield name="DST" low="16" high="21" type="a3xx_regid"/> 3950 <bitfield name="WRMASK" low="22" high="25" type="hex"/> 3951 <bitfield name="HALF" pos="26" type="boolean"/> 3952 <doc>Results in color being zero</doc> 3953 <bitfield name="UNK27" pos="27" type="boolean"/> 3954 <bitfield name="BINDLESS" pos="28" type="boolean"/> 3955 <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/> 3956 </reg32> 3957 </array> 3958 <array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4" variants="A7XX-" usage="rp_blit"> 3959 <reg32 offset="0" name="CMD" variants="A7XX-"> 3960 <bitfield name="SRC" low="0" high="6" type="uint"/> 3961 <bitfield name="SAMP_ID" low="7" high="9" type="uint"/> 3962 <bitfield name="TEX_ID" low="10" high="12" type="uint"/> 3963 <bitfield name="DST" low="13" high="18" type="a3xx_regid"/> 3964 <bitfield name="WRMASK" low="19" high="22" type="hex"/> 3965 <bitfield name="HALF" pos="23" type="boolean"/> 3966 <bitfield name="BINDLESS" pos="25" type="boolean"/> 3967 <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/> 3968 </reg32> 3969 </array> 3970 <array offset="0xa9a3" name="SP_FS_BINDLESS_PREFETCH" stride="1" length="4" usage="rp_blit"> 3971 <reg32 offset="0" name="CMD"> 3972 <bitfield name="SAMP_ID" low="0" high="15" type="uint"/> 3973 <bitfield name="TEX_ID" low="16" high="31" type="uint"/> 3974 </reg32> 3975 </array> 3976 <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" low="0" high="7" type="uint" usage="rp_blit"/> 3977 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? --> 3978 <reg32 offset="0xa9a9" name="SP_FS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="rp_blit"/> 3979 3980 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS --> 3981 3982 3983 3984 3985 <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0" usage="cmd"> 3986 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 3987 <!-- seems to make SP use less concurrent threads when possible? --> 3988 <bitfield name="UNK21" pos="21" type="boolean"/> 3989 <!-- has a small impact on performance, not clear what it does --> 3990 <bitfield name="UNK22" pos="22" type="boolean"/> 3991 <bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/> 3992 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 3993 </reg32> 3994 3995 <!-- set for compute shaders --> 3996 <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" usage="cmd"> 3997 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"> 3998 <doc> 3999 If 0 - all 32k of shared storage is enabled, otherwise 4000 (SHARED_SIZE + 1) * 1k is enabled. 4001 The ldl/stl offset seems to be rewritten to 0 when it is beyond 4002 this limit. This is different from ldlw/stlw, which wraps at 4003 64k (and has 36k of storage on A640 - reads between 36k-64k 4004 always return 0) 4005 </doc> 4006 </bitfield> 4007 <bitfield name="UNK5" pos="5" type="boolean"/> 4008 <!-- always 1 ? --> 4009 <bitfield name="UNK6" pos="6" type="boolean"/> 4010 </reg32> 4011 <reg32 offset="0xa9b2" name="SP_CS_BRANCH_COND" type="hex" usage="cmd"/> 4012 <reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint" usage="cmd"/> 4013 <reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32" usage="cmd"/> 4014 <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/> 4015 <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32" usage="cmd"/> 4016 <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/> 4017 <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" low="0" high="7" type="uint" usage="cmd"/> 4018 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/> 4019 <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" low="0" high="27" type="uint" usage="cmd"/> 4020 <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_HW_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_hw_stack_offset" usage="cmd"/> 4021 <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/> 4022 <reg32 offset="0xa9c5" name="SP_CS_VGPR_CONFIG" variants="A7XX-" usage="cmd"/> 4023 4024 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_0 --> 4025 <reg32 offset="0xa9c2" name="SP_CS_CNTL_0" usage="cmd"> 4026 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 4027 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 4028 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 4029 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 4030 </reg32> 4031 <!-- new in a6xx gen4, matches HLSQ_CS_CNTL_1 --> 4032 <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A6XX" usage="cmd"> 4033 <!-- gl_LocalInvocationIndex --> 4034 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4035 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 4036 one of those 6 "SP cores" --> 4037 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 4038 <!-- Must match SP_CS_CTRL --> 4039 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 4040 <!-- 1 thread per wave (ignored if bit9 set) --> 4041 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 4042 </reg32> 4043 4044 <reg32 offset="0xa9c3" name="SP_CS_CNTL_1" variants="A7XX-" usage="cmd"> 4045 <!-- gl_LocalInvocationIndex --> 4046 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4047 <!-- Must match SP_CS_CTRL --> 4048 <bitfield name="THREADSIZE" pos="8" type="a6xx_threadsize"/> 4049 <!-- 1 thread per wave (would hang if THREAD128 is also set) --> 4050 <bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/> 4051 4052 <!-- Affects getone. If enabled, getone sometimes executed 1? less times 4053 than there are subgroups. 4054 --> 4055 <bitfield name="UNK15" pos="15" type="boolean"/> 4056 </reg32> 4057 4058 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 --> 4059 4060 <reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16" usage="rp_blit"/> 4061 <reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16" usage="cmd"/> 4062 <reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64" usage="rp_blit"/> 4063 <reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64" usage="cmd"/> 4064 4065 <enum name="a6xx_bindless_descriptor_size"> 4066 <doc> 4067 This can alternatively be interpreted as a pitch shift, ie, the 4068 descriptor size is 2 << N dwords 4069 </doc> 4070 <value value="1" name="BINDLESS_DESCRIPTOR_16B"/> 4071 <value value="3" name="BINDLESS_DESCRIPTOR_64B"/> 4072 </enum> 4073 4074 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd"> 4075 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> 4076 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4077 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4078 </reg64> 4079 </array> 4080 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cmd"> 4081 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> 4082 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4083 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4084 </reg64> 4085 </array> 4086 4087 <!-- 4088 IBO state for compute shader: 4089 --> 4090 <reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/> 4091 <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" low="0" high="6" type="uint"/> 4092 4093 <!-- Correlated with avgs/uvgs usage in FS --> 4094 <reg32 offset="0xaa01" name="SP_FS_VGPR_CONFIG" type="uint" variants="A7XX-" usage="cmd"/> 4095 4096 <reg32 offset="0xaa02" name="SP_PS_ALIASED_COMPONENTS_CONTROL" variants="A7XX-" usage="cmd"> 4097 <bitfield name="ENABLED" pos="0" type="boolean"/> 4098 </reg32> 4099 <reg32 offset="0xaa03" name="SP_PS_ALIASED_COMPONENTS" variants="A7XX-" usage="cmd"> 4100 <doc> 4101 Specify for which components the output color should be read 4102 from alias, e.g. for: 4103 4104 alias.1.b32.0 r3.x, c8.x 4105 alias.1.b32.0 r2.x, c4.x 4106 alias.1.b32.0 r1.x, c4.x 4107 alias.1.b32.0 r0.x, c0.x 4108 4109 the SP_PS_ALIASED_COMPONENTS would be 0x00001111 4110 </doc> 4111 4112 <bitfield name="RT0" low="0" high="3"/> 4113 <bitfield name="RT1" low="4" high="7"/> 4114 <bitfield name="RT2" low="8" high="11"/> 4115 <bitfield name="RT3" low="12" high="15"/> 4116 <bitfield name="RT4" low="16" high="19"/> 4117 <bitfield name="RT5" low="20" high="23"/> 4118 <bitfield name="RT6" low="24" high="27"/> 4119 <bitfield name="RT7" low="28" high="31"/> 4120 </reg32> 4121 4122 <reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/> 4123 4124 <!-- 4125 This enum is probably similar in purpose to SNORMMODE on a3xx, 4126 minus the snorm stuff, i.e. it controls what happens with an 4127 out-of-bounds isam/isamm. GL and Vulkan robustness require us to 4128 return 0 on out-of-bound textureFetch(). 4129 --> 4130 <enum name="a6xx_isam_mode"> 4131 <value value="0x1" name="ISAMMODE_CL"/> 4132 <value value="0x2" name="ISAMMODE_GL"/> 4133 </enum> 4134 4135 <reg32 offset="0xab00" name="SP_MODE_CONTROL" usage="rp_blit"> 4136 <!-- 4137 When set, half register loads from the constant file will 4138 load a 32-bit value (so hc0.y loads the same value as c0.y) 4139 and implicitly convert it to 16b (f2f16, or u2u16, based on 4140 operand type). When unset, half register loads from the 4141 constant file will load 16 bits from the packed constant 4142 file (so hc0.y loads the top 16 bits of the value of c0.x) 4143 --> 4144 <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/> 4145 <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/> 4146 <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS --> 4147 </reg32> 4148 4149 <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/> 4150 <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/> 4151 4152 <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 4153 <reg32 offset="0xab05" name="SP_FS_INSTRLEN" low="0" high="27" type="uint" usage="rp_blit"/> 4154 4155 <array offset="0xab10" name="SP_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> 4156 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> 4157 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4158 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4159 </reg64> 4160 </array> 4161 <array offset="0xab0a" name="SP_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit"> 4162 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> 4163 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4164 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4165 </reg64> 4166 </array> 4167 4168 <!-- 4169 Combined IBO state for 3d pipe, used for Image and SSBO write/atomic 4170 instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders. 4171 --> 4172 <reg64 offset="0xab1a" name="SP_IBO" type="address" align="16" usage="cmd"/> 4173 <reg32 offset="0xab20" name="SP_IBO_COUNT" low="0" high="6" type="uint" usage="cmd"/> 4174 4175 <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/> 4176 4177 <bitset name="a6xx_sp_2d_dst_format" inline="yes"> 4178 <bitfield name="NORM" pos="0" type="boolean"/> 4179 <bitfield name="SINT" pos="1" type="boolean"/> 4180 <bitfield name="UINT" pos="2" type="boolean"/> 4181 <!-- looks like HW only cares about the base type of this format, 4182 which matches the ifmt? --> 4183 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/> 4184 <!-- set when ifmt is R2D_UNORM8_SRGB --> 4185 <bitfield name="SRGB" pos="11" type="boolean"/> 4186 <!-- some sort of channel mask, not sure what it is for --> 4187 <bitfield name="MASK" low="12" high="15"/> 4188 </bitset> 4189 4190 <reg32 offset="0xacc0" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A6XX" usage="rp_blit"/> 4191 <reg32 offset="0xa9bf" name="SP_2D_DST_FORMAT" type="a6xx_sp_2d_dst_format" variants="A7XX-" usage="rp_blit"/> 4192 4193 <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/> 4194 <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 4195 <reg32 offset="0xae02" name="SP_NC_MODE_CNTL"> 4196 <!-- TODO: valid bits 0x3c3f, see kernel --> 4197 </reg32> 4198 <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/> 4199 <reg32 offset="0xae04" name="SP_FLOAT_CNTL" usage="cmd"> 4200 <bitfield name="F16_NO_INF" pos="3" type="boolean"/> 4201 </reg32> 4202 4203 <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/> 4204 <reg32 offset="0xae08" name="SP_UNKNOWN_AE08" variants="A7XX-" usage="cmd"/> 4205 <reg32 offset="0xae09" name="SP_UNKNOWN_AE09" variants="A7XX-" usage="cmd"/> 4206 <reg32 offset="0xae0a" name="SP_UNKNOWN_AE0A" variants="A7XX-" usage="cmd"/> 4207 4208 <reg32 offset="0xae0f" name="SP_PERFCTR_ENABLE" usage="cmd"> 4209 <!-- some perfcntrs are affected by a per-stage enable bit 4210 (PERF_SP_ALU_WORKING_CYCLES for example) 4211 TODO: verify position of HS/DS/GS bits --> 4212 <bitfield name="VS" pos="0" type="boolean"/> 4213 <bitfield name="HS" pos="1" type="boolean"/> 4214 <bitfield name="DS" pos="2" type="boolean"/> 4215 <bitfield name="GS" pos="3" type="boolean"/> 4216 <bitfield name="FS" pos="4" type="boolean"/> 4217 <bitfield name="CS" pos="5" type="boolean"/> 4218 </reg32> 4219 <array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/> 4220 <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/> 4221 <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/> 4222 <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/> 4223 <reg32 offset="0xae6c" name="SP_UNKNOWN_AE6C" variants="A7XX-" usage="cmd"/> 4224 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-"> 4225 <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/> 4226 <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/> 4227 <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/> 4228 <bitfield name="USPTP" low="4" high="7"/> 4229 <bitfield name="SPTP" low="0" high="3"/> 4230 </reg32> 4231 <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/> 4232 <reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/> 4233 <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/> 4234 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) --> 4235 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range --> 4236 <reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 4237 4238 <!-- 4239 The downstream kernel calls the debug cluster of registers 4240 "a6xx_sp_ps_tp_cluster" but this actually specifies the border 4241 color base for compute shaders. 4242 --> 4243 <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/> 4244 <reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/> 4245 <reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/> 4246 4247 <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/> 4248 <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/> 4249 4250 <!-- could be all the stuff below here is actually TPL1?? --> 4251 4252 <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL" usage="rp_blit"> 4253 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 4254 <bitfield name="UNK2" low="2" high="3"/> 4255 </reg32> 4256 <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL" usage="rp_blit"> 4257 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 4258 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 4259 </reg32> 4260 4261 <!-- looks to work in the same way as a5xx: --> 4262 <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128" usage="cmd"/> 4263 <reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config" usage="rp_blit"/> 4264 <reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations" usage="rp_blit"/> 4265 <reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations" usage="rp_blit"/> 4266 <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 4267 <reg32 offset="0xb309" name="SP_TP_MODE_CNTL" usage="cmd"> 4268 <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/> 4269 <bitfield name="UNK3" low="2" high="7"/> 4270 </reg32> 4271 <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/> 4272 4273 <!-- 4274 Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either 4275 badly named or the functionality moved in a6xx. But downstream kernel 4276 calls this "a6xx_sp_ps_tp_2d_cluster" 4277 --> 4278 <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info" variants="A6XX" usage="rp_blit"/> 4279 <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE" variants="A6XX" usage="rp_blit"> 4280 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 4281 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 4282 </reg32> 4283 <reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A6XX" usage="rp_blit"/> 4284 <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH" variants="A6XX" usage="rp_blit"> 4285 <bitfield name="UNK0" low="0" high="8"/> 4286 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> 4287 </reg32> 4288 4289 <reg32 offset="0xb2c0" name="SP_PS_2D_SRC_INFO" type="a6xx_2d_surf_info" variants="A7XX-" usage="rp_blit"/> 4290 <reg32 offset="0xb2c1" name="SP_PS_2D_SRC_SIZE" variants="A7XX"> 4291 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 4292 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 4293 </reg32> 4294 <reg64 offset="0xb2c2" name="SP_PS_2D_SRC" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 4295 <reg32 offset="0xb2c4" name="SP_PS_2D_SRC_PITCH" variants="A7XX"> 4296 <bitfield name="UNK0" low="0" high="8"/> 4297 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> 4298 </reg32> 4299 4300 <!-- planes for NV12, etc. (TODO: not tested) --> 4301 <reg64 offset="0xb4c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A6XX"/> 4302 <reg32 offset="0xb4c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A6XX"/> 4303 <reg64 offset="0xb4c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A6XX"/> 4304 4305 <reg64 offset="0xb2c5" name="SP_PS_2D_SRC_PLANE1" type="address" align="16" variants="A7XX-"/> 4306 <reg32 offset="0xb2c7" name="SP_PS_2D_SRC_PLANE_PITCH" low="0" high="11" shr="6" type="uint" variants="A7XX-"/> 4307 <reg64 offset="0xb2c8" name="SP_PS_2D_SRC_PLANE2" type="address" align="16" variants="A7XX-"/> 4308 4309 <reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A6XX" usage="rp_blit"/> 4310 <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/> 4311 4312 <reg64 offset="0xb2ca" name="SP_PS_2D_SRC_FLAGS" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 4313 <reg32 offset="0xb2cc" name="SP_PS_2D_SRC_FLAGS_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/> 4314 4315 <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/> 4316 <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/> 4317 <reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/> 4318 <reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/> 4319 <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="rp_blit"/> 4320 4321 <reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/> 4322 <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/> 4323 <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/> 4324 <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/> 4325 <reg32 offset="0xb2d1" name="SP_PS_2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/> 4326 <reg32 offset="0xb2d2" name="SP_PS_UNKNOWN_B2D2" variants="A7XX-" usage="rp_blit"/> 4327 <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/> 4328 4329 <!-- always 0x100000 or 0x1000000? --> 4330 <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/> 4331 <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 4332 <reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd"/> 4333 <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL"> 4334 <bitfield name="MODE" pos="0" type="boolean"/> 4335 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 4336 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 4337 <bitfield name="UPPER_BIT" pos="4" type="uint"/> 4338 <bitfield name="UNK6" low="6" high="7"/> 4339 </reg32> 4340 <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? --> 4341 4342 <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/> 4343 <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/> 4344 <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/> 4345 <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/> 4346 <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/> 4347 4348 <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage="cmd"/> 4349 <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage="cmd"/> 4350 <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage="cmd"/> 4351 <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage="cmd"/> 4352 <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage="cmd"/> 4353 4354 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12"/> 4355 4356 <!-- TODO: 4 more perfcntr sel at 0xb620 ? --> 4357 4358 <bitset name="a6xx_hlsq_xs_cntl" inline="yes"> 4359 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/> 4360 <bitfield name="ENABLED" pos="8" type="boolean"/> 4361 <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/> 4362 </bitset> 4363 4364 <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 4365 <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 4366 <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 4367 <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 4368 4369 <reg32 offset="0xa827" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 4370 <reg32 offset="0xa83f" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 4371 <reg32 offset="0xa867" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 4372 <reg32 offset="0xa898" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 4373 4374 <reg32 offset="0xa9aa" name="HLSQ_FS_UNKNOWN_A9AA" variants="A7XX-" usage="rp_blit"> 4375 <!-- Tentatively named, appears to disable consts being loaded via CP_LOAD_STATE6_FRAG --> 4376 <bitfield name="CONSTS_LOAD_DISABLE" pos="0" type="boolean"/> 4377 </reg32> 4378 4379 <!-- Always 0 --> 4380 <reg32 offset="0xa9ac" name="HLSQ_UNKNOWN_A9AC" variants="A7XX-" usage="cmd"/> 4381 4382 <!-- Used in VK_KHR_fragment_shading_rate --> 4383 <reg32 offset="0xa9ad" name="HLSQ_UNKNOWN_A9AD" variants="A7XX-" usage="cmd"/> 4384 4385 <reg32 offset="0xa9ae" name="HLSQ_UNKNOWN_A9AE" variants="A7XX-" usage="rp_blit"> 4386 <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/> 4387 <!-- UNK8 is set on a730/a740 --> 4388 <bitfield name="UNK8" pos="8" type="boolean"/> 4389 <!-- UNK9 is set on a750 --> 4390 <bitfield name="UNK9" pos="9" type="boolean"/> 4391 </reg32> 4392 4393 <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/> 4394 <reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/> 4395 <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/> 4396 4397 4398 <bitset name="a6xx_hlsq_fs_cntl_0" inline="yes"> 4399 <!-- must match SP_FS_CTRL --> 4400 <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/> 4401 <bitfield name="VARYINGS" pos="1" type="boolean"/> 4402 <bitfield name="UNK2" low="2" high="11"/> 4403 </bitset> 4404 <bitset name="a6xx_hlsq_control_3_reg" inline="yes"> 4405 <!-- register loaded with position (bary.f) --> 4406 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/> 4407 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/> 4408 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/> 4409 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/> 4410 </bitset> 4411 <bitset name="a6xx_hlsq_control_4_reg" inline="yes"> 4412 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/> 4413 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/> 4414 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/> 4415 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> 4416 </bitset> 4417 <bitset name="a6xx_hlsq_control_5_reg" inline="yes"> 4418 <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/> 4419 <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/> 4420 </bitset> 4421 4422 <reg32 offset="0xb980" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A6XX" usage="rp_blit"/> 4423 <reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob --> 4424 <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A6XX" usage="rp_blit"> 4425 <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the 4426 A3xx field, except that it's not necessary to set it to anything but the maximum, since 4427 the hardware will simply emit smaller waves when it runs out of space. --> 4428 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 4429 </reg32> 4430 <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG" variants="A6XX" usage="rp_blit"> 4431 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 4432 <!-- SAMPLEID is loaded into a half-precision register: --> 4433 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 4434 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 4435 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 4436 </reg32> 4437 <reg32 offset="0xb984" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A6XX" usage="rp_blit"/> 4438 <reg32 offset="0xb985" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A6XX" usage="rp_blit"/> 4439 <reg32 offset="0xb986" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A6XX" usage="rp_blit"/> 4440 <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="cmd"/> 4441 <reg32 offset="0xa9c6" type="a6xx_hlsq_fs_cntl_0" name="HLSQ_FS_CNTL_0" variants="A7XX-" usage="rp_blit"/> 4442 <reg32 offset="0xa9c7" name="HLSQ_CONTROL_1_REG" low="0" high="2" variants="A7XX-" usage="rp_blit"> 4443 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 4444 </reg32> 4445 <reg32 offset="0xa9c8" name="HLSQ_CONTROL_2_REG" variants="A7XX-" usage="rp_blit"> 4446 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 4447 <!-- SAMPLEID is loaded into a half-precision register: --> 4448 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 4449 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 4450 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 4451 </reg32> 4452 <reg32 offset="0xa9c9" type="a6xx_hlsq_control_3_reg" name="HLSQ_CONTROL_3_REG" variants="A7XX-" usage="rp_blit"/> 4453 <reg32 offset="0xa9ca" type="a6xx_hlsq_control_4_reg" name="HLSQ_CONTROL_4_REG" variants="A7XX-" usage="rp_blit"/> 4454 <reg32 offset="0xa9cb" type="a6xx_hlsq_control_5_reg" name="HLSQ_CONTROL_5_REG" variants="A7XX-" usage="rp_blit"/> 4455 <reg32 offset="0xa9cd" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="cmd"/> 4456 4457 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 4458 <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0" variants="A6XX" usage="rp_blit"> 4459 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 4460 <!-- localsize is value minus one: --> 4461 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 4462 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 4463 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 4464 </reg32> 4465 <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1" variants="A6XX" usage="rp_blit"> 4466 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 4467 </reg32> 4468 <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2" variants="A6XX" usage="rp_blit"> 4469 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 4470 </reg32> 4471 <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3" variants="A6XX" usage="rp_blit"> 4472 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 4473 </reg32> 4474 <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4" variants="A6XX" usage="rp_blit"> 4475 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 4476 </reg32> 4477 <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5" variants="A6XX" usage="rp_blit"> 4478 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 4479 </reg32> 4480 <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6" variants="A6XX" usage="rp_blit"> 4481 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 4482 </reg32> 4483 <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0" variants="A6XX" usage="rp_blit"> 4484 <!-- these are all vec3. first 3 need to be high regs 4485 WGSIZECONSTID is the local size (from HLSQ_CS_NDRANGE_0) 4486 WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID 4487 --> 4488 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 4489 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 4490 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 4491 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 4492 </reg32> 4493 <reg32 offset="0xb998" name="HLSQ_CS_CNTL_1" variants="A6XX" usage="rp_blit"> 4494 <!-- gl_LocalInvocationIndex --> 4495 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4496 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 4497 one of those 6 "SP cores" --> 4498 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 4499 <!-- Must match SP_CS_CTRL --> 4500 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 4501 <!-- 1 thread per wave (ignored if bit9 set) --> 4502 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 4503 </reg32> 4504 <!--note: vulkan blob doesn't use these --> 4505 <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/> 4506 <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/> 4507 <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/> 4508 4509 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 4510 <reg32 offset="0xa9d4" name="HLSQ_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit"> 4511 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 4512 <!-- localsize is value minus one: --> 4513 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 4514 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 4515 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 4516 </reg32> 4517 <reg32 offset="0xa9d5" name="HLSQ_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit"> 4518 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 4519 </reg32> 4520 <reg32 offset="0xa9d6" name="HLSQ_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit"> 4521 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 4522 </reg32> 4523 <reg32 offset="0xa9d7" name="HLSQ_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit"> 4524 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 4525 </reg32> 4526 <reg32 offset="0xa9d8" name="HLSQ_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit"> 4527 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 4528 </reg32> 4529 <reg32 offset="0xa9d9" name="HLSQ_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit"> 4530 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 4531 </reg32> 4532 <reg32 offset="0xa9da" name="HLSQ_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit"> 4533 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 4534 </reg32> 4535 <!--note: vulkan blob doesn't use these --> 4536 <reg32 offset="0xa9dc" name="HLSQ_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/> 4537 <reg32 offset="0xa9dd" name="HLSQ_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/> 4538 <reg32 offset="0xa9de" name="HLSQ_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/> 4539 4540 <enum name="a7xx_cs_yalign"> 4541 <value name="CS_YALIGN_1" value="8"/> 4542 <value name="CS_YALIGN_2" value="4"/> 4543 <value name="CS_YALIGN_4" value="2"/> 4544 <value name="CS_YALIGN_8" value="1"/> 4545 </enum> 4546 4547 <reg32 offset="0xa9db" name="HLSQ_CS_CNTL_1" variants="A7XX-" usage="rp_blit"> 4548 <!-- gl_LocalInvocationIndex --> 4549 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 4550 <!-- Must match SP_CS_CTRL --> 4551 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 4552 <bitfield name="UNK11" pos="11" type="boolean"/> 4553 <bitfield name="UNK22" pos="22" type="boolean"/> 4554 <bitfield name="UNK26" pos="26" type="boolean"/> 4555 <bitfield name="YALIGN" low="27" high="30" type="a7xx_cs_yalign"/> 4556 </reg32> 4557 4558 <reg32 offset="0xa9df" name="HLSQ_CS_LOCAL_SIZE" variants="A7XX-" usage="cmd"> 4559 <!-- localsize is value minus one: --> 4560 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 4561 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 4562 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 4563 </reg32> 4564 4565 <reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/> 4566 <reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/> 4567 <reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/> 4568 4569 <!-- mirror of SP_CS_BINDLESS_BASE --> 4570 <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> 4571 <reg64 offset="0" name="DESCRIPTOR"> 4572 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4573 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4574 </reg64> 4575 </array> 4576 4577 <!-- new in a6xx gen4, mirror of SP_CS_UNKNOWN_A9B1? --> 4578 <reg32 offset="0xb9d0" name="HLSQ_CS_UNKNOWN_B9D0" variants="A6XX" usage="cmd"> 4579 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/> 4580 <bitfield name="UNK5" pos="5" type="boolean"/> 4581 <!-- always 1 ? --> 4582 <bitfield name="UNK6" pos="6" type="boolean"/> 4583 </reg32> 4584 4585 <reg32 offset="0xbb00" name="HLSQ_DRAW_CMD"> 4586 <bitfield name="STATE_ID" low="0" high="7"/> 4587 </reg32> 4588 4589 <reg32 offset="0xbb01" name="HLSQ_DISPATCH_CMD"> 4590 <bitfield name="STATE_ID" low="0" high="7"/> 4591 </reg32> 4592 4593 <reg32 offset="0xbb02" name="HLSQ_EVENT_CMD"> 4594 <!-- I think only the low bit is actually used? --> 4595 <bitfield name="STATE_ID" low="16" high="23"/> 4596 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4597 </reg32> 4598 4599 <reg32 offset="0xbb08" name="HLSQ_INVALIDATE_CMD" variants="A6XX" usage="cmd"> 4600 <doc> 4601 This register clears pending loads queued up by 4602 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 4603 CP_LOAD_STATE6. 4604 </doc> 4605 4606 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 4607 <bitfield name="VS_STATE" pos="0" type="boolean"/> 4608 <bitfield name="HS_STATE" pos="1" type="boolean"/> 4609 <bitfield name="DS_STATE" pos="2" type="boolean"/> 4610 <bitfield name="GS_STATE" pos="3" type="boolean"/> 4611 <bitfield name="FS_STATE" pos="4" type="boolean"/> 4612 <bitfield name="CS_STATE" pos="5" type="boolean"/> 4613 4614 <bitfield name="CS_IBO" pos="6" type="boolean"/> 4615 <bitfield name="GFX_IBO" pos="7" type="boolean"/> 4616 4617 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 --> 4618 <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/> 4619 <bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/> 4620 4621 <!-- SS6_BINDLESS: one bit per bindless base --> 4622 <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/> 4623 <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/> 4624 </reg32> 4625 4626 <reg32 offset="0xab1f" name="HLSQ_INVALIDATE_CMD" variants="A7XX-" usage="cmd"> 4627 <doc> 4628 This register clears pending loads queued up by 4629 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 4630 CP_LOAD_STATE6. 4631 </doc> 4632 4633 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 4634 <bitfield name="VS_STATE" pos="0" type="boolean"/> 4635 <bitfield name="HS_STATE" pos="1" type="boolean"/> 4636 <bitfield name="DS_STATE" pos="2" type="boolean"/> 4637 <bitfield name="GS_STATE" pos="3" type="boolean"/> 4638 <bitfield name="FS_STATE" pos="4" type="boolean"/> 4639 <bitfield name="CS_STATE" pos="5" type="boolean"/> 4640 4641 <bitfield name="CS_IBO" pos="6" type="boolean"/> 4642 <bitfield name="GFX_IBO" pos="7" type="boolean"/> 4643 4644 <!-- SS6_BINDLESS: one bit per bindless base --> 4645 <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/> 4646 <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/> 4647 </reg32> 4648 4649 <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A6XX" usage="rp_blit"/> 4650 <reg32 offset="0xab03" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl" variants="A7XX-" usage="rp_blit"/> 4651 4652 <array offset="0xab40" name="HLSQ_SHARED_CONSTS_IMM" stride="1" length="64" variants="A7XX-"/> 4653 4654 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd"> 4655 <doc> 4656 Shared constants are intended to be used for Vulkan push 4657 constants. When enabled, 8 vec4's are reserved in the FS 4658 const pool and 16 in the geometry const pool although 4659 only 8 are actually used (why?) and they are mapped to 4660 c504-c511 in each stage. Both VS and FS shared consts 4661 are written using ST6_CONSTANTS/SB6_IBO, so that both 4662 the geometry and FS shared consts can be written at once 4663 by using CP_LOAD_STATE6 rather than 4664 CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition 4665 DST_OFF and NUM_UNIT are in units of dwords instead of 4666 vec4's. 4667 4668 There is also a separate shared constant pool for CS, 4669 which is loaded through CP_LOAD_STATE6_FRAG with 4670 ST6_UBO/ST6_IBO. However the only real difference for CS 4671 is the dword units. 4672 </doc> 4673 <bitfield name="ENABLE" pos="0" type="boolean"/> 4674 </reg32> 4675 4676 <!-- mirror of SP_BINDLESS_BASE --> 4677 <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd"> 4678 <reg64 offset="0" name="DESCRIPTOR"> 4679 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 4680 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 4681 </reg64> 4682 </array> 4683 4684 <reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD"> 4685 <bitfield name="STATE_ID" low="8" high="15"/> 4686 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 4687 </reg32> 4688 4689 <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 --> 4690 <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/> 4691 <reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="cmd"/> 4692 <reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 4693 <reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/> 4694 <array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/> 4695 4696 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 --> 4697 <reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 4698 4699 <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/> 4700 4701 <!-- Don't know if these are SP, always 0 --> 4702 <reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/> 4703 <reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/> 4704 <reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/> 4705 4706 <!-- 4707 These special registers signal the beginning/end of an event 4708 sequence. The sequence used internally for an event looks like: 4709 - write EVENT_CMD pipe register 4710 - write CP_EVENT_START 4711 - write HLSQ_EVENT_CMD with event or HLSQ_DRAW_CMD 4712 - write PC_EVENT_CMD with event or PC_DRAW_CMD 4713 - write HLSQ_EVENT_CMD(CONTEXT_DONE) 4714 - write PC_EVENT_CMD(CONTEXT_DONE) 4715 - write CP_EVENT_END 4716 Writing to CP_EVENT_END seems to actually trigger the context roll 4717 --> 4718 <reg32 offset="0xd600" name="CP_EVENT_START"> 4719 <bitfield name="STATE_ID" low="0" high="7"/> 4720 </reg32> 4721 <reg32 offset="0xd601" name="CP_EVENT_END"> 4722 <bitfield name="STATE_ID" low="0" high="7"/> 4723 </reg32> 4724 <reg32 offset="0xd700" name="CP_2D_EVENT_START"> 4725 <bitfield name="STATE_ID" low="0" high="7"/> 4726 </reg32> 4727 <reg32 offset="0xd701" name="CP_2D_EVENT_END"> 4728 <bitfield name="STATE_ID" low="0" high="7"/> 4729 </reg32> 4730</domain> 4731 4732<!-- Seems basically the same as a5xx, maybe move to common.xml.. --> 4733<domain name="A6XX_TEX_SAMP" width="32"> 4734 <doc>Texture sampler dwords</doc> 4735 <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> 4736 <value name="A6XX_TEX_NEAREST" value="0"/> 4737 <value name="A6XX_TEX_LINEAR" value="1"/> 4738 <value name="A6XX_TEX_ANISO" value="2"/> 4739 <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> 4740 </enum> 4741 <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> 4742 <value name="A6XX_TEX_REPEAT" value="0"/> 4743 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> 4744 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> 4745 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> 4746 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> 4747 </enum> 4748 <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> 4749 <value name="A6XX_TEX_ANISO_1" value="0"/> 4750 <value name="A6XX_TEX_ANISO_2" value="1"/> 4751 <value name="A6XX_TEX_ANISO_4" value="2"/> 4752 <value name="A6XX_TEX_ANISO_8" value="3"/> 4753 <value name="A6XX_TEX_ANISO_16" value="4"/> 4754 </enum> 4755 <enum name="a6xx_reduction_mode"> 4756 <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> 4757 <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> 4758 <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> 4759 </enum> 4760 4761 <reg32 offset="0" name="0"> 4762 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> 4763 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/> 4764 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/> 4765 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/> 4766 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/> 4767 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/> 4768 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/> 4769 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real --> 4770 </reg32> 4771 <reg32 offset="1" name="1"> 4772 <bitfield name="CLAMPENABLE" pos="0" type="boolean"> 4773 <doc> 4774 clamp result to [0, 1] if the format is unorm or 4775 [-1, 1] if the format is snorm, *after* 4776 filtering. Has no effect for other formats. 4777 </doc> 4778 </bitfield> 4779 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/> 4780 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/> 4781 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/> 4782 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/> 4783 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/> 4784 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/> 4785 </reg32> 4786 <reg32 offset="2" name="2"> 4787 <bitfield name="REDUCTION_MODE" low="0" high="1" type="a6xx_reduction_mode"/> 4788 <bitfield name="CHROMA_LINEAR" pos="5" type="boolean"/> 4789 <bitfield name="BCOLOR" low="7" high="31"/> 4790 </reg32> 4791 <reg32 offset="3" name="3"/> 4792</domain> 4793 4794<domain name="A6XX_TEX_CONST" width="32"> 4795 <doc>Texture constant dwords</doc> 4796 <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> 4797 <value name="A6XX_TEX_X" value="0"/> 4798 <value name="A6XX_TEX_Y" value="1"/> 4799 <value name="A6XX_TEX_Z" value="2"/> 4800 <value name="A6XX_TEX_W" value="3"/> 4801 <value name="A6XX_TEX_ZERO" value="4"/> 4802 <value name="A6XX_TEX_ONE" value="5"/> 4803 </enum> 4804 <enum name="a6xx_tex_type"> <!-- same as a4xx? --> 4805 <value name="A6XX_TEX_1D" value="0"/> 4806 <value name="A6XX_TEX_2D" value="1"/> 4807 <value name="A6XX_TEX_CUBE" value="2"/> 4808 <value name="A6XX_TEX_3D" value="3"/> 4809 <value name="A6XX_TEX_BUFFER" value="4"/> 4810 </enum> 4811 <reg32 offset="0" name="0"> 4812 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 4813 <bitfield name="SRGB" pos="2" type="boolean"/> 4814 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/> 4815 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/> 4816 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/> 4817 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/> 4818 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/> 4819 <!-- overlaps with MIPLVLS --> 4820 <bitfield name="CHROMA_MIDPOINT_X" pos="16" type="boolean"/> 4821 <bitfield name="CHROMA_MIDPOINT_Y" pos="18" type="boolean"/> 4822 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/> 4823 <bitfield name="FMT" low="22" high="29" type="a6xx_format"/> 4824 <!-- 4825 Why is the swap needed in addition to SWIZ_*? The swap 4826 is performed before border color replacement, while the 4827 swizzle is applied after after it. 4828 --> 4829 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/> 4830 </reg32> 4831 <reg32 offset="1" name="1"> 4832 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 4833 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 4834 </reg32> 4835 <reg32 offset="2" name="2"> 4836 <!-- 4837 These fields overlap PITCH, and are used instead of 4838 PITCH/PITCHALIGN when TYPE is A6XX_TEX_BUFFER. 4839 --> 4840 <doc> probably for D3D structured UAVs, normally set to 1 </doc> 4841 <bitfield name="STRUCTSIZETEXELS" low="4" high="15" type="uint"/> 4842 <bitfield name="STARTOFFSETTEXELS" low="16" high="21" type="uint"/> 4843 4844 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 64) --> 4845 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/> 4846 <doc>Pitch in bytes (so actually stride)</doc> 4847 <bitfield name="PITCH" low="7" high="28" type="uint"/> 4848 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 4849 </reg32> 4850 <reg32 offset="3" name="3"> 4851 <!-- 4852 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and 4853 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the 4854 layer size at the point that it stops being reduced moving to 4855 higher (smaller) mipmap levels 4856 --> 4857 <bitfield name="ARRAY_PITCH" low="0" high="22" shr="12" type="uint"/> 4858 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/> 4859 <!-- 4860 by default levels with w < 16 are linear 4861 TILE_ALL makes all levels have tiling 4862 seems required when using UBWC, since all levels have UBWC (can possibly be disabled?) 4863 --> 4864 <bitfield name="TILE_ALL" pos="27" type="boolean"/> 4865 <bitfield name="FLAG" pos="28" type="boolean"/> 4866 </reg32> 4867 <!-- for 2-3 plane format, BASE is flag buffer address (if enabled) 4868 the address of the non-flag base buffer is determined automatically, 4869 and must follow the flag buffer 4870 --> 4871 <reg32 offset="4" name="4"> 4872 <bitfield name="BASE_LO" low="5" high="31" shr="5"/> 4873 </reg32> 4874 <reg32 offset="5" name="5"> 4875 <bitfield name="BASE_HI" low="0" high="16"/> 4876 <bitfield name="DEPTH" low="17" high="29" type="uint"/> 4877 </reg32> 4878 <reg32 offset="6" name="6"> 4879 <!-- overlaps with PLANE_PITCH --> 4880 <bitfield name="MIN_LOD_CLAMP" low="0" high="11" type="ufixed" radix="8"/> 4881 <!-- pitch for plane 2 / plane 3 --> 4882 <bitfield name="PLANE_PITCH" low="8" high="31" type="uint"/> 4883 </reg32> 4884 <!-- 7/8 is plane 2 address for planar formats --> 4885 <reg32 offset="7" name="7"> 4886 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/> 4887 </reg32> 4888 <reg32 offset="8" name="8"> 4889 <bitfield name="FLAG_HI" low="0" high="16"/> 4890 </reg32> 4891 <!-- 9/10 is plane 3 address for planar formats --> 4892 <reg32 offset="9" name="9"> 4893 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/> 4894 </reg32> 4895 <reg32 offset="10" name="10"> 4896 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/> 4897 <!-- log2 size of the first level, required for mipmapping --> 4898 <bitfield name="FLAG_BUFFER_LOGW" low="8" high="11" type="uint"/> 4899 <bitfield name="FLAG_BUFFER_LOGH" low="12" high="15" type="uint"/> 4900 </reg32> 4901 <reg32 offset="11" name="11"/> 4902 <reg32 offset="12" name="12"/> 4903 <reg32 offset="13" name="13"/> 4904 <reg32 offset="14" name="14"/> 4905 <reg32 offset="15" name="15"/> 4906</domain> 4907 4908<domain name="A6XX_UBO" width="32"> 4909 <reg32 offset="0" name="0"> 4910 <bitfield name="BASE_LO" low="0" high="31"/> 4911 </reg32> 4912 <reg32 offset="1" name="1"> 4913 <bitfield name="BASE_HI" low="0" high="16"/> 4914 <bitfield name="SIZE" low="17" high="31"/> <!-- size in vec4 (4xDWORD) units --> 4915 </reg32> 4916</domain> 4917 4918<domain name="A6XX_PDC" width="32"> 4919 <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/> 4920 <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/> 4921 <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/> 4922 <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/> 4923 <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/> 4924 <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/> 4925 <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/> 4926 <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/> 4927 <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/> 4928 <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/> 4929 <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/> 4930 <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/> 4931 <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/> 4932 <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/> 4933 <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/> 4934 <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/> 4935 <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/> 4936 <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/> 4937 <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/> 4938 <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/> 4939 <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/> 4940 <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/> 4941 <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/> 4942 <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/> 4943 <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/> 4944 <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/> 4945</domain> 4946 4947<domain name="A6XX_PDC_GPU_SEQ" width="32"> 4948 <reg32 offset="0x0" name="MEM_0"/> 4949</domain> 4950 4951<domain name="A6XX_CX_DBGC" width="32"> 4952 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A"> 4953 <bitfield high="7" low="0" name="PING_INDEX"/> 4954 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 4955 </reg32> 4956 <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/> 4957 <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/> 4958 <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/> 4959 <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT"> 4960 <bitfield high="5" low="0" name="TRACEEN"/> 4961 <bitfield high="14" low="12" name="GRANU"/> 4962 <bitfield high="31" low="28" name="SEGT"/> 4963 </reg32> 4964 <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM"> 4965 <bitfield high="27" low="24" name="ENABLE"/> 4966 </reg32> 4967 <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/> 4968 <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/> 4969 <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/> 4970 <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/> 4971 <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/> 4972 <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/> 4973 <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/> 4974 <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/> 4975 <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0"> 4976 <bitfield high="3" low="0" name="BYTEL0"/> 4977 <bitfield high="7" low="4" name="BYTEL1"/> 4978 <bitfield high="11" low="8" name="BYTEL2"/> 4979 <bitfield high="15" low="12" name="BYTEL3"/> 4980 <bitfield high="19" low="16" name="BYTEL4"/> 4981 <bitfield high="23" low="20" name="BYTEL5"/> 4982 <bitfield high="27" low="24" name="BYTEL6"/> 4983 <bitfield high="31" low="28" name="BYTEL7"/> 4984 </reg32> 4985 <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1"> 4986 <bitfield high="3" low="0" name="BYTEL8"/> 4987 <bitfield high="7" low="4" name="BYTEL9"/> 4988 <bitfield high="11" low="8" name="BYTEL10"/> 4989 <bitfield high="15" low="12" name="BYTEL11"/> 4990 <bitfield high="19" low="16" name="BYTEL12"/> 4991 <bitfield high="23" low="20" name="BYTEL13"/> 4992 <bitfield high="27" low="24" name="BYTEL14"/> 4993 <bitfield high="31" low="28" name="BYTEL15"/> 4994 </reg32> 4995 4996 <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/> 4997 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> 4998</domain> 4999 5000<domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip"> 5001 <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/> 5002 <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/> 5003 <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/> 5004 <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-"> 5005 <bitfield pos="0" name="FASTBLEND" type="boolean"/> 5006 <bitfield pos="1" name="LPAC" type="boolean"/> 5007 <bitfield pos="2" name="RAYTRACING" type="boolean"/> 5008 </reg32> 5009</domain> 5010 5011</database> 5012