1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7<import file="adreno/adreno_pm4.xml"/> 8<import file="adreno/a6xx_enums.xml"/> 9<import file="adreno/a7xx_enums.xml"/> 10<import file="adreno/a6xx_perfcntrs.xml"/> 11<import file="adreno/a7xx_perfcntrs.xml"/> 12<import file="adreno/a6xx_descriptors.xml"/> 13 14<!-- 15Each register that is actually being used by driver should have "usage" defined, 16currently there are following usages: 17- "cmd" - the register is used outside of renderpass and blits, 18 roughly corresponds to registers used in ib1 for Freedreno 19- "rp_blit" - the register is used inside renderpass or blits 20 (ib2 for Freedreno) 21 22It is expected that register with "cmd" usage may be written into only at 23the start of the command buffer (ib1), while "rp_blit" usage indicates that register 24is either overwritten by renderpass/blit (ib2) or not used if not overwritten 25by a particular renderpass/blit. 26--> 27 28<domain name="A6XX" width="32" prefix="variant" varset="chip"> 29 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no" varset="chip"> 30 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/> 31 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/> 32 <bitfield name="CP_IPC_INTR_0" pos="4" type="boolean" variants="A7XX-"/> 33 <bitfield name="CP_IPC_INTR_1" pos="5" type="boolean" variants="A7XX-"/> 34 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/> 35 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/> 36 <bitfield name="CP_SW" pos="8" type="boolean"/> 37 <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/> 38 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/> 39 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/> 40 <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/> 41 <bitfield name="CP_IB2" pos="13" type="boolean"/> 42 <bitfield name="CP_IB1" pos="14" type="boolean"/> 43 <bitfield name="CP_RB" pos="15" type="boolean" variants="A6XX"/> 44 <!-- Same as above but different name??: --> 45 <bitfield name="PM4CPINTERRUPT" pos="15" type="boolean" variants="A7XX-"/> 46 <bitfield name="PM4CPINTERRUPTLPAC" pos="16" type="boolean" variants="A7XX-"/> 47 <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/> 48 <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/> 49 <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/> 50 <bitfield name="CP_CACHE_FLUSH_TS_LPAC" pos="21" type="boolean" variants="A7XX-"/> 51 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/> 52 <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/> 53 <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/> 54 <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/> 55 <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/> 56 <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/> 57 <bitfield name="TSBWRITEERROR" pos="28" type="boolean" variants="A7XX-"/> 58 <bitfield name="SWFUSEVIOLATION" pos="29" type="boolean" variants="A7XX-"/> 59 <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/> 60 <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/> 61 </bitset> 62 63 <!-- 64 Note the _LPAC bits probably *actually* first appeared in a660, but the 65 _BV bits are new in a7xx 66 --> 67 <bitset name="A6XX_CP_INT" varset="chip"> 68 <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/> 69 <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/> 70 <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/> 71 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/> 72 <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/> 73 <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/> 74 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/> 75 <bitfield name="CP_OPCODE_ERROR_LPAC" pos="8" type="boolean" variants="A7XX-"/> 76 <bitfield name="CP_UCODE_ERROR_LPAC" pos="9" type="boolean" variants="A7XX-"/> 77 <bitfield name="CP_HW_FAULT_ERROR_LPAC" pos="10" type="boolean" variants="A7XX-"/> 78 <bitfield name="CP_REGISTER_PROTECTION_ERROR_LPAC" pos="11" type="boolean" variants="A7XX-"/> 79 <bitfield name="CP_ILLEGAL_INSTR_ERROR_LPAC" pos="12" type="boolean" variants="A7XX-"/> 80 <bitfield name="CP_OPCODE_ERROR_BV" pos="13" type="boolean" variants="A7XX-"/> 81 <bitfield name="CP_UCODE_ERROR_BV" pos="14" type="boolean" variants="A7XX-"/> 82 <bitfield name="CP_HW_FAULT_ERROR_BV" pos="15" type="boolean" variants="A7XX-"/> 83 <bitfield name="CP_REGISTER_PROTECTION_ERROR_BV" pos="16" type="boolean" variants="A7XX-"/> 84 <bitfield name="CP_ILLEGAL_INSTR_ERROR_BV" pos="17" type="boolean" variants="A7XX-"/> 85 </bitset> 86 87 <reg64 offset="0x0800" name="CP_RB_BASE"/> 88 <reg32 offset="0x0802" name="CP_RB_CNTL"/> 89 <reg64 offset="0x0804" name="CP_RB_RPTR_ADDR"/> 90 <reg32 offset="0x0806" name="CP_RB_RPTR"/> 91 <reg32 offset="0x0807" name="CP_RB_WPTR"/> 92 <reg32 offset="0x0808" name="CP_SQE_CNTL"/> 93 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS"> 94 <bitfield name="IFPC" pos="0" type="boolean"/> 95 </reg32> 96 <reg32 offset="0x0821" name="CP_HW_FAULT"/> 97 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS" type="A6XX_CP_INT"/> 98 <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/> 99 <reg32 offset="0x0825" name="CP_STATUS_1"/> 100 <reg64 offset="0x0830" name="CP_SQE_INSTR_BASE"/> 101 <reg32 offset="0x0840" name="CP_MISC_CNTL"/> 102 <reg32 offset="0x0844" name="CP_APRIV_CNTL"> 103 <!-- Crashdumper writes --> 104 <bitfield pos="6" name="CDWRITE" type="boolean"/> 105 <!-- Crashdumper reads --> 106 <bitfield pos="5" name="CDREAD" type="boolean"/> 107 108 <!-- 4 is unknown --> 109 110 <!-- RPTR shadow writes --> 111 <bitfield pos="3" name="RBRPWB" type="boolean"/> 112 <!-- Memory accesses from PM4 packets in the ringbuffer --> 113 <bitfield pos="2" name="RBPRIVLEVEL" type="boolean"/> 114 <!-- Ringbuffer reads --> 115 <bitfield pos="1" name="RBFETCH" type="boolean"/> 116 <!-- Instruction cache fetches --> 117 <bitfield pos="0" name="ICACHE" type="boolean"/> 118 </reg32> 119 <!-- Preemptions taking longer than this threshold increment PERF_CP_LONG_PREEMPTIONS: --> 120 <reg32 offset="0x08C0" name="CP_PREEMPT_THRESHOLD"/> 121 <!-- all the threshold values seem to be in units of quad-dwords: --> 122 <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1"> 123 <doc> 124 b0..7 identifies where MRB data starts (and RB data ends) 125 b8.15 identifies where VSD data starts (and MRB data ends) 126 b16..23 identifies where IB1 data starts (and RB data ends) 127 b24..31 identifies where IB2 data starts (and IB1 data ends) 128 </doc> 129 <bitfield name="MRB_START" low="0" high="7" shr="2"/> 130 <bitfield name="VSD_START" low="8" high="15" shr="2"/> 131 <bitfield name="IB1_START" low="16" high="23" shr="2"/> 132 <bitfield name="IB2_START" low="24" high="31" shr="2"/> 133 </reg32> 134 <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2"> 135 <doc> 136 low bits identify where CP_SET_DRAW_STATE stateobj 137 processing starts (and IB2 data ends). I'm guessing 138 b8 is part of this since (from downstream kgsl): 139 140 /* ROQ sizes are twice as big on a640/a680 than on a630 */ 141 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) { 142 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); 143 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C); 144 } ... 145 </doc> 146 <bitfield name="SDS_START" low="0" high="8" shr="2"/> 147 <!-- total ROQ size: --> 148 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/> 149 </reg32> 150 <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/> 151 <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/> 152 <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 153 <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/> 154 <reg32 offset="0x084F" name="CP_PROTECT_CNTL"> 155 <bitfield pos="3" name="LAST_SPAN_INF_RANGE" type="boolean"/> 156 <bitfield pos="1" name="ACCESS_FAULT_ON_VIOL_EN" type="boolean"/> 157 <bitfield pos="0" name="ACCESS_PROT_EN" type="boolean"/> 158 </reg32> 159 160 <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8"> 161 <reg32 offset="0x0" name="REG" type="uint"/> 162 </array> 163 <array offset="0x0850" name="CP_PROTECT" stride="1" length="32"> 164 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/> 165 </array> 166 167 <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"> 168 <bitfield name="STOP" pos="0" type="boolean"/> 169 <bitfield name="LEVEL" low="6" high="7"/> 170 <bitfield name="USES_GMEM" pos="8" type="boolean"/> 171 <bitfield name="SKIP_SAVE_RESTORE" pos="9" type="boolean"/> 172 </reg32> 173 <reg64 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO"/> 174 <reg64 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR"/> 175 <reg64 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR"/> 176 <reg64 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR"/> 177 <reg32 offset="0x08ab" name="CP_CONTEXT_SWITCH_LEVEL_STATUS" variants="A7XX-"/> 178 <array offset="0x08D0" name="CP_PERFCTR_CP_SEL" stride="1" length="14"/> 179 <array offset="0x08e0" name="CP_BV_PERFCTR_CP_SEL" stride="1" length="7" variants="A7XX-"/> 180 <reg64 offset="0x0900" name="CP_CRASH_DUMP_SCRIPT_BASE"/> 181 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/> 182 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/> 183 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/> 184 <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/> 185 <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/> 186 <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/> 187 <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/> 188 <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/> 189 <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/> 190 <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/> 191 <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/> 192 <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/> 193 <reg64 offset="0x0928" name="CP_IB1_BASE"/> 194 <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/> 195 <reg64 offset="0x092B" name="CP_IB2_BASE"/> 196 <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/> 197 <!-- SDS == CP_SET_DRAW_STATE: --> 198 <reg64 offset="0x092e" name="CP_SDS_BASE"/> 199 <reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/> 200 <!-- MRB == MEM_READ_ADDR/$addr in SQE firmware --> 201 <reg64 offset="0x0931" name="CP_MRB_BASE"/> 202 <reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/> 203 <!-- 204 VSD == Visibility Stream Decode 205 This is used by CP to read the draw stream and skip empty draws 206 --> 207 <reg64 offset="0x0934" name="CP_VSD_BASE"/> 208 209 <bitset name="a6xx_roq_status" inline="yes"> 210 <bitfield name="RPTR" low="0" high="9"/> 211 <bitfield name="WPTR" low="16" high="25"/> 212 </bitset> 213 <reg32 offset="0x0939" name="CP_ROQ_RB_STATUS" type="a6xx_roq_status"/> 214 <reg32 offset="0x093a" name="CP_ROQ_IB1_STATUS" type="a6xx_roq_status"/> 215 <reg32 offset="0x093b" name="CP_ROQ_IB2_STATUS" type="a6xx_roq_status"/> 216 <reg32 offset="0x093c" name="CP_ROQ_SDS_STATUS" type="a6xx_roq_status"/> 217 <reg32 offset="0x093d" name="CP_ROQ_MRB_STATUS" type="a6xx_roq_status"/> 218 <reg32 offset="0x093e" name="CP_ROQ_VSD_STATUS" type="a6xx_roq_status"/> 219 220 <reg32 offset="0x0943" name="CP_IB1_INIT_SIZE"/> 221 <reg32 offset="0x0944" name="CP_IB2_INIT_SIZE"/> 222 <reg32 offset="0x0945" name="CP_SDS_INIT_SIZE"/> 223 <reg32 offset="0x0946" name="CP_MRB_INIT_SIZE"/> 224 <reg32 offset="0x0947" name="CP_VSD_INIT_SIZE"/> 225 226 <reg32 offset="0x0948" name="CP_ROQ_AVAIL_RB"> 227 <doc>number of remaining dwords incl current dword being consumed?</doc> 228 <bitfield name="REM" low="16" high="31"/> 229 </reg32> 230 <reg32 offset="0x0949" name="CP_ROQ_AVAIL_IB1"> 231 <doc>number of remaining dwords incl current dword being consumed?</doc> 232 <bitfield name="REM" low="16" high="31"/> 233 </reg32> 234 <reg32 offset="0x094a" name="CP_ROQ_AVAIL_IB2"> 235 <doc>number of remaining dwords incl current dword being consumed?</doc> 236 <bitfield name="REM" low="16" high="31"/> 237 </reg32> 238 <reg32 offset="0x094b" name="CP_ROQ_AVAIL_SDS"> 239 <doc>number of remaining dwords incl current dword being consumed?</doc> 240 <bitfield name="REM" low="16" high="31"/> 241 </reg32> 242 <reg32 offset="0x094c" name="CP_ROQ_AVAIL_MRB"> 243 <doc>number of dwords that have already been read but haven't been consumed by $addr</doc> 244 <bitfield name="REM" low="16" high="31"/> 245 </reg32> 246 <reg32 offset="0x094d" name="CP_ROQ_AVAIL_VSD"> 247 <doc>number of remaining dwords incl current dword being consumed?</doc> 248 <bitfield name="REM" low="16" high="31"/> 249 </reg32> 250 251 <bitset name="a7xx_aperture_cntl" inline="yes"> 252 <bitfield name="PIPE" low="12" high="13" type="a7xx_pipe"/> 253 <bitfield name="CLUSTER" low="8" high="10" type="a7xx_cluster"/> 254 <bitfield name="CONTEXT" low="4" high="5"/> 255 </bitset> 256 <reg64 offset="0x0980" name="CP_ALWAYS_ON_COUNTER"/> 257 <reg32 offset="0x098D" name="CP_AHB_CNTL"/> 258 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" variants="A6XX"/> 259 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST" type="a7xx_aperture_cntl" variants="A7XX-"/> 260 <reg32 offset="0x0A01" name="CP_APERTURE_CNTL_SQE" variants="A6XX"/> 261 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" variants="A6XX"/> 262 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD" type="a7xx_aperture_cntl" variants="A7XX-"/> 263 264 <reg32 offset="0x0a61" name="CP_BV_PROTECT_STATUS" variants="A7XX-"/> 265 <reg32 offset="0x0a64" name="CP_BV_HW_FAULT" variants="A7XX-"/> 266 <reg32 offset="0x0a81" name="CP_BV_DRAW_STATE_ADDR" variants="A7XX-"/> 267 <reg32 offset="0x0a82" name="CP_BV_DRAW_STATE_DATA" variants="A7XX-"/> 268 <reg32 offset="0x0a83" name="CP_BV_ROQ_DBG_ADDR" variants="A7XX-"/> 269 <reg32 offset="0x0a84" name="CP_BV_ROQ_DBG_DATA" variants="A7XX-"/> 270 <reg32 offset="0x0a85" name="CP_BV_SQE_UCODE_DBG_ADDR" variants="A7XX-"/> 271 <reg32 offset="0x0a86" name="CP_BV_SQE_UCODE_DBG_DATA" variants="A7XX-"/> 272 <reg32 offset="0x0a87" name="CP_BV_SQE_STAT_ADDR" variants="A7XX-"/> 273 <reg32 offset="0x0a88" name="CP_BV_SQE_STAT_DATA" variants="A7XX-"/> 274 <reg32 offset="0x0a96" name="CP_BV_MEM_POOL_DBG_ADDR" variants="A7XX-"/> 275 <reg32 offset="0x0a97" name="CP_BV_MEM_POOL_DBG_DATA" variants="A7XX-"/> 276 <reg64 offset="0x0a98" name="CP_BV_RB_RPTR_ADDR" variants="A7XX-"/> 277 278 <reg32 offset="0x0a9a" name="CP_RESOURCE_TABLE_DBG_ADDR" variants="A7XX-"/> 279 <reg32 offset="0x0a9b" name="CP_RESOURCE_TABLE_DBG_DATA" variants="A7XX-"/> 280 <reg32 offset="0x0ad0" name="CP_BV_APRIV_CNTL" variants="A7XX-"/> 281 <reg32 offset="0x0ada" name="CP_BV_CHICKEN_DBG" variants="A7XX-"/> 282 283 <reg32 offset="0x0b0a" name="CP_LPAC_DRAW_STATE_ADDR" variants="A7XX-"/> 284 <reg32 offset="0x0b0b" name="CP_LPAC_DRAW_STATE_DATA" variants="A7XX-"/> 285 <reg32 offset="0x0b0c" name="CP_LPAC_ROQ_DBG_ADDR" variants="A7XX-"/> 286 <reg32 offset="0x0b27" name="CP_SQE_AC_UCODE_DBG_ADDR" variants="A7XX-"/> 287 <reg32 offset="0x0b28" name="CP_SQE_AC_UCODE_DBG_DATA" variants="A7XX-"/> 288 <reg32 offset="0x0b29" name="CP_SQE_AC_STAT_ADDR" variants="A7XX-"/> 289 <reg32 offset="0x0b2a" name="CP_SQE_AC_STAT_DATA" variants="A7XX-"/> 290 291 <reg32 offset="0x0b31" name="CP_LPAC_APRIV_CNTL" variants="A7XX-"/> 292 <reg32 offset="0x0B34" name="CP_LPAC_PROG_FIFO_SIZE"/> 293 <reg32 offset="0x0b35" name="CP_LPAC_ROQ_DBG_DATA" variants="A7XX-"/> 294 <reg32 offset="0x0b36" name="CP_LPAC_FIFO_DBG_DATA" variants="A7XX-"/> 295 <reg32 offset="0x0b40" name="CP_LPAC_FIFO_DBG_ADDR" variants="A7XX-"/> 296 <reg32 offset="0x0b81" name="CP_LPAC_SQE_CNTL"/> 297 <reg64 offset="0x0b82" name="CP_LPAC_SQE_INSTR_BASE"/> 298 299 <reg64 offset="0x0b70" name="CP_AQE_INSTR_BASE_0" variants="A7XX-"/> 300 <reg64 offset="0x0b72" name="CP_AQE_INSTR_BASE_1" variants="A7XX-"/> 301 <reg32 offset="0x0b78" name="CP_AQE_APRIV_CNTL" variants="A7XX-"/> 302 303 <reg32 offset="0x0ba8" name="CP_AQE_ROQ_DBG_ADDR_0" variants="A7XX-"/> 304 <reg32 offset="0x0ba9" name="CP_AQE_ROQ_DBG_ADDR_1" variants="A7XX-"/> 305 <reg32 offset="0x0bac" name="CP_AQE_ROQ_DBG_DATA_0" variants="A7XX-"/> 306 <reg32 offset="0x0bad" name="CP_AQE_ROQ_DBG_DATA_1" variants="A7XX-"/> 307 <reg32 offset="0x0bb0" name="CP_AQE_UCODE_DBG_ADDR_0" variants="A7XX-"/> 308 <reg32 offset="0x0bb1" name="CP_AQE_UCODE_DBG_ADDR_1" variants="A7XX-"/> 309 <reg32 offset="0x0bb4" name="CP_AQE_UCODE_DBG_DATA_0" variants="A7XX-"/> 310 <reg32 offset="0x0bb5" name="CP_AQE_UCODE_DBG_DATA_1" variants="A7XX-"/> 311 <reg32 offset="0x0bb8" name="CP_AQE_STAT_ADDR_0" variants="A7XX-"/> 312 <reg32 offset="0x0bb9" name="CP_AQE_STAT_ADDR_1" variants="A7XX-"/> 313 <reg32 offset="0x0bbc" name="CP_AQE_STAT_DATA_0" variants="A7XX-"/> 314 <reg32 offset="0x0bbd" name="CP_AQE_STAT_DATA_1" variants="A7XX-"/> 315 316 <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 317 <reg32 offset="0x0018" name="RBBM_GPR0_CNTL"/> 318 <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/> 319 <reg32 offset="0x0210" name="RBBM_STATUS"> 320 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/> 321 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/> 322 <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/> 323 <bitfield pos="20" name="VSC_BUSY" type="boolean"/> 324 <bitfield pos="19" name="TPL1_BUSY" type="boolean"/> 325 <bitfield pos="18" name="SP_BUSY" type="boolean"/> 326 <bitfield pos="17" name="UCHE_BUSY" type="boolean"/> 327 <bitfield pos="16" name="VPC_BUSY" type="boolean"/> 328 <bitfield pos="15" name="VFD_BUSY" type="boolean"/> 329 <bitfield pos="14" name="TESS_BUSY" type="boolean"/> 330 <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/> 331 <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/> 332 <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/> 333 <bitfield pos="10" name="LRZ_BUSY" type="boolean"/> 334 <bitfield pos="9" name="A2D_BUSY" type="boolean"/> 335 <bitfield pos="8" name="CCU_BUSY" type="boolean"/> 336 <bitfield pos="7" name="RB_BUSY" type="boolean"/> 337 <bitfield pos="6" name="RAS_BUSY" type="boolean"/> 338 <bitfield pos="5" name="TSE_BUSY" type="boolean"/> 339 <bitfield pos="4" name="VBIF_BUSY" type="boolean"/> 340 <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/> 341 <bitfield pos="2" name="CP_BUSY" type="boolean"/> 342 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/> 343 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/> 344 </reg32> 345 <reg32 offset="0x0211" name="RBBM_STATUS1"/> 346 <reg32 offset="0x0212" name="RBBM_STATUS2"/> 347 <reg32 offset="0x0213" name="RBBM_STATUS3"> 348 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/> 349 </reg32> 350 <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/> 351 352 <reg32 offset="0x0260" name="RBBM_CLOCK_MODE_CP" variants="A7XX-"/> 353 <reg32 offset="0x0284" name="RBBM_CLOCK_MODE_BV_LRZ" variants="A7XX-"/> 354 <reg32 offset="0x0285" name="RBBM_CLOCK_MODE_BV_GRAS" variants="A7XX-"/> 355 <reg32 offset="0x0286" name="RBBM_CLOCK_MODE2_GRAS" variants="A7XX-"/> 356 <reg32 offset="0x0287" name="RBBM_CLOCK_MODE_BV_VFD" variants="A7XX-"/> 357 <reg32 offset="0x0288" name="RBBM_CLOCK_MODE_BV_GPC" variants="A7XX-"/> 358 359 <reg32 offset="0x02c0" name="RBBM_SW_FUSE_INT_STATUS" variants="A7XX-"/> 360 <reg32 offset="0x02c1" name="RBBM_SW_FUSE_INT_MASK" variants="A7XX-"/> 361 362 <array offset="0x0400" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A6XX"/> 363 <array offset="0x041c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A6XX"/> 364 <array offset="0x0424" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A6XX"/> 365 <array offset="0x0434" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A6XX"/> 366 <array offset="0x0444" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A6XX"/> 367 <array offset="0x0450" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A6XX"/> 368 <array offset="0x045c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A6XX"/> 369 <array offset="0x0466" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A6XX"/> 370 <array offset="0x046e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A6XX"/> 371 <array offset="0x0476" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A6XX"/> 372 <array offset="0x048e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A6XX"/> 373 <array offset="0x04a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A6XX"/> 374 <array offset="0x04d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A6XX"/> 375 <array offset="0x04e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A6XX"/> 376 <array offset="0x04ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A6XX"/> 377 <array offset="0x04f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A6XX"/> 378 379 <array offset="0x0300" name="RBBM_PERFCTR_CP" stride="2" length="14" variants="A7XX-"/> 380 <array offset="0x031c" name="RBBM_PERFCTR_RBBM" stride="2" length="4" variants="A7XX-"/> 381 <array offset="0x0324" name="RBBM_PERFCTR_PC" stride="2" length="8" variants="A7XX-"/> 382 <array offset="0x0334" name="RBBM_PERFCTR_VFD" stride="2" length="8" variants="A7XX-"/> 383 <array offset="0x0344" name="RBBM_PERFCTR_HLSQ" stride="2" length="6" variants="A7XX-"/> 384 <array offset="0x0350" name="RBBM_PERFCTR_VPC" stride="2" length="6" variants="A7XX-"/> 385 <array offset="0x035c" name="RBBM_PERFCTR_CCU" stride="2" length="5" variants="A7XX-"/> 386 <array offset="0x0366" name="RBBM_PERFCTR_TSE" stride="2" length="4" variants="A7XX-"/> 387 <array offset="0x036e" name="RBBM_PERFCTR_RAS" stride="2" length="4" variants="A7XX-"/> 388 <array offset="0x0376" name="RBBM_PERFCTR_UCHE" stride="2" length="12" variants="A7XX-"/> 389 <array offset="0x038e" name="RBBM_PERFCTR_TP" stride="2" length="12" variants="A7XX-"/> 390 <array offset="0x03a6" name="RBBM_PERFCTR_SP" stride="2" length="24" variants="A7XX-"/> 391 <array offset="0x03d6" name="RBBM_PERFCTR_RB" stride="2" length="8" variants="A7XX-"/> 392 <array offset="0x03e6" name="RBBM_PERFCTR_VSC" stride="2" length="2" variants="A7XX-"/> 393 <array offset="0x03ea" name="RBBM_PERFCTR_LRZ" stride="2" length="4" variants="A7XX-"/> 394 <array offset="0x03f2" name="RBBM_PERFCTR_CMP" stride="2" length="4" variants="A7XX-"/> 395 <array offset="0x03fa" name="RBBM_PERFCTR_UFC" stride="2" length="4" variants="A7XX-"/> 396 <array offset="0x0410" name="RBBM_PERFCTR2_HLSQ" stride="2" length="6" variants="A7XX-"/> 397 <array offset="0x041c" name="RBBM_PERFCTR2_CP" stride="2" length="7" variants="A7XX-"/> 398 <array offset="0x042a" name="RBBM_PERFCTR2_SP" stride="2" length="12" variants="A7XX-"/> 399 <array offset="0x0442" name="RBBM_PERFCTR2_TP" stride="2" length="6" variants="A7XX-"/> 400 <array offset="0x044e" name="RBBM_PERFCTR2_UFC" stride="2" length="2" variants="A7XX-"/> 401 <array offset="0x0460" name="RBBM_PERFCTR_BV_PC" stride="2" length="8" variants="A7XX-"/> 402 <array offset="0x0470" name="RBBM_PERFCTR_BV_VFD" stride="2" length="8" variants="A7XX-"/> 403 <array offset="0x0480" name="RBBM_PERFCTR_BV_VPC" stride="2" length="6" variants="A7XX-"/> 404 <array offset="0x048c" name="RBBM_PERFCTR_BV_TSE" stride="2" length="4" variants="A7XX-"/> 405 <array offset="0x0494" name="RBBM_PERFCTR_BV_RAS" stride="2" length="4" variants="A7XX-"/> 406 <array offset="0x049c" name="RBBM_PERFCTR_BV_LRZ" stride="2" length="4" variants="A7XX-"/> 407 408 <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/> 409 <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/> 410 <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/> 411 <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/> 412 <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/> 413 <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/> 414 <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/> 415 <array offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL" stride="1" length="4"/> 416 <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/> 417 <reg32 offset="0x050e" name="RBBM_PERFCTR_SRAM_INIT_CMD"/> 418 <reg32 offset="0x050f" name="RBBM_PERFCTR_SRAM_INIT_STATUS"/> 419 <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/> 420 <reg32 offset="0x0534" name="RBBM_NC_MODE_CNTL"/> 421 <reg32 offset="0x0535" name="RBBM_SNAPSHOT_STATUS" variants="A7XX-"/> 422 423 <!--- 424 This block of registers aren't tied to perf counters. They 425 count various geometry stats, for example number of 426 vertices in, number of primnitives assembled etc. 427 --> 428 429 <reg64 offset="0x0540" name="RBBM_PIPESTAT_IAVERTICES"/> 430 <reg64 offset="0x0542" name="RBBM_PIPESTAT_IAPRIMITIVES"/> 431 <reg64 offset="0x0544" name="RBBM_PIPESTAT_VSINVOCATIONS"/> 432 <reg64 offset="0x0546" name="RBBM_PIPESTAT_HSINVOCATIONS"/> 433 <reg64 offset="0x0548" name="RBBM_PIPESTAT_DSINVOCATIONS"/> 434 <reg64 offset="0x054a" name="RBBM_PIPESTAT_GSINVOCATIONS"/> 435 <reg64 offset="0x054c" name="RBBM_PIPESTAT_GSPRIMITIVES"/> 436 <reg64 offset="0x054e" name="RBBM_PIPESTAT_CINVOCATIONS"/> 437 <reg64 offset="0x0550" name="RBBM_PIPESTAT_CPRIMITIVES"/> 438 <reg64 offset="0x0552" name="RBBM_PIPESTAT_PSINVOCATIONS"/> 439 <reg64 offset="0x0554" name="RBBM_PIPESTAT_CSINVOCATIONS"/> 440 441 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/> 442 <reg64 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE"/> 443 <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/> 444 <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/> 445 <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 446 <reg64 offset="0xfc00" name="RBBM_SECVID_TSB_STATUS" variants="A7XX-"/> 447 <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/> 448 <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/> 449 <reg32 offset="0x00016" name="RBBM_GBIF_HALT"/> 450 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK"/> 451 <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD"> 452 <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/> 453 </reg32> 454 455 <reg32 offset="0x00016" name="RBBM_GBIF_HALT" variants="A7XX-"/> 456 <reg32 offset="0x00017" name="RBBM_GBIF_HALT_ACK" variants="A7XX-"/> 457 <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/> 458 <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/> 459 <reg32 offset="0x00038" name="RBBM_INT_0_MASK" type="A6XX_RBBM_INT_0_MASK"/> 460 <reg32 offset="0x0003a" name="RBBM_INT_2_MASK" variants="A7XX-"/> 461 <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/> 462 <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/> 463 <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/> 464 <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/> 465 <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/> 466 <reg32 offset="0x000ad" name="RBBM_CLOCK_CNTL_GLOBAL" variants="A7XX-"/> 467 <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/> 468 <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/> 469 <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/> 470 <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/> 471 <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/> 472 <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/> 473 <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/> 474 <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/> 475 <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/> 476 <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/> 477 <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/> 478 <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/> 479 <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/> 480 <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/> 481 <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/> 482 <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/> 483 <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/> 484 <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/> 485 <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/> 486 <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/> 487 <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/> 488 <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/> 489 <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/> 490 <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/> 491 <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/> 492 <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/> 493 <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/> 494 <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/> 495 <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/> 496 <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/> 497 <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/> 498 <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/> 499 <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/> 500 <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/> 501 <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/> 502 <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/> 503 <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/> 504 <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/> 505 <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/> 506 <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/> 507 <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/> 508 <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/> 509 <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/> 510 <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/> 511 <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/> 512 <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/> 513 <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/> 514 <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/> 515 <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/> 516 <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/> 517 <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/> 518 <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/> 519 <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/> 520 <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/> 521 <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/> 522 <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/> 523 <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/> 524 <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/> 525 <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/> 526 <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/> 527 <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/> 528 <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/> 529 <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/> 530 <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/> 531 <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/> 532 <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/> 533 <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/> 534 <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/> 535 <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/> 536 <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/> 537 <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/> 538 <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/> 539 <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/> 540 <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/> 541 <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/> 542 <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/> 543 <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/> 544 <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/> 545 <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/> 546 <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/> 547 <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/> 548 <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/> 549 <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/> 550 <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/> 551 <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/> 552 <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/> 553 <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/> 554 <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/> 555 <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/> 556 <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/> 557 <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/> 558 <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/> 559 <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/> 560 <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/> 561 <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/> 562 <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/> 563 <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/> 564 <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/> 565 <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/> 566 <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/> 567 <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/> 568 <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/> 569 <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/> 570 <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/> 571 <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/> 572 <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/> 573 <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/> 574 <reg32 offset="0x0011e" name="RBBM_CGC_GLOBAL_LOAD_CMD" variants="A7XX-"/> 575 <reg32 offset="0x0011f" name="RBBM_CGC_P2S_TRIG_CMD" variants="A7XX-"/> 576 <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/> 577 <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/> 578 <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE" variants="A6XX"/> 579 <reg32 offset="0x00122" name="RBBM_CGC_P2S_STATUS" variants="A7XX-"> 580 <bitfield name="TXDONE" pos="0" type="boolean"/> 581 </reg32> 582 <reg32 offset="0x00123" name="RBBM_CLOCK_CNTL_FCHE"/> 583 <reg32 offset="0x00124" name="RBBM_CLOCK_DELAY_FCHE"/> 584 <reg32 offset="0x00125" name="RBBM_CLOCK_HYST_FCHE"/> 585 <reg32 offset="0x00126" name="RBBM_CLOCK_CNTL_MHUB"/> 586 <reg32 offset="0x00127" name="RBBM_CLOCK_DELAY_MHUB"/> 587 <reg32 offset="0x00128" name="RBBM_CLOCK_HYST_MHUB"/> 588 <reg32 offset="0x00129" name="RBBM_CLOCK_DELAY_GLC"/> 589 <reg32 offset="0x0012a" name="RBBM_CLOCK_HYST_GLC"/> 590 <reg32 offset="0x0012b" name="RBBM_CLOCK_CNTL_GLC"/> 591 <reg32 offset="0x0012f" name="RBBM_CLOCK_HYST2_VFD" variants="A7XX-"/> 592 <reg32 offset="0x005ff" name="RBBM_LPAC_GBIF_CLIENT_QOS_CNTL"/> 593 594 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/> 595 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/> 596 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/> 597 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A6XX"> 598 <bitfield high="7" low="0" name="PING_INDEX"/> 599 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 600 </reg32> 601 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D" variants="A7XX-"> 602 <bitfield high="7" low="0" name="PING_INDEX"/> 603 <bitfield high="24" low="16" name="PING_BLK_SEL"/> 604 </reg32> 605 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT"> 606 <bitfield high="5" low="0" name="TRACEEN"/> 607 <bitfield high="14" low="12" name="GRANU"/> 608 <bitfield high="31" low="28" name="SEGT"/> 609 </reg32> 610 <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM"> 611 <bitfield high="27" low="24" name="ENABLE"/> 612 </reg32> 613 <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/> 614 <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/> 615 <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/> 616 <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/> 617 <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/> 618 <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/> 619 <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/> 620 <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/> 621 <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0"> 622 <bitfield high="3" low="0" name="BYTEL0"/> 623 <bitfield high="7" low="4" name="BYTEL1"/> 624 <bitfield high="11" low="8" name="BYTEL2"/> 625 <bitfield high="15" low="12" name="BYTEL3"/> 626 <bitfield high="19" low="16" name="BYTEL4"/> 627 <bitfield high="23" low="20" name="BYTEL5"/> 628 <bitfield high="27" low="24" name="BYTEL6"/> 629 <bitfield high="31" low="28" name="BYTEL7"/> 630 </reg32> 631 <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1"> 632 <bitfield high="3" low="0" name="BYTEL8"/> 633 <bitfield high="7" low="4" name="BYTEL9"/> 634 <bitfield high="11" low="8" name="BYTEL10"/> 635 <bitfield high="15" low="12" name="BYTEL11"/> 636 <bitfield high="19" low="16" name="BYTEL12"/> 637 <bitfield high="23" low="20" name="BYTEL13"/> 638 <bitfield high="27" low="24" name="BYTEL14"/> 639 <bitfield high="31" low="28" name="BYTEL15"/> 640 </reg32> 641 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/> 642 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/> 643 <array offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL" stride="1" length="2" variants="A6XX"/> 644 <reg32 offset="0x0CD8" name="VSC_UNKNOWN_0CD8" variants="A7XX"> 645 <doc> 646 Set to true when binning, isn't changed afterwards 647 </doc> 648 <bitfield name="BINNING" pos="0" type="boolean"/> 649 </reg32> 650 <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/> 651 <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/> 652 <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 653 <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/> 654 <reg64 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX"/> 655 <reg64 offset="0x0E07" name="UCHE_WRITE_THRU_BASE"/> 656 <reg64 offset="0x0E09" name="UCHE_TRAP_BASE"/> 657 <reg64 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN"/> 658 <reg64 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX"/> 659 <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS" usage="cmd"/> 660 <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/> 661 <reg32 offset="0x0E19" name="UCHE_CLIENT_PF" usage="cmd"> 662 <bitfield high="7" low="0" name="PERFSEL"/> 663 </reg32> 664 <array offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL" stride="1" length="12"/> 665 <reg32 offset="0x0e3a" name="UCHE_GBIF_GX_CONFIG"/> 666 <reg32 offset="0x0e3c" name="UCHE_CMDQ_CONFIG"/> 667 668 <reg32 offset="0x3000" name="VBIF_VERSION"/> 669 <reg32 offset="0x3001" name="VBIF_CLKON"> 670 <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/> 671 </reg32> 672 <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/> 673 <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/> 674 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/> 675 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/> 676 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/> 677 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1"> 678 <bitfield low="0" high="3" name="DATA_SEL"/> 679 </reg32> 680 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/> 681 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1"> 682 <bitfield low="0" high="8" name="DATA_SEL"/> 683 </reg32> 684 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/> 685 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/> 686 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/> 687 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/> 688 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/> 689 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/> 690 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/> 691 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/> 692 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/> 693 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/> 694 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/> 695 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/> 696 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/> 697 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/> 698 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/> 699 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/> 700 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/> 701 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/> 702 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/> 703 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/> 704 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/> 705 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/> 706 707 <reg32 offset="0x3c01" name="GBIF_SCACHE_CNTL0"/> 708 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/> 709 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/> 710 <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/> 711 <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/> 712 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/> 713 <reg32 offset="0x3c45" name="GBIF_HALT"/> 714 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/> 715 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/> 716 <reg32 offset="0x3cc1" name="GBIF_PERF_PWR_CNT_CLR"/> 717 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/> 718 <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/> 719 <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/> 720 <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/> 721 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/> 722 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/> 723 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/> 724 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/> 725 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/> 726 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/> 727 <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/> 728 <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/> 729 <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/> 730 <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/> 731 <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/> 732 <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/> 733 734 <reg32 offset="0x0c00" name="VSC_DBG_ECO_CNTL"/> 735 <reg32 offset="0x0c02" name="VSC_BIN_SIZE" usage="rp_blit"> 736 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/> 737 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/> 738 </reg32> 739 <reg64 offset="0x0c03" name="VSC_SIZE_BASE" type="waddress" usage="cmd"/> 740 <reg32 offset="0x0c06" name="VSC_EXPANDED_BIN_CNTL" usage="rp_blit"> 741 <bitfield name="NX" low="1" high="10" type="uint"/> 742 <bitfield name="NY" low="11" high="20" type="uint"/> 743 </reg32> 744 <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32" usage="rp_blit"> 745 <reg32 offset="0x0" name="REG"> 746 <doc> 747 Configures the mapping between VSC_PIPE buffer and 748 bin, X/Y specify the bin index in the horiz/vert 749 direction (0,0 is upper left, 0,1 is leftmost bin 750 on second row, and so on). W/H specify the number 751 of bins assigned to this VSC_PIPE in the horiz/vert 752 dimension. 753 </doc> 754 <bitfield name="X" low="0" high="9" type="uint"/> 755 <bitfield name="Y" low="10" high="19" type="uint"/> 756 <bitfield name="W" low="20" high="25" type="uint"/> 757 <bitfield name="H" low="26" high="31" type="uint"/> 758 </reg32> 759 </array> 760 <!-- 761 HW binning primitive & draw streams, which enable draws and primitives 762 within a draw to be skipped in the main tile pass. See: 763 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format 764 765 Compared to a5xx and earlier, we just program the address of the first 766 stream and hw adds (pipe_num * VSC_*_STRM_PITCH) 767 768 LIMIT is set to PITCH - 64, to make room for a bit of overflow 769 --> 770 <reg64 offset="0x0c30" name="VSC_PIPE_DATA_PRIM_BASE" type="waddress" usage="cmd"/> 771 <reg32 offset="0x0c32" name="VSC_PIPE_DATA_PRIM_STRIDE" usage="cmd"/> 772 <reg32 offset="0x0c33" name="VSC_PIPE_DATA_PRIM_LENGTH" usage="cmd"/> 773 <reg64 offset="0x0c34" name="VSC_PIPE_DATA_DRAW_BASE" type="waddress" usage="cmd"/> 774 <reg32 offset="0x0c36" name="VSC_PIPE_DATA_DRAW_STRIDE" usage="cmd"/> 775 <reg32 offset="0x0c37" name="VSC_PIPE_DATA_DRAW_LENGTH" usage="cmd"/> 776 777 <array offset="0x0c38" name="VSC_CHANNEL_VISIBILITY" stride="1" length="32" usage="rp_blit"> 778 <doc> 779 Seems to be a bitmap of which tiles mapped to the VSC 780 pipe contain geometry. 781 782 I suppose we can connect a maximum of 32 tiles to a 783 single VSC pipe. 784 </doc> 785 <reg32 offset="0x0" name="REG"/> 786 </array> 787 788 <array offset="0x0c58" name="VSC_PIPE_DATA_PRIM_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 789 <doc> 790 Has the size of data written to corresponding VSC_PRIM_STRM 791 buffer. 792 </doc> 793 <reg32 offset="0x0" name="REG"/> 794 </array> 795 796 <array offset="0x0c78" name="VSC_PIPE_DATA_DRAW_SIZE" stride="1" length="32" variants="A6XX" usage="rp_blit"> 797 <doc> 798 Has the size of data written to corresponding VSC pipe, ie. 799 same thing that is written out to VSC_SIZE_BASE 800 </doc> 801 <reg32 offset="0x0" name="REG"/> 802 </array> 803 804 <reg32 offset="0x0d08" name="VSC_UNKNOWN_0D08" variants="A7XX-" usage="rp_blit"/> 805 806 <reg32 offset="0x0E10" name="UCHE_UNKNOWN_0E10" variants="A7XX-" usage="cmd"/> 807 <reg32 offset="0x0E11" name="UCHE_UNKNOWN_0E11" variants="A7XX-" usage="cmd"/> 808 <!-- always 0x03200000 ? --> 809 <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12" usage="cmd"/> 810 811 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 --> 812 <bitset name="a6xx_reg_xy" inline="yes"> 813 <bitfield name="X" low="0" high="13" type="uint"/> 814 <bitfield name="Y" low="16" high="29" type="uint"/> 815 </bitset> 816 817 <reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit"> 818 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/> 819 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/> 820 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/> 821 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> 822 <!-- controls near z clip behavior (set for vulkan) --> 823 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/> 824 <!-- guess based on a3xx and meaning of bits 8 and 9 825 if the guess is right then this is related to point sprite clipping --> 826 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/> 827 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/> 828 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/> 829 </reg32> 830 831 <bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes"> 832 <bitfield name="CLIP_MASK" low="0" high="7"/> 833 <bitfield name="CULL_MASK" low="8" high="15"/> 834 </bitset> 835 <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 836 <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 837 <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 838 <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit"/> 839 840 <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" usage="rp_blit"> 841 <!-- see also RB_INTERP_CNTL --> 842 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 843 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 844 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 845 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 846 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 847 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 848 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 849 <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/> 850 <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/> 851 </reg32> 852 <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit"> 853 <bitfield name="HORZ" low="0" high="8" type="uint"/> 854 <bitfield name="VERT" low="10" high="18" type="uint"/> 855 </reg32> 856 857 <!-- Something connected to depth-stencil attachment size --> 858 <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/> 859 860 <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/> 861 862 <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/> 863 <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/> 864 <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/> 865 <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/> 866 867 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> --> 868 869 <!-- 0x8006-0x800f invalid --> 870 <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" usage="rp_blit"> 871 <reg32 offset="0" name="XOFFSET" type="float"/> 872 <reg32 offset="1" name="XSCALE" type="float"/> 873 <reg32 offset="2" name="YOFFSET" type="float"/> 874 <reg32 offset="3" name="YSCALE" type="float"/> 875 <reg32 offset="4" name="ZOFFSET" type="float"/> 876 <reg32 offset="5" name="ZSCALE" type="float"/> 877 </array> 878 <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" usage="rp_blit"> 879 <reg32 offset="0" name="MIN" type="float"/> 880 <reg32 offset="1" name="MAX" type="float"/> 881 </array> 882 883 <reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit"> 884 <bitfield name="CULL_FRONT" pos="0" type="boolean"/> 885 <bitfield name="CULL_BACK" pos="1" type="boolean"/> 886 <bitfield name="FRONT_CW" pos="2" type="boolean"/> 887 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/> 888 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/> 889 <bitfield name="UNK12" pos="12"/> 890 <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/> 891 <bitfield name="UNK15" low="15" high="16"/> 892 <!-- 893 On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have 894 the ability to add the view index to either the RT array 895 index or the viewport index, and it seems that 896 MULTIVIEW_ENABLE doesn't do anything, instead we need to 897 set at least one of RENDERTARGETINDEXINCR or 898 VIEWPORTINDEXINCR to enable multiview. The blob still 899 sets MULTIVIEW_ENABLE regardless. 900 TODO: what about gen2 (a640)? 901 --> 902 <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/> 903 <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/> 904 <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/> 905 <bitfield name="UNK20" low="20" high="22"/> 906 </reg32> 907 <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit"> 908 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> 909 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> 910 </reg32> 911 <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="rp_blit"/> 912 <!-- 0x8093 invalid --> 913 <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit"> 914 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 915 </reg32> 916 <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/> 917 <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/> 918 <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/> 919 <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 920 <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit"> 921 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 922 <bitfield name="UNK3" pos="3"/> 923 </reg32> 924 925 <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd"> 926 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 927 <enum name="a6xx_shift_amount"> 928 <value value="0" name="NO_SHIFT"/> 929 <value value="1" name="HALF_PIXEL_SHIFT"/> 930 <value value="2" name="FULL_PIXEL_SHIFT"/> 931 </enum> 932 <bitfield name="SHIFTAMOUNT" low="1" high="2" type="a6xx_shift_amount"/> 933 <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/> 934 <bitfield name="UNK4" low="4" high="5"/> 935 </reg32> 936 <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL"> 937 <bitfield name="UNK0" pos="0" type="boolean"/> 938 <bitfield name="LINELENGTHEN" pos="1" type="boolean"/> 939 </reg32> 940 941 <bitset name="a6xx_gras_us_xs_siv_cntl" inline="yes"> 942 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/> 943 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/> 944 </bitset> 945 <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 946 <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 947 <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 948 <!-- 0x809e/0x809f invalid --> 949 950 <enum name="a6xx_sequenced_thread_dist"> 951 <value value="0x0" name="DIST_SCREEN_COORD"/> 952 <value value="0x1" name="DIST_ALL_TO_RB0"/> 953 </enum> 954 955 <enum name="a6xx_single_prim_mode"> 956 <value value="0x0" name="NO_FLUSH"/> 957 <doc> 958 In addition to FLUSH_PER_OVERLAP, guarantee that UCHE 959 and CCU don't get out of sync when fetching the previous 960 value for the current pixel. With NO_FLUSH, there's the 961 possibility that the flags for the current pixel are 962 flushed before the data or vice-versa, leading to 963 texture fetches via UCHE getting out of sync values. 964 This mode should eliminate that. It's used in bypass 965 mode for coherent blending 966 (GL_KHR_blend_equation_advanced_coherent) as well as 967 non-coherent blending. 968 </doc> 969 <value value="0x1" name="FLUSH_PER_OVERLAP_AND_OVERWRITE"/> 970 <doc> 971 Invalidate UCHE and wait for any pending work to finish 972 if there was possibly an overlapping primitive prior to 973 the current one. This is similar to a combination of 974 GRAS_SC_CONTROL::INJECT_L2_INVALIDATE_EVENT and 975 WAIT_RB_IDLE_ALL_TRI on a3xx. It's used in GMEM mode for 976 coherent blending 977 (GL_KHR_blend_equation_advanced_coherent). 978 </doc> 979 <value value="0x3" name="FLUSH_PER_OVERLAP"/> 980 </enum> 981 982 <!-- this probably has the same meaning as a3xx GRAS_SC_CONTROL::RASTER_MODE --> 983 <enum name="a6xx_raster_mode"> 984 <value value="0x0" name="TYPE_TILED"/> 985 <value value="0x1" name="TYPE_WRITER"/> 986 </enum> 987 988 <!-- I'm guessing this is the same as a3xx --> 989 <enum name="a6xx_raster_direction"> 990 <value value="0x0" name="LR_TB"/> 991 <value value="0x1" name="RL_TB"/> 992 <value value="0x2" name="LR_BT"/> 993 <value value="0x3" name="RB_BT"/> 994 </enum> 995 996 <reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit"> 997 <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/> 998 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/> 999 <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/> 1000 <bitfield name="RASTER_DIRECTION" low="6" high="7" type="a6xx_raster_direction"/> 1001 <bitfield name="SEQUENCED_THREAD_DISTRIBUTION" pos="8" type="a6xx_sequenced_thread_dist"/> 1002 <!-- CCUSINGLECACHELINESIZE is ignored unless bit 9 is set --> 1003 <bitfield name="UNK9" pos="9" type="boolean"/> 1004 <bitfield name="ROTATION" low="10" high="11" type="uint"/> 1005 <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/> 1006 </reg32> 1007 1008 <enum name="a6xx_render_mode"> 1009 <value value="0x0" name="RENDERING_PASS"/> 1010 <value value="0x1" name="BINNING_PASS"/> 1011 </enum> 1012 1013 <enum name="a6xx_buffers_location"> 1014 <value value="0" name="BUFFERS_IN_GMEM"/> 1015 <value value="3" name="BUFFERS_IN_SYSMEM"/> 1016 </enum> 1017 1018 <enum name="a6xx_lrz_feedback_mask"> 1019 <value value="0x0" name="LRZ_FEEDBACK_NONE"/> 1020 <value value="0x1" name="LRZ_FEEDBACK_EARLY_Z"/> 1021 <value value="0x2" name="LRZ_FEEDBACK_EARLY_Z_LATE_Z"/> 1022 <!-- We don't have a flag type and this flags combination is often used --> 1023 <value value="0x3" name="LRZ_FEEDBACK_EARLY_Z_OR_EARLY_Z_LATE_Z"/> 1024 <value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/> 1025 </enum> 1026 1027 <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" usage="rp_blit"> 1028 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1029 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1030 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1031 <doc>Disable LRZ feedback writes</doc> 1032 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1033 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location" variants="A6XX"/> 1034 <doc> 1035 Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have 1036 GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. 1037 In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. 1038 </doc> 1039 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1040 <bitfield name="UNK27" pos="27"/> 1041 </reg32> 1042 1043 <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" usage="rp_blit"> 1044 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1045 <bitfield name="UNK2" pos="2"/> 1046 <bitfield name="UNK3" pos="3"/> 1047 </reg32> 1048 <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" usage="rp_blit"> 1049 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1050 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1051 </reg32> 1052 1053 <bitset name="a6xx_msaa_sample_pos_cntl" inline="yes"> 1054 <bitfield name="UNK0" pos="0"/> 1055 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/> 1056 </bitset> 1057 1058 <bitset name="a6xx_programmable_msaa_pos" inline="yes"> 1059 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/> 1060 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/> 1061 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/> 1062 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/> 1063 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/> 1064 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/> 1065 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/> 1066 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/> 1067 </bitset> 1068 1069 <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 1070 <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1071 <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1072 1073 <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/> 1074 1075 <!-- 0x80a7-0x80ae invalid --> 1076 <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/> 1077 1078 <bitset name="a6xx_scissor_xy" inline="yes"> 1079 <bitfield name="X" low="0" high="15" type="uint"/> 1080 <bitfield name="Y" low="16" high="31" type="uint"/> 1081 </bitset> 1082 <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit"> 1083 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1084 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1085 </array> 1086 <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit"> 1087 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1088 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1089 </array> 1090 1091 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1092 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1093 1094 <enum name="a6xx_fsr_combiner"> 1095 <value value="0" name="FSR_COMBINER_OP_KEEP"/> 1096 <value value="1" name="FSR_COMBINER_OP_REPLACE"/> 1097 <value value="2" name="FSR_COMBINER_OP_MIN"/> 1098 <value value="3" name="FSR_COMBINER_OP_MAX"/> 1099 <value value="4" name="FSR_COMBINER_OP_MUL"/> 1100 </enum> 1101 1102 <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" variants="A7XX-" usage="rp_blit"> 1103 <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 1104 <bitfield name="FRAG_SIZE_X" low="1" high="2" type="uint"/> 1105 <bitfield name="FRAG_SIZE_Y" low="3" high="4" type="uint"/> 1106 <bitfield name="COMBINER_OP_1" low="5" high="7" type="a6xx_fsr_combiner"/> 1107 <bitfield name="COMBINER_OP_2" low="8" high="10" type="a6xx_fsr_combiner"/> 1108 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="13" type="boolean"/> 1109 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="20" type="boolean"/> 1110 </reg32> 1111 <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1112 <bitfield name="LAYERED" pos="0" type="boolean"/> 1113 <bitfield name="TILE_MODE" low="1" high="2" type="a6xx_tile_mode"/> 1114 </reg32> 1115 <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" variants="A7XX-" usage="rp_blit"> 1116 <bitfield name="WIDTH" low="0" high="15" type="uint"/> 1117 <bitfield name="HEIGHT" low="16" high="31" type="uint"/> 1118 </reg32> 1119 <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX-" type="waddress" usage="rp_blit"/> 1120 <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" variants="A7XX-" usage="rp_blit"> 1121 <bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/> 1122 <bitfield name="ARRAY_PITCH" shr="6" low="10" high="28" type="uint"/> 1123 </reg32> 1124 1125 <enum name="a6xx_lrz_dir_status"> 1126 <value value="0x1" name="LRZ_DIR_LE"/> 1127 <value value="0x2" name="LRZ_DIR_GE"/> 1128 <value value="0x3" name="LRZ_DIR_INVALID"/> 1129 </enum> 1130 1131 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit"> 1132 <bitfield name="ENABLE" pos="0" type="boolean"/> 1133 <doc>LRZ write also disabled for blend/etc.</doc> 1134 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> 1135 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc> 1136 <bitfield name="GREATER" pos="2" type="boolean"/> 1137 <doc> 1138 Clears the LRZ block being touched to: 1139 - 0.0 if GREATER 1140 - 1.0 if LESS 1141 </doc> 1142 <bitfield name="FC_ENABLE" pos="3" type="boolean" variants="A6XX"/> 1143 <!-- set when depth-test + depth-write enabled --> 1144 <bitfield name="Z_WRITE_ENABLE" pos="4" type="boolean"/> 1145 <bitfield name="Z_BOUNDS_ENABLE" pos="5" type="boolean"/> 1146 <bitfield name="DIR" low="6" high="7" type="a6xx_lrz_dir_status"/> 1147 <doc> 1148 If DISABLE_ON_WRONG_DIR enabled - write new LRZ direction into 1149 buffer, in case of mismatched direction writes 0 (disables LRZ). 1150 </doc> 1151 <bitfield name="DIR_WRITE" pos="8" type="boolean"/> 1152 <doc> 1153 Disable LRZ based on previous direction and the current one. 1154 If DIR_WRITE is not enabled - there is no write to direction buffer. 1155 </doc> 1156 <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/> 1157 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/> 1158 </reg32> 1159 1160 <enum name="a6xx_fragcoord_sample_mode"> 1161 <value value="0" name="FRAGCOORD_CENTER"/> 1162 <value value="3" name="FRAGCOORD_SAMPLE"/> 1163 </enum> 1164 1165 <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit"> 1166 <bitfield name="SAMPLEID" pos="0" type="boolean"/> 1167 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/> 1168 </reg32> 1169 1170 <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" usage="rp_blit"> 1171 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1172 </reg32> 1173 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/> 1174 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit"> 1175 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/> 1176 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="8" type="uint"/> 1177 </reg32> 1178 1179 <!-- 1180 The LRZ "fast clear" buffer is initialized to zero's by blob, and 1181 read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears 1182 to store 1b/block. It appears that '0' means block has original 1183 depth clear value, and '1' means that the corresponding block in 1184 LRZ has been modified. Ignoring alignment/padding, the size is 1185 given by the formula: 1186 1187 // calculate LRZ size from depth size: 1188 if (nr_samples == 4) { 1189 width *= 2; 1190 height *= 2; 1191 } else if (nr_samples == 2) { 1192 height *= 2; 1193 } 1194 1195 lrz_width = div_round_up(width, 8); 1196 lrz_heigh = div_round_up(height, 8); 1197 1198 // calculate # of blocks: 1199 nblocksx = div_round_up(lrz_width, 16); 1200 nblocksy = div_round_up(lrz_height, 4); 1201 1202 // fast-clear buffer is 1bit/block: 1203 fc_sz = div_round_up(nblocksx * nblocksy, 8); 1204 1205 In practice the blob seems to switch off FC_ENABLE once the size 1206 increases beyond 1 page. Not sure if that is an actual limit or 1207 not. 1208 --> 1209 <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/> 1210 <!-- 0x8108 invalid --> 1211 <reg32 offset="0x8109" name="GRAS_LRZ_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> 1212 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 1213 </reg32> 1214 <!-- 1215 LRZ buffer represents a single array layer + mip level, and there is 1216 a single buffer per depth image. Thus to reuse LRZ between renderpasses 1217 it is necessary to track the depth view used in the past renderpass, which 1218 GRAS_LRZ_VIEW_INFO is for. 1219 GRAS_LRZ_CNTL checks if current value of GRAS_LRZ_VIEW_INFO is equal to 1220 the value stored in the LRZ buffer, if not - LRZ is disabled. 1221 --> 1222 <reg32 offset="0x810a" name="GRAS_LRZ_VIEW_INFO" usage="cmd"> 1223 <bitfield name="BASE_LAYER" low="0" high="10" type="uint"/> 1224 <bitfield name="LAYER_COUNT" low="16" high="26" type="uint"/> 1225 <bitfield name="BASE_MIP_LEVEL" low="28" high="31" type="uint"/> 1226 </reg32> 1227 1228 <reg32 offset="0x810b" name="GRAS_LRZ_CNTL2" variants="A7XX-" usage="rp_blit"> 1229 <bitfield name="DISABLE_ON_WRONG_DIR" pos="0" type="boolean"/> 1230 <bitfield name="FC_ENABLE" pos="1" type="boolean"/> 1231 </reg32> 1232 1233 <!-- 0x810c-0x810f invalid --> 1234 1235 <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/> 1236 1237 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR --> 1238 <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX-"/> 1239 1240 <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1241 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1242 <bitfield name="UNK3" pos="3"/> 1243 </reg32> 1244 1245 <!-- Always written together and always equal 09510840 00000a62 --> 1246 <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/> 1247 <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/> 1248 1249 <!-- 0x8112-0x83ff invalid --> 1250 1251 <enum name="a6xx_rotation"> 1252 <value value="0x0" name="ROTATE_0"/> 1253 <value value="0x1" name="ROTATE_90"/> 1254 <value value="0x2" name="ROTATE_180"/> 1255 <value value="0x3" name="ROTATE_270"/> 1256 <value value="0x4" name="ROTATE_HFLIP"/> 1257 <value value="0x5" name="ROTATE_VFLIP"/> 1258 </enum> 1259 1260 <bitset name="a6xx_a2d_bit_cntl" inline="yes"> 1261 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/> 1262 <bitfield name="OVERWRITEEN" pos="3" type="boolean"/> 1263 <bitfield name="UNK4" low="4" high="6"/> 1264 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/> 1265 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/> 1266 <bitfield name="SCISSOR" pos="16" type="boolean"/> 1267 <bitfield name="UNK17" low="17" high="18"/> 1268 <!-- required when blitting D24S8/D24X8 --> 1269 <bitfield name="D24S8" pos="19" type="boolean"/> 1270 <!-- some sort of channel mask, disabled channels are set to zero ? --> 1271 <bitfield name="MASK" low="20" high="23"/> 1272 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/> 1273 <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/> 1274 <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/> 1275 </bitset> 1276 1277 <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/> 1278 <!-- note: the low 8 bits for src coords are valid, probably fixed point 1279 it would be a bit weird though, since we subtract 1 from BR coords 1280 apparently signed, gallium driver uses negative coords and it works? 1281 --> 1282 <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" usage="rp_blit"/> 1283 <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" usage="rp_blit"/> 1284 <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" usage="rp_blit"/> 1285 <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" usage="rp_blit"/> 1286 <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1287 <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1288 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/> 1289 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/> 1290 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/> 1291 <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1292 <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1293 <!-- 0x840c-0x85ff invalid --> 1294 1295 <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> 1296 <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd"> 1297 <bitfield name="UNK7" pos="7" type="boolean"/> 1298 <bitfield name="LRZCACHELOCKDIS" pos="11" type="boolean"/> 1299 </reg32> 1300 <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 1301 <reg32 offset="0x8602" name="GRAS_NC_MODE_CNTL" variants="A7XX-"/> 1302 <array offset="0x8610" name="GRAS_PERFCTR_TSE_SEL" stride="1" length="4"/> 1303 <array offset="0x8614" name="GRAS_PERFCTR_RAS_SEL" stride="1" length="4"/> 1304 <array offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL" stride="1" length="4"/> 1305 1306 <!-- note 0x8620-0x87ff are not all invalid 1307 (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords) 1308 --> 1309 1310 <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> 1311 <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX" usage="rp_blit"> 1312 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1313 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1314 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1315 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1316 <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/> 1317 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1318 </reg32> 1319 1320 <reg32 offset="0x8800" name="RB_CNTL" variants="A7XX-" usage="rp_blit"> 1321 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1322 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1323 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1324 <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1325 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1326 </reg32> 1327 1328 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit"> 1329 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> 1330 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 1331 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1332 <bitfield name="UNK8" low="8" high="10"/> 1333 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 1334 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 1335 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 1336 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 1337 <!-- bit seems to be set whenever depth buffer enabled: --> 1338 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/> 1339 <!-- bitmask of MRTs using UBWC flag buffer: --> 1340 <bitfield name="FLAG_MRTS" low="16" high="23"/> 1341 </reg32> 1342 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 1343 <bitfield name="EARLYVIZOUTEN" pos="6" type="boolean"/> 1344 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1345 <bitfield name="RASTER_MODE" pos="8" type="a6xx_raster_mode"/> 1346 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 1347 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 1348 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 1349 </reg32> 1350 <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 1351 <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1352 </reg32> 1353 1354 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit"> 1355 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1356 <bitfield name="UNK2" pos="2"/> 1357 <bitfield name="UNK3" pos="3"/> 1358 </reg32> 1359 <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL" usage="rp_blit"> 1360 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1361 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1362 </reg32> 1363 1364 <reg32 offset="0x8804" name="RB_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 1365 <reg32 offset="0x8805" name="RB_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1366 <reg32 offset="0x8806" name="RB_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1367 <!-- 0x8807-0x8808 invalid --> 1368 <!-- 1369 note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL 1370 name comes from kernel and is probably right) 1371 --> 1372 <reg32 offset="0x8809" name="RB_INTERP_CNTL" usage="rp_blit"> 1373 <!-- see also GRAS_CL_INTERP_CNTL --> 1374 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 1375 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> 1376 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/> 1377 <bitfield name="IJ_LINEAR_PIXEL" pos="3" type="boolean"/> 1378 <bitfield name="IJ_LINEAR_CENTROID" pos="4" type="boolean"/> 1379 <bitfield name="IJ_LINEAR_SAMPLE" pos="5" type="boolean"/> 1380 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 1381 <bitfield name="UNK10" pos="10" type="boolean"/> 1382 </reg32> 1383 <reg32 offset="0x880a" name="RB_PS_INPUT_CNTL" usage="rp_blit"> 1384 <!-- enable bits for various FS sysvalue regs: --> 1385 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/> 1386 <bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/> 1387 <bitfield name="FACENESS" pos="2" type="boolean"/> 1388 <bitfield name="SAMPLEID" pos="3" type="boolean"/> 1389 <bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/> 1390 <bitfield name="CENTERRHW" pos="6" type="boolean"/> 1391 <bitfield name="LINELENGTHEN" pos="7" type="boolean"/> 1392 <bitfield name="FOVEATION" pos="8" type="boolean"/> 1393 </reg32> 1394 1395 <reg32 offset="0x880b" name="RB_PS_OUTPUT_CNTL" usage="rp_blit"> 1396 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 1397 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/> 1398 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/> 1399 <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/> 1400 </reg32> 1401 <reg32 offset="0x880c" name="RB_PS_MRT_CNTL" usage="rp_blit"> 1402 <bitfield name="MRT" low="0" high="3" type="uint"/> 1403 </reg32> 1404 <reg32 offset="0x880d" name="RB_PS_OUTPUT_MASK" usage="rp_blit"> 1405 <bitfield name="RT0" low="0" high="3"/> 1406 <bitfield name="RT1" low="4" high="7"/> 1407 <bitfield name="RT2" low="8" high="11"/> 1408 <bitfield name="RT3" low="12" high="15"/> 1409 <bitfield name="RT4" low="16" high="19"/> 1410 <bitfield name="RT5" low="20" high="23"/> 1411 <bitfield name="RT6" low="24" high="27"/> 1412 <bitfield name="RT7" low="28" high="31"/> 1413 </reg32> 1414 <reg32 offset="0x880e" name="RB_DITHER_CNTL" usage="cmd"> 1415 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> 1416 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> 1417 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> 1418 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> 1419 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> 1420 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> 1421 <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/> 1422 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> 1423 </reg32> 1424 <reg32 offset="0x880f" name="RB_SRGB_CNTL" usage="rp_blit"> 1425 <!-- Same as SP_SRGB_CNTL --> 1426 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 1427 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 1428 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 1429 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 1430 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 1431 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 1432 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 1433 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 1434 </reg32> 1435 1436 <reg32 offset="0x8810" name="RB_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> 1437 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 1438 </reg32> 1439 <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6" usage="cmd"/> 1440 <reg32 offset="0x8812" name="RB_UNKNOWN_8812" variants="A7XX-" usage="rp_blit"/> 1441 <!-- 0x8813-0x8817 invalid --> 1442 <!-- always 0x0 ? --> 1443 <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6" usage="cmd"/> 1444 <!-- 0x8819-0x881e all 32 bits --> 1445 <reg32 offset="0x8819" name="RB_UNKNOWN_8819" usage="cmd"/> 1446 <reg32 offset="0x881a" name="RB_UNKNOWN_881A" usage="cmd"/> 1447 <reg32 offset="0x881b" name="RB_UNKNOWN_881B" usage="cmd"/> 1448 <reg32 offset="0x881c" name="RB_UNKNOWN_881C" usage="cmd"/> 1449 <reg32 offset="0x881d" name="RB_UNKNOWN_881D" usage="cmd"/> 1450 <reg32 offset="0x881e" name="RB_UNKNOWN_881E" usage="cmd"/> 1451 <!-- 0x881f invalid --> 1452 <array offset="0x8820" name="RB_MRT" stride="8" length="8" usage="rp_blit"> 1453 <reg32 offset="0x0" name="CONTROL"> 1454 <bitfield name="BLEND" pos="0" type="boolean"/> 1455 <bitfield name="BLEND2" pos="1" type="boolean"/> 1456 <bitfield name="ROP_ENABLE" pos="2" type="boolean"/> 1457 <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/> 1458 <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/> 1459 </reg32> 1460 <reg32 offset="0x1" name="BLEND_CONTROL"> 1461 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/> 1462 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/> 1463 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/> 1464 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/> 1465 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/> 1466 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/> 1467 </reg32> 1468 <reg32 offset="0x2" name="BUF_INFO" variants="A6XX"> 1469 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1470 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 1471 <bitfield name="UNK10" pos="10"/> 1472 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> 1473 </reg32> 1474 <reg32 offset="0x2" name="BUF_INFO" variants="A7XX-"> 1475 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1476 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 1477 <bitfield name="UNK10" pos="10"/> 1478 <bitfield name="LOSSLESSCOMPEN" pos="11" type="boolean"/> 1479 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/> 1480 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/> 1481 </reg32> 1482 <!-- 1483 at least in gmem, things seem to be aligned to pitch of 64.. 1484 maybe an artifact of tiled format used in gmem? 1485 --> 1486 <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/> 1487 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/> 1488 <!-- 1489 Compared to a5xx and before, we configure both a GMEM base and 1490 external base. Not sure if this is to facilitate GMEM save/ 1491 restore for context switch, or just to simplify state setup to 1492 not have to care about GMEM vs BYPASS mode. 1493 --> 1494 <!-- maybe something in low bits since alignment of 1 doesn't make sense? --> 1495 <reg64 offset="0x5" name="BASE" type="waddress" align="1"/> 1496 1497 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/> 1498 </array> 1499 1500 <reg32 offset="0x8860" name="RB_BLEND_CONSTANT_RED_FP32" type="float" usage="rp_blit"/> 1501 <reg32 offset="0x8861" name="RB_BLEND_CONSTANT_GREEN_FP32" type="float" usage="rp_blit"/> 1502 <reg32 offset="0x8862" name="RB_BLEND_CONSTANT_BLUE_FP32" type="float" usage="rp_blit"/> 1503 <reg32 offset="0x8863" name="RB_BLEND_CONSTANT_ALPHA_FP32" type="float" usage="rp_blit"/> 1504 <reg32 offset="0x8864" name="RB_ALPHA_TEST_CNTL" usage="cmd"> 1505 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/> 1506 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/> 1507 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/> 1508 </reg32> 1509 <reg32 offset="0x8865" name="RB_BLEND_CNTL" usage="rp_blit"> 1510 <!-- per-mrt enable bit --> 1511 <bitfield name="BLEND_READS_DEST" low="0" high="7"/> 1512 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/> 1513 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 1514 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 1515 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/> 1516 <bitfield name="SAMPLE_MASK" low="16" high="31"/> 1517 </reg32> 1518 <!-- 0x8866-0x886f invalid --> 1519 <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" usage="rp_blit"> 1520 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 1521 </reg32> 1522 1523 <reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit"> 1524 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 1525 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/> 1526 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/> 1527 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/> 1528 <doc> 1529 Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER 1530 also set when Z_BOUNDS_ENABLE is set 1531 </doc> 1532 <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/> 1533 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/> 1534 </reg32> 1535 <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" usage="rp_blit"> 1536 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 1537 </reg32> 1538 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: --> 1539 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" usage="rp_blit"> 1540 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1541 <bitfield name="UNK3" low="3" high="4"/> 1542 </reg32> 1543 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO --> 1544 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1545 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1546 <bitfield name="UNK3" low="3" high="4"/> 1547 <bitfield name="TILEMODE" low="5" high="6" type="a6xx_tile_mode"/> 1548 <bitfield name="LOSSLESSCOMPEN" pos="7" type="boolean"/> 1549 </reg32> 1550 1551 <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint" usage="rp_blit"/> 1552 <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint" usage="rp_blit"/> 1553 <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1554 <reg32 offset="0x8877" name="RB_DEPTH_GMEM_BASE" low="12" high="31" shr="12" usage="rp_blit"/> 1555 1556 <reg32 offset="0x8878" name="RB_DEPTH_BOUND_MIN" type="float" usage="rp_blit"/> 1557 <reg32 offset="0x8879" name="RB_DEPTH_BOUND_MAX" type="float" usage="rp_blit"/> 1558 <!-- 0x887a-0x887f invalid --> 1559 <reg32 offset="0x8880" name="RB_STENCIL_CNTL" usage="rp_blit"> 1560 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 1561 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/> 1562 <!-- 1563 set for stencil operations that require read from stencil 1564 buffer, but not for example for stencil clear (which does 1565 not require read).. so guessing this is analogous to 1566 READ_DEST_ENABLE for color buffer.. 1567 --> 1568 <bitfield name="STENCIL_READ" pos="2" type="boolean"/> 1569 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/> 1570 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/> 1571 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/> 1572 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/> 1573 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/> 1574 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/> 1575 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> 1576 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> 1577 </reg32> 1578 <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit"> 1579 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 1580 </reg32> 1581 <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A6XX" usage="rp_blit"> 1582 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 1583 <bitfield name="UNK1" pos="1" type="boolean"/> 1584 </reg32> 1585 <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1586 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 1587 <bitfield name="UNK1" pos="1" type="boolean"/> 1588 <bitfield name="TILEMODE" low="2" high="3" type="a6xx_tile_mode"/> 1589 </reg32> 1590 <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint" usage="rp_blit"/> 1591 <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint" usage="rp_blit"/> 1592 <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1593 <reg32 offset="0x8886" name="RB_STENCIL_GMEM_BASE" low="12" high="31" shr="12" usage="rp_blit"/> 1594 <reg32 offset="0x8887" name="RB_STENCIL_REF_CNTL" usage="rp_blit"> 1595 <bitfield name="REF" low="0" high="7"/> 1596 <bitfield name="BFREF" low="8" high="15"/> 1597 </reg32> 1598 <reg32 offset="0x8888" name="RB_STENCIL_MASK" usage="rp_blit"> 1599 <bitfield name="MASK" low="0" high="7"/> 1600 <bitfield name="BFMASK" low="8" high="15"/> 1601 </reg32> 1602 <reg32 offset="0x8889" name="RB_STENCIL_WRITE_MASK" usage="rp_blit"> 1603 <bitfield name="WRMASK" low="0" high="7"/> 1604 <bitfield name="BFWRMASK" low="8" high="15"/> 1605 </reg32> 1606 <!-- 0x888a-0x888f invalid --> 1607 <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 1608 <reg32 offset="0x8891" name="RB_SAMPLE_COUNTER_CNTL" usage="cmd"> 1609 <bitfield name="DISABLE" pos="0" type="boolean"/> 1610 <bitfield name="COPY" pos="1" type="boolean"/> 1611 </reg32> 1612 <!-- 0x8892-0x8897 invalid --> 1613 <reg32 offset="0x8898" name="RB_LRZ_CNTL" usage="rp_blit"> 1614 <bitfield name="ENABLE" pos="0" type="boolean"/> 1615 </reg32> 1616 <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/> 1617 <!-- 0x8899-0x88bf invalid --> 1618 <!-- clamps depth value for depth test/write --> 1619 <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit"/> 1620 <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit"/> 1621 <!-- 0x88c2-0x88cf invalid--> 1622 <reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="rp_blit"> 1623 <bitfield name="UNK0" low="0" high="12"/> 1624 <bitfield name="UNK16" low="16" high="26"/> 1625 </reg32> 1626 <reg32 offset="0x88d1" name="RB_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/> 1627 <reg32 offset="0x88d2" name="RB_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/> 1628 <!-- weird to duplicate other regs from same block?? --> 1629 <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" usage="rp_blit"> 1630 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1631 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1632 </reg32> 1633 <reg32 offset="0x88d4" name="RB_RESOLVE_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 1634 <reg32 offset="0x88d5" name="RB_RESOLVE_GMEM_BUFFER_INFO" usage="rp_blit"> 1635 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 1636 </reg32> 1637 <reg32 offset="0x88d6" name="RB_RESOLVE_GMEM_BUFFER_BASE" low="12" high="31" shr="12" usage="rp_blit"/> 1638 <!-- s/DST_FORMAT/DST_INFO/ probably: --> 1639 <reg32 offset="0x88d7" name="RB_RESOLVE_SYSTEM_BUFFER_INFO" usage="rp_blit"> 1640 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 1641 <bitfield name="FLAGS" pos="2" type="boolean"/> 1642 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/> 1643 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/> 1644 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/> 1645 <bitfield name="UNK15" pos="15" type="boolean"/> 1646 <bitfield name="MUTABLEEN" pos="16" type="boolean" variants="A7XX-"/> 1647 </reg32> 1648 <reg64 offset="0x88d8" name="RB_RESOLVE_SYSTEM_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1649 <reg32 offset="0x88da" name="RB_RESOLVE_SYSTEM_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 1650 <!-- array-pitch is size of layer --> 1651 <reg32 offset="0x88db" name="RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/> 1652 <reg64 offset="0x88dc" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1653 <reg32 offset="0x88de" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH" usage="rp_blit"> 1654 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1655 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 1656 </reg32> 1657 1658 <reg32 offset="0x88df" name="RB_RESOLVE_CLEAR_COLOR_DW0" usage="rp_blit"/> 1659 <reg32 offset="0x88e0" name="RB_RESOLVE_CLEAR_COLOR_DW1" usage="rp_blit"/> 1660 <reg32 offset="0x88e1" name="RB_RESOLVE_CLEAR_COLOR_DW2" usage="rp_blit"/> 1661 <reg32 offset="0x88e2" name="RB_RESOLVE_CLEAR_COLOR_DW3" usage="rp_blit"/> 1662 1663 <enum name="a6xx_blit_event_type"> 1664 <value value="0x0" name="BLIT_EVENT_STORE"/> 1665 <value value="0x1" name="BLIT_EVENT_STORE_AND_CLEAR"/> 1666 <value value="0x2" name="BLIT_EVENT_CLEAR"/> 1667 <value value="0x3" name="BLIT_EVENT_LOAD"/> 1668 </enum> 1669 1670 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: --> 1671 <reg32 offset="0x88e3" name="RB_RESOLVE_OPERATION" usage="rp_blit"> 1672 <bitfield name="TYPE" low="0" high="1" type="a6xx_blit_event_type"/> 1673 <bitfield name="SAMPLE_0" pos="2" type="boolean"/> <!-- takes sample 0 instead of averaging --> 1674 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? --> 1675 <doc> 1676 For clearing depth/stencil 1677 1 - depth 1678 2 - stencil 1679 3 - depth+stencil 1680 For clearing color buffer: 1681 then probably a component mask, I always see 0xf 1682 </doc> 1683 <bitfield name="CLEAR_MASK" low="4" high="7"/> 1684 <!-- set when this is the last resolve on a650+ --> 1685 <bitfield name="LAST" low="8" high="9"/> 1686 <!-- 1687 a618 GLES: color render target number being resolved for CCU_RESOLVE, 0x8 for depth, 0x9 for separate stencil. 1688 a618 VK: 0x8 for depth CCU_RESOLVE, 0x9 for separate stencil, 0 otherwise. 1689 a7xx VK: 0x8 for depth, 0x9 for separate stencil, 0x0 to 0x7 used for concurrent resolves of color render 1690 targets inside a given resolve group. 1691 --> 1692 <bitfield name="BUFFER_ID" low="12" high="15"/> 1693 </reg32> 1694 1695 <enum name="a7xx_blit_clear_mode"> 1696 <value value="0x0" name="CLEAR_MODE_SYSMEM"/> 1697 <value value="0x1" name="CLEAR_MODE_GMEM"/> 1698 </enum> 1699 <reg32 offset="0x88e4" name="RB_CLEAR_TARGET" variants="A7XX-" usage="rp_blit"> 1700 <bitfield name="CLEAR_MODE" pos="0" type="a7xx_blit_clear_mode"/> 1701 </reg32> 1702 1703 <enum name="a6xx_ccu_cache_size"> 1704 <value value="0x0" name="CCU_CACHE_SIZE_FULL"/> 1705 <value value="0x1" name="CCU_CACHE_SIZE_HALF"/> 1706 <value value="0x2" name="CCU_CACHE_SIZE_QUARTER"/> 1707 <value value="0x3" name="CCU_CACHE_SIZE_EIGHTH"/> 1708 </enum> 1709 <reg32 offset="0x88e5" name="RB_CCU_CACHE_CNTL" variants="A7XX-" usage="cmd"> 1710 <bitfield name="DEPTH_OFFSET_HI" pos="0" type="hex"/> 1711 <bitfield name="COLOR_OFFSET_HI" pos="2" type="hex"/> 1712 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> 1713 <!-- GMEM offset of CCU depth cache --> 1714 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/> 1715 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/> 1716 <!-- GMEM offset of CCU color cache 1717 for GMEM rendering, we set it to GMEM size minus the minimum 1718 CCU color cache size. CCU color cache will be needed in some 1719 resolve cases, and in those cases we need to reserve the end 1720 of GMEM for color cache. 1721 --> 1722 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 1723 </reg32> 1724 <!-- 0x88e6-0x88ef invalid --> 1725 <!-- always 0x0 ? --> 1726 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/> 1727 <!-- could be for separate stencil? (or may not be a flag buffer at all) --> 1728 <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/> 1729 <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH"> 1730 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1731 <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/> 1732 </reg32> 1733 1734 <reg32 offset="0x88f4" name="RB_VRS_CONFIG" usage="rp_blit"> 1735 <bitfield name="UNK2" pos="2" type="boolean"/> 1736 <bitfield name="PIPELINE_FSR_ENABLE" pos="4" type="boolean"/> 1737 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="5" type="boolean"/> 1738 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="18" type="boolean"/> 1739 </reg32> 1740 <!-- Connected to VK_EXT_fragment_density_map? --> 1741 <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/> 1742 <!-- 0x88f6-0x88ff invalid --> 1743 <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1744 <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit"> 1745 <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/> 1746 <!-- TODO: actually part of array pitch --> 1747 <bitfield name="UNK8" low="8" high="10"/> 1748 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 1749 </reg32> 1750 <array offset="0x8903" name="RB_COLOR_FLAG_BUFFER" stride="3" length="8" usage="rp_blit"> 1751 <reg64 offset="0" name="ADDR" type="waddress" align="64"/> 1752 <reg32 offset="2" name="PITCH"> 1753 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1754 <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/> 1755 </reg32> 1756 </array> 1757 <!-- 0x891b-0x8926 invalid --> 1758 <doc> 1759 RB_SAMPLE_COUNTER_BASE register is used up to (and including) a730. After that 1760 the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. 1761 </doc> 1762 <reg64 offset="0x8927" name="RB_SAMPLE_COUNTER_BASE" type="waddress" align="16" usage="cmd"/> 1763 <!-- 0x8929-0x89ff invalid --> 1764 1765 <!-- TODO: there are some registers in the 0x8a00-0x8bff range --> 1766 1767 <!-- 1768 These show up in a6xx gen3+ but so far haven't found an example of 1769 blob writing non-zero: 1770 --> 1771 <reg32 offset="0x8a00" name="RB_UNKNOWN_8A00" variants="A6XX" usage="rp_blit"/> 1772 <reg32 offset="0x8a10" name="RB_UNKNOWN_8A10" variants="A6XX" usage="rp_blit"/> 1773 <reg32 offset="0x8a20" name="RB_UNKNOWN_8A20" variants="A6XX" usage="rp_blit"/> 1774 <reg32 offset="0x8a30" name="RB_UNKNOWN_8A30" variants="A6XX" usage="rp_blit"/> 1775 1776 <reg32 offset="0x8c00" name="RB_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/> 1777 <reg32 offset="0x8c01" name="RB_A2D_PIXEL_CNTL" low="0" high="31" usage="rp_blit"/> 1778 1779 <bitset name="a6xx_a2d_src_texture_info" inline="yes"> 1780 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1781 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 1782 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> 1783 <bitfield name="FLAGS" pos="12" type="boolean"/> 1784 <bitfield name="SRGB" pos="13" type="boolean"/> 1785 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> 1786 <bitfield name="FILTER" pos="16" type="boolean"/> 1787 <bitfield name="UNK17" pos="17" type="boolean"/> 1788 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/> 1789 <bitfield name="UNK19" pos="19" type="boolean"/> 1790 <bitfield name="UNK20" pos="20" type="boolean"/> 1791 <bitfield name="UNK21" pos="21" type="boolean"/> 1792 <bitfield name="UNK22" pos="22" type="boolean"/> 1793 <bitfield name="UNK23" low="23" high="26"/> 1794 <bitfield name="UNK28" pos="28" type="boolean"/> 1795 <bitfield name="MUTABLEEN" pos="29" type="boolean" variants="A7XX-"/> 1796 </bitset> 1797 1798 <bitset name="a6xx_a2d_dest_buffer_info" inline="yes"> 1799 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1800 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/> 1801 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/> 1802 <bitfield name="FLAGS" pos="12" type="boolean"/> 1803 <bitfield name="SRGB" pos="13" type="boolean"/> 1804 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/> 1805 <bitfield name="MUTABLEEN" pos="17" type="boolean" variants="A7XX-"/> 1806 </bitset> 1807 1808 <!-- 0x8c02-0x8c16 invalid --> 1809 <reg32 offset="0x8c17" name="RB_A2D_DEST_BUFFER_INFO" type="a6xx_a2d_dest_buffer_info" usage="rp_blit"/> 1810 <reg64 offset="0x8c18" name="RB_A2D_DEST_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1811 <reg32 offset="0x8c1a" name="RB_A2D_DEST_BUFFER_PITCH" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 1812 <!-- this is a guess but seems likely (for NV12/IYUV): --> 1813 <reg64 offset="0x8c1b" name="RB_A2D_DEST_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> 1814 <reg32 offset="0x8c1d" name="RB_A2D_DEST_BUFFER_PITCH_1" low="0" high="15" shr="6" type="uint" usage="rp_blit"/> 1815 <reg64 offset="0x8c1e" name="RB_A2D_DEST_BUFFER_BASE_2" type="waddress" align="64" usage="rp_blit"/> 1816 1817 <reg64 offset="0x8c20" name="RB_A2D_DEST_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1818 <reg32 offset="0x8c22" name="RB_A2D_DEST_FLAG_BUFFER_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 1819 <!-- this is a guess but seems likely (for NV12 with UBWC): --> 1820 <reg64 offset="0x8c23" name="RB_A2D_DEST_FLAG_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> 1821 <reg32 offset="0x8c25" name="RB_A2D_DEST_FLAG_BUFFER_PITCH_1" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 1822 1823 <!-- TODO: 0x8c26-0x8c33 are all full 32-bit registers --> 1824 <!-- unlike a5xx, these are per channel values rather than packed --> 1825 <reg32 offset="0x8c2c" name="RB_A2D_CLEAR_COLOR_DW0" usage="rp_blit"/> 1826 <reg32 offset="0x8c2d" name="RB_A2D_CLEAR_COLOR_DW1" usage="rp_blit"/> 1827 <reg32 offset="0x8c2e" name="RB_A2D_CLEAR_COLOR_DW2" usage="rp_blit"/> 1828 <reg32 offset="0x8c2f" name="RB_A2D_CLEAR_COLOR_DW3" usage="rp_blit"/> 1829 1830 <reg32 offset="0x8c34" name="RB_UNKNOWN_8C34" variants="A7XX-" usage="cmd"/> 1831 1832 <!-- 0x8c35-0x8dff invalid --> 1833 1834 <!-- always 0x1 ? either doesn't exist for a650 or write-only: --> 1835 <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01" usage="cmd"/> 1836 <!-- 0x8e00-0x8e03 invalid --> 1837 <reg32 offset="0x8e04" name="RB_DBG_ECO_CNTL" usage="cmd"/> <!-- TODO: valid mask 0xfffffeff --> 1838 <reg32 offset="0x8e05" name="RB_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 1839 <!-- 0x02080000 in GMEM, zero otherwise? --> 1840 <reg32 offset="0x8e06" name="RB_CCU_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 1841 1842 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A6XX"> 1843 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> 1844 <!-- concurrent resolves are apparently a 2-bit enum on a650+ --> 1845 <bitfield name="CONCURRENT_RESOLVE" pos="2" type="boolean"/> 1846 <bitfield name="DEPTH_OFFSET_HI" pos="7" type="hex"/> 1847 <bitfield name="COLOR_OFFSET_HI" pos="9" type="hex"/> 1848 <bitfield name="DEPTH_CACHE_SIZE" low="10" high="11" type="a6xx_ccu_cache_size"/> 1849 <!-- GMEM offset of CCU depth cache --> 1850 <bitfield name="DEPTH_OFFSET" low="12" high="20" shr="12" type="hex"/> 1851 <bitfield name="COLOR_CACHE_SIZE" low="21" high="22" type="a6xx_ccu_cache_size"/> 1852 <!-- GMEM offset of CCU color cache 1853 for GMEM rendering, we set it to GMEM size minus the minimum 1854 CCU color cache size. CCU color cache will be needed in some 1855 resolve cases, and in those cases we need to reserve the end 1856 of GMEM for color cache. 1857 --> 1858 <bitfield name="COLOR_OFFSET" low="23" high="31" shr="12" type="hex"/> 1859 <!--TODO: valid mask 0xfffffc1f --> 1860 </reg32> 1861 <enum name="a7xx_concurrent_resolve_mode"> 1862 <value value="0x0" name="CONCURRENT_RESOLVE_MODE_DISABLED"/> 1863 <value value="0x1" name="CONCURRENT_RESOLVE_MODE_1"/> 1864 <value value="0x2" name="CONCURRENT_RESOLVE_MODE_2"/> 1865 </enum> 1866 <enum name="a7xx_concurrent_unresolve_mode"> 1867 <value value="0x0" name="CONCURRENT_UNRESOLVE_MODE_DISABLED"/> 1868 <value value="0x1" name="CONCURRENT_UNRESOLVE_MODE_PARTIAL"/> 1869 <value value="0x3" name="CONCURRENT_UNRESOLVE_MODE_FULL"/> 1870 </enum> 1871 <reg32 offset="0x8e07" name="RB_CCU_CNTL" usage="cmd" variants="A7XX-"> 1872 <bitfield name="GMEM_FAST_CLEAR_DISABLE" pos="0" type="boolean"/> 1873 <bitfield name="CONCURRENT_RESOLVE_MODE" low="2" high="3" type="a7xx_concurrent_resolve_mode"/> 1874 <bitfield name="CONCURRENT_UNRESOLVE_MODE" low="5" high="6" type="a7xx_concurrent_unresolve_mode"/> 1875 <!-- rest of the bits were moved to RB_CCU_CACHE_CNTL --> 1876 </reg32> 1877 <reg32 offset="0x8e08" name="RB_NC_MODE_CNTL"> 1878 <bitfield name="MODE" pos="0" type="boolean"/> 1879 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 1880 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 1881 <bitfield name="AMSBC" pos="4" type="boolean"/> 1882 <bitfield name="UPPER_BIT" pos="10" type="uint"/> 1883 <bitfield name="RGB565_PREDICATOR" pos="11" type="boolean"/> 1884 <bitfield name="UNK12" low="12" high="13"/> 1885 </reg32> 1886 <reg32 offset="0x8e09" name="RB_UNKNOWN_8E09" variants="A7XX-" usage="cmd"/> 1887 <!-- 0x8e09-0x8e0f invalid --> 1888 <array offset="0x8e10" name="RB_PERFCTR_RB_SEL" stride="1" length="8"/> 1889 <array offset="0x8e18" name="RB_PERFCTR_CCU_SEL" stride="1" length="5"/> 1890 <!-- 0x8e1d-0x8e1f invalid --> 1891 <!-- 0x8e20-0x8e25 more perfcntr sel? --> 1892 <!-- 0x8e26-0x8e27 invalid --> 1893 <reg32 offset="0x8e28" name="RB_CMP_DBG_ECO_CNTL"/> 1894 <!-- 0x8e29-0x8e2b invalid --> 1895 <array offset="0x8e2c" name="RB_PERFCTR_CMP_SEL" stride="1" length="4"/> 1896 <array offset="0x8e30" name="RB_PERFCTR_UFC_SEL" stride="1" length="6" variants="A7XX-"/> 1897 <reg32 offset="0x8e3b" name="RB_RB_SUB_BLOCK_SEL_CNTL_HOST"/> 1898 <reg32 offset="0x8e3d" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/> 1899 <!-- 0x8e3e-0x8e4f invalid --> 1900 <!-- GMEM save/restore for preemption: --> 1901 <reg32 offset="0x8e50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ENABLE" pos="0" type="boolean"/> 1902 <!-- address for GMEM save/restore? --> 1903 <reg32 offset="0x8e51" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE_ADDR" type="waddress" align="1"/> 1904 <!-- 0x8e53-0x8e7f invalid --> 1905 <reg32 offset="0x8e79" name="RB_UNKNOWN_8E79" variants="A7XX-" usage="cmd"/> 1906 <!-- 0x8e80-0x8e83 are valid --> 1907 <!-- 0x8e84-0x90ff invalid --> 1908 1909 <!-- 0x9000-0x90ff invalid --> 1910 1911 <reg32 offset="0x9100" name="VPC_GS_PARAM" variants="A6XX" usage="rp_blit"> 1912 <bitfield name="LINELENGTHLOC" low="0" high="7" type="uint"/> 1913 </reg32> 1914 1915 <bitset name="a6xx_vpc_xs_clip_cntl" inline="yes"> 1916 <bitfield name="CLIP_MASK" low="0" high="7" type="uint"/> 1917 <!-- there can be up to 8 total clip/cull distance outputs, 1918 but apparenly VPC can only deal with vec4, so when there are 1919 more than 4 outputs a second location needs to be programmed 1920 --> 1921 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/> 1922 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/> 1923 </bitset> 1924 <reg32 offset="0x9101" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1925 <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1926 <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1927 1928 <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1929 <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1930 <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1931 1932 <bitset name="a6xx_vpc_xs_siv_cntl" inline="yes"> 1933 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> 1934 <bitfield name="VIEWLOC" low="8" high="15" type="uint"/> 1935 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/> 1936 </bitset> 1937 1938 <reg32 offset="0x9104" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1939 <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1940 <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1941 1942 <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1943 <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1944 <reg32 offset="0x9316" name="VPC_DS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1945 1946 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit"> 1947 <!-- this mirrors VPC_RAST_STREAM_CNTL::DISCARD, although it seems it's unused --> 1948 <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> 1949 <bitfield name="UNK2" pos="2" type="boolean"/> 1950 </reg32> 1951 <reg32 offset="0x9108" name="VPC_RAST_CNTL" usage="rp_blit"> 1952 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 1953 </reg32> 1954 1955 <bitset name="a6xx_pc_cntl" inline="yes"> 1956 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> 1957 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> 1958 <bitfield name="D3D_VERTEX_ORDERING" pos="2" type="boolean"> 1959 <doc> 1960 Swaps TESS_CW_TRIS/TESS_CCW_TRIS, and also makes 1961 triangle fans and triangle strips use the D3D 1962 order instead of the OpenGL order. 1963 </doc> 1964 </bitfield> 1965 <bitfield name="UNK3" pos="3" type="boolean"/> 1966 </bitset> 1967 1968 <bitset name="a6xx_gs_param_0" inline="yes"> 1969 <doc> 1970 geometry shader 1971 </doc> 1972 <!-- TODO: first 16 bits are valid so something is wrong or missing here --> 1973 <bitfield name="GS_VERTICES_OUT" low="0" high="7" type="uint"/> 1974 <bitfield name="GS_INVOCATIONS" low="10" high="14" type="uint"/> 1975 <bitfield name="LINELENGTHEN" pos="15" type="boolean"/> 1976 <bitfield name="GS_OUTPUT" low="16" high="17" type="a6xx_tess_output"/> 1977 <bitfield name="UNK18" pos="18"/> 1978 </bitset> 1979 1980 <bitset name="a6xx_stereo_rendering_cntl" inline="yes"> 1981 <bitfield name="ENABLE" pos="0" type="boolean"/> 1982 <bitfield name="DISABLEMULTIPOS" pos="1" type="boolean"> 1983 <doc> 1984 Multi-position output lets the last geometry 1985 stage shader write multiple copies of 1986 gl_Position. If disabled then the VS is run once 1987 for each view, and ViewID is passed as a 1988 register to the VS. 1989 </doc> 1990 </bitfield> 1991 <bitfield name="VIEWS" low="2" high="6" type="uint"/> 1992 </bitset> 1993 1994 <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX-" usage="rp_blit"/> 1995 <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX-" usage="rp_blit"/> 1996 <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/> 1997 <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX-" usage="rp_blit"/> 1998 1999 <enum name="a6xx_varying_interp_mode"> 2000 <value value="0" name="INTERP_SMOOTH"/> 2001 <value value="1" name="INTERP_FLAT"/> 2002 <value value="2" name="INTERP_ZERO"/> 2003 <value value="3" name="INTERP_ONE"/> 2004 </enum> 2005 2006 <enum name="a6xx_varying_ps_repl_mode"> 2007 <value value="0" name="PS_REPL_NONE"/> 2008 <value value="1" name="PS_REPL_S"/> 2009 <value value="2" name="PS_REPL_T"/> 2010 <value value="3" name="PS_REPL_ONE_MINUS_T"/> 2011 </enum> 2012 2013 <!-- 0x9109-0x91ff invalid --> 2014 <array offset="0x9200" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" usage="rp_blit"> 2015 <doc>Packed array of a6xx_varying_interp_mode</doc> 2016 <reg32 offset="0x0" name="MODE"/> 2017 </array> 2018 <array offset="0x9208" name="VPC_VARYING_REPLACE_MODE_0" stride="1" length="8" usage="rp_blit"> 2019 <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 2020 <reg32 offset="0x0" name="MODE"/> 2021 </array> 2022 2023 <!-- always 0x0 --> 2024 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/> 2025 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/> 2026 2027 <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL_0" stride="1" length="4" usage="rp_blit"> 2028 <!-- one bit per varying component: --> 2029 <reg32 offset="0" name="DISABLE"/> 2030 </array> 2031 2032 <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" usage="rp_blit"> 2033 <!-- 2034 Choose which DWORD to write to. There is an array of 2035 (4 * 64) DWORD's, dumped in the devcoredump at 2036 HLSQ_INST_RAM dword 0x400. Each DWORD corresponds to a 2037 (VPC location, stream) pair like so: 2038 2039 location 0, stream 0 2040 location 2, stream 0 2041 ... 2042 location 126, stream 0 2043 location 0, stream 1 2044 location 2, stream 1 2045 ... 2046 location 126, stream 1 2047 location 0, stream 2 2048 ... 2049 2050 When EmitStreamVertex(N) happens, the HW goes to DWORD 2051 64 * N and then "executes" the next 64 DWORD's. 2052 2053 This field is auto-incremented when VPC_SO_MAPPING_PORT is 2054 written to. 2055 --> 2056 <bitfield name="ADDR" low="0" high="7" type="hex"/> 2057 <!-- clear all A_EN and B_EN bits for all DWORD's --> 2058 <bitfield name="RESET" pos="16" type="boolean"/> 2059 </reg32> 2060 <!-- special register, write multiple times to load SO program (not readable) --> 2061 <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" usage="rp_blit"> 2062 <bitfield name="A_BUF" low="0" high="1" type="uint"/> 2063 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> 2064 <bitfield name="A_EN" pos="11" type="boolean"/> 2065 <bitfield name="B_BUF" low="12" high="13" type="uint"/> 2066 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> 2067 <bitfield name="B_EN" pos="23" type="boolean"/> 2068 </reg32> 2069 2070 <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" usage="cmd"/> 2071 2072 <array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd"> 2073 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 2074 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 2075 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> 2076 <reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/> 2077 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 2078 </array> 2079 2080 <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" usage="cmd"> 2081 <bitfield name="INVERT" pos="0" type="boolean"/> 2082 </reg32> 2083 <!-- 0x9237-0x92ff invalid --> 2084 <!-- always 0x0 ? --> 2085 <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/> 2086 2087 <bitset name="a6xx_vpc_xs_cntl" inline="yes"> 2088 <doc> 2089 num of varyings plus four for gl_Position (plus one if gl_PointSize) 2090 plus # of transform-feedback (streamout) varyings if using the 2091 hw streamout (rather than stg instructions in shader) 2092 </doc> 2093 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 2094 <bitfield name="POSITIONLOC" low="8" high="15" type="uint"/> 2095 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/> 2096 <bitfield name="EXTRAPOS" low="24" high="27" type="uint"> 2097 <doc> 2098 The number of extra copies of POSITION, i.e. 2099 number of views minus one when multi-position 2100 output is enabled, otherwise 0. 2101 </doc> 2102 </bitfield> 2103 </bitset> 2104 <reg32 offset="0x9301" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2105 <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2106 <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2107 2108 <reg32 offset="0x9304" name="VPC_PS_CNTL" usage="rp_blit"> 2109 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> 2110 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> 2111 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/> 2112 <bitfield name="VARYING" pos="16" type="boolean"/> 2113 <bitfield name="VIEWIDLOC" low="24" high="31" type="uint"> 2114 <doc> 2115 This VPC location will be overwritten with 2116 ViewID when multiview is enabled. It's used when 2117 fragment shaders read ViewID. It's only 2118 strictly required for multi-position output, 2119 where the same VS invocation is used for all the 2120 views at once, but it can be used when multi-pos 2121 output is disabled too, to avoid having to pass 2122 ViewID through the VS. 2123 </doc> 2124 </bitfield> 2125 </reg32> 2126 2127 <reg32 offset="0x9305" name="VPC_SO_CNTL" usage="rp_blit"> 2128 <!-- 2129 It's offset by 1, and 0 means "disabled" 2130 --> 2131 <bitfield name="BUF0_STREAM" low="0" high="2" type="uint"/> 2132 <bitfield name="BUF1_STREAM" low="3" high="5" type="uint"/> 2133 <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/> 2134 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/> 2135 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2136 </reg32> 2137 <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" usage="rp_blit"> 2138 <bitfield name="DISABLE" pos="0" type="boolean"/> 2139 </reg32> 2140 <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" variants="A6XX-" usage="rp_blit"> <!-- A702 + A7xx --> 2141 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2142 </reg32> 2143 <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> 2144 <bitfield name="SIZE_GMEM" low="0" high="31"/> 2145 </reg32> 2146 <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX-" usage="rp_blit"> 2147 <bitfield name="BASE_GMEM" low="0" high="31"/> 2148 </reg32> 2149 <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> 2150 <bitfield name="SIZE_GMEM" low="0" high="31"/> 2151 </reg32> 2152 2153 <!-- 0x9307-0x95ff invalid --> 2154 2155 <!-- TODO: 0x9600-0x97ff range --> 2156 <reg32 offset="0x9600" name="VPC_DBG_ECO_CNTL" usage="cmd"/> <!-- always 0x0 ? TODO: 0x1fbf37ff valid mask --> 2157 <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode" usage="cmd"/> 2158 <reg32 offset="0x9602" name="VPC_UNKNOWN_9602" pos="0" usage="cmd"/> <!-- always 0x0 ? --> 2159 <reg32 offset="0x9603" name="VPC_UNKNOWN_9603" low="0" high="26"/> 2160 <array offset="0x9604" name="VPC_PERFCTR_VPC_SEL" stride="1" length="6" variants="A6XX"/> 2161 <array offset="0x960b" name="VPC_PERFCTR_VPC_SEL" stride="1" length="12" variants="A7XX-"/> 2162 <!-- 0x960a-0x9623 invalid --> 2163 <!-- TODO: regs from 0x9624-0x963a --> 2164 <!-- 0x963b-0x97ff invalid --> 2165 2166 <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" usage="rp_blit"/> 2167 2168 <!-- always 0x0 ? --> 2169 <reg32 offset="0x9801" name="PC_HS_PARAM_1" usage="rp_blit"> 2170 <bitfield name="SIZE" low="0" high="10" type="uint"/> 2171 <bitfield name="UNK13" pos="13"/> 2172 </reg32> 2173 2174 <reg32 offset="0x9802" name="PC_DS_PARAM" usage="rp_blit"> 2175 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> 2176 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> 2177 </reg32> 2178 2179 <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/> 2180 <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/> 2181 2182 <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 2183 2184 <reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit"> 2185 <bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/> 2186 </reg32> 2187 2188 <!-- New in a6xx gen3+ --> 2189 <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" usage="rp_blit"> 2190 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2191 </reg32> 2192 2193 <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL"> 2194 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 2195 </reg32> 2196 <!-- 0x980b-0x983f invalid --> 2197 2198 <!-- 0x9840 - 0x9842 are not readable --> 2199 <reg32 offset="0x9840" name="PC_DRAW_INITIATOR"> 2200 <bitfield name="STATE_ID" low="0" high="7"/> 2201 </reg32> 2202 2203 <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR"> 2204 <bitfield name="STATE_ID" low="0" high="7"/> 2205 </reg32> 2206 2207 <reg32 offset="0x9842" name="PC_EVENT_INITIATOR"> 2208 <!-- I think only the low bit is actually used? --> 2209 <bitfield name="STATE_ID" low="16" high="23"/> 2210 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 2211 </reg32> 2212 2213 <!-- 2214 0x9880 written in a lot of places by SQE, same value gets written 2215 to control reg 0x12a. Set by CP_SET_MARKER, so lets name it after 2216 that 2217 --> 2218 <reg32 offset="0x9880" name="PC_MARKER"/> 2219 2220 <!-- 0x9843-0x997f invalid --> 2221 2222 <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" variants="A6XX" usage="rp_blit"> 2223 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2224 </reg32> 2225 <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" variants="A7XX-" usage="rp_blit"> 2226 <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2227 </reg32> 2228 2229 <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" variants="A6XX" usage="rp_blit"> 2230 <!-- which stream to send to GRAS --> 2231 <bitfield name="STREAM" low="0" high="1" type="uint"/> 2232 <!-- discard primitives before rasterization --> 2233 <bitfield name="DISCARD" pos="2" type="boolean"/> 2234 </reg32> 2235 <!-- VPC_RAST_STREAM_CNTL --> 2236 <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" variants="A7XX-" usage="rp_blit"> 2237 <!-- which stream to send to GRAS --> 2238 <bitfield name="STREAM" low="0" high="1" type="uint"/> 2239 <!-- discard primitives before rasterization --> 2240 <bitfield name="DISCARD" pos="2" type="boolean"/> 2241 </reg32> 2242 <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" variants="A7XX-" usage="rp_blit"> 2243 <!-- which stream to send to GRAS --> 2244 <bitfield name="STREAM" low="0" high="1" type="uint"/> 2245 <!-- discard primitives before rasterization --> 2246 <bitfield name="DISCARD" pos="2" type="boolean"/> 2247 </reg32> 2248 2249 <!-- Both are a750+. 2250 Probably needed to correctly overlap execution of several draws. 2251 --> 2252 <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> 2253 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of 2254 this additional space is not known. 2255 --> 2256 <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> 2257 2258 <!-- 0x9982-0x9aff invalid --> 2259 2260 <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" usage="rp_blit"/> 2261 2262 <bitset name="a6xx_pc_xs_cntl" inline="yes"> 2263 <doc> 2264 num of varyings plus four for gl_Position (plus one if gl_PointSize) 2265 plus # of transform-feedback (streamout) varyings if using the 2266 hw streamout (rather than stg instructions in shader) 2267 </doc> 2268 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/> 2269 <bitfield name="PSIZE" pos="8" type="boolean"/> 2270 <bitfield name="LAYER" pos="9" type="boolean"/> 2271 <bitfield name="VIEW" pos="10" type="boolean"/> 2272 <!-- note: PC_VS_CNTL doesn't have the PRIMITIVE_ID bit --> 2273 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> 2274 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/> 2275 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/> 2276 </bitset> 2277 2278 <reg32 offset="0x9b01" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2279 <reg32 offset="0x9b02" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2280 <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 2281 <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2282 <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2283 2284 <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" usage="rp_blit"/> 2285 2286 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit"> 2287 <doc> 2288 size in vec4s of per-primitive storage for gs. TODO: not actually in VPC 2289 </doc> 2290 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/> 2291 </reg32> 2292 2293 <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="rp_blit"/> 2294 <!-- mask of enabled views, doesn't exist on A630 --> 2295 <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" usage="rp_blit"/> 2296 <!-- 0x9b09-0x9bff invalid --> 2297 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> 2298 <!-- special register (but note first 8 bits can be written/read) --> 2299 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 2300 <bitfield name="STATE_ID" low="8" high="15"/> 2301 </reg32> 2302 <!-- 0x9c01-0x9dff invalid --> 2303 <!-- TODO: 0x9e00-0xa000 range incomplete --> 2304 <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/> 2305 <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2306 <reg64 offset="0x9e04" name="PC_DMA_BASE"/> 2307 <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint"/> 2308 <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint"/> 2309 <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> 2310 <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX-" type="waddress" align="32" usage="cmd"/> 2311 2312 <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx"> 2313 <doc> 2314 Possibly not really "initiating" the draw but the layout is similar 2315 to VGT_DRAW_INITIATOR on older gens 2316 </doc> 2317 </reg32> 2318 <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint"/> 2319 <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint"/> 2320 2321 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> 2322 <reg32 offset="0x9e11" name="PC_VIS_STREAM_CNTL"> 2323 <bitfield name="UNK0" low="0" high="15"/> 2324 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 2325 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 2326 </reg32> 2327 <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32"/> 2328 <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32"/> 2329 2330 <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE"> 2331 <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> 2332 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 2333 </reg32> 2334 2335 <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/> 2336 2337 <array offset="0x9e34" name="PC_PERFCTR_PC_SEL" stride="1" length="8" variants="A6XX"/> 2338 <array offset="0x9e42" name="PC_PERFCTR_PC_SEL" stride="1" length="16" variants="A7XX-"/> 2339 2340 <!-- always 0x0 --> 2341 <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72" usage="cmd"/> 2342 2343 <reg32 offset="0xa000" name="VFD_CNTL_0" usage="rp_blit"> 2344 <bitfield name="FETCH_CNT" low="0" high="5" type="uint"/> 2345 <bitfield name="DECODE_CNT" low="8" high="13" type="uint"/> 2346 </reg32> 2347 <reg32 offset="0xa001" name="VFD_CNTL_1" usage="rp_blit"> 2348 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/> 2349 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/> 2350 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/> 2351 <!-- only used for VS in non-multi-position-output case --> 2352 <bitfield name="REGID4VIEWID" low="24" high="31" type="a3xx_regid"/> 2353 </reg32> 2354 <reg32 offset="0xa002" name="VFD_CNTL_2" usage="rp_blit"> 2355 <bitfield name="REGID_HSRELPATCHID" low="0" high="7" type="a3xx_regid"> 2356 <doc> 2357 This is the ID of the current patch within the 2358 subdraw, used to calculate the offset of the 2359 patch within the HS->DS buffers. When a draw is 2360 split into multiple subdraws then this differs 2361 from gl_PrimitiveID on the second, third, etc. 2362 subdraws. 2363 </doc> 2364 </bitfield> 2365 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/> 2366 </reg32> 2367 <reg32 offset="0xa003" name="VFD_CNTL_3" usage="rp_blit"> 2368 <bitfield name="REGID_DSPRIMID" low="0" high="7" type="a3xx_regid"/> 2369 <bitfield name="REGID_DSRELPATCHID" low="8" high="15" type="a3xx_regid"/> 2370 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/> 2371 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/> 2372 </reg32> 2373 <reg32 offset="0xa004" name="VFD_CNTL_4" usage="rp_blit"> 2374 <bitfield name="UNK0" low="0" high="7" type="a3xx_regid"/> 2375 </reg32> 2376 <reg32 offset="0xa005" name="VFD_CNTL_5" usage="rp_blit"> 2377 <bitfield name="REGID_GSHEADER" low="0" high="7" type="a3xx_regid"/> 2378 <bitfield name="UNK8" low="8" high="15" type="a3xx_regid"/> 2379 </reg32> 2380 <reg32 offset="0xa006" name="VFD_CNTL_6" usage="rp_blit"> 2381 <!-- 2382 True if gl_PrimitiveID is read via the FS 2383 --> 2384 <bitfield name="PRIMID4PSEN" pos="0" type="boolean"/> 2385 </reg32> 2386 2387 <reg32 offset="0xa007" name="VFD_RENDER_MODE" usage="cmd"> 2388 <bitfield name="RENDER_MODE" low="0" high="2" type="a6xx_render_mode"/> 2389 </reg32> 2390 2391 <reg32 offset="0xa008" name="VFD_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="rp_blit"/> 2392 <reg32 offset="0xa009" name="VFD_MODE_CNTL" usage="cmd"> 2393 <!-- add VFD_INDEX_OFFSET to REGID4VTX --> 2394 <bitfield name="VERTEX" pos="0" type="boolean"/> 2395 <!-- add VFD_INSTANCE_START_OFFSET to REGID4INST --> 2396 <bitfield name="INSTANCE" pos="1" type="boolean"/> 2397 </reg32> 2398 2399 <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET" usage="rp_blit"/> 2400 <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET" usage="rp_blit"/> 2401 <array offset="0xa010" name="VFD_VERTEX_BUFFER" stride="4" length="32" usage="rp_blit"> 2402 <reg64 offset="0x0" name="BASE" type="address" align="1"/> 2403 <reg32 offset="0x2" name="SIZE" type="uint"/> 2404 <reg32 offset="0x3" name="STRIDE" low="0" high="11" type="uint"/> 2405 </array> 2406 <array offset="0xa090" name="VFD_FETCH_INSTR" stride="2" length="32" usage="rp_blit"> 2407 <reg32 offset="0x0" name="INSTR"> 2408 <!-- IDX and byte OFFSET into VFD_VERTEX_BUFFER --> 2409 <bitfield name="IDX" low="0" high="4" type="uint"/> 2410 <bitfield name="OFFSET" low="5" high="16"/> 2411 <bitfield name="INSTANCED" pos="17" type="boolean"/> 2412 <bitfield name="FORMAT" low="20" high="27" type="a6xx_format"/> 2413 <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/> 2414 <bitfield name="UNK30" pos="30" type="boolean"/> 2415 <bitfield name="FLOAT" pos="31" type="boolean"/> 2416 </reg32> 2417 <reg32 offset="0x1" name="STEP_RATE" type="uint"/> 2418 </array> 2419 <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32" usage="rp_blit"> 2420 <reg32 offset="0x0" name="INSTR"> 2421 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/> 2422 <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/> 2423 </reg32> 2424 </array> 2425 2426 <reg32 offset="0xa0f8" name="VFD_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 2427 2428 <reg32 offset="0xa600" name="VFD_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 2429 2430 <reg32 offset="0xa601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2431 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="8" variants="A6XX"/> 2432 <array offset="0xa610" name="VFD_PERFCTR_VFD_SEL" stride="1" length="16" variants="A7XX-"/> 2433 2434 <!-- 2435 Note: this seems to always be paired with another bit in another 2436 block. 2437 --> 2438 <enum name="a6xx_threadsize"> 2439 <value value="0" name="THREAD64"/> 2440 <value value="1" name="THREAD128"/> 2441 </enum> 2442 2443 <bitset name="a6xx_sp_xs_cntl_0" inline="yes"> 2444 <!-- if set to SINGLE, only use 1 concurrent wave on each SP --> 2445 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/> 2446 <!-- 2447 When b31 set we just see FULLREGFOOTPRINT set. The pattern of 2448 used registers is a bit odd too: 2449 - used (half): 0-15 68-179 (cnt=128, max=179) 2450 - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127> 2451 whereas we usually see a (mostly) contiguous range of regs used. But if 2452 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)), 2453 then: 2454 - used (merged): 0-191 (cnt=192, max=191) 2455 So I think if b31 is set, then the half precision registers overlap 2456 the full precision registers. (Which seems like a pretty sensible 2457 feature, actually I'm not sure when you *wouldn't* want to use that, 2458 since it gives register allocation more flexibility) 2459 --> 2460 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/> 2461 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/> 2462 <!-- could it be a low bit of branchstack? --> 2463 <bitfield name="UNK13" pos="13" type="boolean"/> 2464 <!-- seems to be nesting level for flow control:.. --> 2465 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/> 2466 </bitset> 2467 2468 <bitset name="a6xx_sp_xs_config" inline="yes"> 2469 <!-- 2470 Each of these are set if the given resource type is used 2471 with the Vulkan/bindless binding model. 2472 --> 2473 <bitfield name="BINDLESS_TEX" pos="0" type="boolean"/> 2474 <bitfield name="BINDLESS_SAMP" pos="1" type="boolean"/> 2475 <bitfield name="BINDLESS_UAV" pos="2" type="boolean"/> 2476 <bitfield name="BINDLESS_UBO" pos="3" type="boolean"/> 2477 2478 <bitfield name="ENABLED" pos="8" type="boolean"/> 2479 <!-- 2480 number of textures and samplers.. these might be swapped, with GL I 2481 always see the same value for both. 2482 --> 2483 <bitfield name="NTEX" low="9" high="16" type="uint"/> 2484 <bitfield name="NSAMP" low="17" high="21" type="uint"/> 2485 <bitfield name="NUAV" low="22" high="28" type="uint"/> 2486 </bitset> 2487 2488 <bitset name="a6xx_sp_xs_output_cntl" inline="yes"> 2489 <!-- # of VS outputs including pos/psize --> 2490 <bitfield name="OUT" low="0" high="5" type="uint"/> 2491 <!-- FLAGS_REGID only for GS --> 2492 <bitfield name="FLAGS_REGID" low="6" high="13" type="a3xx_regid"/> 2493 </bitset> 2494 2495 <reg32 offset="0xa800" name="SP_VS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2496 <!-- 2497 This field actually controls all geometry stages. TCS, TES, and 2498 GS must have the same mergedregs setting as VS. 2499 --> 2500 <bitfield name="MERGEDREGS" pos="20" type="boolean"/> 2501 <!-- 2502 Creates a separate preamble-only thread? 2503 2504 Early preamble has the following limitations: 2505 - Only shared, a1, and consts regs could be used 2506 (accessing other regs would result in GPU fault); 2507 - No cat5/cat6, only stc/ldc variants are working; 2508 - Values writen to shared regs are not accessible by the rest 2509 of the shader; 2510 - Instructions before shps are also considered to be a part of 2511 early preamble; 2512 2513 Note, for all shaders from d3d11 games blob produced preambles 2514 compatible with early preamble mode. 2515 --> 2516 <bitfield name="EARLYPREAMBLE" pos="21" type="boolean"/> 2517 </reg32> 2518 <!-- bitmask of true/false conditions for VS brac.N instructions, 2519 bit N corresponds to brac.N --> 2520 <reg32 offset="0xa801" name="SP_VS_BOOLEAN_CF_MASK" type="hex"/> 2521 <!-- # of VS outputs including pos/psize --> 2522 <reg32 offset="0xa802" name="SP_VS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> 2523 <array offset="0xa803" name="SP_VS_OUTPUT" stride="1" length="16" usage="rp_blit"> 2524 <reg32 offset="0x0" name="REG"> 2525 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 2526 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 2527 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 2528 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 2529 </reg32> 2530 </array> 2531 <!-- 2532 Starting with a5xx, position/psize outputs from shader end up in the 2533 SP_VS_OUTPUT map, with highest OUTLOCn position. (Generally they are 2534 the last entries too, except when gl_PointCoord is used, blob inserts 2535 an extra varying after, but with a lower OUTLOC position. If present, 2536 psize is last, preceded by position. 2537 --> 2538 <array offset="0xa813" name="SP_VS_VPC_DEST" stride="1" length="8" usage="rp_blit"> 2539 <reg32 offset="0x0" name="REG"> 2540 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 2541 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 2542 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 2543 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 2544 </reg32> 2545 </array> 2546 2547 <bitset name="a6xx_sp_xs_pvt_mem_param" inline="yes"> 2548 <bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="9"> 2549 <doc>The size of memory that ldp/stp can address.</doc> 2550 </bitfield> 2551 <bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31"> 2552 <doc> 2553 Seems to be the same as a3xx. The maximum stack 2554 size in units of 4 calls, so a call depth of 7 2555 would result in a value of 2. 2556 TODO: What's the actual size per call, i.e. the 2557 size of the PC? a3xx docs say it's 16 bits 2558 there, but the length register now takes 28 bits 2559 so it's probably been bumped to 32 bits. 2560 </doc> 2561 </bitfield> 2562 </bitset> 2563 2564 <bitset name="a6xx_sp_xs_pvt_mem_size" inline="yes"> 2565 <bitfield name="TOTALPVTMEMSIZE" low="0" high="17" shr="12"/> 2566 <bitfield name="PERWAVEMEMLAYOUT" pos="31" type="boolean"> 2567 <doc> 2568 There are four indices used to compute the 2569 private memory location for an access: 2570 2571 - stp/ldp offset 2572 - fiber id 2573 - wavefront id (a swizzled version of what "getwid" returns) 2574 - SP ID (the same as what "getspid" returns) 2575 2576 The stride for the SP ID is always set by 2577 TOTALPVTMEMSIZE. In the per-wave layout, the 2578 indices are used in this order: 2579 2580 - offset % 4 (offset within dword) 2581 - fiber id 2582 - offset / 4 2583 - wavefront id 2584 - SP ID 2585 2586 and the stride for the wavefront ID is 2587 MEMSIZEPERITEM, multiplied by 128 (fibers per 2588 wavefront). In the per-fiber layout, the indices 2589 are used in this order: 2590 2591 - offset 2592 - fiber id % 4 2593 - wavefront id 2594 - fiber id / 4 2595 - SP ID 2596 2597 and the stride for the fiber id/wavefront id 2598 combo is MEMSIZEPERITEM. 2599 2600 Note: Accesses of more than 1 dword do not work 2601 with per-fiber layout. The blob will fall back 2602 to per-wave instead. 2603 </doc> 2604 </bitfield> 2605 </bitset> 2606 2607 <bitset name="a6xx_sp_xs_pvt_mem_stack_offset" inline="yes"> 2608 <doc> 2609 This seems to be be the equivalent of HWSTACKOFFSET in 2610 a3xx. The ldp/stp offset formula above isn't affected by 2611 HWSTACKSIZEPERTHREAD at all, so the HW return address 2612 stack seems to be after all the normal per-SP private 2613 memory. 2614 </doc> 2615 <bitfield name="OFFSET" low="0" high="18" shr="11"/> 2616 </bitset> 2617 2618 <reg32 offset="0xa81b" name="SP_VS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 2619 <reg64 offset="0xa81c" name="SP_VS_BASE" type="address" align="32" usage="rp_blit"/> 2620 <reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2621 <reg64 offset="0xa81f" name="SP_VS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 2622 <reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2623 <reg32 offset="0xa822" name="SP_VS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2624 <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 2625 <reg32 offset="0xa824" name="SP_VS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 2626 <reg32 offset="0xa825" name="SP_VS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 2627 <reg32 offset="0xa82d" name="SP_VS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2628 2629 <reg32 offset="0xa830" name="SP_HS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2630 <!-- There is no mergedregs bit, that comes from the VS. --> 2631 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 2632 </reg32> 2633 <!-- 2634 Total size of local storage in dwords divided by the wave size. 2635 The maximum value is 64. With the wave size being always 64 for HS, 2636 the maximum size of local storage should be: 2637 64 (wavesize) * 64 (SP_HS_CNTL_1) * 4 = 16k 2638 --> 2639 <reg32 offset="0xa831" name="SP_HS_CNTL_1" low="0" high="7" type="uint" usage="rp_blit"/> 2640 <reg32 offset="0xa832" name="SP_HS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/> 2641 2642 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 2643 <reg32 offset="0xa833" name="SP_HS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 2644 <reg64 offset="0xa834" name="SP_HS_BASE" type="address" align="32" usage="rp_blit"/> 2645 <reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2646 <reg64 offset="0xa837" name="SP_HS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 2647 <reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2648 <reg32 offset="0xa83a" name="SP_HS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2649 <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 2650 <reg32 offset="0xa83c" name="SP_HS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 2651 <reg32 offset="0xa83d" name="SP_HS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 2652 <reg32 offset="0xa82f" name="SP_HS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2653 2654 <reg32 offset="0xa840" name="SP_DS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2655 <!-- There is no mergedregs bit, that comes from the VS. --> 2656 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 2657 </reg32> 2658 <reg32 offset="0xa841" name="SP_DS_BOOLEAN_CF_MASK" type="hex"/> 2659 2660 <!-- TODO: exact same layout as 0xa802-0xa81a --> 2661 <reg32 offset="0xa842" name="SP_DS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> 2662 <array offset="0xa843" name="SP_DS_OUTPUT" stride="1" length="16" usage="rp_blit"> 2663 <reg32 offset="0x0" name="REG"> 2664 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 2665 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 2666 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 2667 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 2668 </reg32> 2669 </array> 2670 <array offset="0xa853" name="SP_DS_VPC_DEST" stride="1" length="8" usage="rp_blit"> 2671 <reg32 offset="0x0" name="REG"> 2672 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 2673 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 2674 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 2675 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 2676 </reg32> 2677 </array> 2678 2679 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 2680 <reg32 offset="0xa85b" name="SP_DS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 2681 <reg64 offset="0xa85c" name="SP_DS_BASE" type="address" align="32" usage="rp_blit"/> 2682 <reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2683 <reg64 offset="0xa85f" name="SP_DS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 2684 <reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2685 <reg32 offset="0xa862" name="SP_DS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2686 <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 2687 <reg32 offset="0xa864" name="SP_DS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 2688 <reg32 offset="0xa865" name="SP_DS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 2689 <reg32 offset="0xa868" name="SP_DS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2690 2691 <reg32 offset="0xa870" name="SP_GS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2692 <!-- There is no mergedregs bit, that comes from the VS. --> 2693 <bitfield name="EARLYPREAMBLE" pos="20" type="boolean"/> 2694 </reg32> 2695 <reg32 offset="0xa871" name="SP_GS_CNTL_1" low="0" high="7" type="uint" usage="rp_blit"> 2696 <doc> 2697 Normally the size of the output of the last stage in 2698 dwords. It should be programmed as follows: 2699 2700 size less than 63 - size 2701 size of 63 (?) or 64 - 63 2702 size greater than 64 - 64 2703 2704 What to program when the size is 61-63 is a guess, but 2705 both the blob and ir3 align the size to 4 dword's so it 2706 doesn't matter in practice. 2707 </doc> 2708 </reg32> 2709 <reg32 offset="0xa872" name="SP_GS_BOOLEAN_CF_MASK" type="hex" usage="rp_blit"/> 2710 2711 <!-- TODO: exact same layout as 0xa802-0xa81a --> 2712 <reg32 offset="0xa873" name="SP_GS_OUTPUT_CNTL" type="a6xx_sp_xs_output_cntl" usage="rp_blit"/> 2713 <array offset="0xa874" name="SP_GS_OUTPUT" stride="1" length="16" usage="rp_blit"> 2714 <reg32 offset="0x0" name="REG"> 2715 <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/> 2716 <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/> 2717 <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/> 2718 <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/> 2719 </reg32> 2720 </array> 2721 2722 <array offset="0xa884" name="SP_GS_VPC_DEST" stride="1" length="8" usage="rp_blit"> 2723 <reg32 offset="0x0" name="REG"> 2724 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/> 2725 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/> 2726 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/> 2727 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/> 2728 </reg32> 2729 </array> 2730 2731 <!-- TODO: exact same layout as 0xa81b-0xa825 --> 2732 <reg32 offset="0xa88c" name="SP_GS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 2733 <reg64 offset="0xa88d" name="SP_GS_BASE" type="address" align="32" usage="rp_blit"/> 2734 <reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2735 <reg64 offset="0xa890" name="SP_GS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 2736 <reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2737 <reg32 offset="0xa893" name="SP_GS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2738 <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 2739 <reg32 offset="0xa895" name="SP_GS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 2740 <reg32 offset="0xa896" name="SP_GS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 2741 <reg32 offset="0xa899" name="SP_GS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2742 2743 <reg64 offset="0xa8a0" name="SP_VS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 2744 <reg64 offset="0xa8a2" name="SP_HS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 2745 <reg64 offset="0xa8a4" name="SP_DS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 2746 <reg64 offset="0xa8a6" name="SP_GS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 2747 <reg64 offset="0xa8a8" name="SP_VS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 2748 <reg64 offset="0xa8aa" name="SP_HS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 2749 <reg64 offset="0xa8ac" name="SP_DS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 2750 <reg64 offset="0xa8ae" name="SP_GS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 2751 2752 <!-- TODO: 4 unknown bool registers 0xa8c0-0xa8c3 --> 2753 2754 <reg32 offset="0xa980" name="SP_PS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="rp_blit"> 2755 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 2756 <bitfield name="UNK21" pos="21" type="boolean"/> 2757 <bitfield name="VARYING" pos="22" type="boolean"/> 2758 <bitfield name="LODPIXMASK" pos="23" type="boolean"> 2759 <doc> 2760 Enable ALL helper invocations in a quad. Necessary for 2761 fine derivatives and quad subgroup ops. 2762 </doc> 2763 </bitfield> 2764 <bitfield name="INOUTREGOVERLAP" pos="24" type="boolean"/> 2765 <bitfield name="UNK25" pos="25" type="boolean"/> 2766 <bitfield name="PIXLODENABLE" pos="26" type="boolean"> 2767 <doc> 2768 Enable helper invocations. Enables 3 out of 4 fragments, 2769 because the coarse derivatives only use half of the quad 2770 and so one pixel's value is always unused. 2771 </doc> 2772 </bitfield> 2773 <bitfield name="UNK27" pos="27" type="boolean"/> 2774 <bitfield name="EARLYPREAMBLE" pos="28" type="boolean"/> 2775 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 2776 </reg32> 2777 <reg32 offset="0xa981" name="SP_PS_BOOLEAN_CF_MASK" type="hex"/> 2778 <reg32 offset="0xa982" name="SP_PS_PROGRAM_COUNTER_OFFSET" type="uint" usage="rp_blit"/> 2779 <reg64 offset="0xa983" name="SP_PS_BASE" type="address" align="32" usage="rp_blit"/> 2780 <reg32 offset="0xa985" name="SP_PS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="rp_blit"/> 2781 <reg64 offset="0xa986" name="SP_PS_PVT_MEM_BASE" type="waddress" align="32" usage="rp_blit"/> 2782 <reg32 offset="0xa988" name="SP_PS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="rp_blit"/> 2783 2784 <reg32 offset="0xa989" name="SP_BLEND_CNTL" usage="rp_blit"> 2785 <!-- per-mrt enable bit --> 2786 <bitfield name="ENABLE_BLEND" low="0" high="7"/> 2787 <bitfield name="UNK8" pos="8" type="boolean"/> 2788 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/> 2789 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/> 2790 </reg32> 2791 <reg32 offset="0xa98a" name="SP_SRGB_CNTL" usage="rp_blit"> 2792 <!-- Same as RB_SRGB_CNTL --> 2793 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/> 2794 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/> 2795 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/> 2796 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/> 2797 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/> 2798 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/> 2799 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/> 2800 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/> 2801 </reg32> 2802 <reg32 offset="0xa98b" name="SP_PS_OUTPUT_MASK" usage="rp_blit"> 2803 <bitfield name="RT0" low="0" high="3"/> 2804 <bitfield name="RT1" low="4" high="7"/> 2805 <bitfield name="RT2" low="8" high="11"/> 2806 <bitfield name="RT3" low="12" high="15"/> 2807 <bitfield name="RT4" low="16" high="19"/> 2808 <bitfield name="RT5" low="20" high="23"/> 2809 <bitfield name="RT6" low="24" high="27"/> 2810 <bitfield name="RT7" low="28" high="31"/> 2811 </reg32> 2812 <reg32 offset="0xa98c" name="SP_PS_OUTPUT_CNTL" usage="rp_blit"> 2813 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/> 2814 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/> 2815 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/> 2816 <bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/> 2817 </reg32> 2818 <reg32 offset="0xa98d" name="SP_PS_MRT_CNTL" usage="rp_blit"> 2819 <bitfield name="MRT" low="0" high="3" type="uint"/> 2820 </reg32> 2821 2822 <array offset="0xa98e" name="SP_PS_OUTPUT" stride="1" length="8" usage="rp_blit"> 2823 <doc>per MRT</doc> 2824 <reg32 offset="0x0" name="REG"> 2825 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/> 2826 <bitfield name="HALF_PRECISION" pos="8" type="boolean"/> 2827 </reg32> 2828 </array> 2829 2830 <array offset="0xa996" name="SP_PS_MRT" stride="1" length="8" usage="rp_blit"> 2831 <reg32 offset="0" name="REG"> 2832 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 2833 <bitfield name="COLOR_SINT" pos="8" type="boolean"/> 2834 <bitfield name="COLOR_UINT" pos="9" type="boolean"/> 2835 <bitfield name="UNK10" pos="10" type="boolean"/> 2836 </reg32> 2837 </array> 2838 2839 <reg32 offset="0xa99e" name="SP_PS_INITIAL_TEX_LOAD_CNTL" usage="rp_blit"> 2840 <bitfield name="COUNT" low="0" high="2" type="uint"/> 2841 <bitfield name="IJ_WRITE_DISABLE" pos="3" type="boolean"/> 2842 <doc> 2843 Similar to "(eq)" flag but disables helper invocations 2844 after the texture prefetch. 2845 </doc> 2846 <bitfield name="ENDOFQUAD" pos="4" type="boolean" /> 2847 <doc> 2848 Bypass writing to regs and overwrite output with color from 2849 CONSTSLOTID const regs. 2850 </doc> 2851 <bitfield name="WRITE_COLOR_TO_OUTPUT" pos="5" type="boolean"/> 2852 <bitfield name="CONSTSLOTID" low="6" high="14" type="uint"/> 2853 <!-- Blob never uses it --> 2854 <bitfield name="CONSTSLOTID4COORD" low="16" high="24" type="uint" variants="A7XX-"/> 2855 </reg32> 2856 <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A6XX" usage="rp_blit"> 2857 <reg32 offset="0" name="CMD" variants="A6XX"> 2858 <bitfield name="SRC" low="0" high="6" type="uint"/> 2859 <bitfield name="SAMP_ID" low="7" high="10" type="uint"/> 2860 <bitfield name="TEX_ID" low="11" high="15" type="uint"/> 2861 <bitfield name="DST" low="16" high="21" type="a3xx_regid"/> 2862 <bitfield name="WRMASK" low="22" high="25" type="hex"/> 2863 <bitfield name="HALF" pos="26" type="boolean"/> 2864 <doc>Results in color being zero</doc> 2865 <bitfield name="UNK27" pos="27" type="boolean"/> 2866 <bitfield name="BINDLESS" pos="28" type="boolean"/> 2867 <bitfield name="CMD" low="29" high="31" type="a6xx_tex_prefetch_cmd"/> 2868 </reg32> 2869 </array> 2870 <array offset="0xa99f" name="SP_PS_INITIAL_TEX_LOAD" stride="1" length="4" variants="A7XX-" usage="rp_blit"> 2871 <reg32 offset="0" name="CMD" variants="A7XX-"> 2872 <bitfield name="SRC" low="0" high="6" type="uint"/> 2873 <bitfield name="SAMP_ID" low="7" high="9" type="uint"/> 2874 <bitfield name="TEX_ID" low="10" high="12" type="uint"/> 2875 <bitfield name="DST" low="13" high="18" type="a3xx_regid"/> 2876 <bitfield name="WRMASK" low="19" high="22" type="hex"/> 2877 <bitfield name="HALF" pos="23" type="boolean"/> 2878 <bitfield name="BINDLESS" pos="25" type="boolean"/> 2879 <bitfield name="CMD" low="26" high="29" type="a6xx_tex_prefetch_cmd"/> 2880 </reg32> 2881 </array> 2882 <array offset="0xa9a3" name="SP_PS_INITIAL_TEX_INDEX" stride="1" length="4" usage="rp_blit"> 2883 <reg32 offset="0" name="CMD"> 2884 <bitfield name="SAMP_ID" low="0" high="15" type="uint"/> 2885 <bitfield name="TEX_ID" low="16" high="31" type="uint"/> 2886 </reg32> 2887 </array> 2888 <reg32 offset="0xa9a7" name="SP_PS_TSIZE" low="0" high="7" type="uint" usage="rp_blit"/> 2889 <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8" low="0" high="16" usage="cmd"/> <!-- always 0x0 ? --> 2890 <reg32 offset="0xa9a9" name="SP_PS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="rp_blit"/> 2891 <reg32 offset="0xa9ab" name="SP_PS_UNKNOWN_A9AB" variants="A7XX-" usage="cmd"/> 2892 2893 <!-- TODO: unknown bool register at 0xa9aa, likely same as 0xa8c0-0xa8c3 but for FS --> 2894 2895 2896 2897 2898 <reg32 offset="0xa9b0" name="SP_CS_CNTL_0" type="a6xx_sp_xs_cntl_0" usage="cmd"> 2899 <bitfield name="THREADSIZE" pos="20" type="a6xx_threadsize"/> 2900 <!-- seems to make SP use less concurrent threads when possible? --> 2901 <bitfield name="UNK21" pos="21" type="boolean"/> 2902 <!-- has a small impact on performance, not clear what it does --> 2903 <bitfield name="UNK22" pos="22" type="boolean"/> 2904 <bitfield name="EARLYPREAMBLE" pos="23" type="boolean"/> 2905 <bitfield name="MERGEDREGS" pos="31" type="boolean"/> 2906 </reg32> 2907 2908 <enum name="a6xx_const_ram_mode"> 2909 <value value="0x0" name="CONSTLEN_128"/> 2910 <value value="0x1" name="CONSTLEN_192"/> 2911 <value value="0x2" name="CONSTLEN_256"/> 2912 <value value="0x3" name="CONSTLEN_512"/> <!-- a7xx only --> 2913 </enum> 2914 2915 <!-- set for compute shaders --> 2916 <reg32 offset="0xa9b1" name="SP_CS_CNTL_1" usage="cmd"> 2917 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"> 2918 <doc> 2919 If 0 - all 32k of shared storage is enabled, otherwise 2920 (SHARED_SIZE + 1) * 1k is enabled. 2921 The ldl/stl offset seems to be rewritten to 0 when it is beyond 2922 this limit. This is different from ldlw/stlw, which wraps at 2923 64k (and has 36k of storage on A640 - reads between 36k-64k 2924 always return 0) 2925 </doc> 2926 </bitfield> 2927 <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"> 2928 <doc> 2929 This defines the split between consts and local 2930 memory in the Local Buffer. The programmed value 2931 must be at least the actual CONSTLEN. 2932 </doc> 2933 </bitfield> 2934 </reg32> 2935 <reg32 offset="0xa9b2" name="SP_CS_BOOLEAN_CF_MASK" type="hex" usage="cmd"/> 2936 <reg32 offset="0xa9b3" name="SP_CS_PROGRAM_COUNTER_OFFSET" type="uint" usage="cmd"/> 2937 <reg64 offset="0xa9b4" name="SP_CS_BASE" type="address" align="32" usage="cmd"/> 2938 <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/> 2939 <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_BASE" align="32" usage="cmd"/> 2940 <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/> 2941 <reg32 offset="0xa9ba" name="SP_CS_TSIZE" low="0" high="7" type="uint" usage="cmd"/> 2942 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/> 2943 <reg32 offset="0xa9bc" name="SP_CS_INSTR_SIZE" low="0" high="27" type="uint" usage="cmd"/> 2944 <reg32 offset="0xa9bd" name="SP_CS_PVT_MEM_STACK_OFFSET" type="a6xx_sp_xs_pvt_mem_stack_offset" usage="cmd"/> 2945 <reg32 offset="0xa9be" name="SP_CS_UNKNOWN_A9BE" variants="A7XX-" usage="cmd"/> 2946 <reg32 offset="0xa9c5" name="SP_CS_VGS_CNTL" variants="A7XX-" usage="cmd"/> 2947 2948 <!-- new in a6xx gen4, matches SP_CS_CONST_CONFIG_0 --> 2949 <reg32 offset="0xa9c2" name="SP_CS_WIE_CNTL_0" usage="cmd"> 2950 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 2951 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 2952 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 2953 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 2954 </reg32> 2955 <!-- new in a6xx gen4, matches SP_CS_WGE_CNTL --> 2956 <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A6XX" usage="cmd"> 2957 <!-- gl_LocalInvocationIndex --> 2958 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 2959 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 2960 one of those 6 "SP cores" --> 2961 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 2962 <!-- Must match SP_CS_CTRL --> 2963 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 2964 <!-- 1 thread per wave (ignored if bit9 set) --> 2965 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 2966 </reg32> 2967 2968 <enum name="a7xx_workitem_rast_order"> 2969 <value value="0x0" name="WORKITEMRASTORDER_LINEAR"/> 2970 <doc> 2971 This is a fixed tiling, with 4x4 invocation outer tiles 2972 containing 2x2 invocation inner tiles. The intent is to 2973 improve cache locality with textures and images accessed 2974 using gl_LocalInvocationID. 2975 </doc> 2976 <value value="0x1" name="WORKITEMRASTORDER_TILED"/> 2977 </enum> 2978 2979 <reg32 offset="0xa9c3" name="SP_CS_WIE_CNTL_1" variants="A7XX-" usage="cmd"> 2980 <!-- gl_LocalInvocationIndex --> 2981 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 2982 <!-- Must match SP_CS_CTRL --> 2983 <bitfield name="THREADSIZE" pos="8" type="a6xx_threadsize"/> 2984 <!-- 1 thread per wave (would hang if THREAD128 is also set) --> 2985 <bitfield name="THREADSIZE_SCALAR" pos="9" type="boolean"/> 2986 2987 <doc>How invocations/fibers within a workgroup are tiled.</doc> 2988 <bitfield name="WORKITEMRASTORDER" pos="15" type="a7xx_workitem_rast_order"/> 2989 </reg32> 2990 2991 <!-- TODO: two 64kb aligned addresses at a9d0/a9d2 --> 2992 2993 <reg64 offset="0xa9e0" name="SP_PS_SAMPLER_BASE" type="address" align="16" usage="rp_blit"/> 2994 <reg64 offset="0xa9e2" name="SP_CS_SAMPLER_BASE" type="address" align="16" usage="cmd"/> 2995 <reg64 offset="0xa9e4" name="SP_PS_TEXMEMOBJ_BASE" type="address" align="64" usage="rp_blit"/> 2996 <reg64 offset="0xa9e6" name="SP_CS_TEXMEMOBJ_BASE" type="address" align="64" usage="cmd"/> 2997 2998 <enum name="a6xx_bindless_descriptor_size"> 2999 <doc> 3000 This can alternatively be interpreted as a pitch shift, ie, the 3001 descriptor size is 2 << N dwords 3002 </doc> 3003 <value value="1" name="BINDLESS_DESCRIPTOR_16B"/> 3004 <value value="3" name="BINDLESS_DESCRIPTOR_64B"/> 3005 </enum> 3006 3007 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd"> 3008 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> 3009 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 3010 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 3011 </reg64> 3012 </array> 3013 <array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="cmd"> 3014 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> 3015 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 3016 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 3017 </reg64> 3018 </array> 3019 3020 <!-- 3021 UAV state for compute shader: 3022 --> 3023 <reg64 offset="0xa9f2" name="SP_CS_UAV_BASE" type="address" align="16" variants="A6XX"/> 3024 <reg64 offset="0xa9f8" name="SP_CS_UAV_BASE" type="address" align="16" variants="A7XX"/> 3025 <reg32 offset="0xaa00" name="SP_CS_USIZE" low="0" high="6" type="uint"/> 3026 3027 <!-- Correlated with avgs/uvgs usage in FS --> 3028 <reg32 offset="0xaa01" name="SP_PS_VGS_CNTL" type="uint" variants="A7XX-" usage="cmd"/> 3029 3030 <reg32 offset="0xaa02" name="SP_PS_OUTPUT_CONST_CNTL" variants="A7XX-" usage="cmd"> 3031 <bitfield name="ENABLED" pos="0" type="boolean"/> 3032 </reg32> 3033 <reg32 offset="0xaa03" name="SP_PS_OUTPUT_CONST_MASK" variants="A7XX-" usage="cmd"> 3034 <doc> 3035 Specify for which components the output color should be read 3036 from alias, e.g. for: 3037 3038 alias.1.b32.0 r3.x, c8.x 3039 alias.1.b32.0 r2.x, c4.x 3040 alias.1.b32.0 r1.x, c4.x 3041 alias.1.b32.0 r0.x, c0.x 3042 3043 the SP_PS_OUTPUT_CONST_MASK would be 0x00001111 3044 </doc> 3045 3046 <bitfield name="RT0" low="0" high="3"/> 3047 <bitfield name="RT1" low="4" high="7"/> 3048 <bitfield name="RT2" low="8" high="11"/> 3049 <bitfield name="RT3" low="12" high="15"/> 3050 <bitfield name="RT4" low="16" high="19"/> 3051 <bitfield name="RT5" low="20" high="23"/> 3052 <bitfield name="RT6" low="24" high="27"/> 3053 <bitfield name="RT7" low="28" high="31"/> 3054 </reg32> 3055 3056 <reg32 offset="0xaaf2" name="SP_UNKNOWN_AAF2" type="uint" usage="cmd"/> 3057 3058 <!-- 3059 This enum is probably similar in purpose to SNORMMODE on a3xx, 3060 minus the snorm stuff, i.e. it controls what happens with an 3061 out-of-bounds isam/isamm. GL and Vulkan robustness require us to 3062 return 0 on out-of-bound textureFetch(). 3063 --> 3064 <enum name="a6xx_isam_mode"> 3065 <value value="0x1" name="ISAMMODE_CL"/> 3066 <value value="0x2" name="ISAMMODE_GL"/> 3067 </enum> 3068 3069 <reg32 offset="0xab00" name="SP_MODE_CNTL" usage="rp_blit"> 3070 <!-- 3071 When set, half register loads from the constant file will 3072 load a 32-bit value (so hc0.y loads the same value as c0.y) 3073 and implicitly convert it to 16b (f2f16, or u2u16, based on 3074 operand type). When unset, half register loads from the 3075 constant file will load 16 bits from the packed constant 3076 file (so hc0.y loads the top 16 bits of the value of c0.x) 3077 --> 3078 <bitfield name="CONSTANT_DEMOTION_ENABLE" pos="0" type="boolean"/> 3079 <bitfield name="ISAMMODE" low="1" high="2" type="a6xx_isam_mode"/> 3080 <bitfield name="SHARED_CONSTS_ENABLE" pos="3" type="boolean"/> <!-- see HLSQ_SHARED_CONSTS --> 3081 </reg32> 3082 3083 <reg32 offset="0xab01" name="SP_UNKNOWN_AB01" variants="A7XX-" usage="cmd"/> 3084 <reg32 offset="0xab02" name="SP_UNKNOWN_AB02" variants="A7XX-" usage="cmd"/> 3085 3086 <reg32 offset="0xab04" name="SP_PS_CONFIG" type="a6xx_sp_xs_config" usage="rp_blit"/> 3087 <reg32 offset="0xab05" name="SP_PS_INSTR_SIZE" low="0" high="27" type="uint" usage="rp_blit"/> 3088 3089 <array offset="0xab10" name="SP_GFX_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> 3090 <reg64 offset="0" name="DESCRIPTOR" variants="A6XX"> 3091 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 3092 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 3093 </reg64> 3094 </array> 3095 <array offset="0xab0a" name="SP_GFX_BINDLESS_BASE" stride="2" length="8" variants="A7XX-" usage="rp_blit"> 3096 <reg64 offset="0" name="DESCRIPTOR" variants="A7XX-"> 3097 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 3098 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 3099 </reg64> 3100 </array> 3101 3102 <!-- 3103 Combined UAV state for 3d pipe, used for Image and SSBO write/atomic 3104 instructions VS/HS/DS/GS/FS. See SP_CS_UAV_BASE_* for compute shaders. 3105 --> 3106 <reg64 offset="0xab1a" name="SP_GFX_UAV_BASE" type="address" align="16" usage="cmd"/> 3107 <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" usage="cmd"/> 3108 3109 <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/> 3110 3111 <bitset name="a6xx_sp_a2d_output_info" inline="yes"> 3112 <bitfield name="NORM" pos="0" type="boolean"/> 3113 <bitfield name="SINT" pos="1" type="boolean"/> 3114 <bitfield name="UINT" pos="2" type="boolean"/> 3115 <!-- looks like HW only cares about the base type of this format, 3116 which matches the ifmt? --> 3117 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/> 3118 <!-- set when ifmt is R2D_UNORM8_SRGB --> 3119 <bitfield name="SRGB" pos="11" type="boolean"/> 3120 <!-- some sort of channel mask, not sure what it is for --> 3121 <bitfield name="MASK" low="12" high="15"/> 3122 </bitset> 3123 3124 <reg32 offset="0xacc0" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A6XX" usage="rp_blit"/> 3125 <reg32 offset="0xa9bf" name="SP_A2D_OUTPUT_INFO" type="a6xx_sp_a2d_output_info" variants="A7XX-" usage="rp_blit"/> 3126 3127 <reg32 offset="0xae00" name="SP_DBG_ECO_CNTL" usage="cmd"/> 3128 <reg32 offset="0xae01" name="SP_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/> 3129 <reg32 offset="0xae02" name="SP_NC_MODE_CNTL"> 3130 <!-- TODO: valid bits 0x3c3f, see kernel --> 3131 </reg32> 3132 <reg32 offset="0xae03" name="SP_CHICKEN_BITS" usage="cmd"/> 3133 <reg32 offset="0xae04" name="SP_NC_MODE_CNTL_2" usage="cmd"> 3134 <bitfield name="F16_NO_INF" pos="3" type="boolean"/> 3135 </reg32> 3136 3137 <reg32 offset="0xae06" name="SP_UNKNOWN_AE06" variants="A7XX-" usage="cmd"/> 3138 <reg32 offset="0xae08" name="SP_CHICKEN_BITS_1" variants="A7XX-" usage="cmd"/> 3139 <reg32 offset="0xae09" name="SP_CHICKEN_BITS_2" variants="A7XX-" usage="cmd"/> 3140 <reg32 offset="0xae0a" name="SP_CHICKEN_BITS_3" variants="A7XX-" usage="cmd"/> 3141 3142 <reg32 offset="0xae0f" name="SP_PERFCTR_SHADER_MASK" usage="cmd"> 3143 <!-- some perfcntrs are affected by a per-stage enable bit 3144 (PERF_SP_ALU_WORKING_CYCLES for example) 3145 TODO: verify position of HS/DS/GS bits --> 3146 <bitfield name="VS" pos="0" type="boolean"/> 3147 <bitfield name="HS" pos="1" type="boolean"/> 3148 <bitfield name="DS" pos="2" type="boolean"/> 3149 <bitfield name="GS" pos="3" type="boolean"/> 3150 <bitfield name="FS" pos="4" type="boolean"/> 3151 <bitfield name="CS" pos="5" type="boolean"/> 3152 </reg32> 3153 <array offset="0xae10" name="SP_PERFCTR_SP_SEL" stride="1" length="24"/> 3154 <array offset="0xae60" name="SP_PERFCTR_HLSQ_SEL" stride="1" length="6" variants="A7XX-"/> 3155 <reg32 offset="0xae6a" name="SP_UNKNOWN_AE6A" variants="A7XX-" usage="cmd"/> 3156 <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/> 3157 <reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 3158 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-"> 3159 <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/> 3160 <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/> 3161 <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/> 3162 <bitfield name="USPTP" low="4" high="7"/> 3163 <bitfield name="SPTP" low="0" high="3"/> 3164 </reg32> 3165 <reg32 offset="0xae71" name="SP_DBG_CNTL" variants="A7XX-"/> 3166 <reg32 offset="0xae73" name="SP_UNKNOWN_AE73" variants="A7XX-" usage="cmd"/> 3167 <array offset="0xae80" name="SP_PERFCTR_SP_SEL" stride="1" length="36" variants="A7XX-"/> 3168 <!-- TODO: there are 4 more percntr select registers (0xae28-0xae2b) --> 3169 <!-- TODO: there are a few unknown registers in the 0xae30-0xae52 range --> 3170 <reg32 offset="0xbe22" name="SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 3171 3172 <!-- 3173 The downstream kernel calls the debug cluster of registers 3174 "a6xx_sp_ps_tp_cluster" but this actually specifies the border 3175 color base for compute shaders. 3176 --> 3177 <reg64 offset="0xb180" name="TPL1_CS_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 3178 <reg32 offset="0xb182" name="SP_UNKNOWN_B182" low="0" high="2" usage="cmd"/> 3179 <reg32 offset="0xb183" name="SP_UNKNOWN_B183" low="0" high="23" usage="cmd"/> 3180 3181 <reg32 offset="0xb190" name="SP_UNKNOWN_B190"/> 3182 <reg32 offset="0xb191" name="SP_UNKNOWN_B191"/> 3183 3184 <reg32 offset="0xb300" name="TPL1_RAS_MSAA_CNTL" usage="rp_blit"> 3185 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 3186 <bitfield name="UNK2" low="2" high="3"/> 3187 </reg32> 3188 <reg32 offset="0xb301" name="TPL1_DEST_MSAA_CNTL" usage="rp_blit"> 3189 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 3190 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 3191 </reg32> 3192 3193 <!-- looks to work in the same way as a5xx: --> 3194 <reg64 offset="0xb302" name="TPL1_GFX_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 3195 <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 3196 <reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 3197 <reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 3198 <reg32 offset="0xb307" name="TPL1_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> 3199 3200 <enum name="a6xx_coord_round"> 3201 <value value="0" name="COORD_TRUNCATE"/> 3202 <value value="1" name="COORD_ROUND_NEAREST_EVEN"/> 3203 </enum> 3204 3205 <enum name="a6xx_nearest_mode"> 3206 <value value="0" name="ROUND_CLAMP_TRUNCATE"/> 3207 <value value="1" name="CLAMP_ROUND_TRUNCATE"/> 3208 </enum> 3209 3210 <reg32 offset="0xb309" name="TPL1_MODE_CNTL" usage="cmd"> 3211 <bitfield name="ISAMMODE" low="0" high="1" type="a6xx_isam_mode"/> 3212 <bitfield name="TEXCOORDROUNDMODE" pos="2" type="a6xx_coord_round"/> 3213 <bitfield name="NEARESTMIPSNAP" pos="5" type="a6xx_nearest_mode"/> 3214 <bitfield name="DESTDATATYPEOVERRIDE" pos="7" type="boolean"/> 3215 </reg32> 3216 <reg32 offset="0xb310" name="SP_UNKNOWN_B310" variants="A7XX-" usage="cmd"/> 3217 3218 <!-- 3219 Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either 3220 badly named or the functionality moved in a6xx. But downstream kernel 3221 calls this "a6xx_sp_ps_tp_2d_cluster" 3222 --> 3223 <reg32 offset="0xb4c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A6XX" usage="rp_blit"/> 3224 <reg32 offset="0xb4c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A6XX" usage="rp_blit"> 3225 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 3226 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 3227 </reg32> 3228 <reg64 offset="0xb4c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A6XX" usage="rp_blit"/> 3229 <reg32 offset="0xb4c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A6XX" usage="rp_blit"> 3230 <bitfield name="UNK0" low="0" high="8"/> 3231 <bitfield name="PITCH" low="9" high="23" shr="6" type="uint"/> 3232 </reg32> 3233 3234 <reg32 offset="0xb2c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A7XX-" usage="rp_blit"/> 3235 <reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX"> 3236 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 3237 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 3238 </reg32> 3239 <reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 3240 <reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX"> 3241 <!-- 3242 Bits from 3..9 must be zero unless 'TPL1_A2D_BLT_CNTL::TYPE' 3243 is A6XX_TEX_IMG_BUFFER, which allows for lower alignment. 3244 --> 3245 <bitfield name="PITCH" low="3" high="23" type="uint"/> 3246 </reg32> 3247 3248 <!-- planes for NV12, etc. (TODO: not tested) --> 3249 <reg64 offset="0xb4c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A6XX"/> 3250 <reg32 offset="0xb4c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A6XX"/> 3251 <reg64 offset="0xb4c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A6XX"/> 3252 3253 <reg64 offset="0xb2c5" name="TPL1_A2D_SRC_TEXTURE_BASE_1" type="address" align="16" variants="A7XX-"/> 3254 <reg32 offset="0xb2c7" name="TPL1_A2D_SRC_TEXTURE_PITCH_1" low="0" high="11" shr="6" type="uint" variants="A7XX-"/> 3255 <reg64 offset="0xb2c8" name="TPL1_A2D_SRC_TEXTURE_BASE_2" type="address" align="16" variants="A7XX-"/> 3256 3257 <reg64 offset="0xb4ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A6XX" usage="rp_blit"/> 3258 <reg32 offset="0xb4cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A6XX" usage="rp_blit"/> 3259 3260 <reg64 offset="0xb2ca" name="TPL1_A2D_SRC_TEXTURE_FLAG_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 3261 <reg32 offset="0xb2cc" name="TPL1_A2D_SRC_TEXTURE_FLAG_PITCH" low="0" high="7" shr="6" type="uint" variants="A7XX-" usage="rp_blit"/> 3262 3263 <reg32 offset="0xb4cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A6XX"/> 3264 <reg32 offset="0xb4ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A6XX"/> 3265 <reg32 offset="0xb4cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A6XX"/> 3266 <reg32 offset="0xb4d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A6XX"/> 3267 <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A6XX" usage="rp_blit"/> 3268 3269 <reg32 offset="0xb2cd" name="SP_PS_UNKNOWN_B4CD" low="6" high="31" variants="A7XX"/> 3270 <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/> 3271 <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/> 3272 <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/> 3273 <reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/> 3274 <reg32 offset="0xb2d2" name="TPL1_A2D_BLT_CNTL" variants="A7XX-" usage="rp_blit"> 3275 <bitfield name="RAW_COPY" pos="0" type="boolean"/> 3276 <bitfield name="START_OFFSET_TEXELS" low="16" high="21"/> 3277 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 3278 </reg32> 3279 <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/> 3280 3281 <!-- always 0x100000 or 0x1000000? --> 3282 <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/> 3283 <reg32 offset="0xb601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 3284 <reg32 offset="0xb602" name="TPL1_DBG_ECO_CNTL1" usage="cmd"> 3285 <!-- Affects UBWC in some way, if BLIT_OP_SCALE is done with this bit set 3286 and if other blit is done without it - UBWC image may be copied incorrectly. 3287 --> 3288 <bitfield name="TP_UBWC_FLAG_HINT" pos="18" type="boolean"/> 3289 </reg32> 3290 <reg32 offset="0xb604" name="TPL1_NC_MODE_CNTL"> 3291 <bitfield name="MODE" pos="0" type="boolean"/> 3292 <bitfield name="LOWER_BIT" low="1" high="2" type="uint"/> 3293 <bitfield name="MIN_ACCESS_LENGTH" pos="3" type="boolean"/> <!-- true=64b false=32b --> 3294 <bitfield name="UPPER_BIT" pos="4" type="uint"/> 3295 <bitfield name="UNK6" low="6" high="7"/> 3296 </reg32> 3297 <reg32 offset="0xb605" name="TPL1_UNKNOWN_B605" low="0" high="7" type="uint" variants="A6XX" usage="cmd"/> <!-- always 0x0 or 0x44 ? --> 3298 3299 <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A6XX"/> 3300 <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A6XX"/> 3301 <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A6XX"/> 3302 <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A6XX"/> 3303 <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A6XX"/> 3304 3305 <reg32 offset="0xb608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0" low="0" high="29" variants="A7XX" usage="cmd"/> 3306 <reg32 offset="0xb609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1" low="0" high="29" variants="A7XX" usage="cmd"/> 3307 <reg32 offset="0xb60a" name="TPL1_BICUBIC_WEIGHTS_TABLE_2" low="0" high="29" variants="A7XX" usage="cmd"/> 3308 <reg32 offset="0xb60b" name="TPL1_BICUBIC_WEIGHTS_TABLE_3" low="0" high="29" variants="A7XX" usage="cmd"/> 3309 <reg32 offset="0xb60c" name="TPL1_BICUBIC_WEIGHTS_TABLE_4" low="0" high="29" variants="A7XX" usage="cmd"/> 3310 3311 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="12" variants="A6XX"/> 3312 <array offset="0xb610" name="TPL1_PERFCTR_TP_SEL" stride="1" length="18" variants="A7XX"/> 3313 3314 <!-- TODO: 4 more perfcntr sel at 0xb620 ? --> 3315 3316 <bitset name="a6xx_xs_const_config" inline="yes"> 3317 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/> 3318 <bitfield name="ENABLED" pos="8" type="boolean"/> 3319 <bitfield name="READ_IMM_SHARED_CONSTS" pos="9" type="boolean" variants="A7XX-"/> 3320 </bitset> 3321 3322 <reg32 offset="0xb800" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 3323 <reg32 offset="0xb801" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 3324 <reg32 offset="0xb802" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 3325 <reg32 offset="0xb803" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 3326 3327 <reg32 offset="0xa827" name="SP_VS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 3328 <reg32 offset="0xa83f" name="SP_HS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 3329 <reg32 offset="0xa867" name="SP_DS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 3330 <reg32 offset="0xa898" name="SP_GS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 3331 3332 <reg32 offset="0xa9aa" name="SP_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 3333 <bitfield name="FS_DISABLE" pos="0" type="boolean"/> 3334 </reg32> 3335 3336 <reg32 offset="0xa9ac" name="SP_DITHER_CNTL" variants="A7XX-" usage="cmd"> 3337 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/> 3338 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/> 3339 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/> 3340 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/> 3341 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/> 3342 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/> 3343 <bitfield name="DITHER_MODE_MRT6" low="12" high="13" type="adreno_rb_dither_mode"/> 3344 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/> 3345 </reg32> 3346 3347 <reg32 offset="0xa9ad" name="SP_VRS_CONFIG" variants="A7XX-" usage="rp_blit"> 3348 <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 3349 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="1" type="boolean"/> 3350 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="3" type="boolean"/> 3351 </reg32> 3352 3353 <reg32 offset="0xa9ae" name="SP_PS_CNTL_1" variants="A7XX-" usage="rp_blit"> 3354 <bitfield name="SYSVAL_REGS_COUNT" low="0" high="7" type="uint"/> 3355 <!-- UNK8 is set on a730/a740 --> 3356 <bitfield name="UNK8" pos="8" type="boolean"/> 3357 <!-- UNK9 is set on a750 --> 3358 <bitfield name="UNK9" pos="9" type="boolean"/> 3359 </reg32> 3360 3361 <reg32 offset="0xb820" name="HLSQ_LOAD_STATE_GEOM_CMD"/> 3362 <reg64 offset="0xb821" name="HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR" align="16" type="address"/> 3363 <reg32 offset="0xb823" name="HLSQ_LOAD_STATE_GEOM_DATA"/> 3364 3365 3366 <bitset name="a6xx_sp_ps_wave_cntl" inline="yes"> 3367 <!-- must match SP_FS_CTRL --> 3368 <bitfield name="THREADSIZE" pos="0" type="a6xx_threadsize"/> 3369 <bitfield name="VARYINGS" pos="1" type="boolean"/> 3370 <bitfield name="UNK2" low="2" high="11"/> 3371 </bitset> 3372 <bitset name="a6xx_sp_reg_prog_id_1" inline="yes"> 3373 <!-- register loaded with position (bary.f) --> 3374 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/> 3375 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/> 3376 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/> 3377 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/> 3378 </bitset> 3379 <bitset name="a6xx_sp_reg_prog_id_2" inline="yes"> 3380 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/> 3381 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/> 3382 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/> 3383 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/> 3384 </bitset> 3385 <bitset name="a6xx_sp_reg_prog_id_3" inline="yes"> 3386 <bitfield name="LINELENGTHREGID" low="0" high="7" type="a3xx_regid"/> 3387 <bitfield name="FOVEATIONQUALITYREGID" low="8" high="15" type="a3xx_regid"/> 3388 </bitset> 3389 3390 <reg32 offset="0xb980" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A6XX" usage="rp_blit"/> 3391 <reg32 offset="0xb981" name="HLSQ_UNKNOWN_B981" pos="0" type="boolean" variants="A6XX"/> <!-- never used by blob --> 3392 <reg32 offset="0xb982" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A6XX" usage="rp_blit"> 3393 <!-- Sets the maximum number of primitives allowed in one FS wave minus one, similarly to the 3394 A3xx field, except that it's not necessary to set it to anything but the maximum, since 3395 the hardware will simply emit smaller waves when it runs out of space. --> 3396 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 3397 </reg32> 3398 <reg32 offset="0xb983" name="SP_REG_PROG_ID_0" variants="A6XX" usage="rp_blit"> 3399 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 3400 <!-- SAMPLEID is loaded into a half-precision register: --> 3401 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 3402 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 3403 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 3404 </reg32> 3405 <reg32 offset="0xb984" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A6XX" usage="rp_blit"/> 3406 <reg32 offset="0xb985" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A6XX" usage="rp_blit"/> 3407 <reg32 offset="0xb986" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A6XX" usage="rp_blit"/> 3408 <reg32 offset="0xb987" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="cmd"/> 3409 <reg32 offset="0xa9c6" type="a6xx_sp_ps_wave_cntl" name="SP_PS_WAVE_CNTL" variants="A7XX-" usage="rp_blit"/> 3410 <reg32 offset="0xa9c7" name="SP_LB_PARAM_LIMIT" low="0" high="2" variants="A7XX-" usage="rp_blit"> 3411 <bitfield name="PRIMALLOCTHRESHOLD" low="0" high="2" type="uint"/> 3412 </reg32> 3413 <reg32 offset="0xa9c8" name="SP_REG_PROG_ID_0" variants="A7XX-" usage="rp_blit"> 3414 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/> 3415 <!-- SAMPLEID is loaded into a half-precision register: --> 3416 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/> 3417 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/> 3418 <bitfield name="CENTERRHW" low="24" high="31" type="a3xx_regid"/> 3419 </reg32> 3420 <reg32 offset="0xa9c9" type="a6xx_sp_reg_prog_id_1" name="SP_REG_PROG_ID_1" variants="A7XX-" usage="rp_blit"/> 3421 <reg32 offset="0xa9ca" type="a6xx_sp_reg_prog_id_2" name="SP_REG_PROG_ID_2" variants="A7XX-" usage="rp_blit"/> 3422 <reg32 offset="0xa9cb" type="a6xx_sp_reg_prog_id_3" name="SP_REG_PROG_ID_3" variants="A7XX-" usage="rp_blit"/> 3423 <reg32 offset="0xa9cd" name="SP_CS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="cmd"/> 3424 3425 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 3426 <reg32 offset="0xb990" name="SP_CS_NDRANGE_0" variants="A6XX" usage="rp_blit"> 3427 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 3428 <!-- localsize is value minus one: --> 3429 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 3430 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 3431 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 3432 </reg32> 3433 <reg32 offset="0xb991" name="SP_CS_NDRANGE_1" variants="A6XX" usage="rp_blit"> 3434 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 3435 </reg32> 3436 <reg32 offset="0xb992" name="SP_CS_NDRANGE_2" variants="A6XX" usage="rp_blit"> 3437 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 3438 </reg32> 3439 <reg32 offset="0xb993" name="SP_CS_NDRANGE_3" variants="A6XX" usage="rp_blit"> 3440 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 3441 </reg32> 3442 <reg32 offset="0xb994" name="SP_CS_NDRANGE_4" variants="A6XX" usage="rp_blit"> 3443 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 3444 </reg32> 3445 <reg32 offset="0xb995" name="SP_CS_NDRANGE_5" variants="A6XX" usage="rp_blit"> 3446 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 3447 </reg32> 3448 <reg32 offset="0xb996" name="SP_CS_NDRANGE_6" variants="A6XX" usage="rp_blit"> 3449 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 3450 </reg32> 3451 <reg32 offset="0xb997" name="SP_CS_CONST_CONFIG_0" variants="A6XX" usage="rp_blit"> 3452 <!-- these are all vec3. first 3 need to be high regs 3453 WGSIZECONSTID is the local size (from SP_CS_NDRANGE_0) 3454 WGOFFSETCONSTID is WGIDCONSTID*WGSIZECONSTID 3455 --> 3456 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/> 3457 <bitfield name="WGSIZECONSTID" low="8" high="15" type="a3xx_regid"/> 3458 <bitfield name="WGOFFSETCONSTID" low="16" high="23" type="a3xx_regid"/> 3459 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/> 3460 </reg32> 3461 <reg32 offset="0xb998" name="SP_CS_WGE_CNTL" variants="A6XX" usage="rp_blit"> 3462 <!-- gl_LocalInvocationIndex --> 3463 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 3464 <!-- a650 has 6 "SP cores" (but 3 "SP"). this makes it use only 3465 one of those 6 "SP cores" --> 3466 <bitfield name="SINGLE_SP_CORE" pos="8" type="boolean"/> 3467 <!-- Must match SP_CS_CTRL --> 3468 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 3469 <!-- 1 thread per wave (ignored if bit9 set) --> 3470 <bitfield name="THREADSIZE_SCALAR" pos="10" type="boolean"/> 3471 </reg32> 3472 <!--note: vulkan blob doesn't use these --> 3473 <reg32 offset="0xb999" name="SP_CS_KERNEL_GROUP_X" variants="A6XX" usage="rp_blit"/> 3474 <reg32 offset="0xb99a" name="SP_CS_KERNEL_GROUP_Y" variants="A6XX" usage="rp_blit"/> 3475 <reg32 offset="0xb99b" name="SP_CS_KERNEL_GROUP_Z" variants="A6XX" usage="rp_blit"/> 3476 3477 <!-- TODO: what does KERNELDIM do exactly (blob sets it differently from turnip) --> 3478 <reg32 offset="0xa9d4" name="SP_CS_NDRANGE_0" variants="A7XX-" usage="rp_blit"> 3479 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/> 3480 <!-- localsize is value minus one: --> 3481 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 3482 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 3483 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 3484 </reg32> 3485 <reg32 offset="0xa9d5" name="SP_CS_NDRANGE_1" variants="A7XX-" usage="rp_blit"> 3486 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/> 3487 </reg32> 3488 <reg32 offset="0xa9d6" name="SP_CS_NDRANGE_2" variants="A7XX-" usage="rp_blit"> 3489 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/> 3490 </reg32> 3491 <reg32 offset="0xa9d7" name="SP_CS_NDRANGE_3" variants="A7XX-" usage="rp_blit"> 3492 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/> 3493 </reg32> 3494 <reg32 offset="0xa9d8" name="SP_CS_NDRANGE_4" variants="A7XX-" usage="rp_blit"> 3495 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/> 3496 </reg32> 3497 <reg32 offset="0xa9d9" name="SP_CS_NDRANGE_5" variants="A7XX-" usage="rp_blit"> 3498 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/> 3499 </reg32> 3500 <reg32 offset="0xa9da" name="SP_CS_NDRANGE_6" variants="A7XX-" usage="rp_blit"> 3501 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/> 3502 </reg32> 3503 <!--note: vulkan blob doesn't use these --> 3504 <reg32 offset="0xa9dc" name="SP_CS_KERNEL_GROUP_X" variants="A7XX-" usage="rp_blit"/> 3505 <reg32 offset="0xa9dd" name="SP_CS_KERNEL_GROUP_Y" variants="A7XX-" usage="rp_blit"/> 3506 <reg32 offset="0xa9de" name="SP_CS_KERNEL_GROUP_Z" variants="A7XX-" usage="rp_blit"/> 3507 3508 <enum name="a7xx_cs_yalign"> 3509 <value name="CS_YALIGN_1" value="8"/> 3510 <value name="CS_YALIGN_2" value="4"/> 3511 <value name="CS_YALIGN_4" value="2"/> 3512 <value name="CS_YALIGN_8" value="1"/> 3513 </enum> 3514 3515 <reg32 offset="0xa9db" name="SP_CS_WGE_CNTL" variants="A7XX-" usage="rp_blit"> 3516 <!-- gl_LocalInvocationIndex --> 3517 <bitfield name="LINEARLOCALIDREGID" low="0" high="7" type="a3xx_regid"/> 3518 <!-- Must match SP_CS_CTRL --> 3519 <bitfield name="THREADSIZE" pos="9" type="a6xx_threadsize"/> 3520 <doc> 3521 When this bit is enabled, the dispatch order interleaves 3522 the z coordinate instead of launching all workgroups 3523 with z=0, then all with z=1 and so on. 3524 </doc> 3525 <bitfield name="WORKGROUPRASTORDERZFIRSTEN" pos="11" type="boolean"/> 3526 <doc> 3527 When both fields are non-0 then the dispatcher uses 3528 these tile sizes to launch workgroups in a tiled manner 3529 when the x and y workgroup counts are 3530 both more than 1. 3531 </doc> 3532 <bitfield name="WGTILEWIDTH" low="20" high="25"/> 3533 <bitfield name="WGTILEHEIGHT" low="26" high="31"/> 3534 </reg32> 3535 3536 <reg32 offset="0xa9df" name="SP_CS_NDRANGE_7" variants="A7XX-" usage="cmd"> 3537 <!-- The size of the last workgroup. localsize is value minus one: --> 3538 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> 3539 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/> 3540 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/> 3541 </reg32> 3542 3543 <reg32 offset="0xb9a0" name="HLSQ_LOAD_STATE_FRAG_CMD"/> 3544 <reg64 offset="0xb9a1" name="HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR" align="16" type="address"/> 3545 <reg32 offset="0xb9a3" name="HLSQ_LOAD_STATE_FRAG_DATA"/> 3546 3547 <!-- mirror of SP_CS_BINDLESS_BASE --> 3548 <array offset="0xb9c0" name="HLSQ_CS_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="rp_blit"> 3549 <reg64 offset="0" name="DESCRIPTOR"> 3550 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 3551 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 3552 </reg64> 3553 </array> 3554 3555 <!-- new in a6xx gen4, mirror of SP_CS_CNTL_1? --> 3556 <reg32 offset="0xb9d0" name="HLSQ_CS_CTRL_REG1" variants="A6XX" usage="cmd"> 3557 <bitfield name="SHARED_SIZE" low="0" high="4" type="uint"/> 3558 <bitfield name="CONSTANTRAMMODE" low="5" high="6" type="a6xx_const_ram_mode"/> 3559 </reg32> 3560 3561 <reg32 offset="0xbb00" name="SP_DRAW_INITIATOR" variants="A6XX"> 3562 <bitfield name="STATE_ID" low="0" high="7"/> 3563 </reg32> 3564 3565 <reg32 offset="0xbb01" name="SP_KERNEL_INITIATOR" variants="A6XX"> 3566 <bitfield name="STATE_ID" low="0" high="7"/> 3567 </reg32> 3568 3569 <reg32 offset="0xbb02" name="SP_EVENT_INITIATOR" variants="A6XX"> 3570 <!-- I think only the low bit is actually used? --> 3571 <bitfield name="STATE_ID" low="16" high="23"/> 3572 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3573 </reg32> 3574 3575 <reg32 offset="0xbb08" name="SP_UPDATE_CNTL" variants="A6XX" usage="cmd"> 3576 <doc> 3577 This register clears pending loads queued up by 3578 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 3579 CP_LOAD_STATE6. 3580 </doc> 3581 3582 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 3583 <bitfield name="VS_STATE" pos="0" type="boolean"/> 3584 <bitfield name="HS_STATE" pos="1" type="boolean"/> 3585 <bitfield name="DS_STATE" pos="2" type="boolean"/> 3586 <bitfield name="GS_STATE" pos="3" type="boolean"/> 3587 <bitfield name="FS_STATE" pos="4" type="boolean"/> 3588 <bitfield name="CS_STATE" pos="5" type="boolean"/> 3589 3590 <bitfield name="CS_UAV" pos="6" type="boolean"/> 3591 <bitfield name="GFX_UAV" pos="7" type="boolean"/> 3592 3593 <!-- Note: these only do something when HLSQ_SHARED_CONSTS is set to 1 --> 3594 <bitfield name="CS_SHARED_CONST" pos="19" type="boolean"/> 3595 <bitfield name="GFX_SHARED_CONST" pos="8" type="boolean"/> 3596 3597 <!-- SS6_BINDLESS: one bit per bindless base --> 3598 <bitfield name="CS_BINDLESS" low="9" high="13" type="hex"/> 3599 <bitfield name="GFX_BINDLESS" low="14" high="18" type="hex"/> 3600 </reg32> 3601 3602 <reg32 offset="0xab1c" name="SP_DRAW_INITIATOR" variants="A7XX-"> 3603 <bitfield name="STATE_ID" low="0" high="7"/> 3604 </reg32> 3605 3606 <reg32 offset="0xab1d" name="SP_KERNEL_INITIATOR" variants="A7XX-"> 3607 <bitfield name="STATE_ID" low="0" high="7"/> 3608 </reg32> 3609 3610 <reg32 offset="0xab1e" name="SP_EVENT_INITIATOR" variants="A7XX-"> 3611 <bitfield name="STATE_ID" low="16" high="23"/> 3612 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3613 </reg32> 3614 3615 <reg32 offset="0xab1f" name="SP_UPDATE_CNTL" variants="A7XX-" usage="cmd"> 3616 <doc> 3617 This register clears pending loads queued up by 3618 CP_LOAD_STATE6. Each bit resets a particular kind(s) of 3619 CP_LOAD_STATE6. 3620 </doc> 3621 3622 <!-- per-stage state: shader, non-bindless UBO, textures, and samplers --> 3623 <bitfield name="VS_STATE" pos="0" type="boolean"/> 3624 <bitfield name="HS_STATE" pos="1" type="boolean"/> 3625 <bitfield name="DS_STATE" pos="2" type="boolean"/> 3626 <bitfield name="GS_STATE" pos="3" type="boolean"/> 3627 <bitfield name="FS_STATE" pos="4" type="boolean"/> 3628 <bitfield name="CS_STATE" pos="5" type="boolean"/> 3629 3630 <bitfield name="CS_UAV" pos="6" type="boolean"/> 3631 <bitfield name="GFX_UAV" pos="7" type="boolean"/> 3632 3633 <!-- SS6_BINDLESS: one bit per bindless base --> 3634 <bitfield name="CS_BINDLESS" low="9" high="16" type="hex"/> 3635 <bitfield name="GFX_BINDLESS" low="17" high="24" type="hex"/> 3636 </reg32> 3637 3638 <reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 3639 <reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 3640 3641 <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX_0" stride="1" length="64" variants="A7XX-"/> 3642 3643 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd"> 3644 <doc> 3645 Shared constants are intended to be used for Vulkan push 3646 constants. When enabled, 8 vec4's are reserved in the FS 3647 const pool and 16 in the geometry const pool although 3648 only 8 are actually used (why?) and they are mapped to 3649 c504-c511 in each stage. Both VS and FS shared consts 3650 are written using ST6_CONSTANTS/SB6_UAV, so that both 3651 the geometry and FS shared consts can be written at once 3652 by using CP_LOAD_STATE6 rather than 3653 CP_LOAD_STATE6_FRAG/CP_LOAD_STATE6_GEOM. In addition 3654 DST_OFF and NUM_UNIT are in units of dwords instead of 3655 vec4's. 3656 3657 There is also a separate shared constant pool for CS, 3658 which is loaded through CP_LOAD_STATE6_FRAG with 3659 ST6_UBO/ST6_UAV. However the only real difference for CS 3660 is the dword units. 3661 </doc> 3662 <bitfield name="ENABLE" pos="0" type="boolean"/> 3663 </reg32> 3664 3665 <!-- mirror of SP_GFX_BINDLESS_BASE --> 3666 <array offset="0xbb20" name="HLSQ_BINDLESS_BASE" stride="2" length="5" variants="A6XX" usage="cmd"> 3667 <reg64 offset="0" name="DESCRIPTOR"> 3668 <bitfield name="DESC_SIZE" low="0" high="1" type="a6xx_bindless_descriptor_size"/> 3669 <bitfield name="ADDR" low="2" high="63" shr="2" type="address"/> 3670 </reg64> 3671 </array> 3672 3673 <reg32 offset="0xbd80" name="HLSQ_2D_EVENT_CMD"> 3674 <bitfield name="STATE_ID" low="8" high="15"/> 3675 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 3676 </reg32> 3677 3678 <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00" variants="A6XX" usage="cmd"/> <!-- all bits valid except bit 29 --> 3679 <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01" low="4" high="6" variants="A6XX" usage="cmd"/> 3680 <reg32 offset="0xbe04" name="HLSQ_DBG_ECO_CNTL" variants="A6XX" usage="cmd"/> 3681 <reg32 offset="0xbe05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 3682 <reg32 offset="0xbe08" name="HLSQ_UNKNOWN_BE08" low="0" high="15"/> 3683 <array offset="0xbe10" name="HLSQ_PERFCTR_HLSQ_SEL" stride="1" length="6"/> 3684 3685 <!-- TODO: some valid registers between 0xbe20 and 0xbe33 --> 3686 <reg32 offset="0xbe22" name="HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE"/> 3687 3688 <reg32 offset="0xc000" name="SP_AHB_READ_APERTURE" variants="A7XX-"/> 3689 3690 <!-- Don't know if these are SP, always 0 --> 3691 <reg64 offset="0x0ce2" name="SP_UNKNOWN_0CE2" variants="A7XX-" usage="cmd"/> 3692 <reg64 offset="0x0ce4" name="SP_UNKNOWN_0CE4" variants="A7XX-" usage="cmd"/> 3693 <reg64 offset="0x0ce6" name="SP_UNKNOWN_0CE6" variants="A7XX-" usage="cmd"/> 3694 3695 <!-- 3696 These special registers signal the beginning/end of an event 3697 sequence. The sequence used internally for an event looks like: 3698 - write EVENT_CMD pipe register 3699 - write CP_EVENT_START 3700 - write SP_EVENT_INITIATOR with event or SP_DRAW_INITIATOR 3701 - write PC_EVENT_INITIATOR with event or PC_DRAW_INITIATOR 3702 - write SP_EVENT_INITIATOR(CONTEXT_DONE) 3703 - write PC_EVENT_INITIATOR(CONTEXT_DONE) 3704 - write CP_EVENT_END 3705 Writing to CP_EVENT_END seems to actually trigger the context roll 3706 --> 3707 <reg32 offset="0xd600" name="CP_EVENT_START"> 3708 <bitfield name="STATE_ID" low="0" high="7"/> 3709 </reg32> 3710 <reg32 offset="0xd601" name="CP_EVENT_END"> 3711 <bitfield name="STATE_ID" low="0" high="7"/> 3712 </reg32> 3713 <reg32 offset="0xd700" name="CP_2D_EVENT_START"> 3714 <bitfield name="STATE_ID" low="0" high="7"/> 3715 </reg32> 3716 <reg32 offset="0xd701" name="CP_2D_EVENT_END"> 3717 <bitfield name="STATE_ID" low="0" high="7"/> 3718 </reg32> 3719</domain> 3720 3721<domain name="A6XX_PDC" width="32"> 3722 <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/> 3723 <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/> 3724 <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/> 3725 <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/> 3726 <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/> 3727 <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/> 3728 <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/> 3729 <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/> 3730 <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/> 3731 <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/> 3732 <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/> 3733 <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/> 3734 <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/> 3735 <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/> 3736 <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/> 3737 <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/> 3738 <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/> 3739 <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/> 3740 <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/> 3741 <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/> 3742 <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/> 3743 <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/> 3744 <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/> 3745 <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/> 3746 <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/> 3747 <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/> 3748</domain> 3749 3750<domain name="A6XX_PDC_GPU_SEQ" width="32"> 3751 <reg32 offset="0x0" name="MEM_0"/> 3752</domain> 3753 3754<domain name="A6XX_CX_DBGC" width="32"> 3755 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A"> 3756 <bitfield high="7" low="0" name="PING_INDEX"/> 3757 <bitfield high="15" low="8" name="PING_BLK_SEL"/> 3758 </reg32> 3759 <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/> 3760 <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/> 3761 <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/> 3762 <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT"> 3763 <bitfield high="5" low="0" name="TRACEEN"/> 3764 <bitfield high="14" low="12" name="GRANU"/> 3765 <bitfield high="31" low="28" name="SEGT"/> 3766 </reg32> 3767 <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM"> 3768 <bitfield high="27" low="24" name="ENABLE"/> 3769 </reg32> 3770 <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/> 3771 <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/> 3772 <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/> 3773 <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/> 3774 <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/> 3775 <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/> 3776 <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/> 3777 <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/> 3778 <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0"> 3779 <bitfield high="3" low="0" name="BYTEL0"/> 3780 <bitfield high="7" low="4" name="BYTEL1"/> 3781 <bitfield high="11" low="8" name="BYTEL2"/> 3782 <bitfield high="15" low="12" name="BYTEL3"/> 3783 <bitfield high="19" low="16" name="BYTEL4"/> 3784 <bitfield high="23" low="20" name="BYTEL5"/> 3785 <bitfield high="27" low="24" name="BYTEL6"/> 3786 <bitfield high="31" low="28" name="BYTEL7"/> 3787 </reg32> 3788 <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1"> 3789 <bitfield high="3" low="0" name="BYTEL8"/> 3790 <bitfield high="7" low="4" name="BYTEL9"/> 3791 <bitfield high="11" low="8" name="BYTEL10"/> 3792 <bitfield high="15" low="12" name="BYTEL11"/> 3793 <bitfield high="19" low="16" name="BYTEL12"/> 3794 <bitfield high="23" low="20" name="BYTEL13"/> 3795 <bitfield high="27" low="24" name="BYTEL14"/> 3796 <bitfield high="31" low="28" name="BYTEL15"/> 3797 </reg32> 3798 3799 <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/> 3800 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> 3801</domain> 3802 3803<domain name="A7XX_CX_DBGC" width="32"> 3804 <!-- Bitfields shifted, but otherwise the same: --> 3805 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A" variants="A7XX-"> 3806 <bitfield high="7" low="0" name="PING_INDEX"/> 3807 <bitfield high="24" low="16" name="PING_BLK_SEL"/> 3808 </reg32> 3809</domain> 3810 3811<domain name="A6XX_CX_MISC" width="32" prefix="variant" varset="chip"> 3812 <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/> 3813 <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/> 3814 <reg32 offset="0x0039" name="CX_MISC_TCM_RET_CNTL" variants="A7XX-"/> 3815 <reg32 offset="0x0400" name="CX_MISC_SW_FUSE_VALUE" variants="A7XX-"> 3816 <bitfield pos="0" name="FASTBLEND" type="boolean"/> 3817 <bitfield pos="1" name="LPAC" type="boolean"/> 3818 <bitfield pos="2" name="RAYTRACING" type="boolean"/> 3819 </reg32> 3820</domain> 3821 3822</database> 3823