xref: /linux/drivers/gpu/drm/msm/registers/adreno/a5xx_perfcntrs.json (revision 637315cb400eed1dbe721954fea437a61a2d65b2)
1*5442bafdSRob Clark{
2*5442bafdSRob Clark    "chip": "A5XX",
3*5442bafdSRob Clark    "groups": [
4*5442bafdSRob Clark        {
5*5442bafdSRob Clark            "name": "CP",
6*5442bafdSRob Clark            "num": 8,
7*5442bafdSRob Clark            "reserved": [ 0 ],
8*5442bafdSRob Clark            "select": "CP_PERFCTR_CP_SEL_{}",
9*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_CP_{}_LO",
10*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_CP_{}_HI",
11*5442bafdSRob Clark            "countable_type": "a5xx_cp_perfcounter_select"
12*5442bafdSRob Clark        },
13*5442bafdSRob Clark        {
14*5442bafdSRob Clark            "name": "CCU",
15*5442bafdSRob Clark            "num": 4,
16*5442bafdSRob Clark            "select": "RB_PERFCTR_CCU_SEL_{}",
17*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_CCU_{}_LO",
18*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_CCU_{}_HI",
19*5442bafdSRob Clark            "countable_type": "a5xx_ccu_perfcounter_select"
20*5442bafdSRob Clark        },
21*5442bafdSRob Clark        {
22*5442bafdSRob Clark            "name": "TSE",
23*5442bafdSRob Clark            "num": 4,
24*5442bafdSRob Clark            "select": "GRAS_PERFCTR_TSE_SEL_{}",
25*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_TSE_{}_LO",
26*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_TSE_{}_HI",
27*5442bafdSRob Clark            "countable_type": "a5xx_tse_perfcounter_select"
28*5442bafdSRob Clark        },
29*5442bafdSRob Clark        {
30*5442bafdSRob Clark            "name": "RAS",
31*5442bafdSRob Clark            "num": 4,
32*5442bafdSRob Clark            "select": "GRAS_PERFCTR_RAS_SEL_{}",
33*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_RAS_{}_LO",
34*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_RAS_{}_HI",
35*5442bafdSRob Clark            "countable_type": "a5xx_ras_perfcounter_select"
36*5442bafdSRob Clark        },
37*5442bafdSRob Clark        {
38*5442bafdSRob Clark            "name": "LRZ",
39*5442bafdSRob Clark            "num": 4,
40*5442bafdSRob Clark            "select": "GRAS_PERFCTR_LRZ_SEL_{}",
41*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_LRZ_{}_LO",
42*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_LRZ_{}_HI",
43*5442bafdSRob Clark            "countable_type": "a5xx_lrz_perfcounter_select"
44*5442bafdSRob Clark        },
45*5442bafdSRob Clark        {
46*5442bafdSRob Clark            "name": "HLSQ",
47*5442bafdSRob Clark            "num": 8,
48*5442bafdSRob Clark            "select": "HLSQ_PERFCTR_HLSQ_SEL_{}",
49*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_HLSQ_{}_LO",
50*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_HLSQ_{}_HI",
51*5442bafdSRob Clark            "countable_type": "a5xx_hlsq_perfcounter_select"
52*5442bafdSRob Clark        },
53*5442bafdSRob Clark        {
54*5442bafdSRob Clark            "name": "PC",
55*5442bafdSRob Clark            "num": 8,
56*5442bafdSRob Clark            "select": "PC_PERFCTR_PC_SEL_{}",
57*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_PC_{}_LO",
58*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_PC_{}_HI",
59*5442bafdSRob Clark            "countable_type": "a5xx_pc_perfcounter_select"
60*5442bafdSRob Clark        },
61*5442bafdSRob Clark        {
62*5442bafdSRob Clark            "name": "RB",
63*5442bafdSRob Clark            "num": 8,
64*5442bafdSRob Clark            "select": "RB_PERFCTR_RB_SEL_{}",
65*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_RB_{}_LO",
66*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_RB_{}_HI",
67*5442bafdSRob Clark            "countable_type": "a5xx_rb_perfcounter_select"
68*5442bafdSRob Clark        },
69*5442bafdSRob Clark        {
70*5442bafdSRob Clark            "name": "RBBM",
71*5442bafdSRob Clark            "num": 4,
72*5442bafdSRob Clark            "reserved": [ 0 ],
73*5442bafdSRob Clark            "select": "RBBM_PERFCTR_RBBM_SEL_{}",
74*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_RBBM_{}_LO",
75*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_RBBM_{}_HI",
76*5442bafdSRob Clark            "countable_type": "a5xx_rbbm_perfcounter_select"
77*5442bafdSRob Clark        },
78*5442bafdSRob Clark        {
79*5442bafdSRob Clark            "name": "SP",
80*5442bafdSRob Clark            "num": 12,
81*5442bafdSRob Clark            "reserved": [ 0 ],
82*5442bafdSRob Clark            "select": "SP_PERFCTR_SP_SEL_{}",
83*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_SP_{}_LO",
84*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_SP_{}_HI",
85*5442bafdSRob Clark            "countable_type": "a5xx_sp_perfcounter_select"
86*5442bafdSRob Clark        },
87*5442bafdSRob Clark        {
88*5442bafdSRob Clark            "name": "TP",
89*5442bafdSRob Clark            "num": 8,
90*5442bafdSRob Clark            "select": "TPL1_PERFCTR_TP_SEL_{}",
91*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_TP_{}_LO",
92*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_TP_{}_HI",
93*5442bafdSRob Clark            "countable_type": "a5xx_tp_perfcounter_select"
94*5442bafdSRob Clark        },
95*5442bafdSRob Clark        {
96*5442bafdSRob Clark            "name": "UCHE",
97*5442bafdSRob Clark            "num": 8,
98*5442bafdSRob Clark            "select": "UCHE_PERFCTR_UCHE_SEL_{}",
99*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_UCHE_{}_LO",
100*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_UCHE_{}_HI",
101*5442bafdSRob Clark            "countable_type": "a5xx_uche_perfcounter_select"
102*5442bafdSRob Clark        },
103*5442bafdSRob Clark        {
104*5442bafdSRob Clark            "name": "VFD",
105*5442bafdSRob Clark            "num": 8,
106*5442bafdSRob Clark            "select": "VFD_PERFCTR_VFD_SEL_{}",
107*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_VFD_{}_LO",
108*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_VFD_{}_HI",
109*5442bafdSRob Clark            "countable_type": "a5xx_vfd_perfcounter_select"
110*5442bafdSRob Clark        },
111*5442bafdSRob Clark        {
112*5442bafdSRob Clark            "name": "VPC",
113*5442bafdSRob Clark            "num": 4,
114*5442bafdSRob Clark            "select": "VPC_PERFCTR_VPC_SEL_{}",
115*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_VPC_{}_LO",
116*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_VPC_{}_HI",
117*5442bafdSRob Clark            "countable_type": "a5xx_vpc_perfcounter_select"
118*5442bafdSRob Clark        },
119*5442bafdSRob Clark        {
120*5442bafdSRob Clark            "name": "VSC",
121*5442bafdSRob Clark            "num": 2,
122*5442bafdSRob Clark            "select": "VSC_PERFCTR_VSC_SEL_{}",
123*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCTR_VSC_{}_LO",
124*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCTR_VSC_{}_HI",
125*5442bafdSRob Clark            "countable_type": "a5xx_vsc_perfcounter_select"
126*5442bafdSRob Clark        }
127*5442bafdSRob Clark    ]
128*5442bafdSRob Clark}
129