xref: /linux/drivers/gpu/drm/msm/registers/adreno/a2xx_perfcntrs.json (revision 637315cb400eed1dbe721954fea437a61a2d65b2)
1*5442bafdSRob Clark{
2*5442bafdSRob Clark    "chip": "A2XX",
3*5442bafdSRob Clark    "groups": [
4*5442bafdSRob Clark        {
5*5442bafdSRob Clark            "name": "CP",
6*5442bafdSRob Clark            "num": 1,
7*5442bafdSRob Clark            "select": "CP_PERFCOUNTER_SELECT",
8*5442bafdSRob Clark            "counter_lo": "CP_PERFCOUNTER_LO",
9*5442bafdSRob Clark            "counter_hi": "CP_PERFCOUNTER_HI",
10*5442bafdSRob Clark            "countable_type": "a2xx_cp_perfcount_sel"
11*5442bafdSRob Clark        },
12*5442bafdSRob Clark        {
13*5442bafdSRob Clark            "name": "PA_SU",
14*5442bafdSRob Clark            "num": 4,
15*5442bafdSRob Clark            "select": "PA_SU_PERFCOUNTER{}_SELECT",
16*5442bafdSRob Clark            "counter_lo": "PA_SU_PERFCOUNTER{}_LOW",
17*5442bafdSRob Clark            "counter_hi": "PA_SU_PERFCOUNTER{}_HI",
18*5442bafdSRob Clark            "countable_type": "a2xx_su_perfcnt_select"
19*5442bafdSRob Clark        },
20*5442bafdSRob Clark        {
21*5442bafdSRob Clark            "name": "PA_SC",
22*5442bafdSRob Clark            "num": 1,
23*5442bafdSRob Clark            "select": "PA_SC_PERFCOUNTER{}_SELECT",
24*5442bafdSRob Clark            "counter_lo": "PA_SC_PERFCOUNTER{}_LOW",
25*5442bafdSRob Clark            "counter_hi": "PA_SC_PERFCOUNTER{}_HI",
26*5442bafdSRob Clark            "countable_type": "a2xx_sc_perfcnt_select"
27*5442bafdSRob Clark        },
28*5442bafdSRob Clark        {
29*5442bafdSRob Clark            "name": "VGT",
30*5442bafdSRob Clark            "num": 4,
31*5442bafdSRob Clark            "select": "VGT_PERFCOUNTER{}_SELECT",
32*5442bafdSRob Clark            "counter_lo": "VGT_PERFCOUNTER{}_LOW",
33*5442bafdSRob Clark            "counter_hi": "VGT_PERFCOUNTER{}_HI",
34*5442bafdSRob Clark            "countable_type": "a2xx_vgt_perfcount_select"
35*5442bafdSRob Clark        },
36*5442bafdSRob Clark        {
37*5442bafdSRob Clark            "name": "TCR",
38*5442bafdSRob Clark            "num": 2,
39*5442bafdSRob Clark            "select": "TCR_PERFCOUNTER{}_SELECT",
40*5442bafdSRob Clark            "counter_lo": "TCR_PERFCOUNTER{}_LOW",
41*5442bafdSRob Clark            "counter_hi": "TCR_PERFCOUNTER{}_HI",
42*5442bafdSRob Clark            "countable_type": "a2xx_tcr_perfcount_select"
43*5442bafdSRob Clark        },
44*5442bafdSRob Clark        {
45*5442bafdSRob Clark            "name": "TP0",
46*5442bafdSRob Clark            "num": 2,
47*5442bafdSRob Clark            "select": "TP0_PERFCOUNTER{}_SELECT",
48*5442bafdSRob Clark            "counter_lo": "TP0_PERFCOUNTER{}_LOW",
49*5442bafdSRob Clark            "counter_hi": "TP0_PERFCOUNTER{}_HI",
50*5442bafdSRob Clark            "countable_type": "a2xx_tp_perfcount_select"
51*5442bafdSRob Clark        },
52*5442bafdSRob Clark        {
53*5442bafdSRob Clark            "name": "TCM",
54*5442bafdSRob Clark            "num": 2,
55*5442bafdSRob Clark            "select": "TCM_PERFCOUNTER{}_SELECT",
56*5442bafdSRob Clark            "counter_lo": "TCM_PERFCOUNTER{}_LOW",
57*5442bafdSRob Clark            "counter_hi": "TCM_PERFCOUNTER{}_HI",
58*5442bafdSRob Clark            "countable_type": "a2xx_tcm_perfcount_select"
59*5442bafdSRob Clark        },
60*5442bafdSRob Clark        {
61*5442bafdSRob Clark            "name": "TCF",
62*5442bafdSRob Clark            "num": 12,
63*5442bafdSRob Clark            "select": "TCF_PERFCOUNTER{}_SELECT",
64*5442bafdSRob Clark            "counter_lo": "TCF_PERFCOUNTER{}_LOW",
65*5442bafdSRob Clark            "counter_hi": "TCF_PERFCOUNTER{}_HI",
66*5442bafdSRob Clark            "countable_type": "a2xx_tcf_perfcount_select"
67*5442bafdSRob Clark        },
68*5442bafdSRob Clark        {
69*5442bafdSRob Clark            "name": "SQ",
70*5442bafdSRob Clark            "num": 4,
71*5442bafdSRob Clark            "select": "SQ_PERFCOUNTER{}_SELECT",
72*5442bafdSRob Clark            "counter_lo": "SQ_PERFCOUNTER{}_LOW",
73*5442bafdSRob Clark            "counter_hi": "SQ_PERFCOUNTER{}_HI",
74*5442bafdSRob Clark            "countable_type": "a2xx_sq_perfcnt_select"
75*5442bafdSRob Clark        },
76*5442bafdSRob Clark        {
77*5442bafdSRob Clark            "name": "SX",
78*5442bafdSRob Clark            "num": 1,
79*5442bafdSRob Clark            "select": "SX_PERFCOUNTER{}_SELECT",
80*5442bafdSRob Clark            "counter_lo": "SX_PERFCOUNTER{}_LOW",
81*5442bafdSRob Clark            "counter_hi": "SX_PERFCOUNTER{}_HI",
82*5442bafdSRob Clark            "countable_type": "a2xx_sx_perfcnt_select"
83*5442bafdSRob Clark        },
84*5442bafdSRob Clark        {
85*5442bafdSRob Clark            "name": "MH",
86*5442bafdSRob Clark            "num": 2,
87*5442bafdSRob Clark            "select": "MH_PERFCOUNTER{}_SELECT",
88*5442bafdSRob Clark            "counter_lo": "MH_PERFCOUNTER{}_LOW",
89*5442bafdSRob Clark            "counter_hi": "MH_PERFCOUNTER{}_HI",
90*5442bafdSRob Clark            "countable_type": "a2xx_mh_perfcnt_select"
91*5442bafdSRob Clark        },
92*5442bafdSRob Clark        {
93*5442bafdSRob Clark            "name": "RBBM",
94*5442bafdSRob Clark            "num": 2,
95*5442bafdSRob Clark            "select": "RBBM_PERFCOUNTER{}_SELECT",
96*5442bafdSRob Clark            "counter_lo": "RBBM_PERFCOUNTER{}_LO",
97*5442bafdSRob Clark            "counter_hi": "RBBM_PERFCOUNTER{}_HI",
98*5442bafdSRob Clark            "countable_type": "a2xx_rbbm_perfcount1_sel"
99*5442bafdSRob Clark        },
100*5442bafdSRob Clark        {
101*5442bafdSRob Clark            "name": "RB",
102*5442bafdSRob Clark            "num": 4,
103*5442bafdSRob Clark            "select": "RB_PERFCOUNTER{}_SELECT",
104*5442bafdSRob Clark            "counter_lo": "RB_PERFCOUNTER{}_LOW",
105*5442bafdSRob Clark            "counter_hi": "RB_PERFCOUNTER{}_HI",
106*5442bafdSRob Clark            "countable_type": "a2xx_rb_perfcnt_select"
107*5442bafdSRob Clark        }
108*5442bafdSRob Clark    ]
109*5442bafdSRob Clark}
110