1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include "msm_ringbuffer.h" 8 #include "msm_gpu.h" 9 10 static uint num_hw_submissions = 8; 11 MODULE_PARM_DESC(num_hw_submissions, "The max # of jobs to write into ringbuffer (default 8)"); 12 module_param(num_hw_submissions, uint, 0600); 13 14 static struct dma_fence *msm_job_run(struct drm_sched_job *job) 15 { 16 struct msm_gem_submit *submit = to_msm_submit(job); 17 struct msm_fence_context *fctx = submit->ring->fctx; 18 struct msm_gpu *gpu = submit->gpu; 19 int i; 20 21 msm_fence_init(submit->hw_fence, fctx); 22 23 for (i = 0; i < submit->nr_bos; i++) { 24 struct drm_gem_object *obj = &submit->bos[i].obj->base; 25 26 msm_gem_vma_unpin_fenced(submit->bos[i].vma, fctx); 27 msm_gem_unpin_active(obj); 28 submit->bos[i].flags &= ~(BO_VMA_PINNED | BO_OBJ_PINNED); 29 } 30 31 /* TODO move submit path over to using a per-ring lock.. */ 32 mutex_lock(&gpu->lock); 33 34 msm_gpu_submit(gpu, submit); 35 36 mutex_unlock(&gpu->lock); 37 38 return dma_fence_get(submit->hw_fence); 39 } 40 41 static void msm_job_free(struct drm_sched_job *job) 42 { 43 struct msm_gem_submit *submit = to_msm_submit(job); 44 45 drm_sched_job_cleanup(job); 46 msm_gem_submit_put(submit); 47 } 48 49 static const struct drm_sched_backend_ops msm_sched_ops = { 50 .run_job = msm_job_run, 51 .free_job = msm_job_free 52 }; 53 54 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, 55 void *memptrs, uint64_t memptrs_iova) 56 { 57 struct msm_ringbuffer *ring; 58 long sched_timeout; 59 char name[32]; 60 int ret; 61 62 /* We assume everwhere that MSM_GPU_RINGBUFFER_SZ is a power of 2 */ 63 BUILD_BUG_ON(!is_power_of_2(MSM_GPU_RINGBUFFER_SZ)); 64 65 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 66 if (!ring) { 67 ret = -ENOMEM; 68 goto fail; 69 } 70 71 ring->gpu = gpu; 72 ring->id = id; 73 74 ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ, 75 check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY), 76 gpu->aspace, &ring->bo, &ring->iova); 77 78 if (IS_ERR(ring->start)) { 79 ret = PTR_ERR(ring->start); 80 ring->start = NULL; 81 goto fail; 82 } 83 84 msm_gem_object_set_name(ring->bo, "ring%d", id); 85 86 ring->end = ring->start + (MSM_GPU_RINGBUFFER_SZ >> 2); 87 ring->next = ring->start; 88 ring->cur = ring->start; 89 90 ring->memptrs = memptrs; 91 ring->memptrs_iova = memptrs_iova; 92 93 /* currently managing hangcheck ourselves: */ 94 sched_timeout = MAX_SCHEDULE_TIMEOUT; 95 96 ret = drm_sched_init(&ring->sched, &msm_sched_ops, 97 num_hw_submissions, 0, sched_timeout, 98 NULL, NULL, to_msm_bo(ring->bo)->name, gpu->dev->dev); 99 if (ret) { 100 goto fail; 101 } 102 103 INIT_LIST_HEAD(&ring->submits); 104 spin_lock_init(&ring->submit_lock); 105 spin_lock_init(&ring->preempt_lock); 106 107 snprintf(name, sizeof(name), "gpu-ring-%d", ring->id); 108 109 ring->fctx = msm_fence_context_alloc(gpu->dev, &ring->memptrs->fence, name); 110 111 return ring; 112 113 fail: 114 msm_ringbuffer_destroy(ring); 115 return ERR_PTR(ret); 116 } 117 118 void msm_ringbuffer_destroy(struct msm_ringbuffer *ring) 119 { 120 if (IS_ERR_OR_NULL(ring)) 121 return; 122 123 drm_sched_fini(&ring->sched); 124 125 msm_fence_context_free(ring->fctx); 126 127 msm_gem_kernel_put(ring->bo, ring->gpu->aspace); 128 129 kfree(ring); 130 } 131