1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include "msm_ringbuffer.h" 8 #include "msm_gpu.h" 9 10 static uint num_hw_submissions = 8; 11 MODULE_PARM_DESC(num_hw_submissions, "The max # of jobs to write into ringbuffer (default 8)"); 12 module_param(num_hw_submissions, uint, 0600); 13 14 static struct dma_fence *msm_job_run(struct drm_sched_job *job) 15 { 16 struct msm_gem_submit *submit = to_msm_submit(job); 17 struct msm_fence_context *fctx = submit->ring->fctx; 18 struct msm_gpu *gpu = submit->gpu; 19 struct drm_device *dev = gpu->dev; 20 unsigned nr_cmds = submit->nr_cmds; 21 int i; 22 23 msm_fence_init(submit->hw_fence, fctx); 24 25 mutex_lock(&dev->gem_lru_mutex); 26 27 for (i = 0; i < submit->nr_bos; i++) { 28 struct drm_gem_object *obj = submit->bos[i].obj; 29 30 msm_gem_unpin_active(obj); 31 } 32 33 submit->bos_pinned = false; 34 35 mutex_unlock(&dev->gem_lru_mutex); 36 37 /* TODO move submit path over to using a per-ring lock.. */ 38 mutex_lock(&gpu->lock); 39 40 if (submit->queue->ctx->closed) 41 submit->nr_cmds = 0; 42 43 msm_gpu_submit(gpu, submit); 44 45 submit->nr_cmds = nr_cmds; 46 47 mutex_unlock(&gpu->lock); 48 49 return dma_fence_get(submit->hw_fence); 50 } 51 52 static void msm_job_free(struct drm_sched_job *job) 53 { 54 struct msm_gem_submit *submit = to_msm_submit(job); 55 56 drm_sched_job_cleanup(job); 57 msm_gem_submit_put(submit); 58 } 59 60 static const struct drm_sched_backend_ops msm_sched_ops = { 61 .run_job = msm_job_run, 62 .free_job = msm_job_free 63 }; 64 65 struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id, 66 void *memptrs, uint64_t memptrs_iova) 67 { 68 struct drm_sched_init_args args = { 69 .ops = &msm_sched_ops, 70 .credit_limit = num_hw_submissions, 71 .timeout = MAX_SCHEDULE_TIMEOUT, 72 .dev = gpu->dev->dev, 73 }; 74 struct msm_ringbuffer *ring; 75 char name[32]; 76 int ret; 77 78 /* We assume everywhere that MSM_GPU_RINGBUFFER_SZ is a power of 2 */ 79 BUILD_BUG_ON(!is_power_of_2(MSM_GPU_RINGBUFFER_SZ)); 80 81 ring = kzalloc_obj(*ring); 82 if (!ring) { 83 ret = -ENOMEM; 84 goto fail; 85 } 86 87 ring->gpu = gpu; 88 ring->id = id; 89 90 ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ, 91 check_apriv(gpu, MSM_BO_WC | MSM_BO_GPU_READONLY), 92 gpu->vm, &ring->bo, &ring->iova); 93 94 if (IS_ERR(ring->start)) { 95 ret = PTR_ERR(ring->start); 96 ring->start = NULL; 97 goto fail; 98 } 99 100 msm_gem_object_set_name(ring->bo, "ring%d", id); 101 args.name = to_msm_bo(ring->bo)->name; 102 103 ring->end = ring->start + (MSM_GPU_RINGBUFFER_SZ >> 2); 104 ring->next = ring->start; 105 ring->cur = ring->start; 106 107 ring->memptrs = memptrs; 108 ring->memptrs_iova = memptrs_iova; 109 110 ret = drm_sched_init(&ring->sched, &args); 111 if (ret) { 112 goto fail; 113 } 114 115 INIT_LIST_HEAD(&ring->submits); 116 spin_lock_init(&ring->submit_lock); 117 spin_lock_init(&ring->preempt_lock); 118 119 snprintf(name, sizeof(name), "gpu-ring-%d", ring->id); 120 121 ring->fctx = msm_fence_context_alloc(gpu->dev, &ring->memptrs->fence, name); 122 123 return ring; 124 125 fail: 126 msm_ringbuffer_destroy(ring); 127 return ERR_PTR(ret); 128 } 129 130 void msm_ringbuffer_destroy(struct msm_ringbuffer *ring) 131 { 132 if (IS_ERR_OR_NULL(ring)) 133 return; 134 135 drm_sched_fini(&ring->sched); 136 137 msm_fence_context_free(ring->fctx); 138 139 msm_gem_kernel_put(ring->bo, ring->gpu->vm); 140 141 kfree(ring); 142 } 143