xref: /linux/drivers/gpu/drm/msm/msm_rd.c (revision f2527d8f566a45fa00ee5abd04d1c9476d4d704f) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 /* For debugging crashes, userspace can:
8  *
9  *   tail -f /sys/kernel/debug/dri/<minor>/rd > logfile.rd
10  *
11  * to log the cmdstream in a format that is understood by freedreno/cffdump
12  * utility.  By comparing the last successfully completed fence #, to the
13  * cmdstream for the next fence, you can narrow down which process and submit
14  * caused the gpu crash/lockup.
15  *
16  * Additionally:
17  *
18  *   tail -f /sys/kernel/debug/dri/<minor>/hangrd > logfile.rd
19  *
20  * will capture just the cmdstream from submits which triggered a GPU hang.
21  *
22  * This bypasses drm_debugfs_create_files() mainly because we need to use
23  * our own fops for a bit more control.  In particular, we don't want to
24  * do anything if userspace doesn't have the debugfs file open.
25  *
26  * The module-param "rd_full", which defaults to false, enables snapshotting
27  * all (non-written) buffers in the submit, rather than just cmdstream bo's.
28  * This is useful to capture the contents of (for example) vbo's or textures,
29  * or shader programs (if not emitted inline in cmdstream).
30  */
31 
32 #include <linux/circ_buf.h>
33 #include <linux/debugfs.h>
34 #include <linux/kfifo.h>
35 #include <linux/uaccess.h>
36 #include <linux/wait.h>
37 
38 #include <drm/drm_file.h>
39 
40 #include "msm_drv.h"
41 #include "msm_gpu.h"
42 #include "msm_gem.h"
43 
44 bool rd_full = false;
45 MODULE_PARM_DESC(rd_full, "If true, $debugfs/.../rd will snapshot all buffer contents");
46 module_param_named(rd_full, rd_full, bool, 0600);
47 
48 #ifdef CONFIG_DEBUG_FS
49 
50 enum rd_sect_type {
51 	RD_NONE,
52 	RD_TEST,       /* ascii text */
53 	RD_CMD,        /* ascii text */
54 	RD_GPUADDR,    /* u32 gpuaddr, u32 size */
55 	RD_CONTEXT,    /* raw dump */
56 	RD_CMDSTREAM,  /* raw dump */
57 	RD_CMDSTREAM_ADDR, /* gpu addr of cmdstream */
58 	RD_PARAM,      /* u32 param_type, u32 param_val, u32 bitlen */
59 	RD_FLUSH,      /* empty, clear previous params */
60 	RD_PROGRAM,    /* shader program, raw dump */
61 	RD_VERT_SHADER,
62 	RD_FRAG_SHADER,
63 	RD_BUFFER_CONTENTS,
64 	RD_GPU_ID,
65 	RD_CHIP_ID,
66 };
67 
68 #define BUF_SZ 512  /* should be power of 2 */
69 
70 /* space used: */
71 #define circ_count(circ) \
72 	(CIRC_CNT((circ)->head, (circ)->tail, BUF_SZ))
73 #define circ_count_to_end(circ) \
74 	(CIRC_CNT_TO_END((circ)->head, (circ)->tail, BUF_SZ))
75 /* space available: */
76 #define circ_space(circ) \
77 	(CIRC_SPACE((circ)->head, (circ)->tail, BUF_SZ))
78 #define circ_space_to_end(circ) \
79 	(CIRC_SPACE_TO_END((circ)->head, (circ)->tail, BUF_SZ))
80 
81 struct msm_rd_state {
82 	struct drm_device *dev;
83 
84 	bool open;
85 
86 	/* current submit to read out: */
87 	struct msm_gem_submit *submit;
88 
89 	/* fifo access is synchronized on the producer side by
90 	 * gpu->lock held by submit code (otherwise we could
91 	 * end up w/ cmds logged in different order than they
92 	 * were executed).  And read_lock synchronizes the reads
93 	 */
94 	struct mutex read_lock;
95 
96 	wait_queue_head_t fifo_event;
97 	struct circ_buf fifo;
98 
99 	char buf[BUF_SZ];
100 };
101 
102 static void rd_write(struct msm_rd_state *rd, const void *buf, int sz)
103 {
104 	struct circ_buf *fifo = &rd->fifo;
105 	const char *ptr = buf;
106 
107 	while (sz > 0) {
108 		char *fptr = &fifo->buf[fifo->head];
109 		int n;
110 
111 		wait_event(rd->fifo_event, circ_space(&rd->fifo) > 0 || !rd->open);
112 		if (!rd->open)
113 			return;
114 
115 		/* Note that smp_load_acquire() is not strictly required
116 		 * as CIRC_SPACE_TO_END() does not access the tail more
117 		 * than once.
118 		 */
119 		n = min(sz, circ_space_to_end(&rd->fifo));
120 		memcpy(fptr, ptr, n);
121 
122 		smp_store_release(&fifo->head, (fifo->head + n) & (BUF_SZ - 1));
123 		sz  -= n;
124 		ptr += n;
125 
126 		wake_up_all(&rd->fifo_event);
127 	}
128 }
129 
130 static void rd_write_section(struct msm_rd_state *rd,
131 		enum rd_sect_type type, const void *buf, int sz)
132 {
133 	rd_write(rd, &type, 4);
134 	rd_write(rd, &sz, 4);
135 	rd_write(rd, buf, sz);
136 }
137 
138 static ssize_t rd_read(struct file *file, char __user *buf,
139 		size_t sz, loff_t *ppos)
140 {
141 	struct msm_rd_state *rd = file->private_data;
142 	struct circ_buf *fifo = &rd->fifo;
143 	const char *fptr = &fifo->buf[fifo->tail];
144 	int n = 0, ret = 0;
145 
146 	mutex_lock(&rd->read_lock);
147 
148 	ret = wait_event_interruptible(rd->fifo_event,
149 			circ_count(&rd->fifo) > 0);
150 	if (ret)
151 		goto out;
152 
153 	/* Note that smp_load_acquire() is not strictly required
154 	 * as CIRC_CNT_TO_END() does not access the head more than
155 	 * once.
156 	 */
157 	n = min_t(int, sz, circ_count_to_end(&rd->fifo));
158 	if (copy_to_user(buf, fptr, n)) {
159 		ret = -EFAULT;
160 		goto out;
161 	}
162 
163 	smp_store_release(&fifo->tail, (fifo->tail + n) & (BUF_SZ - 1));
164 	*ppos += n;
165 
166 	wake_up_all(&rd->fifo_event);
167 
168 out:
169 	mutex_unlock(&rd->read_lock);
170 	if (ret)
171 		return ret;
172 	return n;
173 }
174 
175 static int rd_open(struct inode *inode, struct file *file)
176 {
177 	struct msm_rd_state *rd = inode->i_private;
178 	struct drm_device *dev = rd->dev;
179 	struct msm_drm_private *priv = dev->dev_private;
180 	struct msm_gpu *gpu = priv->gpu;
181 	uint64_t val;
182 	uint32_t gpu_id;
183 	uint32_t zero = 0;
184 	int ret = 0;
185 
186 	if (!gpu)
187 		return -ENODEV;
188 
189 	mutex_lock(&gpu->lock);
190 
191 	if (rd->open) {
192 		ret = -EBUSY;
193 		goto out;
194 	}
195 
196 	file->private_data = rd;
197 	rd->open = true;
198 
199 	/* Reset fifo to clear any previously unread data: */
200 	rd->fifo.head = rd->fifo.tail = 0;
201 
202 	/* the parsing tools need to know gpu-id to know which
203 	 * register database to load.
204 	 *
205 	 * Note: These particular params do not require a context
206 	 */
207 	gpu->funcs->get_param(gpu, NULL, MSM_PARAM_GPU_ID, &val, &zero);
208 	gpu_id = val;
209 
210 	rd_write_section(rd, RD_GPU_ID, &gpu_id, sizeof(gpu_id));
211 
212 	gpu->funcs->get_param(gpu, NULL, MSM_PARAM_CHIP_ID, &val, &zero);
213 	rd_write_section(rd, RD_CHIP_ID, &val, sizeof(val));
214 
215 out:
216 	mutex_unlock(&gpu->lock);
217 	return ret;
218 }
219 
220 static int rd_release(struct inode *inode, struct file *file)
221 {
222 	struct msm_rd_state *rd = inode->i_private;
223 
224 	rd->open = false;
225 	wake_up_all(&rd->fifo_event);
226 
227 	return 0;
228 }
229 
230 
231 static const struct file_operations rd_debugfs_fops = {
232 	.owner = THIS_MODULE,
233 	.open = rd_open,
234 	.read = rd_read,
235 	.llseek = no_llseek,
236 	.release = rd_release,
237 };
238 
239 
240 static void rd_cleanup(struct msm_rd_state *rd)
241 {
242 	if (!rd)
243 		return;
244 
245 	mutex_destroy(&rd->read_lock);
246 	kfree(rd);
247 }
248 
249 static struct msm_rd_state *rd_init(struct drm_minor *minor, const char *name)
250 {
251 	struct msm_rd_state *rd;
252 
253 	rd = kzalloc(sizeof(*rd), GFP_KERNEL);
254 	if (!rd)
255 		return ERR_PTR(-ENOMEM);
256 
257 	rd->dev = minor->dev;
258 	rd->fifo.buf = rd->buf;
259 
260 	mutex_init(&rd->read_lock);
261 
262 	init_waitqueue_head(&rd->fifo_event);
263 
264 	debugfs_create_file(name, S_IFREG | S_IRUGO, minor->debugfs_root, rd,
265 			    &rd_debugfs_fops);
266 
267 	return rd;
268 }
269 
270 int msm_rd_debugfs_init(struct drm_minor *minor)
271 {
272 	struct msm_drm_private *priv = minor->dev->dev_private;
273 	struct msm_rd_state *rd;
274 	int ret;
275 
276 	/* only create on first minor: */
277 	if (priv->rd)
278 		return 0;
279 
280 	rd = rd_init(minor, "rd");
281 	if (IS_ERR(rd)) {
282 		ret = PTR_ERR(rd);
283 		goto fail;
284 	}
285 
286 	priv->rd = rd;
287 
288 	rd = rd_init(minor, "hangrd");
289 	if (IS_ERR(rd)) {
290 		ret = PTR_ERR(rd);
291 		goto fail;
292 	}
293 
294 	priv->hangrd = rd;
295 
296 	return 0;
297 
298 fail:
299 	msm_rd_debugfs_cleanup(priv);
300 	return ret;
301 }
302 
303 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv)
304 {
305 	rd_cleanup(priv->rd);
306 	priv->rd = NULL;
307 
308 	rd_cleanup(priv->hangrd);
309 	priv->hangrd = NULL;
310 }
311 
312 static void snapshot_buf(struct msm_rd_state *rd,
313 		struct msm_gem_submit *submit, int idx,
314 		uint64_t iova, uint32_t size, bool full)
315 {
316 	struct msm_gem_object *obj = submit->bos[idx].obj;
317 	unsigned offset = 0;
318 	const char *buf;
319 
320 	if (iova) {
321 		offset = iova - submit->bos[idx].iova;
322 	} else {
323 		iova = submit->bos[idx].iova;
324 		size = obj->base.size;
325 	}
326 
327 	/*
328 	 * Always write the GPUADDR header so can get a complete list of all the
329 	 * buffers in the cmd
330 	 */
331 	rd_write_section(rd, RD_GPUADDR,
332 			(uint32_t[3]){ iova, size, iova >> 32 }, 12);
333 
334 	if (!full)
335 		return;
336 
337 	/* But only dump the contents of buffers marked READ */
338 	if (!(submit->bos[idx].flags & MSM_SUBMIT_BO_READ))
339 		return;
340 
341 	msm_gem_lock(&obj->base);
342 	buf = msm_gem_get_vaddr_active(&obj->base);
343 	if (IS_ERR(buf))
344 		goto out_unlock;
345 
346 	buf += offset;
347 
348 	rd_write_section(rd, RD_BUFFER_CONTENTS, buf, size);
349 
350 	msm_gem_put_vaddr_locked(&obj->base);
351 
352 out_unlock:
353 	msm_gem_unlock(&obj->base);
354 }
355 
356 /* called under gpu->lock */
357 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit,
358 		const char *fmt, ...)
359 {
360 	struct task_struct *task;
361 	char msg[256];
362 	int i, n;
363 
364 	if (!rd->open)
365 		return;
366 
367 	/* writing into fifo is serialized by caller, and
368 	 * rd->read_lock is used to serialize the reads
369 	 */
370 	WARN_ON(!mutex_is_locked(&submit->gpu->lock));
371 
372 	if (fmt) {
373 		va_list args;
374 
375 		va_start(args, fmt);
376 		n = vscnprintf(msg, sizeof(msg), fmt, args);
377 		va_end(args);
378 
379 		rd_write_section(rd, RD_CMD, msg, ALIGN(n, 4));
380 	}
381 
382 	rcu_read_lock();
383 	task = pid_task(submit->pid, PIDTYPE_PID);
384 	if (task) {
385 		n = scnprintf(msg, sizeof(msg), "%.*s/%d: fence=%u",
386 				TASK_COMM_LEN, task->comm,
387 				pid_nr(submit->pid), submit->seqno);
388 	} else {
389 		n = scnprintf(msg, sizeof(msg), "???/%d: fence=%u",
390 				pid_nr(submit->pid), submit->seqno);
391 	}
392 	rcu_read_unlock();
393 
394 	rd_write_section(rd, RD_CMD, msg, ALIGN(n, 4));
395 
396 	for (i = 0; i < submit->nr_bos; i++)
397 		snapshot_buf(rd, submit, i, 0, 0, should_dump(submit, i));
398 
399 	for (i = 0; i < submit->nr_cmds; i++) {
400 		uint32_t szd  = submit->cmd[i].size; /* in dwords */
401 
402 		/* snapshot cmdstream bo's (if we haven't already): */
403 		if (!should_dump(submit, i)) {
404 			snapshot_buf(rd, submit, submit->cmd[i].idx,
405 					submit->cmd[i].iova, szd * 4, true);
406 		}
407 	}
408 
409 	for (i = 0; i < submit->nr_cmds; i++) {
410 		uint64_t iova = submit->cmd[i].iova;
411 		uint32_t szd  = submit->cmd[i].size; /* in dwords */
412 
413 		switch (submit->cmd[i].type) {
414 		case MSM_SUBMIT_CMD_IB_TARGET_BUF:
415 			/* ignore IB-targets, we've logged the buffer, the
416 			 * parser tool will follow the IB based on the logged
417 			 * buffer/gpuaddr, so nothing more to do.
418 			 */
419 			break;
420 		case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
421 		case MSM_SUBMIT_CMD_BUF:
422 			rd_write_section(rd, RD_CMDSTREAM_ADDR,
423 				(uint32_t[3]){ iova, szd, iova >> 32 }, 12);
424 			break;
425 		}
426 	}
427 }
428 #endif
429