1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018, The Linux Foundation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/interconnect.h> 9 #include <linux/irq.h> 10 #include <linux/irqchip.h> 11 #include <linux/irqdesc.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/of_platform.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 18 #include "msm_mdss.h" 19 #include "msm_kms.h" 20 21 #define HW_REV 0x0 22 #define HW_INTR_STATUS 0x0010 23 24 #define UBWC_DEC_HW_VERSION 0x58 25 #define UBWC_STATIC 0x144 26 #define UBWC_CTRL_2 0x150 27 #define UBWC_PREDICTION_MODE 0x154 28 29 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ 30 31 #define DEFAULT_REG_BW 153600 /* Used in mdss fbdev driver */ 32 33 struct msm_mdss { 34 struct device *dev; 35 36 void __iomem *mmio; 37 struct clk_bulk_data *clocks; 38 size_t num_clocks; 39 bool is_mdp5; 40 struct { 41 unsigned long enabled_mask; 42 struct irq_domain *domain; 43 } irq_controller; 44 const struct msm_mdss_data *mdss_data; 45 struct icc_path *mdp_path[2]; 46 u32 num_mdp_paths; 47 struct icc_path *reg_bus_path; 48 }; 49 50 static int msm_mdss_parse_data_bus_icc_path(struct device *dev, 51 struct msm_mdss *msm_mdss) 52 { 53 struct icc_path *path0; 54 struct icc_path *path1; 55 struct icc_path *reg_bus_path; 56 57 path0 = devm_of_icc_get(dev, "mdp0-mem"); 58 if (IS_ERR_OR_NULL(path0)) 59 return PTR_ERR_OR_ZERO(path0); 60 61 msm_mdss->mdp_path[0] = path0; 62 msm_mdss->num_mdp_paths = 1; 63 64 path1 = devm_of_icc_get(dev, "mdp1-mem"); 65 if (!IS_ERR_OR_NULL(path1)) { 66 msm_mdss->mdp_path[1] = path1; 67 msm_mdss->num_mdp_paths++; 68 } 69 70 reg_bus_path = of_icc_get(dev, "cpu-cfg"); 71 if (!IS_ERR_OR_NULL(reg_bus_path)) 72 msm_mdss->reg_bus_path = reg_bus_path; 73 74 return 0; 75 } 76 77 static void msm_mdss_irq(struct irq_desc *desc) 78 { 79 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); 80 struct irq_chip *chip = irq_desc_get_chip(desc); 81 u32 interrupts; 82 83 chained_irq_enter(chip, desc); 84 85 interrupts = readl_relaxed(msm_mdss->mmio + HW_INTR_STATUS); 86 87 while (interrupts) { 88 irq_hw_number_t hwirq = fls(interrupts) - 1; 89 int rc; 90 91 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain, 92 hwirq); 93 if (rc < 0) { 94 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n", 95 hwirq, rc); 96 break; 97 } 98 99 interrupts &= ~(1 << hwirq); 100 } 101 102 chained_irq_exit(chip, desc); 103 } 104 105 static void msm_mdss_irq_mask(struct irq_data *irqd) 106 { 107 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 108 109 /* memory barrier */ 110 smp_mb__before_atomic(); 111 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 112 /* memory barrier */ 113 smp_mb__after_atomic(); 114 } 115 116 static void msm_mdss_irq_unmask(struct irq_data *irqd) 117 { 118 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 119 120 /* memory barrier */ 121 smp_mb__before_atomic(); 122 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 123 /* memory barrier */ 124 smp_mb__after_atomic(); 125 } 126 127 static struct irq_chip msm_mdss_irq_chip = { 128 .name = "msm_mdss", 129 .irq_mask = msm_mdss_irq_mask, 130 .irq_unmask = msm_mdss_irq_unmask, 131 }; 132 133 static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key; 134 135 static int msm_mdss_irqdomain_map(struct irq_domain *domain, 136 unsigned int irq, irq_hw_number_t hwirq) 137 { 138 struct msm_mdss *msm_mdss = domain->host_data; 139 140 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key); 141 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq); 142 143 return irq_set_chip_data(irq, msm_mdss); 144 } 145 146 static const struct irq_domain_ops msm_mdss_irqdomain_ops = { 147 .map = msm_mdss_irqdomain_map, 148 .xlate = irq_domain_xlate_onecell, 149 }; 150 151 static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) 152 { 153 struct device *dev; 154 struct irq_domain *domain; 155 156 dev = msm_mdss->dev; 157 158 domain = irq_domain_add_linear(dev->of_node, 32, 159 &msm_mdss_irqdomain_ops, msm_mdss); 160 if (!domain) { 161 dev_err(dev, "failed to add irq_domain\n"); 162 return -EINVAL; 163 } 164 165 msm_mdss->irq_controller.enabled_mask = 0; 166 msm_mdss->irq_controller.domain = domain; 167 168 return 0; 169 } 170 171 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) 172 { 173 const struct msm_mdss_data *data = msm_mdss->mdss_data; 174 175 writel_relaxed(data->ubwc_static, msm_mdss->mmio + UBWC_STATIC); 176 } 177 178 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) 179 { 180 const struct msm_mdss_data *data = msm_mdss->mdss_data; 181 u32 value = (data->ubwc_swizzle & 0x1) | 182 (data->highest_bank_bit & 0x3) << 4 | 183 (data->macrotile_mode & 0x1) << 12; 184 185 if (data->ubwc_enc_version == UBWC_3_0) 186 value |= BIT(10); 187 188 if (data->ubwc_enc_version == UBWC_1_0) 189 value |= BIT(8); 190 191 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 192 } 193 194 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) 195 { 196 const struct msm_mdss_data *data = msm_mdss->mdss_data; 197 u32 value = (data->ubwc_swizzle & 0x7) | 198 (data->ubwc_static & 0x1) << 3 | 199 (data->highest_bank_bit & 0x7) << 4 | 200 (data->macrotile_mode & 0x1) << 12; 201 202 writel_relaxed(value, msm_mdss->mmio + UBWC_STATIC); 203 204 if (data->ubwc_enc_version == UBWC_3_0) { 205 writel_relaxed(1, msm_mdss->mmio + UBWC_CTRL_2); 206 writel_relaxed(0, msm_mdss->mmio + UBWC_PREDICTION_MODE); 207 } else { 208 if (data->ubwc_dec_version == UBWC_4_3) 209 writel_relaxed(3, msm_mdss->mmio + UBWC_CTRL_2); 210 else 211 writel_relaxed(2, msm_mdss->mmio + UBWC_CTRL_2); 212 writel_relaxed(1, msm_mdss->mmio + UBWC_PREDICTION_MODE); 213 } 214 } 215 216 const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) 217 { 218 struct msm_mdss *mdss; 219 220 if (!dev) 221 return ERR_PTR(-EINVAL); 222 223 mdss = dev_get_drvdata(dev); 224 225 return mdss->mdss_data; 226 } 227 228 static int msm_mdss_enable(struct msm_mdss *msm_mdss) 229 { 230 int ret, i; 231 232 /* 233 * Several components have AXI clocks that can only be turned on if 234 * the interconnect is enabled (non-zero bandwidth). Let's make sure 235 * that the interconnects are at least at a minimum amount. 236 */ 237 for (i = 0; i < msm_mdss->num_mdp_paths; i++) 238 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); 239 240 if (msm_mdss->mdss_data && msm_mdss->mdss_data->reg_bus_bw) 241 icc_set_bw(msm_mdss->reg_bus_path, 0, 242 msm_mdss->mdss_data->reg_bus_bw); 243 else 244 icc_set_bw(msm_mdss->reg_bus_path, 0, 245 DEFAULT_REG_BW); 246 247 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); 248 if (ret) { 249 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); 250 return ret; 251 } 252 253 /* 254 * Register access requires MDSS_MDP_CLK, which is not enabled by the 255 * mdss on mdp5 hardware. Skip it for now. 256 */ 257 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data) 258 return 0; 259 260 /* 261 * ubwc config is part of the "mdss" region which is not accessible 262 * from the rest of the driver. hardcode known configurations here 263 * 264 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, 265 * UBWC_n and the rest of params comes from hw data. 266 */ 267 switch (msm_mdss->mdss_data->ubwc_dec_version) { 268 case 0: /* no UBWC */ 269 case UBWC_1_0: 270 /* do nothing */ 271 break; 272 case UBWC_2_0: 273 msm_mdss_setup_ubwc_dec_20(msm_mdss); 274 break; 275 case UBWC_3_0: 276 msm_mdss_setup_ubwc_dec_30(msm_mdss); 277 break; 278 case UBWC_4_0: 279 case UBWC_4_3: 280 msm_mdss_setup_ubwc_dec_40(msm_mdss); 281 break; 282 default: 283 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", 284 msm_mdss->mdss_data->ubwc_dec_version); 285 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", 286 readl_relaxed(msm_mdss->mmio + HW_REV)); 287 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", 288 readl_relaxed(msm_mdss->mmio + UBWC_DEC_HW_VERSION)); 289 break; 290 } 291 292 return ret; 293 } 294 295 static int msm_mdss_disable(struct msm_mdss *msm_mdss) 296 { 297 int i; 298 299 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); 300 301 for (i = 0; i < msm_mdss->num_mdp_paths; i++) 302 icc_set_bw(msm_mdss->mdp_path[i], 0, 0); 303 304 if (msm_mdss->reg_bus_path) 305 icc_set_bw(msm_mdss->reg_bus_path, 0, 0); 306 307 return 0; 308 } 309 310 static void msm_mdss_destroy(struct msm_mdss *msm_mdss) 311 { 312 struct platform_device *pdev = to_platform_device(msm_mdss->dev); 313 int irq; 314 315 pm_runtime_suspend(msm_mdss->dev); 316 pm_runtime_disable(msm_mdss->dev); 317 irq_domain_remove(msm_mdss->irq_controller.domain); 318 msm_mdss->irq_controller.domain = NULL; 319 irq = platform_get_irq(pdev, 0); 320 irq_set_chained_handler_and_data(irq, NULL, NULL); 321 } 322 323 static int msm_mdss_reset(struct device *dev) 324 { 325 struct reset_control *reset; 326 327 reset = reset_control_get_optional_exclusive(dev, NULL); 328 if (!reset) { 329 /* Optional reset not specified */ 330 return 0; 331 } else if (IS_ERR(reset)) { 332 return dev_err_probe(dev, PTR_ERR(reset), 333 "failed to acquire mdss reset\n"); 334 } 335 336 reset_control_assert(reset); 337 /* 338 * Tests indicate that reset has to be held for some period of time, 339 * make it one frame in a typical system 340 */ 341 msleep(20); 342 reset_control_deassert(reset); 343 344 reset_control_put(reset); 345 346 return 0; 347 } 348 349 /* 350 * MDP5 MDSS uses at most three specified clocks. 351 */ 352 #define MDP5_MDSS_NUM_CLOCKS 3 353 static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks) 354 { 355 struct clk_bulk_data *bulk; 356 int num_clocks = 0; 357 int ret; 358 359 if (!pdev) 360 return -EINVAL; 361 362 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL); 363 if (!bulk) 364 return -ENOMEM; 365 366 bulk[num_clocks++].id = "iface"; 367 bulk[num_clocks++].id = "bus"; 368 bulk[num_clocks++].id = "vsync"; 369 370 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk); 371 if (ret) 372 return ret; 373 374 *clocks = bulk; 375 376 return num_clocks; 377 } 378 379 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5) 380 { 381 struct msm_mdss *msm_mdss; 382 int ret; 383 int irq; 384 385 ret = msm_mdss_reset(&pdev->dev); 386 if (ret) 387 return ERR_PTR(ret); 388 389 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL); 390 if (!msm_mdss) 391 return ERR_PTR(-ENOMEM); 392 393 msm_mdss->mdss_data = of_device_get_match_data(&pdev->dev); 394 395 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); 396 if (IS_ERR(msm_mdss->mmio)) 397 return ERR_CAST(msm_mdss->mmio); 398 399 dev_dbg(&pdev->dev, "mapped mdss address space @%pK\n", msm_mdss->mmio); 400 401 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 402 if (ret) 403 return ERR_PTR(ret); 404 405 if (is_mdp5) 406 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks); 407 else 408 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks); 409 if (ret < 0) { 410 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret); 411 return ERR_PTR(ret); 412 } 413 msm_mdss->num_clocks = ret; 414 msm_mdss->is_mdp5 = is_mdp5; 415 416 msm_mdss->dev = &pdev->dev; 417 418 irq = platform_get_irq(pdev, 0); 419 if (irq < 0) 420 return ERR_PTR(irq); 421 422 ret = _msm_mdss_irq_domain_add(msm_mdss); 423 if (ret) 424 return ERR_PTR(ret); 425 426 irq_set_chained_handler_and_data(irq, msm_mdss_irq, 427 msm_mdss); 428 429 pm_runtime_enable(&pdev->dev); 430 431 return msm_mdss; 432 } 433 434 static int __maybe_unused mdss_runtime_suspend(struct device *dev) 435 { 436 struct msm_mdss *mdss = dev_get_drvdata(dev); 437 438 DBG(""); 439 440 return msm_mdss_disable(mdss); 441 } 442 443 static int __maybe_unused mdss_runtime_resume(struct device *dev) 444 { 445 struct msm_mdss *mdss = dev_get_drvdata(dev); 446 447 DBG(""); 448 449 return msm_mdss_enable(mdss); 450 } 451 452 static int __maybe_unused mdss_pm_suspend(struct device *dev) 453 { 454 455 if (pm_runtime_suspended(dev)) 456 return 0; 457 458 return mdss_runtime_suspend(dev); 459 } 460 461 static int __maybe_unused mdss_pm_resume(struct device *dev) 462 { 463 if (pm_runtime_suspended(dev)) 464 return 0; 465 466 return mdss_runtime_resume(dev); 467 } 468 469 static const struct dev_pm_ops mdss_pm_ops = { 470 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume) 471 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL) 472 }; 473 474 static int mdss_probe(struct platform_device *pdev) 475 { 476 struct msm_mdss *mdss; 477 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); 478 struct device *dev = &pdev->dev; 479 int ret; 480 481 mdss = msm_mdss_init(pdev, is_mdp5); 482 if (IS_ERR(mdss)) 483 return PTR_ERR(mdss); 484 485 platform_set_drvdata(pdev, mdss); 486 487 /* 488 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 489 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 490 * Populate the children devices, find the MDP5/DPU node, and then add 491 * the interfaces to our components list. 492 */ 493 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 494 if (ret) { 495 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 496 msm_mdss_destroy(mdss); 497 return ret; 498 } 499 500 return 0; 501 } 502 503 static void mdss_remove(struct platform_device *pdev) 504 { 505 struct msm_mdss *mdss = platform_get_drvdata(pdev); 506 507 of_platform_depopulate(&pdev->dev); 508 509 msm_mdss_destroy(mdss); 510 } 511 512 static const struct msm_mdss_data msm8998_data = { 513 .ubwc_enc_version = UBWC_1_0, 514 .ubwc_dec_version = UBWC_1_0, 515 .highest_bank_bit = 2, 516 .reg_bus_bw = 76800, 517 }; 518 519 static const struct msm_mdss_data qcm2290_data = { 520 /* no UBWC */ 521 .highest_bank_bit = 0x2, 522 .reg_bus_bw = 76800, 523 }; 524 525 static const struct msm_mdss_data sc7180_data = { 526 .ubwc_enc_version = UBWC_2_0, 527 .ubwc_dec_version = UBWC_2_0, 528 .ubwc_static = 0x1e, 529 .highest_bank_bit = 0x3, 530 .reg_bus_bw = 76800, 531 }; 532 533 static const struct msm_mdss_data sc7280_data = { 534 .ubwc_enc_version = UBWC_3_0, 535 .ubwc_dec_version = UBWC_4_0, 536 .ubwc_swizzle = 6, 537 .ubwc_static = 1, 538 .highest_bank_bit = 1, 539 .macrotile_mode = 1, 540 .reg_bus_bw = 74000, 541 }; 542 543 static const struct msm_mdss_data sc8180x_data = { 544 .ubwc_enc_version = UBWC_3_0, 545 .ubwc_dec_version = UBWC_3_0, 546 .highest_bank_bit = 3, 547 .macrotile_mode = 1, 548 .reg_bus_bw = 76800, 549 }; 550 551 static const struct msm_mdss_data sc8280xp_data = { 552 .ubwc_enc_version = UBWC_4_0, 553 .ubwc_dec_version = UBWC_4_0, 554 .ubwc_swizzle = 6, 555 .ubwc_static = 1, 556 .highest_bank_bit = 3, 557 .macrotile_mode = 1, 558 .reg_bus_bw = 76800, 559 }; 560 561 static const struct msm_mdss_data sdm670_data = { 562 .ubwc_enc_version = UBWC_2_0, 563 .ubwc_dec_version = UBWC_2_0, 564 .highest_bank_bit = 1, 565 }; 566 567 static const struct msm_mdss_data sdm845_data = { 568 .ubwc_enc_version = UBWC_2_0, 569 .ubwc_dec_version = UBWC_2_0, 570 .highest_bank_bit = 2, 571 .reg_bus_bw = 76800, 572 }; 573 574 static const struct msm_mdss_data sm6350_data = { 575 .ubwc_enc_version = UBWC_2_0, 576 .ubwc_dec_version = UBWC_2_0, 577 .ubwc_swizzle = 6, 578 .ubwc_static = 0x1e, 579 .highest_bank_bit = 1, 580 .reg_bus_bw = 76800, 581 }; 582 583 static const struct msm_mdss_data sm8150_data = { 584 .ubwc_enc_version = UBWC_3_0, 585 .ubwc_dec_version = UBWC_3_0, 586 .highest_bank_bit = 2, 587 .reg_bus_bw = 76800, 588 }; 589 590 static const struct msm_mdss_data sm6115_data = { 591 .ubwc_enc_version = UBWC_1_0, 592 .ubwc_dec_version = UBWC_2_0, 593 .ubwc_swizzle = 7, 594 .ubwc_static = 0x11f, 595 .highest_bank_bit = 0x1, 596 .reg_bus_bw = 76800, 597 }; 598 599 static const struct msm_mdss_data sm6125_data = { 600 .ubwc_enc_version = UBWC_1_0, 601 .ubwc_dec_version = UBWC_3_0, 602 .ubwc_swizzle = 1, 603 .highest_bank_bit = 1, 604 }; 605 606 static const struct msm_mdss_data sm8250_data = { 607 .ubwc_enc_version = UBWC_4_0, 608 .ubwc_dec_version = UBWC_4_0, 609 .ubwc_swizzle = 6, 610 .ubwc_static = 1, 611 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 612 .highest_bank_bit = 3, 613 .macrotile_mode = 1, 614 .reg_bus_bw = 76800, 615 }; 616 617 static const struct msm_mdss_data sm8350_data = { 618 .ubwc_enc_version = UBWC_4_0, 619 .ubwc_dec_version = UBWC_4_0, 620 .ubwc_swizzle = 6, 621 .ubwc_static = 1, 622 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 623 .highest_bank_bit = 3, 624 .macrotile_mode = 1, 625 .reg_bus_bw = 74000, 626 }; 627 628 static const struct msm_mdss_data sm8550_data = { 629 .ubwc_enc_version = UBWC_4_0, 630 .ubwc_dec_version = UBWC_4_3, 631 .ubwc_swizzle = 6, 632 .ubwc_static = 1, 633 /* TODO: highest_bank_bit = 2 for LP_DDR4 */ 634 .highest_bank_bit = 3, 635 .macrotile_mode = 1, 636 .reg_bus_bw = 57000, 637 }; 638 static const struct of_device_id mdss_dt_match[] = { 639 { .compatible = "qcom,mdss" }, 640 { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data }, 641 { .compatible = "qcom,qcm2290-mdss", .data = &qcm2290_data }, 642 { .compatible = "qcom,sdm670-mdss", .data = &sdm670_data }, 643 { .compatible = "qcom,sdm845-mdss", .data = &sdm845_data }, 644 { .compatible = "qcom,sc7180-mdss", .data = &sc7180_data }, 645 { .compatible = "qcom,sc7280-mdss", .data = &sc7280_data }, 646 { .compatible = "qcom,sc8180x-mdss", .data = &sc8180x_data }, 647 { .compatible = "qcom,sc8280xp-mdss", .data = &sc8280xp_data }, 648 { .compatible = "qcom,sm6115-mdss", .data = &sm6115_data }, 649 { .compatible = "qcom,sm6125-mdss", .data = &sm6125_data }, 650 { .compatible = "qcom,sm6350-mdss", .data = &sm6350_data }, 651 { .compatible = "qcom,sm6375-mdss", .data = &sm6350_data }, 652 { .compatible = "qcom,sm8150-mdss", .data = &sm8150_data }, 653 { .compatible = "qcom,sm8250-mdss", .data = &sm8250_data }, 654 { .compatible = "qcom,sm8350-mdss", .data = &sm8350_data }, 655 { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data }, 656 { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data }, 657 { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data}, 658 {} 659 }; 660 MODULE_DEVICE_TABLE(of, mdss_dt_match); 661 662 static struct platform_driver mdss_platform_driver = { 663 .probe = mdss_probe, 664 .remove_new = mdss_remove, 665 .driver = { 666 .name = "msm-mdss", 667 .of_match_table = mdss_dt_match, 668 .pm = &mdss_pm_ops, 669 }, 670 }; 671 672 void __init msm_mdss_register(void) 673 { 674 platform_driver_register(&mdss_platform_driver); 675 } 676 677 void __exit msm_mdss_unregister(void) 678 { 679 platform_driver_unregister(&mdss_platform_driver); 680 } 681