1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018, The Linux Foundation 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/interconnect.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqdesc.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <linux/soc/qcom/ubwc.h> 20 21 #include "msm_kms.h" 22 23 #include <generated/mdss.xml.h> 24 25 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ 26 27 struct msm_mdss_data { 28 u32 reg_bus_bw; 29 }; 30 31 struct msm_mdss { 32 struct device *dev; 33 34 void __iomem *mmio; 35 struct clk_bulk_data *clocks; 36 size_t num_clocks; 37 bool is_mdp5; 38 struct { 39 unsigned long enabled_mask; 40 struct irq_domain *domain; 41 } irq_controller; 42 const struct qcom_ubwc_cfg_data *mdss_data; 43 u32 reg_bus_bw; 44 struct icc_path *mdp_path[2]; 45 u32 num_mdp_paths; 46 struct icc_path *reg_bus_path; 47 }; 48 49 static int msm_mdss_parse_data_bus_icc_path(struct device *dev, 50 struct msm_mdss *msm_mdss) 51 { 52 struct icc_path *path0; 53 struct icc_path *path1; 54 struct icc_path *reg_bus_path; 55 56 path0 = devm_of_icc_get(dev, "mdp0-mem"); 57 if (IS_ERR_OR_NULL(path0)) 58 return PTR_ERR_OR_ZERO(path0); 59 60 msm_mdss->mdp_path[0] = path0; 61 msm_mdss->num_mdp_paths = 1; 62 63 path1 = devm_of_icc_get(dev, "mdp1-mem"); 64 if (!IS_ERR_OR_NULL(path1)) { 65 msm_mdss->mdp_path[1] = path1; 66 msm_mdss->num_mdp_paths++; 67 } 68 69 reg_bus_path = of_icc_get(dev, "cpu-cfg"); 70 if (!IS_ERR_OR_NULL(reg_bus_path)) 71 msm_mdss->reg_bus_path = reg_bus_path; 72 73 return 0; 74 } 75 76 static void msm_mdss_irq(struct irq_desc *desc) 77 { 78 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); 79 struct irq_chip *chip = irq_desc_get_chip(desc); 80 u32 interrupts; 81 82 chained_irq_enter(chip, desc); 83 84 interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS); 85 86 while (interrupts) { 87 irq_hw_number_t hwirq = fls(interrupts) - 1; 88 int rc; 89 90 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain, 91 hwirq); 92 if (rc < 0) { 93 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n", 94 hwirq, rc); 95 break; 96 } 97 98 interrupts &= ~(1 << hwirq); 99 } 100 101 chained_irq_exit(chip, desc); 102 } 103 104 static void msm_mdss_irq_mask(struct irq_data *irqd) 105 { 106 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 107 108 /* memory barrier */ 109 smp_mb__before_atomic(); 110 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 111 /* memory barrier */ 112 smp_mb__after_atomic(); 113 } 114 115 static void msm_mdss_irq_unmask(struct irq_data *irqd) 116 { 117 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 118 119 /* memory barrier */ 120 smp_mb__before_atomic(); 121 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 122 /* memory barrier */ 123 smp_mb__after_atomic(); 124 } 125 126 static struct irq_chip msm_mdss_irq_chip = { 127 .name = "msm_mdss", 128 .irq_mask = msm_mdss_irq_mask, 129 .irq_unmask = msm_mdss_irq_unmask, 130 }; 131 132 static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key; 133 134 static int msm_mdss_irqdomain_map(struct irq_domain *domain, 135 unsigned int irq, irq_hw_number_t hwirq) 136 { 137 struct msm_mdss *msm_mdss = domain->host_data; 138 139 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key); 140 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq); 141 142 return irq_set_chip_data(irq, msm_mdss); 143 } 144 145 static const struct irq_domain_ops msm_mdss_irqdomain_ops = { 146 .map = msm_mdss_irqdomain_map, 147 .xlate = irq_domain_xlate_onecell, 148 }; 149 150 static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) 151 { 152 struct device *dev; 153 struct irq_domain *domain; 154 155 dev = msm_mdss->dev; 156 157 domain = irq_domain_create_linear(dev_fwnode(dev), 32, &msm_mdss_irqdomain_ops, msm_mdss); 158 if (!domain) { 159 dev_err(dev, "failed to add irq_domain\n"); 160 return -EINVAL; 161 } 162 163 msm_mdss->irq_controller.enabled_mask = 0; 164 msm_mdss->irq_controller.domain = domain; 165 166 return 0; 167 } 168 169 static void msm_mdss_4x_setup_ubwc(struct msm_mdss *msm_mdss) 170 { 171 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; 172 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(qcom_ubwc_swizzle(data) & 173 UBWC_SWIZZLE_ENABLE_LVL1) | 174 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 175 176 value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(qcom_ubwc_min_acc_length_64b(data)); 177 178 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 179 } 180 181 static void msm_mdss_5x_setup_ubwc(struct msm_mdss *msm_mdss) 182 { 183 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; 184 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(qcom_ubwc_swizzle(data) & 185 UBWC_SWIZZLE_ENABLE_LVL1) | 186 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 187 188 if (qcom_ubwc_macrotile_mode(data)) 189 value |= MDSS_UBWC_STATIC_MACROTILE_MODE; 190 191 if (qcom_ubwc_enable_amsbc(data)) 192 value |= MDSS_UBWC_STATIC_UBWC_AMSBC; 193 194 value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(qcom_ubwc_min_acc_length_64b(data)); 195 196 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 197 } 198 199 static void msm_mdss_6x_setup_ubwc(struct msm_mdss *msm_mdss) 200 { 201 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; 202 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(qcom_ubwc_swizzle(data)) | 203 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 204 u32 prediction_mode; 205 206 if (qcom_ubwc_bank_spread(data)) 207 value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; 208 209 if (qcom_ubwc_macrotile_mode(data)) 210 value |= MDSS_UBWC_STATIC_MACROTILE_MODE; 211 212 value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(qcom_ubwc_min_acc_length_64b(data)); 213 214 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 215 216 if (data->ubwc_enc_version < UBWC_4_0) 217 prediction_mode = 0; 218 else 219 prediction_mode = 1; 220 221 writel_relaxed(qcom_ubwc_version_tag(data), 222 msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); 223 writel_relaxed(prediction_mode, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); 224 } 225 226 #define MDSS_HW_VER(major, minor, step) \ 227 ((((major) & 0xf) << 28) | \ 228 (((minor) & 0xfff) << 16) | \ 229 ((step) & 0xffff)) 230 231 static int msm_mdss_enable(struct msm_mdss *msm_mdss) 232 { 233 int ret, i; 234 u32 hw_rev; 235 236 /* 237 * Several components have AXI clocks that can only be turned on if 238 * the interconnect is enabled (non-zero bandwidth). Let's make sure 239 * that the interconnects are at least at a minimum amount. 240 */ 241 for (i = 0; i < msm_mdss->num_mdp_paths; i++) 242 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); 243 244 icc_set_bw(msm_mdss->reg_bus_path, 0, 245 msm_mdss->reg_bus_bw); 246 247 /* 248 * TODO: 249 * Previous users (e.g. the bootloader) may have left this clock at a high rate, which 250 * would remain set, as prepare_enable() doesn't reprogram it. This theoretically poses a 251 * risk of brownout, but realistically this path is almost exclusively excercised after the 252 * correct OPP has been set in one of the MDPn or DPU drivers, or during initial probe, 253 * before the RPM(H)PD sync_state is done. 254 */ 255 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); 256 if (ret) { 257 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); 258 return ret; 259 } 260 261 /* 262 * Register access requires MDSS_MDP_CLK, which is not enabled by the 263 * mdss on mdp5 hardware. Skip it for now. 264 */ 265 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data) 266 return 0; 267 268 hw_rev = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION); 269 270 if (hw_rev >= MDSS_HW_VER(6, 0, 0)) 271 msm_mdss_6x_setup_ubwc(msm_mdss); 272 else if (hw_rev >= MDSS_HW_VER(5, 0, 0)) 273 msm_mdss_5x_setup_ubwc(msm_mdss); 274 else if (hw_rev >= MDSS_HW_VER(4, 0, 0)) 275 msm_mdss_4x_setup_ubwc(msm_mdss); 276 /* else UBWC 1.0 or none, no params to program */ 277 278 return ret; 279 } 280 281 static int msm_mdss_disable(struct msm_mdss *msm_mdss) 282 { 283 int i; 284 285 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); 286 287 for (i = 0; i < msm_mdss->num_mdp_paths; i++) 288 icc_set_bw(msm_mdss->mdp_path[i], 0, 0); 289 290 if (msm_mdss->reg_bus_path) 291 icc_set_bw(msm_mdss->reg_bus_path, 0, 0); 292 293 return 0; 294 } 295 296 static void msm_mdss_destroy(struct msm_mdss *msm_mdss) 297 { 298 struct platform_device *pdev = to_platform_device(msm_mdss->dev); 299 int irq; 300 301 pm_runtime_suspend(msm_mdss->dev); 302 pm_runtime_disable(msm_mdss->dev); 303 irq_domain_remove(msm_mdss->irq_controller.domain); 304 msm_mdss->irq_controller.domain = NULL; 305 irq = platform_get_irq(pdev, 0); 306 irq_set_chained_handler_and_data(irq, NULL, NULL); 307 } 308 309 static int msm_mdss_reset(struct device *dev) 310 { 311 struct reset_control *reset; 312 313 reset = reset_control_get_optional_exclusive(dev, NULL); 314 if (!reset) { 315 /* Optional reset not specified */ 316 return 0; 317 } else if (IS_ERR(reset)) { 318 return dev_err_probe(dev, PTR_ERR(reset), 319 "failed to acquire mdss reset\n"); 320 } 321 322 reset_control_assert(reset); 323 /* 324 * Tests indicate that reset has to be held for some period of time, 325 * make it one frame in a typical system 326 */ 327 msleep(20); 328 reset_control_deassert(reset); 329 330 reset_control_put(reset); 331 332 return 0; 333 } 334 335 /* 336 * MDP5 MDSS uses at most three specified clocks. 337 */ 338 #define MDP5_MDSS_NUM_CLOCKS 3 339 static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks) 340 { 341 struct clk_bulk_data *bulk; 342 int num_clocks = 0; 343 int ret; 344 345 if (!pdev) 346 return -EINVAL; 347 348 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL); 349 if (!bulk) 350 return -ENOMEM; 351 352 bulk[num_clocks++].id = "iface"; 353 bulk[num_clocks++].id = "bus"; 354 bulk[num_clocks++].id = "vsync"; 355 356 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk); 357 if (ret) 358 return ret; 359 360 *clocks = bulk; 361 362 return num_clocks; 363 } 364 365 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5) 366 { 367 const struct msm_mdss_data *mdss_data; 368 struct msm_mdss *msm_mdss; 369 int ret; 370 int irq; 371 372 ret = msm_mdss_reset(&pdev->dev); 373 if (ret) 374 return ERR_PTR(ret); 375 376 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL); 377 if (!msm_mdss) 378 return ERR_PTR(-ENOMEM); 379 380 msm_mdss->mdss_data = qcom_ubwc_config_get_data(); 381 if (IS_ERR(msm_mdss->mdss_data)) 382 return ERR_CAST(msm_mdss->mdss_data); 383 384 mdss_data = of_device_get_match_data(&pdev->dev); 385 if (!mdss_data) 386 return ERR_PTR(-EINVAL); 387 388 msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw; 389 390 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); 391 if (IS_ERR(msm_mdss->mmio)) 392 return ERR_CAST(msm_mdss->mmio); 393 394 dev_dbg(&pdev->dev, "mapped mdss address space @%p\n", msm_mdss->mmio); 395 396 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 397 if (ret) 398 return ERR_PTR(ret); 399 400 if (is_mdp5) 401 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks); 402 else 403 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks); 404 if (ret < 0) { 405 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret); 406 return ERR_PTR(ret); 407 } 408 msm_mdss->num_clocks = ret; 409 msm_mdss->is_mdp5 = is_mdp5; 410 411 msm_mdss->dev = &pdev->dev; 412 413 irq = platform_get_irq(pdev, 0); 414 if (irq < 0) 415 return ERR_PTR(irq); 416 417 ret = _msm_mdss_irq_domain_add(msm_mdss); 418 if (ret) 419 return ERR_PTR(ret); 420 421 irq_set_chained_handler_and_data(irq, msm_mdss_irq, 422 msm_mdss); 423 424 pm_runtime_enable(&pdev->dev); 425 426 return msm_mdss; 427 } 428 429 static int __maybe_unused mdss_runtime_suspend(struct device *dev) 430 { 431 struct msm_mdss *mdss = dev_get_drvdata(dev); 432 433 DBG(""); 434 435 return msm_mdss_disable(mdss); 436 } 437 438 static int __maybe_unused mdss_runtime_resume(struct device *dev) 439 { 440 struct msm_mdss *mdss = dev_get_drvdata(dev); 441 442 DBG(""); 443 444 return msm_mdss_enable(mdss); 445 } 446 447 static int __maybe_unused mdss_pm_suspend(struct device *dev) 448 { 449 450 if (pm_runtime_suspended(dev)) 451 return 0; 452 453 return mdss_runtime_suspend(dev); 454 } 455 456 static int __maybe_unused mdss_pm_resume(struct device *dev) 457 { 458 if (pm_runtime_suspended(dev)) 459 return 0; 460 461 return mdss_runtime_resume(dev); 462 } 463 464 static const struct dev_pm_ops mdss_pm_ops = { 465 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume) 466 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL) 467 }; 468 469 static int mdss_probe(struct platform_device *pdev) 470 { 471 struct msm_mdss *mdss; 472 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); 473 struct device *dev = &pdev->dev; 474 int ret; 475 476 mdss = msm_mdss_init(pdev, is_mdp5); 477 if (IS_ERR(mdss)) 478 return PTR_ERR(mdss); 479 480 platform_set_drvdata(pdev, mdss); 481 482 /* 483 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 484 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 485 * Populate the children devices, find the MDP5/DPU node, and then add 486 * the interfaces to our components list. 487 */ 488 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 489 if (ret) { 490 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 491 msm_mdss_destroy(mdss); 492 return ret; 493 } 494 495 return 0; 496 } 497 498 static void mdss_remove(struct platform_device *pdev) 499 { 500 struct msm_mdss *mdss = platform_get_drvdata(pdev); 501 502 of_platform_depopulate(&pdev->dev); 503 504 msm_mdss_destroy(mdss); 505 } 506 507 static const struct msm_mdss_data data_14k = { 508 .reg_bus_bw = 14000, 509 }; 510 511 static const struct msm_mdss_data data_57k = { 512 .reg_bus_bw = 57000, 513 }; 514 515 static const struct msm_mdss_data data_74k = { 516 .reg_bus_bw = 74000, 517 }; 518 519 static const struct msm_mdss_data data_76k8 = { 520 .reg_bus_bw = 76800, 521 }; 522 523 static const struct msm_mdss_data data_153k6 = { 524 .reg_bus_bw = 153600, 525 }; 526 527 static const struct of_device_id mdss_dt_match[] = { 528 { .compatible = "qcom,mdss", .data = &data_153k6 }, 529 { .compatible = "qcom,eliza-mdss", .data = &data_57k }, 530 { .compatible = "qcom,glymur-mdss", .data = &data_57k }, 531 { .compatible = "qcom,kaanapali-mdss", .data = &data_57k }, 532 { .compatible = "qcom,milos-mdss", .data = &data_14k }, 533 { .compatible = "qcom,msm8998-mdss", .data = &data_76k8 }, 534 { .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 }, 535 { .compatible = "qcom,qcs8300-mdss", .data = &data_74k }, 536 { .compatible = "qcom,sa8775p-mdss", .data = &data_74k }, 537 { .compatible = "qcom,sar2130p-mdss", .data = &data_74k }, 538 { .compatible = "qcom,sdm670-mdss", .data = &data_76k8 }, 539 { .compatible = "qcom,sdm845-mdss", .data = &data_76k8 }, 540 { .compatible = "qcom,sc7180-mdss", .data = &data_76k8 }, 541 { .compatible = "qcom,sc7280-mdss", .data = &data_74k }, 542 { .compatible = "qcom,sc8180x-mdss", .data = &data_76k8 }, 543 { .compatible = "qcom,sc8280xp-mdss", .data = &data_76k8 }, 544 { .compatible = "qcom,sm6115-mdss", .data = &data_76k8 }, 545 { .compatible = "qcom,sm6125-mdss", .data = &data_76k8 }, 546 { .compatible = "qcom,sm6150-mdss", .data = &data_76k8 }, 547 { .compatible = "qcom,sm6350-mdss", .data = &data_76k8 }, 548 { .compatible = "qcom,sm6375-mdss", .data = &data_76k8 }, 549 { .compatible = "qcom,sm7150-mdss", .data = &data_76k8 }, 550 { .compatible = "qcom,sm8150-mdss", .data = &data_76k8 }, 551 { .compatible = "qcom,sm8250-mdss", .data = &data_76k8 }, 552 { .compatible = "qcom,sm8350-mdss", .data = &data_74k }, 553 { .compatible = "qcom,sm8450-mdss", .data = &data_74k }, 554 { .compatible = "qcom,sm8550-mdss", .data = &data_57k }, 555 { .compatible = "qcom,sm8650-mdss", .data = &data_57k }, 556 { .compatible = "qcom,sm8750-mdss", .data = &data_57k }, 557 /* TODO: x1e8: Add reg_bus_bw with real value */ 558 { .compatible = "qcom,x1e80100-mdss", .data = &data_153k6 }, 559 {} 560 }; 561 MODULE_DEVICE_TABLE(of, mdss_dt_match); 562 563 static struct platform_driver mdss_platform_driver = { 564 .probe = mdss_probe, 565 .remove = mdss_remove, 566 .driver = { 567 .name = "msm-mdss", 568 .of_match_table = mdss_dt_match, 569 .pm = &mdss_pm_ops, 570 }, 571 }; 572 573 void __init msm_mdss_register(void) 574 { 575 platform_driver_register(&mdss_platform_driver); 576 } 577 578 void __exit msm_mdss_unregister(void) 579 { 580 platform_driver_unregister(&mdss_platform_driver); 581 } 582