1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2018, The Linux Foundation 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/interconnect.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqdesc.h> 13 #include <linux/irqchip/chained_irq.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <linux/soc/qcom/ubwc.h> 20 21 #include "msm_kms.h" 22 23 #include <generated/mdss.xml.h> 24 25 #define MIN_IB_BW 400000000UL /* Min ib vote 400MB */ 26 27 struct msm_mdss_data { 28 u32 reg_bus_bw; 29 }; 30 31 struct msm_mdss { 32 struct device *dev; 33 34 void __iomem *mmio; 35 struct clk_bulk_data *clocks; 36 size_t num_clocks; 37 bool is_mdp5; 38 struct { 39 unsigned long enabled_mask; 40 struct irq_domain *domain; 41 } irq_controller; 42 const struct qcom_ubwc_cfg_data *mdss_data; 43 u32 reg_bus_bw; 44 struct icc_path *mdp_path[2]; 45 u32 num_mdp_paths; 46 struct icc_path *reg_bus_path; 47 }; 48 49 static int msm_mdss_parse_data_bus_icc_path(struct device *dev, 50 struct msm_mdss *msm_mdss) 51 { 52 struct icc_path *path0; 53 struct icc_path *path1; 54 struct icc_path *reg_bus_path; 55 56 path0 = devm_of_icc_get(dev, "mdp0-mem"); 57 if (IS_ERR_OR_NULL(path0)) 58 return PTR_ERR_OR_ZERO(path0); 59 60 msm_mdss->mdp_path[0] = path0; 61 msm_mdss->num_mdp_paths = 1; 62 63 path1 = devm_of_icc_get(dev, "mdp1-mem"); 64 if (!IS_ERR_OR_NULL(path1)) { 65 msm_mdss->mdp_path[1] = path1; 66 msm_mdss->num_mdp_paths++; 67 } 68 69 reg_bus_path = of_icc_get(dev, "cpu-cfg"); 70 if (!IS_ERR_OR_NULL(reg_bus_path)) 71 msm_mdss->reg_bus_path = reg_bus_path; 72 73 return 0; 74 } 75 76 static void msm_mdss_irq(struct irq_desc *desc) 77 { 78 struct msm_mdss *msm_mdss = irq_desc_get_handler_data(desc); 79 struct irq_chip *chip = irq_desc_get_chip(desc); 80 u32 interrupts; 81 82 chained_irq_enter(chip, desc); 83 84 interrupts = readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_INTR_STATUS); 85 86 while (interrupts) { 87 irq_hw_number_t hwirq = fls(interrupts) - 1; 88 int rc; 89 90 rc = generic_handle_domain_irq(msm_mdss->irq_controller.domain, 91 hwirq); 92 if (rc < 0) { 93 dev_err(msm_mdss->dev, "handle irq fail: irq=%lu rc=%d\n", 94 hwirq, rc); 95 break; 96 } 97 98 interrupts &= ~(1 << hwirq); 99 } 100 101 chained_irq_exit(chip, desc); 102 } 103 104 static void msm_mdss_irq_mask(struct irq_data *irqd) 105 { 106 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 107 108 /* memory barrier */ 109 smp_mb__before_atomic(); 110 clear_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 111 /* memory barrier */ 112 smp_mb__after_atomic(); 113 } 114 115 static void msm_mdss_irq_unmask(struct irq_data *irqd) 116 { 117 struct msm_mdss *msm_mdss = irq_data_get_irq_chip_data(irqd); 118 119 /* memory barrier */ 120 smp_mb__before_atomic(); 121 set_bit(irqd->hwirq, &msm_mdss->irq_controller.enabled_mask); 122 /* memory barrier */ 123 smp_mb__after_atomic(); 124 } 125 126 static struct irq_chip msm_mdss_irq_chip = { 127 .name = "msm_mdss", 128 .irq_mask = msm_mdss_irq_mask, 129 .irq_unmask = msm_mdss_irq_unmask, 130 }; 131 132 static struct lock_class_key msm_mdss_lock_key, msm_mdss_request_key; 133 134 static int msm_mdss_irqdomain_map(struct irq_domain *domain, 135 unsigned int irq, irq_hw_number_t hwirq) 136 { 137 struct msm_mdss *msm_mdss = domain->host_data; 138 139 irq_set_lockdep_class(irq, &msm_mdss_lock_key, &msm_mdss_request_key); 140 irq_set_chip_and_handler(irq, &msm_mdss_irq_chip, handle_level_irq); 141 142 return irq_set_chip_data(irq, msm_mdss); 143 } 144 145 static const struct irq_domain_ops msm_mdss_irqdomain_ops = { 146 .map = msm_mdss_irqdomain_map, 147 .xlate = irq_domain_xlate_onecell, 148 }; 149 150 static int _msm_mdss_irq_domain_add(struct msm_mdss *msm_mdss) 151 { 152 struct device *dev; 153 struct irq_domain *domain; 154 155 dev = msm_mdss->dev; 156 157 domain = irq_domain_create_linear(dev_fwnode(dev), 32, &msm_mdss_irqdomain_ops, msm_mdss); 158 if (!domain) { 159 dev_err(dev, "failed to add irq_domain\n"); 160 return -EINVAL; 161 } 162 163 msm_mdss->irq_controller.enabled_mask = 0; 164 msm_mdss->irq_controller.domain = domain; 165 166 return 0; 167 } 168 169 static void msm_mdss_setup_ubwc_dec_20(struct msm_mdss *msm_mdss) 170 { 171 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; 172 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | 173 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 174 175 if (data->ubwc_bank_spread) 176 value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; 177 178 if (data->ubwc_enc_version == UBWC_1_0) 179 value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(1); 180 181 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 182 } 183 184 static void msm_mdss_setup_ubwc_dec_30(struct msm_mdss *msm_mdss) 185 { 186 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; 187 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle & 0x1) | 188 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 189 190 if (data->macrotile_mode) 191 value |= MDSS_UBWC_STATIC_MACROTILE_MODE; 192 193 if (data->ubwc_enc_version == UBWC_3_0) 194 value |= MDSS_UBWC_STATIC_UBWC_AMSBC; 195 196 if (data->ubwc_enc_version == UBWC_1_0) 197 value |= MDSS_UBWC_STATIC_UBWC_MIN_ACC_LEN(1); 198 199 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 200 } 201 202 static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) 203 { 204 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; 205 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | 206 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 207 208 if (data->ubwc_bank_spread) 209 value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; 210 211 if (data->macrotile_mode) 212 value |= MDSS_UBWC_STATIC_MACROTILE_MODE; 213 214 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 215 216 if (data->ubwc_enc_version == UBWC_3_0) { 217 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); 218 writel_relaxed(0, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); 219 } else { 220 if (data->ubwc_dec_version == UBWC_4_3) 221 writel_relaxed(3, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); 222 else 223 writel_relaxed(2, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); 224 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); 225 } 226 } 227 228 static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss) 229 { 230 const struct qcom_ubwc_cfg_data *data = msm_mdss->mdss_data; 231 u32 value = MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | 232 MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit - 13); 233 234 if (data->ubwc_bank_spread) 235 value |= MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; 236 237 if (data->macrotile_mode) 238 value |= MDSS_UBWC_STATIC_MACROTILE_MODE; 239 240 writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); 241 242 if (data->ubwc_dec_version == UBWC_6_0) 243 writel_relaxed(5, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); 244 else 245 writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); 246 247 writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); 248 } 249 250 static int msm_mdss_enable(struct msm_mdss *msm_mdss) 251 { 252 int ret, i; 253 254 /* 255 * Several components have AXI clocks that can only be turned on if 256 * the interconnect is enabled (non-zero bandwidth). Let's make sure 257 * that the interconnects are at least at a minimum amount. 258 */ 259 for (i = 0; i < msm_mdss->num_mdp_paths; i++) 260 icc_set_bw(msm_mdss->mdp_path[i], 0, Bps_to_icc(MIN_IB_BW)); 261 262 icc_set_bw(msm_mdss->reg_bus_path, 0, 263 msm_mdss->reg_bus_bw); 264 265 /* 266 * TODO: 267 * Previous users (e.g. the bootloader) may have left this clock at a high rate, which 268 * would remain set, as prepare_enable() doesn't reprogram it. This theoretically poses a 269 * risk of brownout, but realistically this path is almost exclusively excercised after the 270 * correct OPP has been set in one of the MDPn or DPU drivers, or during initial probe, 271 * before the RPM(H)PD sync_state is done. 272 */ 273 ret = clk_bulk_prepare_enable(msm_mdss->num_clocks, msm_mdss->clocks); 274 if (ret) { 275 dev_err(msm_mdss->dev, "clock enable failed, ret:%d\n", ret); 276 return ret; 277 } 278 279 /* 280 * Register access requires MDSS_MDP_CLK, which is not enabled by the 281 * mdss on mdp5 hardware. Skip it for now. 282 */ 283 if (msm_mdss->is_mdp5 || !msm_mdss->mdss_data) 284 return 0; 285 286 /* 287 * ubwc config is part of the "mdss" region which is not accessible 288 * from the rest of the driver. hardcode known configurations here 289 * 290 * Decoder version can be read from the UBWC_DEC_HW_VERSION reg, 291 * UBWC_n and the rest of params comes from hw data. 292 */ 293 switch (msm_mdss->mdss_data->ubwc_dec_version) { 294 case 0: /* no UBWC */ 295 case UBWC_1_0: 296 /* do nothing */ 297 break; 298 case UBWC_2_0: 299 msm_mdss_setup_ubwc_dec_20(msm_mdss); 300 break; 301 case UBWC_3_0: 302 msm_mdss_setup_ubwc_dec_30(msm_mdss); 303 break; 304 case UBWC_4_0: 305 case UBWC_4_3: 306 msm_mdss_setup_ubwc_dec_40(msm_mdss); 307 break; 308 case UBWC_5_0: 309 msm_mdss_setup_ubwc_dec_50(msm_mdss); 310 break; 311 case UBWC_6_0: 312 msm_mdss_setup_ubwc_dec_50(msm_mdss); 313 break; 314 default: 315 dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", 316 msm_mdss->mdss_data->ubwc_dec_version); 317 dev_err(msm_mdss->dev, "HW_REV: 0x%x\n", 318 readl_relaxed(msm_mdss->mmio + REG_MDSS_HW_VERSION)); 319 dev_err(msm_mdss->dev, "UBWC_DEC_HW_VERSION: 0x%x\n", 320 readl_relaxed(msm_mdss->mmio + REG_MDSS_UBWC_DEC_HW_VERSION)); 321 break; 322 } 323 324 return ret; 325 } 326 327 static int msm_mdss_disable(struct msm_mdss *msm_mdss) 328 { 329 int i; 330 331 clk_bulk_disable_unprepare(msm_mdss->num_clocks, msm_mdss->clocks); 332 333 for (i = 0; i < msm_mdss->num_mdp_paths; i++) 334 icc_set_bw(msm_mdss->mdp_path[i], 0, 0); 335 336 if (msm_mdss->reg_bus_path) 337 icc_set_bw(msm_mdss->reg_bus_path, 0, 0); 338 339 return 0; 340 } 341 342 static void msm_mdss_destroy(struct msm_mdss *msm_mdss) 343 { 344 struct platform_device *pdev = to_platform_device(msm_mdss->dev); 345 int irq; 346 347 pm_runtime_suspend(msm_mdss->dev); 348 pm_runtime_disable(msm_mdss->dev); 349 irq_domain_remove(msm_mdss->irq_controller.domain); 350 msm_mdss->irq_controller.domain = NULL; 351 irq = platform_get_irq(pdev, 0); 352 irq_set_chained_handler_and_data(irq, NULL, NULL); 353 } 354 355 static int msm_mdss_reset(struct device *dev) 356 { 357 struct reset_control *reset; 358 359 reset = reset_control_get_optional_exclusive(dev, NULL); 360 if (!reset) { 361 /* Optional reset not specified */ 362 return 0; 363 } else if (IS_ERR(reset)) { 364 return dev_err_probe(dev, PTR_ERR(reset), 365 "failed to acquire mdss reset\n"); 366 } 367 368 reset_control_assert(reset); 369 /* 370 * Tests indicate that reset has to be held for some period of time, 371 * make it one frame in a typical system 372 */ 373 msleep(20); 374 reset_control_deassert(reset); 375 376 reset_control_put(reset); 377 378 return 0; 379 } 380 381 /* 382 * MDP5 MDSS uses at most three specified clocks. 383 */ 384 #define MDP5_MDSS_NUM_CLOCKS 3 385 static int mdp5_mdss_parse_clock(struct platform_device *pdev, struct clk_bulk_data **clocks) 386 { 387 struct clk_bulk_data *bulk; 388 int num_clocks = 0; 389 int ret; 390 391 if (!pdev) 392 return -EINVAL; 393 394 bulk = devm_kcalloc(&pdev->dev, MDP5_MDSS_NUM_CLOCKS, sizeof(struct clk_bulk_data), GFP_KERNEL); 395 if (!bulk) 396 return -ENOMEM; 397 398 bulk[num_clocks++].id = "iface"; 399 bulk[num_clocks++].id = "bus"; 400 bulk[num_clocks++].id = "vsync"; 401 402 ret = devm_clk_bulk_get_optional(&pdev->dev, num_clocks, bulk); 403 if (ret) 404 return ret; 405 406 *clocks = bulk; 407 408 return num_clocks; 409 } 410 411 static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5) 412 { 413 const struct msm_mdss_data *mdss_data; 414 struct msm_mdss *msm_mdss; 415 int ret; 416 int irq; 417 418 ret = msm_mdss_reset(&pdev->dev); 419 if (ret) 420 return ERR_PTR(ret); 421 422 msm_mdss = devm_kzalloc(&pdev->dev, sizeof(*msm_mdss), GFP_KERNEL); 423 if (!msm_mdss) 424 return ERR_PTR(-ENOMEM); 425 426 msm_mdss->mdss_data = qcom_ubwc_config_get_data(); 427 if (IS_ERR(msm_mdss->mdss_data)) 428 return ERR_CAST(msm_mdss->mdss_data); 429 430 mdss_data = of_device_get_match_data(&pdev->dev); 431 if (!mdss_data) 432 return ERR_PTR(-EINVAL); 433 434 msm_mdss->reg_bus_bw = mdss_data->reg_bus_bw; 435 436 msm_mdss->mmio = devm_platform_ioremap_resource_byname(pdev, is_mdp5 ? "mdss_phys" : "mdss"); 437 if (IS_ERR(msm_mdss->mmio)) 438 return ERR_CAST(msm_mdss->mmio); 439 440 dev_dbg(&pdev->dev, "mapped mdss address space @%p\n", msm_mdss->mmio); 441 442 ret = msm_mdss_parse_data_bus_icc_path(&pdev->dev, msm_mdss); 443 if (ret) 444 return ERR_PTR(ret); 445 446 if (is_mdp5) 447 ret = mdp5_mdss_parse_clock(pdev, &msm_mdss->clocks); 448 else 449 ret = devm_clk_bulk_get_all(&pdev->dev, &msm_mdss->clocks); 450 if (ret < 0) { 451 dev_err(&pdev->dev, "failed to parse clocks, ret=%d\n", ret); 452 return ERR_PTR(ret); 453 } 454 msm_mdss->num_clocks = ret; 455 msm_mdss->is_mdp5 = is_mdp5; 456 457 msm_mdss->dev = &pdev->dev; 458 459 irq = platform_get_irq(pdev, 0); 460 if (irq < 0) 461 return ERR_PTR(irq); 462 463 ret = _msm_mdss_irq_domain_add(msm_mdss); 464 if (ret) 465 return ERR_PTR(ret); 466 467 irq_set_chained_handler_and_data(irq, msm_mdss_irq, 468 msm_mdss); 469 470 pm_runtime_enable(&pdev->dev); 471 472 return msm_mdss; 473 } 474 475 static int __maybe_unused mdss_runtime_suspend(struct device *dev) 476 { 477 struct msm_mdss *mdss = dev_get_drvdata(dev); 478 479 DBG(""); 480 481 return msm_mdss_disable(mdss); 482 } 483 484 static int __maybe_unused mdss_runtime_resume(struct device *dev) 485 { 486 struct msm_mdss *mdss = dev_get_drvdata(dev); 487 488 DBG(""); 489 490 return msm_mdss_enable(mdss); 491 } 492 493 static int __maybe_unused mdss_pm_suspend(struct device *dev) 494 { 495 496 if (pm_runtime_suspended(dev)) 497 return 0; 498 499 return mdss_runtime_suspend(dev); 500 } 501 502 static int __maybe_unused mdss_pm_resume(struct device *dev) 503 { 504 if (pm_runtime_suspended(dev)) 505 return 0; 506 507 return mdss_runtime_resume(dev); 508 } 509 510 static const struct dev_pm_ops mdss_pm_ops = { 511 SET_SYSTEM_SLEEP_PM_OPS(mdss_pm_suspend, mdss_pm_resume) 512 SET_RUNTIME_PM_OPS(mdss_runtime_suspend, mdss_runtime_resume, NULL) 513 }; 514 515 static int mdss_probe(struct platform_device *pdev) 516 { 517 struct msm_mdss *mdss; 518 bool is_mdp5 = of_device_is_compatible(pdev->dev.of_node, "qcom,mdss"); 519 struct device *dev = &pdev->dev; 520 int ret; 521 522 mdss = msm_mdss_init(pdev, is_mdp5); 523 if (IS_ERR(mdss)) 524 return PTR_ERR(mdss); 525 526 platform_set_drvdata(pdev, mdss); 527 528 /* 529 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 530 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 531 * Populate the children devices, find the MDP5/DPU node, and then add 532 * the interfaces to our components list. 533 */ 534 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 535 if (ret) { 536 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 537 msm_mdss_destroy(mdss); 538 return ret; 539 } 540 541 return 0; 542 } 543 544 static void mdss_remove(struct platform_device *pdev) 545 { 546 struct msm_mdss *mdss = platform_get_drvdata(pdev); 547 548 of_platform_depopulate(&pdev->dev); 549 550 msm_mdss_destroy(mdss); 551 } 552 553 static const struct msm_mdss_data data_57k = { 554 .reg_bus_bw = 57000, 555 }; 556 557 static const struct msm_mdss_data data_74k = { 558 .reg_bus_bw = 74000, 559 }; 560 561 static const struct msm_mdss_data data_76k8 = { 562 .reg_bus_bw = 76800, 563 }; 564 565 static const struct msm_mdss_data data_153k6 = { 566 .reg_bus_bw = 153600, 567 }; 568 569 static const struct of_device_id mdss_dt_match[] = { 570 { .compatible = "qcom,mdss", .data = &data_153k6 }, 571 { .compatible = "qcom,eliza-mdss", .data = &data_57k }, 572 { .compatible = "qcom,glymur-mdss", .data = &data_57k }, 573 { .compatible = "qcom,kaanapali-mdss", .data = &data_57k }, 574 { .compatible = "qcom,msm8998-mdss", .data = &data_76k8 }, 575 { .compatible = "qcom,qcm2290-mdss", .data = &data_76k8 }, 576 { .compatible = "qcom,qcs8300-mdss", .data = &data_74k }, 577 { .compatible = "qcom,sa8775p-mdss", .data = &data_74k }, 578 { .compatible = "qcom,sar2130p-mdss", .data = &data_74k }, 579 { .compatible = "qcom,sdm670-mdss", .data = &data_76k8 }, 580 { .compatible = "qcom,sdm845-mdss", .data = &data_76k8 }, 581 { .compatible = "qcom,sc7180-mdss", .data = &data_76k8 }, 582 { .compatible = "qcom,sc7280-mdss", .data = &data_74k }, 583 { .compatible = "qcom,sc8180x-mdss", .data = &data_76k8 }, 584 { .compatible = "qcom,sc8280xp-mdss", .data = &data_76k8 }, 585 { .compatible = "qcom,sm6115-mdss", .data = &data_76k8 }, 586 { .compatible = "qcom,sm6125-mdss", .data = &data_76k8 }, 587 { .compatible = "qcom,sm6150-mdss", .data = &data_76k8 }, 588 { .compatible = "qcom,sm6350-mdss", .data = &data_76k8 }, 589 { .compatible = "qcom,sm6375-mdss", .data = &data_76k8 }, 590 { .compatible = "qcom,sm7150-mdss", .data = &data_76k8 }, 591 { .compatible = "qcom,sm8150-mdss", .data = &data_76k8 }, 592 { .compatible = "qcom,sm8250-mdss", .data = &data_76k8 }, 593 { .compatible = "qcom,sm8350-mdss", .data = &data_74k }, 594 { .compatible = "qcom,sm8450-mdss", .data = &data_74k }, 595 { .compatible = "qcom,sm8550-mdss", .data = &data_57k }, 596 { .compatible = "qcom,sm8650-mdss", .data = &data_57k }, 597 { .compatible = "qcom,sm8750-mdss", .data = &data_57k }, 598 /* TODO: x1e8: Add reg_bus_bw with real value */ 599 { .compatible = "qcom,x1e80100-mdss", .data = &data_153k6 }, 600 {} 601 }; 602 MODULE_DEVICE_TABLE(of, mdss_dt_match); 603 604 static struct platform_driver mdss_platform_driver = { 605 .probe = mdss_probe, 606 .remove = mdss_remove, 607 .driver = { 608 .name = "msm-mdss", 609 .of_match_table = mdss_dt_match, 610 .pm = &mdss_pm_ops, 611 }, 612 }; 613 614 void __init msm_mdss_register(void) 615 { 616 platform_driver_register(&mdss_platform_driver); 617 } 618 619 void __exit msm_mdss_unregister(void) 620 { 621 platform_driver_unregister(&mdss_platform_driver); 622 } 623