1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_GPU_H__ 19 #define __MSM_GPU_H__ 20 21 #include <linux/clk.h> 22 #include <linux/regulator/consumer.h> 23 24 #include "msm_drv.h" 25 #include "msm_fence.h" 26 #include "msm_ringbuffer.h" 27 28 struct msm_gem_submit; 29 struct msm_gpu_perfcntr; 30 struct msm_gpu_state; 31 32 struct msm_gpu_config { 33 const char *ioname; 34 const char *irqname; 35 uint64_t va_start; 36 uint64_t va_end; 37 unsigned int nr_rings; 38 }; 39 40 /* So far, with hardware that I've seen to date, we can have: 41 * + zero, one, or two z180 2d cores 42 * + a3xx or a2xx 3d core, which share a common CP (the firmware 43 * for the CP seems to implement some different PM4 packet types 44 * but the basics of cmdstream submission are the same) 45 * 46 * Which means that the eventual complete "class" hierarchy, once 47 * support for all past and present hw is in place, becomes: 48 * + msm_gpu 49 * + adreno_gpu 50 * + a3xx_gpu 51 * + a2xx_gpu 52 * + z180_gpu 53 */ 54 struct msm_gpu_funcs { 55 int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 56 int (*hw_init)(struct msm_gpu *gpu); 57 int (*pm_suspend)(struct msm_gpu *gpu); 58 int (*pm_resume)(struct msm_gpu *gpu); 59 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, 60 struct msm_file_private *ctx); 61 void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); 62 irqreturn_t (*irq)(struct msm_gpu *irq); 63 struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu); 64 void (*recover)(struct msm_gpu *gpu); 65 void (*destroy)(struct msm_gpu *gpu); 66 #ifdef CONFIG_DEBUG_FS 67 /* show GPU status in debugfs: */ 68 void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state, 69 struct drm_printer *p); 70 /* for generation specific debugfs: */ 71 int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor); 72 #endif 73 unsigned long (*gpu_busy)(struct msm_gpu *gpu); 74 struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); 75 int (*gpu_state_put)(struct msm_gpu_state *state); 76 unsigned long (*gpu_get_freq)(struct msm_gpu *gpu); 77 void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq); 78 }; 79 80 struct msm_gpu { 81 const char *name; 82 struct drm_device *dev; 83 struct platform_device *pdev; 84 const struct msm_gpu_funcs *funcs; 85 86 /* performance counters (hw & sw): */ 87 spinlock_t perf_lock; 88 bool perfcntr_active; 89 struct { 90 bool active; 91 ktime_t time; 92 } last_sample; 93 uint32_t totaltime, activetime; /* sw counters */ 94 uint32_t last_cntrs[5]; /* hw counters */ 95 const struct msm_gpu_perfcntr *perfcntrs; 96 uint32_t num_perfcntrs; 97 98 struct msm_ringbuffer *rb[MSM_GPU_MAX_RINGS]; 99 int nr_rings; 100 101 /* list of GEM active objects: */ 102 struct list_head active_list; 103 104 /* does gpu need hw_init? */ 105 bool needs_hw_init; 106 107 /* worker for handling active-list retiring: */ 108 struct work_struct retire_work; 109 110 void __iomem *mmio; 111 int irq; 112 113 struct msm_gem_address_space *aspace; 114 115 /* Power Control: */ 116 struct regulator *gpu_reg, *gpu_cx; 117 struct clk_bulk_data *grp_clks; 118 int nr_clocks; 119 struct clk *ebi1_clk, *core_clk, *rbbmtimer_clk; 120 uint32_t fast_rate; 121 122 /* Hang and Inactivity Detection: 123 */ 124 #define DRM_MSM_INACTIVE_PERIOD 66 /* in ms (roughly four frames) */ 125 126 #define DRM_MSM_HANGCHECK_PERIOD 500 /* in ms */ 127 #define DRM_MSM_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_MSM_HANGCHECK_PERIOD) 128 struct timer_list hangcheck_timer; 129 struct work_struct recover_work; 130 131 struct drm_gem_object *memptrs_bo; 132 133 struct { 134 struct devfreq *devfreq; 135 u64 busy_cycles; 136 ktime_t time; 137 } devfreq; 138 139 struct msm_gpu_state *crashstate; 140 }; 141 142 /* It turns out that all targets use the same ringbuffer size */ 143 #define MSM_GPU_RINGBUFFER_SZ SZ_32K 144 #define MSM_GPU_RINGBUFFER_BLKSIZE 32 145 146 #define MSM_GPU_RB_CNTL_DEFAULT \ 147 (AXXX_CP_RB_CNTL_BUFSZ(ilog2(MSM_GPU_RINGBUFFER_SZ / 8)) | \ 148 AXXX_CP_RB_CNTL_BLKSZ(ilog2(MSM_GPU_RINGBUFFER_BLKSIZE / 8))) 149 150 static inline bool msm_gpu_active(struct msm_gpu *gpu) 151 { 152 int i; 153 154 for (i = 0; i < gpu->nr_rings; i++) { 155 struct msm_ringbuffer *ring = gpu->rb[i]; 156 157 if (ring->seqno > ring->memptrs->fence) 158 return true; 159 } 160 161 return false; 162 } 163 164 /* Perf-Counters: 165 * The select_reg and select_val are just there for the benefit of the child 166 * class that actually enables the perf counter.. but msm_gpu base class 167 * will handle sampling/displaying the counters. 168 */ 169 170 struct msm_gpu_perfcntr { 171 uint32_t select_reg; 172 uint32_t sample_reg; 173 uint32_t select_val; 174 const char *name; 175 }; 176 177 struct msm_gpu_submitqueue { 178 int id; 179 u32 flags; 180 u32 prio; 181 int faults; 182 struct list_head node; 183 struct kref ref; 184 }; 185 186 struct msm_gpu_state_bo { 187 u64 iova; 188 size_t size; 189 void *data; 190 bool encoded; 191 }; 192 193 struct msm_gpu_state { 194 struct kref ref; 195 struct timespec64 time; 196 197 struct { 198 u64 iova; 199 u32 fence; 200 u32 seqno; 201 u32 rptr; 202 u32 wptr; 203 void *data; 204 int data_size; 205 bool encoded; 206 } ring[MSM_GPU_MAX_RINGS]; 207 208 int nr_registers; 209 u32 *registers; 210 211 u32 rbbm_status; 212 213 char *comm; 214 char *cmd; 215 216 int nr_bos; 217 struct msm_gpu_state_bo *bos; 218 }; 219 220 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) 221 { 222 msm_writel(data, gpu->mmio + (reg << 2)); 223 } 224 225 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) 226 { 227 return msm_readl(gpu->mmio + (reg << 2)); 228 } 229 230 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or) 231 { 232 uint32_t val = gpu_read(gpu, reg); 233 234 val &= ~mask; 235 gpu_write(gpu, reg, val | or); 236 } 237 238 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi) 239 { 240 u64 val; 241 242 /* 243 * Why not a readq here? Two reasons: 1) many of the LO registers are 244 * not quad word aligned and 2) the GPU hardware designers have a bit 245 * of a history of putting registers where they fit, especially in 246 * spins. The longer a GPU family goes the higher the chance that 247 * we'll get burned. We could do a series of validity checks if we 248 * wanted to, but really is a readq() that much better? Nah. 249 */ 250 251 /* 252 * For some lo/hi registers (like perfcounters), the hi value is latched 253 * when the lo is read, so make sure to read the lo first to trigger 254 * that 255 */ 256 val = (u64) msm_readl(gpu->mmio + (lo << 2)); 257 val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32); 258 259 return val; 260 } 261 262 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val) 263 { 264 /* Why not a writeq here? Read the screed above */ 265 msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2)); 266 msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2)); 267 } 268 269 int msm_gpu_pm_suspend(struct msm_gpu *gpu); 270 int msm_gpu_pm_resume(struct msm_gpu *gpu); 271 void msm_gpu_resume_devfreq(struct msm_gpu *gpu); 272 273 int msm_gpu_hw_init(struct msm_gpu *gpu); 274 275 void msm_gpu_perfcntr_start(struct msm_gpu *gpu); 276 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu); 277 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 278 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs); 279 280 void msm_gpu_retire(struct msm_gpu *gpu); 281 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 282 struct msm_file_private *ctx); 283 284 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 285 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 286 const char *name, struct msm_gpu_config *config); 287 288 void msm_gpu_cleanup(struct msm_gpu *gpu); 289 290 struct msm_gpu *adreno_load_gpu(struct drm_device *dev); 291 void __init adreno_register(void); 292 void __exit adreno_unregister(void); 293 294 static inline void msm_submitqueue_put(struct msm_gpu_submitqueue *queue) 295 { 296 if (queue) 297 kref_put(&queue->ref, msm_submitqueue_destroy); 298 } 299 300 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu) 301 { 302 struct msm_gpu_state *state = NULL; 303 304 mutex_lock(&gpu->dev->struct_mutex); 305 306 if (gpu->crashstate) { 307 kref_get(&gpu->crashstate->ref); 308 state = gpu->crashstate; 309 } 310 311 mutex_unlock(&gpu->dev->struct_mutex); 312 313 return state; 314 } 315 316 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu) 317 { 318 mutex_lock(&gpu->dev->struct_mutex); 319 320 if (gpu->crashstate) { 321 if (gpu->funcs->gpu_state_put(gpu->crashstate)) 322 gpu->crashstate = NULL; 323 } 324 325 mutex_unlock(&gpu->dev->struct_mutex); 326 } 327 328 #endif /* __MSM_GPU_H__ */ 329