1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include "drm/drm_drv.h" 8 9 #include "msm_gpu.h" 10 #include "msm_gem.h" 11 #include "msm_mmu.h" 12 #include "msm_fence.h" 13 #include "msm_gpu_trace.h" 14 //#include "adreno/adreno_gpu.h" 15 16 #include <generated/utsrelease.h> 17 #include <linux/string_helpers.h> 18 #include <linux/devcoredump.h> 19 #include <linux/sched/task.h> 20 21 /* 22 * Power Management: 23 */ 24 25 static int enable_pwrrail(struct msm_gpu *gpu) 26 { 27 struct drm_device *dev = gpu->dev; 28 int ret = 0; 29 30 if (gpu->gpu_reg) { 31 ret = regulator_enable(gpu->gpu_reg); 32 if (ret) { 33 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); 34 return ret; 35 } 36 } 37 38 if (gpu->gpu_cx) { 39 ret = regulator_enable(gpu->gpu_cx); 40 if (ret) { 41 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); 42 return ret; 43 } 44 } 45 46 return 0; 47 } 48 49 static int disable_pwrrail(struct msm_gpu *gpu) 50 { 51 if (gpu->gpu_cx) 52 regulator_disable(gpu->gpu_cx); 53 if (gpu->gpu_reg) 54 regulator_disable(gpu->gpu_reg); 55 return 0; 56 } 57 58 static int enable_clk(struct msm_gpu *gpu) 59 { 60 if (gpu->core_clk && gpu->fast_rate) 61 dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); 62 63 /* Set the RBBM timer rate to 19.2Mhz */ 64 if (gpu->rbbmtimer_clk) 65 clk_set_rate(gpu->rbbmtimer_clk, 19200000); 66 67 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 68 } 69 70 static int disable_clk(struct msm_gpu *gpu) 71 { 72 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 73 74 /* 75 * Set the clock to a deliberately low rate. On older targets the clock 76 * speed had to be non zero to avoid problems. On newer targets this 77 * will be rounded down to zero anyway so it all works out. 78 */ 79 if (gpu->core_clk) 80 dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); 81 82 if (gpu->rbbmtimer_clk) 83 clk_set_rate(gpu->rbbmtimer_clk, 0); 84 85 return 0; 86 } 87 88 static int enable_axi(struct msm_gpu *gpu) 89 { 90 return clk_prepare_enable(gpu->ebi1_clk); 91 } 92 93 static int disable_axi(struct msm_gpu *gpu) 94 { 95 clk_disable_unprepare(gpu->ebi1_clk); 96 return 0; 97 } 98 99 int msm_gpu_pm_resume(struct msm_gpu *gpu) 100 { 101 int ret; 102 103 DBG("%s", gpu->name); 104 trace_msm_gpu_resume(0); 105 106 ret = enable_pwrrail(gpu); 107 if (ret) 108 return ret; 109 110 ret = enable_clk(gpu); 111 if (ret) 112 return ret; 113 114 ret = enable_axi(gpu); 115 if (ret) 116 return ret; 117 118 msm_devfreq_resume(gpu); 119 120 gpu->needs_hw_init = true; 121 122 return 0; 123 } 124 125 int msm_gpu_pm_suspend(struct msm_gpu *gpu) 126 { 127 int ret; 128 129 DBG("%s", gpu->name); 130 trace_msm_gpu_suspend(0); 131 132 msm_devfreq_suspend(gpu); 133 134 ret = disable_axi(gpu); 135 if (ret) 136 return ret; 137 138 ret = disable_clk(gpu); 139 if (ret) 140 return ret; 141 142 ret = disable_pwrrail(gpu); 143 if (ret) 144 return ret; 145 146 gpu->suspend_count++; 147 148 return 0; 149 } 150 151 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_context *ctx, 152 struct drm_printer *p) 153 { 154 drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns); 155 drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles); 156 drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate); 157 } 158 159 int msm_gpu_hw_init(struct msm_gpu *gpu) 160 { 161 int ret; 162 163 WARN_ON(!mutex_is_locked(&gpu->lock)); 164 165 if (!gpu->needs_hw_init) 166 return 0; 167 168 disable_irq(gpu->irq); 169 ret = gpu->funcs->hw_init(gpu); 170 if (!ret) 171 gpu->needs_hw_init = false; 172 enable_irq(gpu->irq); 173 174 return ret; 175 } 176 177 #ifdef CONFIG_DEV_COREDUMP 178 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, 179 size_t count, void *data, size_t datalen) 180 { 181 struct msm_gpu *gpu = data; 182 struct drm_print_iterator iter; 183 struct drm_printer p; 184 struct msm_gpu_state *state; 185 186 state = msm_gpu_crashstate_get(gpu); 187 if (!state) 188 return 0; 189 190 iter.data = buffer; 191 iter.offset = 0; 192 iter.start = offset; 193 iter.remain = count; 194 195 p = drm_coredump_printer(&iter); 196 197 drm_printf(&p, "---\n"); 198 drm_printf(&p, "kernel: " UTS_RELEASE "\n"); 199 drm_printf(&p, "module: " KBUILD_MODNAME "\n"); 200 drm_printf(&p, "time: %ptSp\n", &state->time); 201 if (state->comm) 202 drm_printf(&p, "comm: %s\n", state->comm); 203 if (state->cmd) 204 drm_printf(&p, "cmdline: %s\n", state->cmd); 205 206 gpu->funcs->show(gpu, state, &p); 207 208 msm_gpu_crashstate_put(gpu); 209 210 return count - iter.remain; 211 } 212 213 static void msm_gpu_devcoredump_free(void *data) 214 { 215 struct msm_gpu *gpu = data; 216 217 msm_gpu_crashstate_put(gpu); 218 } 219 220 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, 221 struct drm_gem_object *obj, u64 iova, 222 bool full, size_t offset, size_t size) 223 { 224 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; 225 struct msm_gem_object *msm_obj = to_msm_bo(obj); 226 227 /* Don't record write only objects */ 228 state_bo->size = size; 229 state_bo->flags = msm_obj->flags; 230 state_bo->iova = iova; 231 232 BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(msm_obj->name)); 233 234 memcpy(state_bo->name, msm_obj->name, sizeof(state_bo->name)); 235 236 if (full) { 237 void *ptr; 238 239 state_bo->data = kvmalloc(size, GFP_KERNEL); 240 if (!state_bo->data) 241 goto out; 242 243 ptr = msm_gem_get_vaddr_active(obj); 244 if (IS_ERR(ptr)) { 245 kvfree(state_bo->data); 246 state_bo->data = NULL; 247 goto out; 248 } 249 250 memcpy(state_bo->data, ptr + offset, size); 251 msm_gem_put_vaddr_locked(obj); 252 } 253 out: 254 state->nr_bos++; 255 } 256 257 static void crashstate_get_bos(struct msm_gpu_state *state, struct msm_gem_submit *submit) 258 { 259 extern bool rd_full; 260 261 if (msm_context_is_vmbind(submit->queue->ctx)) { 262 struct drm_exec exec; 263 struct drm_gpuva *vma; 264 unsigned cnt = 0; 265 266 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); 267 drm_exec_until_all_locked(&exec) { 268 cnt = 0; 269 270 drm_exec_lock_obj(&exec, drm_gpuvm_resv_obj(submit->vm)); 271 drm_exec_retry_on_contention(&exec); 272 273 drm_gpuvm_for_each_va (vma, submit->vm) { 274 if (!vma->gem.obj) 275 continue; 276 277 cnt++; 278 drm_exec_lock_obj(&exec, vma->gem.obj); 279 drm_exec_retry_on_contention(&exec); 280 } 281 282 } 283 284 drm_gpuvm_for_each_va (vma, submit->vm) 285 cnt++; 286 287 state->bos = kcalloc(cnt, sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 288 289 drm_gpuvm_for_each_va (vma, submit->vm) { 290 bool dump = rd_full || (vma->flags & MSM_VMA_DUMP); 291 292 /* Skip MAP_NULL/PRR VMAs: */ 293 if (!vma->gem.obj) 294 continue; 295 296 msm_gpu_crashstate_get_bo(state, vma->gem.obj, vma->va.addr, 297 dump, vma->gem.offset, vma->va.range); 298 } 299 300 drm_exec_fini(&exec); 301 } else { 302 state->bos = kcalloc(submit->nr_bos, 303 sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 304 305 for (int i = 0; state->bos && i < submit->nr_bos; i++) { 306 struct drm_gem_object *obj = submit->bos[i].obj; 307 bool dump = rd_full || (submit->bos[i].flags & MSM_SUBMIT_BO_DUMP); 308 309 msm_gem_lock(obj); 310 msm_gpu_crashstate_get_bo(state, obj, submit->bos[i].iova, 311 dump, 0, obj->size); 312 msm_gem_unlock(obj); 313 } 314 } 315 } 316 317 static void crashstate_get_vm_logs(struct msm_gpu_state *state, struct msm_gem_vm *vm) 318 { 319 uint32_t vm_log_len = (1 << vm->log_shift); 320 uint32_t vm_log_mask = vm_log_len - 1; 321 int first; 322 323 /* Bail if no log, or empty log: */ 324 if (!vm->log || !vm->log[0].op) 325 return; 326 327 mutex_lock(&vm->mmu_lock); 328 329 /* 330 * log_idx is the next entry to overwrite, meaning it is the oldest, or 331 * first, entry (other than the special case handled below where the 332 * log hasn't wrapped around yet) 333 */ 334 first = vm->log_idx; 335 336 if (!vm->log[first].op) { 337 /* 338 * If the next log entry has not been written yet, then only 339 * entries 0 to idx-1 are valid (ie. we haven't wrapped around 340 * yet) 341 */ 342 state->nr_vm_logs = MAX(0, first - 1); 343 first = 0; 344 } else { 345 state->nr_vm_logs = vm_log_len; 346 } 347 348 state->vm_logs = kmalloc_array( 349 state->nr_vm_logs, sizeof(vm->log[0]), GFP_KERNEL); 350 for (int i = 0; i < state->nr_vm_logs; i++) { 351 int idx = (i + first) & vm_log_mask; 352 353 state->vm_logs[i] = vm->log[idx]; 354 } 355 356 mutex_unlock(&vm->mmu_lock); 357 } 358 359 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 360 struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info, 361 char *comm, char *cmd) 362 { 363 struct msm_gpu_state *state; 364 365 /* Check if the target supports capturing crash state */ 366 if (!gpu->funcs->gpu_state_get) 367 return; 368 369 /* Only save one crash state at a time */ 370 if (gpu->crashstate) 371 return; 372 373 state = gpu->funcs->gpu_state_get(gpu); 374 if (IS_ERR_OR_NULL(state)) 375 return; 376 377 /* Fill in the additional crash state information */ 378 state->comm = kstrdup(comm, GFP_KERNEL); 379 state->cmd = kstrdup(cmd, GFP_KERNEL); 380 if (fault_info) 381 state->fault_info = *fault_info; 382 383 if (submit && state->fault_info.ttbr0) { 384 struct msm_gpu_fault_info *info = &state->fault_info; 385 struct msm_mmu *mmu = to_msm_vm(submit->vm)->mmu; 386 387 msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0, 388 &info->asid); 389 msm_iommu_pagetable_walk(mmu, info->iova, info->ptes); 390 } 391 392 if (submit) { 393 crashstate_get_vm_logs(state, to_msm_vm(submit->vm)); 394 crashstate_get_bos(state, submit); 395 } 396 397 /* Set the active crash state to be dumped on failure */ 398 gpu->crashstate = state; 399 400 dev_coredumpm(&gpu->pdev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, 401 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free); 402 } 403 #else 404 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 405 struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info, 406 char *comm, char *cmd) 407 { 408 } 409 #endif 410 411 /* 412 * Hangcheck detection for locked gpu: 413 */ 414 415 static struct msm_gem_submit * 416 find_submit(struct msm_ringbuffer *ring, uint32_t fence) 417 { 418 struct msm_gem_submit *submit; 419 unsigned long flags; 420 421 spin_lock_irqsave(&ring->submit_lock, flags); 422 list_for_each_entry(submit, &ring->submits, node) { 423 if (submit->seqno == fence) { 424 spin_unlock_irqrestore(&ring->submit_lock, flags); 425 return submit; 426 } 427 } 428 spin_unlock_irqrestore(&ring->submit_lock, flags); 429 430 return NULL; 431 } 432 433 static void retire_submits(struct msm_gpu *gpu); 434 435 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd) 436 { 437 struct msm_context *ctx = submit->queue->ctx; 438 struct task_struct *task; 439 440 WARN_ON(!mutex_is_locked(&submit->gpu->lock)); 441 442 /* Note that kstrdup will return NULL if argument is NULL: */ 443 *comm = kstrdup(ctx->comm, GFP_KERNEL); 444 *cmd = kstrdup(ctx->cmdline, GFP_KERNEL); 445 446 task = get_pid_task(submit->pid, PIDTYPE_PID); 447 if (!task) 448 return; 449 450 if (!*comm) 451 *comm = kstrdup(task->comm, GFP_KERNEL); 452 453 if (!*cmd) 454 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 455 456 put_task_struct(task); 457 } 458 459 static void recover_worker(struct kthread_work *work) 460 { 461 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); 462 struct drm_device *dev = gpu->dev; 463 struct msm_drm_private *priv = dev->dev_private; 464 struct msm_gem_submit *submit; 465 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 466 char *comm = NULL, *cmd = NULL; 467 struct task_struct *task; 468 int i; 469 470 mutex_lock(&gpu->lock); 471 472 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name); 473 474 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 475 476 /* 477 * If the submit retired while we were waiting for the worker to run, 478 * or waiting to acquire the gpu lock, then nothing more to do. 479 */ 480 if (!submit) 481 goto out_unlock; 482 483 /* Increment the fault counts */ 484 submit->queue->faults++; 485 486 task = get_pid_task(submit->pid, PIDTYPE_PID); 487 if (!task) 488 gpu->global_faults++; 489 else { 490 struct msm_gem_vm *vm = to_msm_vm(submit->vm); 491 492 vm->faults++; 493 494 /* 495 * If userspace has opted-in to VM_BIND (and therefore userspace 496 * management of the VM), faults mark the VM as unusable. This 497 * matches vulkan expectations (vulkan is the main target for 498 * VM_BIND). 499 */ 500 if (!vm->managed) 501 msm_gem_vm_unusable(submit->vm); 502 } 503 504 get_comm_cmdline(submit, &comm, &cmd); 505 506 if (comm && cmd) { 507 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n", 508 gpu->name, comm, cmd); 509 510 msm_rd_dump_submit(priv->hangrd, submit, 511 "offending task: %s (%s)", comm, cmd); 512 } else { 513 DRM_DEV_ERROR(dev->dev, "%s: offending task: unknown\n", gpu->name); 514 515 msm_rd_dump_submit(priv->hangrd, submit, NULL); 516 } 517 518 /* Record the crash state */ 519 pm_runtime_get_sync(&gpu->pdev->dev); 520 msm_gpu_crashstate_capture(gpu, submit, NULL, comm, cmd); 521 522 kfree(cmd); 523 kfree(comm); 524 525 /* 526 * Update all the rings with the latest and greatest fence.. this 527 * needs to happen after msm_rd_dump_submit() to ensure that the 528 * bo's referenced by the offending submit are still around. 529 */ 530 for (i = 0; i < gpu->nr_rings; i++) { 531 struct msm_ringbuffer *ring = gpu->rb[i]; 532 533 uint32_t fence = ring->memptrs->fence; 534 535 /* 536 * For the current (faulting?) ring/submit advance the fence by 537 * one more to clear the faulting submit 538 */ 539 if (ring == cur_ring) 540 ring->memptrs->fence = ++fence; 541 542 msm_update_fence(ring->fctx, fence); 543 } 544 545 if (msm_gpu_active(gpu)) { 546 /* retire completed submits, plus the one that hung: */ 547 retire_submits(gpu); 548 549 gpu->funcs->recover(gpu); 550 551 /* 552 * Replay all remaining submits starting with highest priority 553 * ring 554 */ 555 for (i = 0; i < gpu->nr_rings; i++) { 556 struct msm_ringbuffer *ring = gpu->rb[i]; 557 unsigned long flags; 558 559 spin_lock_irqsave(&ring->submit_lock, flags); 560 list_for_each_entry(submit, &ring->submits, node) { 561 /* 562 * If the submit uses an unusable vm make sure 563 * we don't actually run it 564 */ 565 if (to_msm_vm(submit->vm)->unusable) 566 submit->nr_cmds = 0; 567 gpu->funcs->submit(gpu, submit); 568 } 569 spin_unlock_irqrestore(&ring->submit_lock, flags); 570 } 571 } 572 573 pm_runtime_put(&gpu->pdev->dev); 574 575 out_unlock: 576 mutex_unlock(&gpu->lock); 577 578 msm_gpu_retire(gpu); 579 } 580 581 void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info) 582 { 583 struct msm_gem_submit *submit; 584 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 585 char *comm = NULL, *cmd = NULL; 586 587 mutex_lock(&gpu->lock); 588 589 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 590 if (submit && submit->fault_dumped) 591 goto resume_smmu; 592 593 if (submit) { 594 get_comm_cmdline(submit, &comm, &cmd); 595 596 /* 597 * When we get GPU iova faults, we can get 1000s of them, 598 * but we really only want to log the first one. 599 */ 600 submit->fault_dumped = true; 601 } 602 603 /* Record the crash state */ 604 pm_runtime_get_sync(&gpu->pdev->dev); 605 msm_gpu_crashstate_capture(gpu, submit, fault_info, comm, cmd); 606 pm_runtime_put_sync(&gpu->pdev->dev); 607 608 kfree(cmd); 609 kfree(comm); 610 611 resume_smmu: 612 mutex_unlock(&gpu->lock); 613 } 614 615 static void hangcheck_timer_reset(struct msm_gpu *gpu) 616 { 617 struct msm_drm_private *priv = gpu->dev->dev_private; 618 mod_timer(&gpu->hangcheck_timer, 619 round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period))); 620 } 621 622 static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 623 { 624 if (ring->hangcheck_progress_retries >= DRM_MSM_HANGCHECK_PROGRESS_RETRIES) 625 return false; 626 627 if (!gpu->funcs->progress) 628 return false; 629 630 if (!gpu->funcs->progress(gpu, ring)) 631 return false; 632 633 ring->hangcheck_progress_retries++; 634 return true; 635 } 636 637 static void hangcheck_handler(struct timer_list *t) 638 { 639 struct msm_gpu *gpu = timer_container_of(gpu, t, hangcheck_timer); 640 struct drm_device *dev = gpu->dev; 641 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 642 uint32_t fence = ring->memptrs->fence; 643 644 if (fence != ring->hangcheck_fence) { 645 /* some progress has been made.. ya! */ 646 ring->hangcheck_fence = fence; 647 ring->hangcheck_progress_retries = 0; 648 } else if (fence_before(fence, ring->fctx->last_fence) && 649 !made_progress(gpu, ring)) { 650 /* no progress and not done.. hung! */ 651 ring->hangcheck_fence = fence; 652 ring->hangcheck_progress_retries = 0; 653 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", 654 gpu->name, ring->id); 655 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n", 656 gpu->name, fence); 657 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n", 658 gpu->name, ring->fctx->last_fence); 659 660 kthread_queue_work(gpu->worker, &gpu->recover_work); 661 } 662 663 /* if still more pending work, reset the hangcheck timer: */ 664 if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence)) 665 hangcheck_timer_reset(gpu); 666 667 /* workaround for missing irq: */ 668 msm_gpu_retire(gpu); 669 } 670 671 /* 672 * Performance Counters: 673 */ 674 675 /* called under perf_lock */ 676 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) 677 { 678 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; 679 int i, n = min(ncntrs, gpu->num_perfcntrs); 680 681 /* read current values: */ 682 for (i = 0; i < gpu->num_perfcntrs; i++) 683 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); 684 685 /* update cntrs: */ 686 for (i = 0; i < n; i++) 687 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; 688 689 /* save current values: */ 690 for (i = 0; i < gpu->num_perfcntrs; i++) 691 gpu->last_cntrs[i] = current_cntrs[i]; 692 693 return n; 694 } 695 696 static void update_sw_cntrs(struct msm_gpu *gpu) 697 { 698 ktime_t time; 699 uint32_t elapsed; 700 unsigned long flags; 701 702 spin_lock_irqsave(&gpu->perf_lock, flags); 703 if (!gpu->perfcntr_active) 704 goto out; 705 706 time = ktime_get(); 707 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); 708 709 gpu->totaltime += elapsed; 710 if (gpu->last_sample.active) 711 gpu->activetime += elapsed; 712 713 gpu->last_sample.active = msm_gpu_active(gpu); 714 gpu->last_sample.time = time; 715 716 out: 717 spin_unlock_irqrestore(&gpu->perf_lock, flags); 718 } 719 720 void msm_gpu_perfcntr_start(struct msm_gpu *gpu) 721 { 722 unsigned long flags; 723 724 pm_runtime_get_sync(&gpu->pdev->dev); 725 726 spin_lock_irqsave(&gpu->perf_lock, flags); 727 /* we could dynamically enable/disable perfcntr registers too.. */ 728 gpu->last_sample.active = msm_gpu_active(gpu); 729 gpu->last_sample.time = ktime_get(); 730 gpu->activetime = gpu->totaltime = 0; 731 gpu->perfcntr_active = true; 732 update_hw_cntrs(gpu, 0, NULL); 733 spin_unlock_irqrestore(&gpu->perf_lock, flags); 734 } 735 736 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) 737 { 738 gpu->perfcntr_active = false; 739 pm_runtime_put_sync(&gpu->pdev->dev); 740 } 741 742 /* returns -errno or # of cntrs sampled */ 743 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 744 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) 745 { 746 unsigned long flags; 747 int ret; 748 749 spin_lock_irqsave(&gpu->perf_lock, flags); 750 751 if (!gpu->perfcntr_active) { 752 ret = -EINVAL; 753 goto out; 754 } 755 756 *activetime = gpu->activetime; 757 *totaltime = gpu->totaltime; 758 759 gpu->activetime = gpu->totaltime = 0; 760 761 ret = update_hw_cntrs(gpu, ncntrs, cntrs); 762 763 out: 764 spin_unlock_irqrestore(&gpu->perf_lock, flags); 765 766 return ret; 767 } 768 769 /* 770 * Cmdstream submission/retirement: 771 */ 772 773 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 774 struct msm_gem_submit *submit) 775 { 776 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 777 volatile struct msm_gpu_submit_stats *stats; 778 u64 elapsed, clock = 0, cycles; 779 unsigned long flags; 780 781 stats = &ring->memptrs->stats[index]; 782 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */ 783 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000; 784 do_div(elapsed, 192); 785 786 cycles = stats->cpcycles_end - stats->cpcycles_start; 787 788 /* Calculate the clock frequency from the number of CP cycles */ 789 if (elapsed) { 790 clock = cycles * 1000; 791 do_div(clock, elapsed); 792 } 793 794 submit->queue->ctx->elapsed_ns += elapsed; 795 submit->queue->ctx->cycles += cycles; 796 797 trace_msm_gpu_submit_retired(submit, elapsed, clock, 798 stats->alwayson_start, stats->alwayson_end); 799 800 msm_submit_retire(submit); 801 802 pm_runtime_mark_last_busy(&gpu->pdev->dev); 803 804 spin_lock_irqsave(&ring->submit_lock, flags); 805 list_del(&submit->node); 806 spin_unlock_irqrestore(&ring->submit_lock, flags); 807 808 /* Update devfreq on transition from active->idle: */ 809 mutex_lock(&gpu->active_lock); 810 gpu->active_submits--; 811 WARN_ON(gpu->active_submits < 0); 812 if (!gpu->active_submits) { 813 msm_devfreq_idle(gpu); 814 pm_runtime_put_autosuspend(&gpu->pdev->dev); 815 } 816 817 mutex_unlock(&gpu->active_lock); 818 819 msm_gem_submit_put(submit); 820 } 821 822 static void retire_submits(struct msm_gpu *gpu) 823 { 824 int i; 825 826 /* Retire the commits starting with highest priority */ 827 for (i = 0; i < gpu->nr_rings; i++) { 828 struct msm_ringbuffer *ring = gpu->rb[i]; 829 830 while (true) { 831 struct msm_gem_submit *submit = NULL; 832 unsigned long flags; 833 834 spin_lock_irqsave(&ring->submit_lock, flags); 835 submit = list_first_entry_or_null(&ring->submits, 836 struct msm_gem_submit, node); 837 spin_unlock_irqrestore(&ring->submit_lock, flags); 838 839 /* 840 * If no submit, we are done. If submit->fence hasn't 841 * been signalled, then later submits are not signalled 842 * either, so we are also done. 843 */ 844 if (submit && dma_fence_is_signaled(submit->hw_fence)) { 845 retire_submit(gpu, ring, submit); 846 } else { 847 break; 848 } 849 } 850 } 851 852 wake_up_all(&gpu->retire_event); 853 } 854 855 static void retire_worker(struct kthread_work *work) 856 { 857 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); 858 859 retire_submits(gpu); 860 } 861 862 /* call from irq handler to schedule work to retire bo's */ 863 void msm_gpu_retire(struct msm_gpu *gpu) 864 { 865 int i; 866 867 for (i = 0; i < gpu->nr_rings; i++) 868 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence); 869 870 kthread_queue_work(gpu->worker, &gpu->retire_work); 871 update_sw_cntrs(gpu); 872 } 873 874 /* add bo's to gpu's ring, and kick gpu: */ 875 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 876 { 877 struct msm_ringbuffer *ring = submit->ring; 878 unsigned long flags; 879 880 WARN_ON(!mutex_is_locked(&gpu->lock)); 881 882 pm_runtime_get_sync(&gpu->pdev->dev); 883 884 msm_gpu_hw_init(gpu); 885 886 submit->seqno = submit->hw_fence->seqno; 887 888 update_sw_cntrs(gpu); 889 890 /* 891 * ring->submits holds a ref to the submit, to deal with the case 892 * that a submit completes before msm_ioctl_gem_submit() returns. 893 */ 894 msm_gem_submit_get(submit); 895 896 spin_lock_irqsave(&ring->submit_lock, flags); 897 list_add_tail(&submit->node, &ring->submits); 898 spin_unlock_irqrestore(&ring->submit_lock, flags); 899 900 /* Update devfreq on transition from idle->active: */ 901 mutex_lock(&gpu->active_lock); 902 if (!gpu->active_submits) { 903 pm_runtime_get(&gpu->pdev->dev); 904 msm_devfreq_active(gpu); 905 } 906 gpu->active_submits++; 907 mutex_unlock(&gpu->active_lock); 908 909 gpu->funcs->submit(gpu, submit); 910 submit->ring->cur_ctx_seqno = submit->queue->ctx->seqno; 911 912 pm_runtime_put(&gpu->pdev->dev); 913 hangcheck_timer_reset(gpu); 914 } 915 916 /* 917 * Init/Cleanup: 918 */ 919 920 static irqreturn_t irq_handler(int irq, void *data) 921 { 922 struct msm_gpu *gpu = data; 923 return gpu->funcs->irq(gpu); 924 } 925 926 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) 927 { 928 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks); 929 930 if (ret < 1) { 931 gpu->nr_clocks = 0; 932 return ret; 933 } 934 935 gpu->nr_clocks = ret; 936 937 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 938 gpu->nr_clocks, "core"); 939 940 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 941 gpu->nr_clocks, "rbbmtimer"); 942 943 return 0; 944 } 945 946 /* Return a new address space for a msm_drm_private instance */ 947 struct drm_gpuvm * 948 msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task, 949 bool kernel_managed) 950 { 951 struct drm_gpuvm *vm = NULL; 952 953 if (!gpu) 954 return NULL; 955 956 /* 957 * If the target doesn't support private address spaces then return 958 * the global one 959 */ 960 if (gpu->funcs->create_private_vm) { 961 vm = gpu->funcs->create_private_vm(gpu, kernel_managed); 962 if (!IS_ERR(vm)) 963 to_msm_vm(vm)->pid = get_pid(task_pid(task)); 964 } 965 966 if (IS_ERR_OR_NULL(vm)) 967 vm = drm_gpuvm_get(gpu->vm); 968 969 return vm; 970 } 971 972 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 973 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 974 const char *name, struct msm_gpu_config *config) 975 { 976 struct msm_drm_private *priv = drm->dev_private; 977 int i, ret, nr_rings = config->nr_rings; 978 void *memptrs; 979 uint64_t memptrs_iova; 980 981 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) 982 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); 983 984 gpu->dev = drm; 985 gpu->funcs = funcs; 986 gpu->name = name; 987 988 gpu->worker = kthread_run_worker(0, "gpu-worker"); 989 if (IS_ERR(gpu->worker)) { 990 ret = PTR_ERR(gpu->worker); 991 gpu->worker = NULL; 992 goto fail; 993 } 994 995 sched_set_fifo_low(gpu->worker->task); 996 997 mutex_init(&gpu->active_lock); 998 mutex_init(&gpu->lock); 999 init_waitqueue_head(&gpu->retire_event); 1000 kthread_init_work(&gpu->retire_work, retire_worker); 1001 kthread_init_work(&gpu->recover_work, recover_worker); 1002 1003 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; 1004 1005 /* 1006 * If progress detection is supported, halve the hangcheck timer 1007 * duration, as it takes two iterations of the hangcheck handler 1008 * to detect a hang. 1009 */ 1010 if (funcs->progress) 1011 priv->hangcheck_period /= 2; 1012 1013 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); 1014 1015 spin_lock_init(&gpu->perf_lock); 1016 1017 1018 /* Map registers: */ 1019 gpu->mmio = msm_ioremap(pdev, config->ioname); 1020 if (IS_ERR(gpu->mmio)) { 1021 ret = PTR_ERR(gpu->mmio); 1022 goto fail; 1023 } 1024 1025 /* Get Interrupt: */ 1026 gpu->irq = platform_get_irq(pdev, 0); 1027 if (gpu->irq < 0) { 1028 ret = gpu->irq; 1029 goto fail; 1030 } 1031 1032 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 1033 IRQF_TRIGGER_HIGH, "gpu-irq", gpu); 1034 if (ret) { 1035 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); 1036 goto fail; 1037 } 1038 1039 ret = get_clocks(pdev, gpu); 1040 if (ret) 1041 goto fail; 1042 1043 gpu->ebi1_clk = msm_clk_get(pdev, "bus"); 1044 DBG("ebi1_clk: %p", gpu->ebi1_clk); 1045 if (IS_ERR(gpu->ebi1_clk)) 1046 gpu->ebi1_clk = NULL; 1047 1048 /* Acquire regulators: */ 1049 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); 1050 DBG("gpu_reg: %p", gpu->gpu_reg); 1051 if (IS_ERR(gpu->gpu_reg)) 1052 gpu->gpu_reg = NULL; 1053 1054 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); 1055 DBG("gpu_cx: %p", gpu->gpu_cx); 1056 if (IS_ERR(gpu->gpu_cx)) 1057 gpu->gpu_cx = NULL; 1058 1059 platform_set_drvdata(pdev, &gpu->adreno_smmu); 1060 1061 msm_devfreq_init(gpu); 1062 1063 gpu->vm = gpu->funcs->create_vm(gpu, pdev); 1064 if (IS_ERR(gpu->vm)) { 1065 ret = PTR_ERR(gpu->vm); 1066 goto fail; 1067 } 1068 1069 memptrs = msm_gem_kernel_new(drm, 1070 sizeof(struct msm_rbmemptrs) * nr_rings, 1071 check_apriv(gpu, MSM_BO_WC), gpu->vm, &gpu->memptrs_bo, 1072 &memptrs_iova); 1073 1074 if (IS_ERR(memptrs)) { 1075 ret = PTR_ERR(memptrs); 1076 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret); 1077 goto fail; 1078 } 1079 1080 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs"); 1081 1082 if (nr_rings > ARRAY_SIZE(gpu->rb)) { 1083 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", 1084 ARRAY_SIZE(gpu->rb)); 1085 nr_rings = ARRAY_SIZE(gpu->rb); 1086 } 1087 1088 /* Create ringbuffer(s): */ 1089 for (i = 0; i < nr_rings; i++) { 1090 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); 1091 1092 if (IS_ERR(gpu->rb[i])) { 1093 ret = PTR_ERR(gpu->rb[i]); 1094 DRM_DEV_ERROR(drm->dev, 1095 "could not create ringbuffer %d: %d\n", i, ret); 1096 goto fail; 1097 } 1098 1099 memptrs += sizeof(struct msm_rbmemptrs); 1100 memptrs_iova += sizeof(struct msm_rbmemptrs); 1101 } 1102 1103 gpu->nr_rings = nr_rings; 1104 1105 refcount_set(&gpu->sysprof_active, 1); 1106 1107 return 0; 1108 1109 fail: 1110 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 1111 msm_ringbuffer_destroy(gpu->rb[i]); 1112 gpu->rb[i] = NULL; 1113 } 1114 1115 msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm); 1116 1117 platform_set_drvdata(pdev, NULL); 1118 return ret; 1119 } 1120 1121 void msm_gpu_cleanup(struct msm_gpu *gpu) 1122 { 1123 int i; 1124 1125 DBG("%s", gpu->name); 1126 1127 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 1128 msm_ringbuffer_destroy(gpu->rb[i]); 1129 gpu->rb[i] = NULL; 1130 } 1131 1132 msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm); 1133 1134 if (!IS_ERR_OR_NULL(gpu->vm)) { 1135 struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu; 1136 mmu->funcs->detach(mmu); 1137 drm_gpuvm_put(gpu->vm); 1138 } 1139 1140 if (gpu->worker) { 1141 kthread_destroy_worker(gpu->worker); 1142 } 1143 1144 msm_devfreq_cleanup(gpu); 1145 1146 platform_set_drvdata(gpu->pdev, NULL); 1147 } 1148