1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include "drm/drm_drv.h" 8 9 #include "msm_gpu.h" 10 #include "msm_gem.h" 11 #include "msm_mmu.h" 12 #include "msm_fence.h" 13 #include "msm_gpu_trace.h" 14 //#include "adreno/adreno_gpu.h" 15 16 #include <generated/utsrelease.h> 17 #include <linux/string_helpers.h> 18 #include <linux/devcoredump.h> 19 #include <linux/sched/task.h> 20 21 /* 22 * Power Management: 23 */ 24 25 static int enable_pwrrail(struct msm_gpu *gpu) 26 { 27 struct drm_device *dev = gpu->dev; 28 int ret = 0; 29 30 if (gpu->gpu_reg) { 31 ret = regulator_enable(gpu->gpu_reg); 32 if (ret) { 33 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); 34 return ret; 35 } 36 } 37 38 if (gpu->gpu_cx) { 39 ret = regulator_enable(gpu->gpu_cx); 40 if (ret) { 41 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); 42 return ret; 43 } 44 } 45 46 return 0; 47 } 48 49 static int disable_pwrrail(struct msm_gpu *gpu) 50 { 51 if (gpu->gpu_cx) 52 regulator_disable(gpu->gpu_cx); 53 if (gpu->gpu_reg) 54 regulator_disable(gpu->gpu_reg); 55 return 0; 56 } 57 58 static int enable_clk(struct msm_gpu *gpu) 59 { 60 if (gpu->core_clk && gpu->fast_rate) 61 dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); 62 63 /* Set the RBBM timer rate to 19.2Mhz */ 64 if (gpu->rbbmtimer_clk) 65 clk_set_rate(gpu->rbbmtimer_clk, 19200000); 66 67 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 68 } 69 70 static int disable_clk(struct msm_gpu *gpu) 71 { 72 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 73 74 /* 75 * Set the clock to a deliberately low rate. On older targets the clock 76 * speed had to be non zero to avoid problems. On newer targets this 77 * will be rounded down to zero anyway so it all works out. 78 */ 79 if (gpu->core_clk) 80 dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); 81 82 if (gpu->rbbmtimer_clk) 83 clk_set_rate(gpu->rbbmtimer_clk, 0); 84 85 return 0; 86 } 87 88 static int enable_axi(struct msm_gpu *gpu) 89 { 90 return clk_prepare_enable(gpu->ebi1_clk); 91 } 92 93 static int disable_axi(struct msm_gpu *gpu) 94 { 95 clk_disable_unprepare(gpu->ebi1_clk); 96 return 0; 97 } 98 99 int msm_gpu_pm_resume(struct msm_gpu *gpu) 100 { 101 int ret; 102 103 DBG("%s", gpu->name); 104 trace_msm_gpu_resume(0); 105 106 ret = enable_pwrrail(gpu); 107 if (ret) 108 return ret; 109 110 ret = enable_clk(gpu); 111 if (ret) 112 return ret; 113 114 ret = enable_axi(gpu); 115 if (ret) 116 return ret; 117 118 msm_devfreq_resume(gpu); 119 120 gpu->needs_hw_init = true; 121 122 return 0; 123 } 124 125 int msm_gpu_pm_suspend(struct msm_gpu *gpu) 126 { 127 int ret; 128 129 DBG("%s", gpu->name); 130 trace_msm_gpu_suspend(0); 131 132 msm_devfreq_suspend(gpu); 133 134 ret = disable_axi(gpu); 135 if (ret) 136 return ret; 137 138 ret = disable_clk(gpu); 139 if (ret) 140 return ret; 141 142 ret = disable_pwrrail(gpu); 143 if (ret) 144 return ret; 145 146 gpu->suspend_count++; 147 148 return 0; 149 } 150 151 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_file_private *ctx, 152 struct drm_printer *p) 153 { 154 drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns); 155 drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles); 156 drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate); 157 } 158 159 int msm_gpu_hw_init(struct msm_gpu *gpu) 160 { 161 int ret; 162 163 WARN_ON(!mutex_is_locked(&gpu->lock)); 164 165 if (!gpu->needs_hw_init) 166 return 0; 167 168 disable_irq(gpu->irq); 169 ret = gpu->funcs->hw_init(gpu); 170 if (!ret) 171 gpu->needs_hw_init = false; 172 enable_irq(gpu->irq); 173 174 return ret; 175 } 176 177 #ifdef CONFIG_DEV_COREDUMP 178 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, 179 size_t count, void *data, size_t datalen) 180 { 181 struct msm_gpu *gpu = data; 182 struct drm_print_iterator iter; 183 struct drm_printer p; 184 struct msm_gpu_state *state; 185 186 state = msm_gpu_crashstate_get(gpu); 187 if (!state) 188 return 0; 189 190 iter.data = buffer; 191 iter.offset = 0; 192 iter.start = offset; 193 iter.remain = count; 194 195 p = drm_coredump_printer(&iter); 196 197 drm_printf(&p, "---\n"); 198 drm_printf(&p, "kernel: " UTS_RELEASE "\n"); 199 drm_printf(&p, "module: " KBUILD_MODNAME "\n"); 200 drm_printf(&p, "time: %lld.%09ld\n", 201 state->time.tv_sec, state->time.tv_nsec); 202 if (state->comm) 203 drm_printf(&p, "comm: %s\n", state->comm); 204 if (state->cmd) 205 drm_printf(&p, "cmdline: %s\n", state->cmd); 206 207 gpu->funcs->show(gpu, state, &p); 208 209 msm_gpu_crashstate_put(gpu); 210 211 return count - iter.remain; 212 } 213 214 static void msm_gpu_devcoredump_free(void *data) 215 { 216 struct msm_gpu *gpu = data; 217 218 msm_gpu_crashstate_put(gpu); 219 } 220 221 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, 222 struct drm_gem_object *obj, u64 iova, bool full) 223 { 224 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; 225 struct msm_gem_object *msm_obj = to_msm_bo(obj); 226 227 /* Don't record write only objects */ 228 state_bo->size = obj->size; 229 state_bo->flags = msm_obj->flags; 230 state_bo->iova = iova; 231 232 BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(msm_obj->name)); 233 234 memcpy(state_bo->name, msm_obj->name, sizeof(state_bo->name)); 235 236 if (full) { 237 void *ptr; 238 239 state_bo->data = kvmalloc(obj->size, GFP_KERNEL); 240 if (!state_bo->data) 241 goto out; 242 243 msm_gem_lock(obj); 244 ptr = msm_gem_get_vaddr_active(obj); 245 msm_gem_unlock(obj); 246 if (IS_ERR(ptr)) { 247 kvfree(state_bo->data); 248 state_bo->data = NULL; 249 goto out; 250 } 251 252 memcpy(state_bo->data, ptr, obj->size); 253 msm_gem_put_vaddr(obj); 254 } 255 out: 256 state->nr_bos++; 257 } 258 259 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 260 struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info, 261 char *comm, char *cmd) 262 { 263 struct msm_gpu_state *state; 264 265 /* Check if the target supports capturing crash state */ 266 if (!gpu->funcs->gpu_state_get) 267 return; 268 269 /* Only save one crash state at a time */ 270 if (gpu->crashstate) 271 return; 272 273 state = gpu->funcs->gpu_state_get(gpu); 274 if (IS_ERR_OR_NULL(state)) 275 return; 276 277 /* Fill in the additional crash state information */ 278 state->comm = kstrdup(comm, GFP_KERNEL); 279 state->cmd = kstrdup(cmd, GFP_KERNEL); 280 if (fault_info) 281 state->fault_info = *fault_info; 282 283 if (submit) { 284 int i; 285 286 if (state->fault_info.ttbr0) { 287 struct msm_gpu_fault_info *info = &state->fault_info; 288 struct msm_mmu *mmu = submit->aspace->mmu; 289 290 msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0, 291 &info->asid); 292 msm_iommu_pagetable_walk(mmu, info->iova, info->ptes); 293 } 294 295 state->bos = kcalloc(submit->nr_bos, 296 sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 297 298 for (i = 0; state->bos && i < submit->nr_bos; i++) { 299 msm_gpu_crashstate_get_bo(state, submit->bos[i].obj, 300 submit->bos[i].iova, 301 should_dump(submit, i)); 302 } 303 } 304 305 /* Set the active crash state to be dumped on failure */ 306 gpu->crashstate = state; 307 308 dev_coredumpm(&gpu->pdev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, 309 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free); 310 } 311 #else 312 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 313 struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info, 314 char *comm, char *cmd) 315 { 316 } 317 #endif 318 319 /* 320 * Hangcheck detection for locked gpu: 321 */ 322 323 static struct msm_gem_submit * 324 find_submit(struct msm_ringbuffer *ring, uint32_t fence) 325 { 326 struct msm_gem_submit *submit; 327 unsigned long flags; 328 329 spin_lock_irqsave(&ring->submit_lock, flags); 330 list_for_each_entry(submit, &ring->submits, node) { 331 if (submit->seqno == fence) { 332 spin_unlock_irqrestore(&ring->submit_lock, flags); 333 return submit; 334 } 335 } 336 spin_unlock_irqrestore(&ring->submit_lock, flags); 337 338 return NULL; 339 } 340 341 static void retire_submits(struct msm_gpu *gpu); 342 343 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd) 344 { 345 struct msm_file_private *ctx = submit->queue->ctx; 346 struct task_struct *task; 347 348 WARN_ON(!mutex_is_locked(&submit->gpu->lock)); 349 350 /* Note that kstrdup will return NULL if argument is NULL: */ 351 *comm = kstrdup(ctx->comm, GFP_KERNEL); 352 *cmd = kstrdup(ctx->cmdline, GFP_KERNEL); 353 354 task = get_pid_task(submit->pid, PIDTYPE_PID); 355 if (!task) 356 return; 357 358 if (!*comm) 359 *comm = kstrdup(task->comm, GFP_KERNEL); 360 361 if (!*cmd) 362 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 363 364 put_task_struct(task); 365 } 366 367 static void recover_worker(struct kthread_work *work) 368 { 369 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); 370 struct drm_device *dev = gpu->dev; 371 struct msm_drm_private *priv = dev->dev_private; 372 struct msm_gem_submit *submit; 373 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 374 char *comm = NULL, *cmd = NULL; 375 int i; 376 377 mutex_lock(&gpu->lock); 378 379 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name); 380 381 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 382 383 /* 384 * If the submit retired while we were waiting for the worker to run, 385 * or waiting to acquire the gpu lock, then nothing more to do. 386 */ 387 if (!submit) 388 goto out_unlock; 389 390 /* Increment the fault counts */ 391 submit->queue->faults++; 392 if (submit->aspace) 393 submit->aspace->faults++; 394 395 get_comm_cmdline(submit, &comm, &cmd); 396 397 if (comm && cmd) { 398 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n", 399 gpu->name, comm, cmd); 400 401 msm_rd_dump_submit(priv->hangrd, submit, 402 "offending task: %s (%s)", comm, cmd); 403 } else { 404 DRM_DEV_ERROR(dev->dev, "%s: offending task: unknown\n", gpu->name); 405 406 msm_rd_dump_submit(priv->hangrd, submit, NULL); 407 } 408 409 /* Record the crash state */ 410 pm_runtime_get_sync(&gpu->pdev->dev); 411 msm_gpu_crashstate_capture(gpu, submit, NULL, comm, cmd); 412 413 kfree(cmd); 414 kfree(comm); 415 416 /* 417 * Update all the rings with the latest and greatest fence.. this 418 * needs to happen after msm_rd_dump_submit() to ensure that the 419 * bo's referenced by the offending submit are still around. 420 */ 421 for (i = 0; i < gpu->nr_rings; i++) { 422 struct msm_ringbuffer *ring = gpu->rb[i]; 423 424 uint32_t fence = ring->memptrs->fence; 425 426 /* 427 * For the current (faulting?) ring/submit advance the fence by 428 * one more to clear the faulting submit 429 */ 430 if (ring == cur_ring) 431 ring->memptrs->fence = ++fence; 432 433 msm_update_fence(ring->fctx, fence); 434 } 435 436 if (msm_gpu_active(gpu)) { 437 /* retire completed submits, plus the one that hung: */ 438 retire_submits(gpu); 439 440 gpu->funcs->recover(gpu); 441 442 /* 443 * Replay all remaining submits starting with highest priority 444 * ring 445 */ 446 for (i = 0; i < gpu->nr_rings; i++) { 447 struct msm_ringbuffer *ring = gpu->rb[i]; 448 unsigned long flags; 449 450 spin_lock_irqsave(&ring->submit_lock, flags); 451 list_for_each_entry(submit, &ring->submits, node) 452 gpu->funcs->submit(gpu, submit); 453 spin_unlock_irqrestore(&ring->submit_lock, flags); 454 } 455 } 456 457 pm_runtime_put(&gpu->pdev->dev); 458 459 out_unlock: 460 mutex_unlock(&gpu->lock); 461 462 msm_gpu_retire(gpu); 463 } 464 465 void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info) 466 { 467 struct msm_gem_submit *submit; 468 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 469 char *comm = NULL, *cmd = NULL; 470 471 mutex_lock(&gpu->lock); 472 473 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 474 if (submit && submit->fault_dumped) 475 goto resume_smmu; 476 477 if (submit) { 478 get_comm_cmdline(submit, &comm, &cmd); 479 480 /* 481 * When we get GPU iova faults, we can get 1000s of them, 482 * but we really only want to log the first one. 483 */ 484 submit->fault_dumped = true; 485 } 486 487 /* Record the crash state */ 488 pm_runtime_get_sync(&gpu->pdev->dev); 489 msm_gpu_crashstate_capture(gpu, submit, fault_info, comm, cmd); 490 pm_runtime_put_sync(&gpu->pdev->dev); 491 492 kfree(cmd); 493 kfree(comm); 494 495 resume_smmu: 496 mutex_unlock(&gpu->lock); 497 } 498 499 static void hangcheck_timer_reset(struct msm_gpu *gpu) 500 { 501 struct msm_drm_private *priv = gpu->dev->dev_private; 502 mod_timer(&gpu->hangcheck_timer, 503 round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period))); 504 } 505 506 static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 507 { 508 if (ring->hangcheck_progress_retries >= DRM_MSM_HANGCHECK_PROGRESS_RETRIES) 509 return false; 510 511 if (!gpu->funcs->progress) 512 return false; 513 514 if (!gpu->funcs->progress(gpu, ring)) 515 return false; 516 517 ring->hangcheck_progress_retries++; 518 return true; 519 } 520 521 static void hangcheck_handler(struct timer_list *t) 522 { 523 struct msm_gpu *gpu = timer_container_of(gpu, t, hangcheck_timer); 524 struct drm_device *dev = gpu->dev; 525 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 526 uint32_t fence = ring->memptrs->fence; 527 528 if (fence != ring->hangcheck_fence) { 529 /* some progress has been made.. ya! */ 530 ring->hangcheck_fence = fence; 531 ring->hangcheck_progress_retries = 0; 532 } else if (fence_before(fence, ring->fctx->last_fence) && 533 !made_progress(gpu, ring)) { 534 /* no progress and not done.. hung! */ 535 ring->hangcheck_fence = fence; 536 ring->hangcheck_progress_retries = 0; 537 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", 538 gpu->name, ring->id); 539 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n", 540 gpu->name, fence); 541 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n", 542 gpu->name, ring->fctx->last_fence); 543 544 kthread_queue_work(gpu->worker, &gpu->recover_work); 545 } 546 547 /* if still more pending work, reset the hangcheck timer: */ 548 if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence)) 549 hangcheck_timer_reset(gpu); 550 551 /* workaround for missing irq: */ 552 msm_gpu_retire(gpu); 553 } 554 555 /* 556 * Performance Counters: 557 */ 558 559 /* called under perf_lock */ 560 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) 561 { 562 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; 563 int i, n = min(ncntrs, gpu->num_perfcntrs); 564 565 /* read current values: */ 566 for (i = 0; i < gpu->num_perfcntrs; i++) 567 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); 568 569 /* update cntrs: */ 570 for (i = 0; i < n; i++) 571 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; 572 573 /* save current values: */ 574 for (i = 0; i < gpu->num_perfcntrs; i++) 575 gpu->last_cntrs[i] = current_cntrs[i]; 576 577 return n; 578 } 579 580 static void update_sw_cntrs(struct msm_gpu *gpu) 581 { 582 ktime_t time; 583 uint32_t elapsed; 584 unsigned long flags; 585 586 spin_lock_irqsave(&gpu->perf_lock, flags); 587 if (!gpu->perfcntr_active) 588 goto out; 589 590 time = ktime_get(); 591 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); 592 593 gpu->totaltime += elapsed; 594 if (gpu->last_sample.active) 595 gpu->activetime += elapsed; 596 597 gpu->last_sample.active = msm_gpu_active(gpu); 598 gpu->last_sample.time = time; 599 600 out: 601 spin_unlock_irqrestore(&gpu->perf_lock, flags); 602 } 603 604 void msm_gpu_perfcntr_start(struct msm_gpu *gpu) 605 { 606 unsigned long flags; 607 608 pm_runtime_get_sync(&gpu->pdev->dev); 609 610 spin_lock_irqsave(&gpu->perf_lock, flags); 611 /* we could dynamically enable/disable perfcntr registers too.. */ 612 gpu->last_sample.active = msm_gpu_active(gpu); 613 gpu->last_sample.time = ktime_get(); 614 gpu->activetime = gpu->totaltime = 0; 615 gpu->perfcntr_active = true; 616 update_hw_cntrs(gpu, 0, NULL); 617 spin_unlock_irqrestore(&gpu->perf_lock, flags); 618 } 619 620 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) 621 { 622 gpu->perfcntr_active = false; 623 pm_runtime_put_sync(&gpu->pdev->dev); 624 } 625 626 /* returns -errno or # of cntrs sampled */ 627 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 628 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) 629 { 630 unsigned long flags; 631 int ret; 632 633 spin_lock_irqsave(&gpu->perf_lock, flags); 634 635 if (!gpu->perfcntr_active) { 636 ret = -EINVAL; 637 goto out; 638 } 639 640 *activetime = gpu->activetime; 641 *totaltime = gpu->totaltime; 642 643 gpu->activetime = gpu->totaltime = 0; 644 645 ret = update_hw_cntrs(gpu, ncntrs, cntrs); 646 647 out: 648 spin_unlock_irqrestore(&gpu->perf_lock, flags); 649 650 return ret; 651 } 652 653 /* 654 * Cmdstream submission/retirement: 655 */ 656 657 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 658 struct msm_gem_submit *submit) 659 { 660 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 661 volatile struct msm_gpu_submit_stats *stats; 662 u64 elapsed, clock = 0, cycles; 663 unsigned long flags; 664 665 stats = &ring->memptrs->stats[index]; 666 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */ 667 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000; 668 do_div(elapsed, 192); 669 670 cycles = stats->cpcycles_end - stats->cpcycles_start; 671 672 /* Calculate the clock frequency from the number of CP cycles */ 673 if (elapsed) { 674 clock = cycles * 1000; 675 do_div(clock, elapsed); 676 } 677 678 submit->queue->ctx->elapsed_ns += elapsed; 679 submit->queue->ctx->cycles += cycles; 680 681 trace_msm_gpu_submit_retired(submit, elapsed, clock, 682 stats->alwayson_start, stats->alwayson_end); 683 684 msm_submit_retire(submit); 685 686 pm_runtime_mark_last_busy(&gpu->pdev->dev); 687 688 spin_lock_irqsave(&ring->submit_lock, flags); 689 list_del(&submit->node); 690 spin_unlock_irqrestore(&ring->submit_lock, flags); 691 692 /* Update devfreq on transition from active->idle: */ 693 mutex_lock(&gpu->active_lock); 694 gpu->active_submits--; 695 WARN_ON(gpu->active_submits < 0); 696 if (!gpu->active_submits) { 697 msm_devfreq_idle(gpu); 698 pm_runtime_put_autosuspend(&gpu->pdev->dev); 699 } 700 701 mutex_unlock(&gpu->active_lock); 702 703 msm_gem_submit_put(submit); 704 } 705 706 static void retire_submits(struct msm_gpu *gpu) 707 { 708 int i; 709 710 /* Retire the commits starting with highest priority */ 711 for (i = 0; i < gpu->nr_rings; i++) { 712 struct msm_ringbuffer *ring = gpu->rb[i]; 713 714 while (true) { 715 struct msm_gem_submit *submit = NULL; 716 unsigned long flags; 717 718 spin_lock_irqsave(&ring->submit_lock, flags); 719 submit = list_first_entry_or_null(&ring->submits, 720 struct msm_gem_submit, node); 721 spin_unlock_irqrestore(&ring->submit_lock, flags); 722 723 /* 724 * If no submit, we are done. If submit->fence hasn't 725 * been signalled, then later submits are not signalled 726 * either, so we are also done. 727 */ 728 if (submit && dma_fence_is_signaled(submit->hw_fence)) { 729 retire_submit(gpu, ring, submit); 730 } else { 731 break; 732 } 733 } 734 } 735 736 wake_up_all(&gpu->retire_event); 737 } 738 739 static void retire_worker(struct kthread_work *work) 740 { 741 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); 742 743 retire_submits(gpu); 744 } 745 746 /* call from irq handler to schedule work to retire bo's */ 747 void msm_gpu_retire(struct msm_gpu *gpu) 748 { 749 int i; 750 751 for (i = 0; i < gpu->nr_rings; i++) 752 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence); 753 754 kthread_queue_work(gpu->worker, &gpu->retire_work); 755 update_sw_cntrs(gpu); 756 } 757 758 /* add bo's to gpu's ring, and kick gpu: */ 759 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 760 { 761 struct msm_ringbuffer *ring = submit->ring; 762 unsigned long flags; 763 764 WARN_ON(!mutex_is_locked(&gpu->lock)); 765 766 pm_runtime_get_sync(&gpu->pdev->dev); 767 768 msm_gpu_hw_init(gpu); 769 770 submit->seqno = submit->hw_fence->seqno; 771 772 update_sw_cntrs(gpu); 773 774 /* 775 * ring->submits holds a ref to the submit, to deal with the case 776 * that a submit completes before msm_ioctl_gem_submit() returns. 777 */ 778 msm_gem_submit_get(submit); 779 780 spin_lock_irqsave(&ring->submit_lock, flags); 781 list_add_tail(&submit->node, &ring->submits); 782 spin_unlock_irqrestore(&ring->submit_lock, flags); 783 784 /* Update devfreq on transition from idle->active: */ 785 mutex_lock(&gpu->active_lock); 786 if (!gpu->active_submits) { 787 pm_runtime_get(&gpu->pdev->dev); 788 msm_devfreq_active(gpu); 789 } 790 gpu->active_submits++; 791 mutex_unlock(&gpu->active_lock); 792 793 gpu->funcs->submit(gpu, submit); 794 submit->ring->cur_ctx_seqno = submit->queue->ctx->seqno; 795 796 pm_runtime_put(&gpu->pdev->dev); 797 hangcheck_timer_reset(gpu); 798 } 799 800 /* 801 * Init/Cleanup: 802 */ 803 804 static irqreturn_t irq_handler(int irq, void *data) 805 { 806 struct msm_gpu *gpu = data; 807 return gpu->funcs->irq(gpu); 808 } 809 810 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) 811 { 812 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks); 813 814 if (ret < 1) { 815 gpu->nr_clocks = 0; 816 return ret; 817 } 818 819 gpu->nr_clocks = ret; 820 821 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 822 gpu->nr_clocks, "core"); 823 824 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 825 gpu->nr_clocks, "rbbmtimer"); 826 827 return 0; 828 } 829 830 /* Return a new address space for a msm_drm_private instance */ 831 struct msm_gem_address_space * 832 msm_gpu_create_private_address_space(struct msm_gpu *gpu, struct task_struct *task) 833 { 834 struct msm_gem_address_space *aspace = NULL; 835 if (!gpu) 836 return NULL; 837 838 /* 839 * If the target doesn't support private address spaces then return 840 * the global one 841 */ 842 if (gpu->funcs->create_private_address_space) { 843 aspace = gpu->funcs->create_private_address_space(gpu); 844 if (!IS_ERR(aspace)) 845 aspace->pid = get_pid(task_pid(task)); 846 } 847 848 if (IS_ERR_OR_NULL(aspace)) 849 aspace = msm_gem_address_space_get(gpu->aspace); 850 851 return aspace; 852 } 853 854 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 855 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 856 const char *name, struct msm_gpu_config *config) 857 { 858 struct msm_drm_private *priv = drm->dev_private; 859 int i, ret, nr_rings = config->nr_rings; 860 void *memptrs; 861 uint64_t memptrs_iova; 862 863 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) 864 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); 865 866 gpu->dev = drm; 867 gpu->funcs = funcs; 868 gpu->name = name; 869 870 gpu->worker = kthread_run_worker(0, "gpu-worker"); 871 if (IS_ERR(gpu->worker)) { 872 ret = PTR_ERR(gpu->worker); 873 gpu->worker = NULL; 874 goto fail; 875 } 876 877 sched_set_fifo_low(gpu->worker->task); 878 879 mutex_init(&gpu->active_lock); 880 mutex_init(&gpu->lock); 881 init_waitqueue_head(&gpu->retire_event); 882 kthread_init_work(&gpu->retire_work, retire_worker); 883 kthread_init_work(&gpu->recover_work, recover_worker); 884 885 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; 886 887 /* 888 * If progress detection is supported, halve the hangcheck timer 889 * duration, as it takes two iterations of the hangcheck handler 890 * to detect a hang. 891 */ 892 if (funcs->progress) 893 priv->hangcheck_period /= 2; 894 895 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); 896 897 spin_lock_init(&gpu->perf_lock); 898 899 900 /* Map registers: */ 901 gpu->mmio = msm_ioremap(pdev, config->ioname); 902 if (IS_ERR(gpu->mmio)) { 903 ret = PTR_ERR(gpu->mmio); 904 goto fail; 905 } 906 907 /* Get Interrupt: */ 908 gpu->irq = platform_get_irq(pdev, 0); 909 if (gpu->irq < 0) { 910 ret = gpu->irq; 911 goto fail; 912 } 913 914 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 915 IRQF_TRIGGER_HIGH, "gpu-irq", gpu); 916 if (ret) { 917 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); 918 goto fail; 919 } 920 921 ret = get_clocks(pdev, gpu); 922 if (ret) 923 goto fail; 924 925 gpu->ebi1_clk = msm_clk_get(pdev, "bus"); 926 DBG("ebi1_clk: %p", gpu->ebi1_clk); 927 if (IS_ERR(gpu->ebi1_clk)) 928 gpu->ebi1_clk = NULL; 929 930 /* Acquire regulators: */ 931 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); 932 DBG("gpu_reg: %p", gpu->gpu_reg); 933 if (IS_ERR(gpu->gpu_reg)) 934 gpu->gpu_reg = NULL; 935 936 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); 937 DBG("gpu_cx: %p", gpu->gpu_cx); 938 if (IS_ERR(gpu->gpu_cx)) 939 gpu->gpu_cx = NULL; 940 941 platform_set_drvdata(pdev, &gpu->adreno_smmu); 942 943 msm_devfreq_init(gpu); 944 945 946 gpu->aspace = gpu->funcs->create_address_space(gpu, pdev); 947 948 if (gpu->aspace == NULL) 949 DRM_DEV_INFO(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name); 950 else if (IS_ERR(gpu->aspace)) { 951 ret = PTR_ERR(gpu->aspace); 952 goto fail; 953 } 954 955 memptrs = msm_gem_kernel_new(drm, 956 sizeof(struct msm_rbmemptrs) * nr_rings, 957 check_apriv(gpu, MSM_BO_WC), gpu->aspace, &gpu->memptrs_bo, 958 &memptrs_iova); 959 960 if (IS_ERR(memptrs)) { 961 ret = PTR_ERR(memptrs); 962 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret); 963 goto fail; 964 } 965 966 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs"); 967 968 if (nr_rings > ARRAY_SIZE(gpu->rb)) { 969 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", 970 ARRAY_SIZE(gpu->rb)); 971 nr_rings = ARRAY_SIZE(gpu->rb); 972 } 973 974 /* Create ringbuffer(s): */ 975 for (i = 0; i < nr_rings; i++) { 976 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); 977 978 if (IS_ERR(gpu->rb[i])) { 979 ret = PTR_ERR(gpu->rb[i]); 980 DRM_DEV_ERROR(drm->dev, 981 "could not create ringbuffer %d: %d\n", i, ret); 982 goto fail; 983 } 984 985 memptrs += sizeof(struct msm_rbmemptrs); 986 memptrs_iova += sizeof(struct msm_rbmemptrs); 987 } 988 989 gpu->nr_rings = nr_rings; 990 991 refcount_set(&gpu->sysprof_active, 1); 992 993 return 0; 994 995 fail: 996 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 997 msm_ringbuffer_destroy(gpu->rb[i]); 998 gpu->rb[i] = NULL; 999 } 1000 1001 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace); 1002 1003 platform_set_drvdata(pdev, NULL); 1004 return ret; 1005 } 1006 1007 void msm_gpu_cleanup(struct msm_gpu *gpu) 1008 { 1009 int i; 1010 1011 DBG("%s", gpu->name); 1012 1013 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 1014 msm_ringbuffer_destroy(gpu->rb[i]); 1015 gpu->rb[i] = NULL; 1016 } 1017 1018 msm_gem_kernel_put(gpu->memptrs_bo, gpu->aspace); 1019 1020 if (!IS_ERR_OR_NULL(gpu->aspace)) { 1021 gpu->aspace->mmu->funcs->detach(gpu->aspace->mmu); 1022 msm_gem_address_space_put(gpu->aspace); 1023 } 1024 1025 if (gpu->worker) { 1026 kthread_destroy_worker(gpu->worker); 1027 } 1028 1029 msm_devfreq_cleanup(gpu); 1030 1031 platform_set_drvdata(gpu->pdev, NULL); 1032 } 1033