1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include "drm/drm_drv.h" 8 9 #include "msm_gpu.h" 10 #include "msm_gem.h" 11 #include "msm_mmu.h" 12 #include "msm_fence.h" 13 #include "msm_gpu_trace.h" 14 //#include "adreno/adreno_gpu.h" 15 16 #include <generated/utsrelease.h> 17 #include <linux/string_helpers.h> 18 #include <linux/devcoredump.h> 19 #include <linux/sched/task.h> 20 21 /* 22 * Power Management: 23 */ 24 25 static int enable_pwrrail(struct msm_gpu *gpu) 26 { 27 struct drm_device *dev = gpu->dev; 28 int ret = 0; 29 30 if (gpu->gpu_reg) { 31 ret = regulator_enable(gpu->gpu_reg); 32 if (ret) { 33 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_reg': %d\n", ret); 34 return ret; 35 } 36 } 37 38 if (gpu->gpu_cx) { 39 ret = regulator_enable(gpu->gpu_cx); 40 if (ret) { 41 DRM_DEV_ERROR(dev->dev, "failed to enable 'gpu_cx': %d\n", ret); 42 return ret; 43 } 44 } 45 46 return 0; 47 } 48 49 static int disable_pwrrail(struct msm_gpu *gpu) 50 { 51 if (gpu->gpu_cx) 52 regulator_disable(gpu->gpu_cx); 53 if (gpu->gpu_reg) 54 regulator_disable(gpu->gpu_reg); 55 return 0; 56 } 57 58 static int enable_clk(struct msm_gpu *gpu) 59 { 60 if (gpu->core_clk && gpu->fast_rate) 61 dev_pm_opp_set_rate(&gpu->pdev->dev, gpu->fast_rate); 62 63 /* Set the RBBM timer rate to 19.2Mhz */ 64 if (gpu->rbbmtimer_clk) 65 clk_set_rate(gpu->rbbmtimer_clk, 19200000); 66 67 return clk_bulk_prepare_enable(gpu->nr_clocks, gpu->grp_clks); 68 } 69 70 static int disable_clk(struct msm_gpu *gpu) 71 { 72 clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks); 73 74 /* 75 * Set the clock to a deliberately low rate. On older targets the clock 76 * speed had to be non zero to avoid problems. On newer targets this 77 * will be rounded down to zero anyway so it all works out. 78 */ 79 if (gpu->core_clk) 80 dev_pm_opp_set_rate(&gpu->pdev->dev, 27000000); 81 82 if (gpu->rbbmtimer_clk) 83 clk_set_rate(gpu->rbbmtimer_clk, 0); 84 85 return 0; 86 } 87 88 static int enable_axi(struct msm_gpu *gpu) 89 { 90 return clk_prepare_enable(gpu->ebi1_clk); 91 } 92 93 static int disable_axi(struct msm_gpu *gpu) 94 { 95 clk_disable_unprepare(gpu->ebi1_clk); 96 return 0; 97 } 98 99 int msm_gpu_pm_resume(struct msm_gpu *gpu) 100 { 101 int ret; 102 103 DBG("%s", gpu->name); 104 trace_msm_gpu_resume(0); 105 106 ret = enable_pwrrail(gpu); 107 if (ret) 108 return ret; 109 110 ret = enable_clk(gpu); 111 if (ret) 112 return ret; 113 114 ret = enable_axi(gpu); 115 if (ret) 116 return ret; 117 118 msm_devfreq_resume(gpu); 119 120 gpu->needs_hw_init = true; 121 122 return 0; 123 } 124 125 int msm_gpu_pm_suspend(struct msm_gpu *gpu) 126 { 127 int ret; 128 129 DBG("%s", gpu->name); 130 trace_msm_gpu_suspend(0); 131 132 msm_devfreq_suspend(gpu); 133 134 ret = disable_axi(gpu); 135 if (ret) 136 return ret; 137 138 ret = disable_clk(gpu); 139 if (ret) 140 return ret; 141 142 ret = disable_pwrrail(gpu); 143 if (ret) 144 return ret; 145 146 gpu->suspend_count++; 147 148 return 0; 149 } 150 151 void msm_gpu_show_fdinfo(struct msm_gpu *gpu, struct msm_context *ctx, 152 struct drm_printer *p) 153 { 154 drm_printf(p, "drm-engine-gpu:\t%llu ns\n", ctx->elapsed_ns); 155 drm_printf(p, "drm-cycles-gpu:\t%llu\n", ctx->cycles); 156 drm_printf(p, "drm-maxfreq-gpu:\t%u Hz\n", gpu->fast_rate); 157 } 158 159 int msm_gpu_hw_init(struct msm_gpu *gpu) 160 { 161 int ret; 162 163 WARN_ON(!mutex_is_locked(&gpu->lock)); 164 165 if (!gpu->needs_hw_init) 166 return 0; 167 168 disable_irq(gpu->irq); 169 ret = gpu->funcs->hw_init(gpu); 170 if (!ret) 171 gpu->needs_hw_init = false; 172 enable_irq(gpu->irq); 173 174 return ret; 175 } 176 177 #ifdef CONFIG_DEV_COREDUMP 178 static ssize_t msm_gpu_devcoredump_read(char *buffer, loff_t offset, 179 size_t count, void *data, size_t datalen) 180 { 181 struct msm_gpu *gpu = data; 182 struct drm_print_iterator iter; 183 struct drm_printer p; 184 struct msm_gpu_state *state; 185 186 state = msm_gpu_crashstate_get(gpu); 187 if (!state) 188 return 0; 189 190 iter.data = buffer; 191 iter.offset = 0; 192 iter.start = offset; 193 iter.remain = count; 194 195 p = drm_coredump_printer(&iter); 196 197 drm_printf(&p, "---\n"); 198 drm_printf(&p, "kernel: " UTS_RELEASE "\n"); 199 drm_printf(&p, "module: " KBUILD_MODNAME "\n"); 200 drm_printf(&p, "time: %lld.%09ld\n", 201 state->time.tv_sec, state->time.tv_nsec); 202 if (state->comm) 203 drm_printf(&p, "comm: %s\n", state->comm); 204 if (state->cmd) 205 drm_printf(&p, "cmdline: %s\n", state->cmd); 206 207 gpu->funcs->show(gpu, state, &p); 208 209 msm_gpu_crashstate_put(gpu); 210 211 return count - iter.remain; 212 } 213 214 static void msm_gpu_devcoredump_free(void *data) 215 { 216 struct msm_gpu *gpu = data; 217 218 msm_gpu_crashstate_put(gpu); 219 } 220 221 static void msm_gpu_crashstate_get_bo(struct msm_gpu_state *state, 222 struct drm_gem_object *obj, u64 iova, 223 bool full, size_t offset, size_t size) 224 { 225 struct msm_gpu_state_bo *state_bo = &state->bos[state->nr_bos]; 226 struct msm_gem_object *msm_obj = to_msm_bo(obj); 227 228 /* Don't record write only objects */ 229 state_bo->size = size; 230 state_bo->flags = msm_obj->flags; 231 state_bo->iova = iova; 232 233 BUILD_BUG_ON(sizeof(state_bo->name) != sizeof(msm_obj->name)); 234 235 memcpy(state_bo->name, msm_obj->name, sizeof(state_bo->name)); 236 237 if (full) { 238 void *ptr; 239 240 state_bo->data = kvmalloc(size, GFP_KERNEL); 241 if (!state_bo->data) 242 goto out; 243 244 ptr = msm_gem_get_vaddr_active(obj); 245 if (IS_ERR(ptr)) { 246 kvfree(state_bo->data); 247 state_bo->data = NULL; 248 goto out; 249 } 250 251 memcpy(state_bo->data, ptr + offset, size); 252 msm_gem_put_vaddr_locked(obj); 253 } 254 out: 255 state->nr_bos++; 256 } 257 258 static void crashstate_get_bos(struct msm_gpu_state *state, struct msm_gem_submit *submit) 259 { 260 extern bool rd_full; 261 262 if (msm_context_is_vmbind(submit->queue->ctx)) { 263 struct drm_exec exec; 264 struct drm_gpuva *vma; 265 unsigned cnt = 0; 266 267 drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0); 268 drm_exec_until_all_locked(&exec) { 269 cnt = 0; 270 271 drm_exec_lock_obj(&exec, drm_gpuvm_resv_obj(submit->vm)); 272 drm_exec_retry_on_contention(&exec); 273 274 drm_gpuvm_for_each_va (vma, submit->vm) { 275 if (!vma->gem.obj) 276 continue; 277 278 cnt++; 279 drm_exec_lock_obj(&exec, vma->gem.obj); 280 drm_exec_retry_on_contention(&exec); 281 } 282 283 } 284 285 drm_gpuvm_for_each_va (vma, submit->vm) 286 cnt++; 287 288 state->bos = kcalloc(cnt, sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 289 290 drm_gpuvm_for_each_va (vma, submit->vm) { 291 bool dump = rd_full || (vma->flags & MSM_VMA_DUMP); 292 293 /* Skip MAP_NULL/PRR VMAs: */ 294 if (!vma->gem.obj) 295 continue; 296 297 msm_gpu_crashstate_get_bo(state, vma->gem.obj, vma->va.addr, 298 dump, vma->gem.offset, vma->va.range); 299 } 300 301 drm_exec_fini(&exec); 302 } else { 303 state->bos = kcalloc(submit->nr_bos, 304 sizeof(struct msm_gpu_state_bo), GFP_KERNEL); 305 306 for (int i = 0; state->bos && i < submit->nr_bos; i++) { 307 struct drm_gem_object *obj = submit->bos[i].obj;; 308 bool dump = rd_full || (submit->bos[i].flags & MSM_SUBMIT_BO_DUMP); 309 310 msm_gem_lock(obj); 311 msm_gpu_crashstate_get_bo(state, obj, submit->bos[i].iova, 312 dump, 0, obj->size); 313 msm_gem_unlock(obj); 314 } 315 } 316 } 317 318 static void crashstate_get_vm_logs(struct msm_gpu_state *state, struct msm_gem_vm *vm) 319 { 320 uint32_t vm_log_len = (1 << vm->log_shift); 321 uint32_t vm_log_mask = vm_log_len - 1; 322 int first; 323 324 /* Bail if no log, or empty log: */ 325 if (!vm->log || !vm->log[0].op) 326 return; 327 328 mutex_lock(&vm->mmu_lock); 329 330 /* 331 * log_idx is the next entry to overwrite, meaning it is the oldest, or 332 * first, entry (other than the special case handled below where the 333 * log hasn't wrapped around yet) 334 */ 335 first = vm->log_idx; 336 337 if (!vm->log[first].op) { 338 /* 339 * If the next log entry has not been written yet, then only 340 * entries 0 to idx-1 are valid (ie. we haven't wrapped around 341 * yet) 342 */ 343 state->nr_vm_logs = MAX(0, first - 1); 344 first = 0; 345 } else { 346 state->nr_vm_logs = vm_log_len; 347 } 348 349 state->vm_logs = kmalloc_array( 350 state->nr_vm_logs, sizeof(vm->log[0]), GFP_KERNEL); 351 for (int i = 0; i < state->nr_vm_logs; i++) { 352 int idx = (i + first) & vm_log_mask; 353 354 state->vm_logs[i] = vm->log[idx]; 355 } 356 357 mutex_unlock(&vm->mmu_lock); 358 } 359 360 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 361 struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info, 362 char *comm, char *cmd) 363 { 364 struct msm_gpu_state *state; 365 366 /* Check if the target supports capturing crash state */ 367 if (!gpu->funcs->gpu_state_get) 368 return; 369 370 /* Only save one crash state at a time */ 371 if (gpu->crashstate) 372 return; 373 374 state = gpu->funcs->gpu_state_get(gpu); 375 if (IS_ERR_OR_NULL(state)) 376 return; 377 378 /* Fill in the additional crash state information */ 379 state->comm = kstrdup(comm, GFP_KERNEL); 380 state->cmd = kstrdup(cmd, GFP_KERNEL); 381 if (fault_info) 382 state->fault_info = *fault_info; 383 384 if (submit && state->fault_info.ttbr0) { 385 struct msm_gpu_fault_info *info = &state->fault_info; 386 struct msm_mmu *mmu = to_msm_vm(submit->vm)->mmu; 387 388 msm_iommu_pagetable_params(mmu, &info->pgtbl_ttbr0, 389 &info->asid); 390 msm_iommu_pagetable_walk(mmu, info->iova, info->ptes); 391 } 392 393 if (submit) { 394 crashstate_get_vm_logs(state, to_msm_vm(submit->vm)); 395 crashstate_get_bos(state, submit); 396 } 397 398 /* Set the active crash state to be dumped on failure */ 399 gpu->crashstate = state; 400 401 dev_coredumpm(&gpu->pdev->dev, THIS_MODULE, gpu, 0, GFP_KERNEL, 402 msm_gpu_devcoredump_read, msm_gpu_devcoredump_free); 403 } 404 #else 405 static void msm_gpu_crashstate_capture(struct msm_gpu *gpu, 406 struct msm_gem_submit *submit, struct msm_gpu_fault_info *fault_info, 407 char *comm, char *cmd) 408 { 409 } 410 #endif 411 412 /* 413 * Hangcheck detection for locked gpu: 414 */ 415 416 static struct msm_gem_submit * 417 find_submit(struct msm_ringbuffer *ring, uint32_t fence) 418 { 419 struct msm_gem_submit *submit; 420 unsigned long flags; 421 422 spin_lock_irqsave(&ring->submit_lock, flags); 423 list_for_each_entry(submit, &ring->submits, node) { 424 if (submit->seqno == fence) { 425 spin_unlock_irqrestore(&ring->submit_lock, flags); 426 return submit; 427 } 428 } 429 spin_unlock_irqrestore(&ring->submit_lock, flags); 430 431 return NULL; 432 } 433 434 static void retire_submits(struct msm_gpu *gpu); 435 436 static void get_comm_cmdline(struct msm_gem_submit *submit, char **comm, char **cmd) 437 { 438 struct msm_context *ctx = submit->queue->ctx; 439 struct task_struct *task; 440 441 WARN_ON(!mutex_is_locked(&submit->gpu->lock)); 442 443 /* Note that kstrdup will return NULL if argument is NULL: */ 444 *comm = kstrdup(ctx->comm, GFP_KERNEL); 445 *cmd = kstrdup(ctx->cmdline, GFP_KERNEL); 446 447 task = get_pid_task(submit->pid, PIDTYPE_PID); 448 if (!task) 449 return; 450 451 if (!*comm) 452 *comm = kstrdup(task->comm, GFP_KERNEL); 453 454 if (!*cmd) 455 *cmd = kstrdup_quotable_cmdline(task, GFP_KERNEL); 456 457 put_task_struct(task); 458 } 459 460 static void recover_worker(struct kthread_work *work) 461 { 462 struct msm_gpu *gpu = container_of(work, struct msm_gpu, recover_work); 463 struct drm_device *dev = gpu->dev; 464 struct msm_drm_private *priv = dev->dev_private; 465 struct msm_gem_submit *submit; 466 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 467 char *comm = NULL, *cmd = NULL; 468 int i; 469 470 mutex_lock(&gpu->lock); 471 472 DRM_DEV_ERROR(dev->dev, "%s: hangcheck recover!\n", gpu->name); 473 474 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 475 476 /* 477 * If the submit retired while we were waiting for the worker to run, 478 * or waiting to acquire the gpu lock, then nothing more to do. 479 */ 480 if (!submit) 481 goto out_unlock; 482 483 /* Increment the fault counts */ 484 submit->queue->faults++; 485 if (submit->vm) { 486 struct msm_gem_vm *vm = to_msm_vm(submit->vm); 487 488 vm->faults++; 489 490 /* 491 * If userspace has opted-in to VM_BIND (and therefore userspace 492 * management of the VM), faults mark the VM as unusuable. This 493 * matches vulkan expectations (vulkan is the main target for 494 * VM_BIND) 495 */ 496 if (!vm->managed) 497 msm_gem_vm_unusable(submit->vm); 498 } 499 500 get_comm_cmdline(submit, &comm, &cmd); 501 502 if (comm && cmd) { 503 DRM_DEV_ERROR(dev->dev, "%s: offending task: %s (%s)\n", 504 gpu->name, comm, cmd); 505 506 msm_rd_dump_submit(priv->hangrd, submit, 507 "offending task: %s (%s)", comm, cmd); 508 } else { 509 DRM_DEV_ERROR(dev->dev, "%s: offending task: unknown\n", gpu->name); 510 511 msm_rd_dump_submit(priv->hangrd, submit, NULL); 512 } 513 514 /* Record the crash state */ 515 pm_runtime_get_sync(&gpu->pdev->dev); 516 msm_gpu_crashstate_capture(gpu, submit, NULL, comm, cmd); 517 518 kfree(cmd); 519 kfree(comm); 520 521 /* 522 * Update all the rings with the latest and greatest fence.. this 523 * needs to happen after msm_rd_dump_submit() to ensure that the 524 * bo's referenced by the offending submit are still around. 525 */ 526 for (i = 0; i < gpu->nr_rings; i++) { 527 struct msm_ringbuffer *ring = gpu->rb[i]; 528 529 uint32_t fence = ring->memptrs->fence; 530 531 /* 532 * For the current (faulting?) ring/submit advance the fence by 533 * one more to clear the faulting submit 534 */ 535 if (ring == cur_ring) 536 ring->memptrs->fence = ++fence; 537 538 msm_update_fence(ring->fctx, fence); 539 } 540 541 if (msm_gpu_active(gpu)) { 542 /* retire completed submits, plus the one that hung: */ 543 retire_submits(gpu); 544 545 gpu->funcs->recover(gpu); 546 547 /* 548 * Replay all remaining submits starting with highest priority 549 * ring 550 */ 551 for (i = 0; i < gpu->nr_rings; i++) { 552 struct msm_ringbuffer *ring = gpu->rb[i]; 553 unsigned long flags; 554 555 spin_lock_irqsave(&ring->submit_lock, flags); 556 list_for_each_entry(submit, &ring->submits, node) 557 gpu->funcs->submit(gpu, submit); 558 spin_unlock_irqrestore(&ring->submit_lock, flags); 559 } 560 } 561 562 pm_runtime_put(&gpu->pdev->dev); 563 564 out_unlock: 565 mutex_unlock(&gpu->lock); 566 567 msm_gpu_retire(gpu); 568 } 569 570 void msm_gpu_fault_crashstate_capture(struct msm_gpu *gpu, struct msm_gpu_fault_info *fault_info) 571 { 572 struct msm_gem_submit *submit; 573 struct msm_ringbuffer *cur_ring = gpu->funcs->active_ring(gpu); 574 char *comm = NULL, *cmd = NULL; 575 576 mutex_lock(&gpu->lock); 577 578 submit = find_submit(cur_ring, cur_ring->memptrs->fence + 1); 579 if (submit && submit->fault_dumped) 580 goto resume_smmu; 581 582 if (submit) { 583 get_comm_cmdline(submit, &comm, &cmd); 584 585 /* 586 * When we get GPU iova faults, we can get 1000s of them, 587 * but we really only want to log the first one. 588 */ 589 submit->fault_dumped = true; 590 } 591 592 /* Record the crash state */ 593 pm_runtime_get_sync(&gpu->pdev->dev); 594 msm_gpu_crashstate_capture(gpu, submit, fault_info, comm, cmd); 595 pm_runtime_put_sync(&gpu->pdev->dev); 596 597 kfree(cmd); 598 kfree(comm); 599 600 resume_smmu: 601 mutex_unlock(&gpu->lock); 602 } 603 604 static void hangcheck_timer_reset(struct msm_gpu *gpu) 605 { 606 struct msm_drm_private *priv = gpu->dev->dev_private; 607 mod_timer(&gpu->hangcheck_timer, 608 round_jiffies_up(jiffies + msecs_to_jiffies(priv->hangcheck_period))); 609 } 610 611 static bool made_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 612 { 613 if (ring->hangcheck_progress_retries >= DRM_MSM_HANGCHECK_PROGRESS_RETRIES) 614 return false; 615 616 if (!gpu->funcs->progress) 617 return false; 618 619 if (!gpu->funcs->progress(gpu, ring)) 620 return false; 621 622 ring->hangcheck_progress_retries++; 623 return true; 624 } 625 626 static void hangcheck_handler(struct timer_list *t) 627 { 628 struct msm_gpu *gpu = timer_container_of(gpu, t, hangcheck_timer); 629 struct drm_device *dev = gpu->dev; 630 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); 631 uint32_t fence = ring->memptrs->fence; 632 633 if (fence != ring->hangcheck_fence) { 634 /* some progress has been made.. ya! */ 635 ring->hangcheck_fence = fence; 636 ring->hangcheck_progress_retries = 0; 637 } else if (fence_before(fence, ring->fctx->last_fence) && 638 !made_progress(gpu, ring)) { 639 /* no progress and not done.. hung! */ 640 ring->hangcheck_fence = fence; 641 ring->hangcheck_progress_retries = 0; 642 DRM_DEV_ERROR(dev->dev, "%s: hangcheck detected gpu lockup rb %d!\n", 643 gpu->name, ring->id); 644 DRM_DEV_ERROR(dev->dev, "%s: completed fence: %u\n", 645 gpu->name, fence); 646 DRM_DEV_ERROR(dev->dev, "%s: submitted fence: %u\n", 647 gpu->name, ring->fctx->last_fence); 648 649 kthread_queue_work(gpu->worker, &gpu->recover_work); 650 } 651 652 /* if still more pending work, reset the hangcheck timer: */ 653 if (fence_after(ring->fctx->last_fence, ring->hangcheck_fence)) 654 hangcheck_timer_reset(gpu); 655 656 /* workaround for missing irq: */ 657 msm_gpu_retire(gpu); 658 } 659 660 /* 661 * Performance Counters: 662 */ 663 664 /* called under perf_lock */ 665 static int update_hw_cntrs(struct msm_gpu *gpu, uint32_t ncntrs, uint32_t *cntrs) 666 { 667 uint32_t current_cntrs[ARRAY_SIZE(gpu->last_cntrs)]; 668 int i, n = min(ncntrs, gpu->num_perfcntrs); 669 670 /* read current values: */ 671 for (i = 0; i < gpu->num_perfcntrs; i++) 672 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); 673 674 /* update cntrs: */ 675 for (i = 0; i < n; i++) 676 cntrs[i] = current_cntrs[i] - gpu->last_cntrs[i]; 677 678 /* save current values: */ 679 for (i = 0; i < gpu->num_perfcntrs; i++) 680 gpu->last_cntrs[i] = current_cntrs[i]; 681 682 return n; 683 } 684 685 static void update_sw_cntrs(struct msm_gpu *gpu) 686 { 687 ktime_t time; 688 uint32_t elapsed; 689 unsigned long flags; 690 691 spin_lock_irqsave(&gpu->perf_lock, flags); 692 if (!gpu->perfcntr_active) 693 goto out; 694 695 time = ktime_get(); 696 elapsed = ktime_to_us(ktime_sub(time, gpu->last_sample.time)); 697 698 gpu->totaltime += elapsed; 699 if (gpu->last_sample.active) 700 gpu->activetime += elapsed; 701 702 gpu->last_sample.active = msm_gpu_active(gpu); 703 gpu->last_sample.time = time; 704 705 out: 706 spin_unlock_irqrestore(&gpu->perf_lock, flags); 707 } 708 709 void msm_gpu_perfcntr_start(struct msm_gpu *gpu) 710 { 711 unsigned long flags; 712 713 pm_runtime_get_sync(&gpu->pdev->dev); 714 715 spin_lock_irqsave(&gpu->perf_lock, flags); 716 /* we could dynamically enable/disable perfcntr registers too.. */ 717 gpu->last_sample.active = msm_gpu_active(gpu); 718 gpu->last_sample.time = ktime_get(); 719 gpu->activetime = gpu->totaltime = 0; 720 gpu->perfcntr_active = true; 721 update_hw_cntrs(gpu, 0, NULL); 722 spin_unlock_irqrestore(&gpu->perf_lock, flags); 723 } 724 725 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu) 726 { 727 gpu->perfcntr_active = false; 728 pm_runtime_put_sync(&gpu->pdev->dev); 729 } 730 731 /* returns -errno or # of cntrs sampled */ 732 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime, 733 uint32_t *totaltime, uint32_t ncntrs, uint32_t *cntrs) 734 { 735 unsigned long flags; 736 int ret; 737 738 spin_lock_irqsave(&gpu->perf_lock, flags); 739 740 if (!gpu->perfcntr_active) { 741 ret = -EINVAL; 742 goto out; 743 } 744 745 *activetime = gpu->activetime; 746 *totaltime = gpu->totaltime; 747 748 gpu->activetime = gpu->totaltime = 0; 749 750 ret = update_hw_cntrs(gpu, ncntrs, cntrs); 751 752 out: 753 spin_unlock_irqrestore(&gpu->perf_lock, flags); 754 755 return ret; 756 } 757 758 /* 759 * Cmdstream submission/retirement: 760 */ 761 762 static void retire_submit(struct msm_gpu *gpu, struct msm_ringbuffer *ring, 763 struct msm_gem_submit *submit) 764 { 765 int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT; 766 volatile struct msm_gpu_submit_stats *stats; 767 u64 elapsed, clock = 0, cycles; 768 unsigned long flags; 769 770 stats = &ring->memptrs->stats[index]; 771 /* Convert 19.2Mhz alwayson ticks to nanoseconds for elapsed time */ 772 elapsed = (stats->alwayson_end - stats->alwayson_start) * 10000; 773 do_div(elapsed, 192); 774 775 cycles = stats->cpcycles_end - stats->cpcycles_start; 776 777 /* Calculate the clock frequency from the number of CP cycles */ 778 if (elapsed) { 779 clock = cycles * 1000; 780 do_div(clock, elapsed); 781 } 782 783 submit->queue->ctx->elapsed_ns += elapsed; 784 submit->queue->ctx->cycles += cycles; 785 786 trace_msm_gpu_submit_retired(submit, elapsed, clock, 787 stats->alwayson_start, stats->alwayson_end); 788 789 msm_submit_retire(submit); 790 791 pm_runtime_mark_last_busy(&gpu->pdev->dev); 792 793 spin_lock_irqsave(&ring->submit_lock, flags); 794 list_del(&submit->node); 795 spin_unlock_irqrestore(&ring->submit_lock, flags); 796 797 /* Update devfreq on transition from active->idle: */ 798 mutex_lock(&gpu->active_lock); 799 gpu->active_submits--; 800 WARN_ON(gpu->active_submits < 0); 801 if (!gpu->active_submits) { 802 msm_devfreq_idle(gpu); 803 pm_runtime_put_autosuspend(&gpu->pdev->dev); 804 } 805 806 mutex_unlock(&gpu->active_lock); 807 808 msm_gem_submit_put(submit); 809 } 810 811 static void retire_submits(struct msm_gpu *gpu) 812 { 813 int i; 814 815 /* Retire the commits starting with highest priority */ 816 for (i = 0; i < gpu->nr_rings; i++) { 817 struct msm_ringbuffer *ring = gpu->rb[i]; 818 819 while (true) { 820 struct msm_gem_submit *submit = NULL; 821 unsigned long flags; 822 823 spin_lock_irqsave(&ring->submit_lock, flags); 824 submit = list_first_entry_or_null(&ring->submits, 825 struct msm_gem_submit, node); 826 spin_unlock_irqrestore(&ring->submit_lock, flags); 827 828 /* 829 * If no submit, we are done. If submit->fence hasn't 830 * been signalled, then later submits are not signalled 831 * either, so we are also done. 832 */ 833 if (submit && dma_fence_is_signaled(submit->hw_fence)) { 834 retire_submit(gpu, ring, submit); 835 } else { 836 break; 837 } 838 } 839 } 840 841 wake_up_all(&gpu->retire_event); 842 } 843 844 static void retire_worker(struct kthread_work *work) 845 { 846 struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work); 847 848 retire_submits(gpu); 849 } 850 851 /* call from irq handler to schedule work to retire bo's */ 852 void msm_gpu_retire(struct msm_gpu *gpu) 853 { 854 int i; 855 856 for (i = 0; i < gpu->nr_rings; i++) 857 msm_update_fence(gpu->rb[i]->fctx, gpu->rb[i]->memptrs->fence); 858 859 kthread_queue_work(gpu->worker, &gpu->retire_work); 860 update_sw_cntrs(gpu); 861 } 862 863 /* add bo's to gpu's ring, and kick gpu: */ 864 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 865 { 866 struct msm_ringbuffer *ring = submit->ring; 867 unsigned long flags; 868 869 WARN_ON(!mutex_is_locked(&gpu->lock)); 870 871 pm_runtime_get_sync(&gpu->pdev->dev); 872 873 msm_gpu_hw_init(gpu); 874 875 submit->seqno = submit->hw_fence->seqno; 876 877 update_sw_cntrs(gpu); 878 879 /* 880 * ring->submits holds a ref to the submit, to deal with the case 881 * that a submit completes before msm_ioctl_gem_submit() returns. 882 */ 883 msm_gem_submit_get(submit); 884 885 spin_lock_irqsave(&ring->submit_lock, flags); 886 list_add_tail(&submit->node, &ring->submits); 887 spin_unlock_irqrestore(&ring->submit_lock, flags); 888 889 /* Update devfreq on transition from idle->active: */ 890 mutex_lock(&gpu->active_lock); 891 if (!gpu->active_submits) { 892 pm_runtime_get(&gpu->pdev->dev); 893 msm_devfreq_active(gpu); 894 } 895 gpu->active_submits++; 896 mutex_unlock(&gpu->active_lock); 897 898 gpu->funcs->submit(gpu, submit); 899 submit->ring->cur_ctx_seqno = submit->queue->ctx->seqno; 900 901 pm_runtime_put(&gpu->pdev->dev); 902 hangcheck_timer_reset(gpu); 903 } 904 905 /* 906 * Init/Cleanup: 907 */ 908 909 static irqreturn_t irq_handler(int irq, void *data) 910 { 911 struct msm_gpu *gpu = data; 912 return gpu->funcs->irq(gpu); 913 } 914 915 static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu) 916 { 917 int ret = devm_clk_bulk_get_all(&pdev->dev, &gpu->grp_clks); 918 919 if (ret < 1) { 920 gpu->nr_clocks = 0; 921 return ret; 922 } 923 924 gpu->nr_clocks = ret; 925 926 gpu->core_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 927 gpu->nr_clocks, "core"); 928 929 gpu->rbbmtimer_clk = msm_clk_bulk_get_clock(gpu->grp_clks, 930 gpu->nr_clocks, "rbbmtimer"); 931 932 return 0; 933 } 934 935 /* Return a new address space for a msm_drm_private instance */ 936 struct drm_gpuvm * 937 msm_gpu_create_private_vm(struct msm_gpu *gpu, struct task_struct *task, 938 bool kernel_managed) 939 { 940 struct drm_gpuvm *vm = NULL; 941 942 if (!gpu) 943 return NULL; 944 945 /* 946 * If the target doesn't support private address spaces then return 947 * the global one 948 */ 949 if (gpu->funcs->create_private_vm) { 950 vm = gpu->funcs->create_private_vm(gpu, kernel_managed); 951 if (!IS_ERR(vm)) 952 to_msm_vm(vm)->pid = get_pid(task_pid(task)); 953 } 954 955 if (IS_ERR_OR_NULL(vm)) 956 vm = drm_gpuvm_get(gpu->vm); 957 958 return vm; 959 } 960 961 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev, 962 struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs, 963 const char *name, struct msm_gpu_config *config) 964 { 965 struct msm_drm_private *priv = drm->dev_private; 966 int i, ret, nr_rings = config->nr_rings; 967 void *memptrs; 968 uint64_t memptrs_iova; 969 970 if (WARN_ON(gpu->num_perfcntrs > ARRAY_SIZE(gpu->last_cntrs))) 971 gpu->num_perfcntrs = ARRAY_SIZE(gpu->last_cntrs); 972 973 gpu->dev = drm; 974 gpu->funcs = funcs; 975 gpu->name = name; 976 977 gpu->worker = kthread_run_worker(0, "gpu-worker"); 978 if (IS_ERR(gpu->worker)) { 979 ret = PTR_ERR(gpu->worker); 980 gpu->worker = NULL; 981 goto fail; 982 } 983 984 sched_set_fifo_low(gpu->worker->task); 985 986 mutex_init(&gpu->active_lock); 987 mutex_init(&gpu->lock); 988 init_waitqueue_head(&gpu->retire_event); 989 kthread_init_work(&gpu->retire_work, retire_worker); 990 kthread_init_work(&gpu->recover_work, recover_worker); 991 992 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; 993 994 /* 995 * If progress detection is supported, halve the hangcheck timer 996 * duration, as it takes two iterations of the hangcheck handler 997 * to detect a hang. 998 */ 999 if (funcs->progress) 1000 priv->hangcheck_period /= 2; 1001 1002 timer_setup(&gpu->hangcheck_timer, hangcheck_handler, 0); 1003 1004 spin_lock_init(&gpu->perf_lock); 1005 1006 1007 /* Map registers: */ 1008 gpu->mmio = msm_ioremap(pdev, config->ioname); 1009 if (IS_ERR(gpu->mmio)) { 1010 ret = PTR_ERR(gpu->mmio); 1011 goto fail; 1012 } 1013 1014 /* Get Interrupt: */ 1015 gpu->irq = platform_get_irq(pdev, 0); 1016 if (gpu->irq < 0) { 1017 ret = gpu->irq; 1018 goto fail; 1019 } 1020 1021 ret = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 1022 IRQF_TRIGGER_HIGH, "gpu-irq", gpu); 1023 if (ret) { 1024 DRM_DEV_ERROR(drm->dev, "failed to request IRQ%u: %d\n", gpu->irq, ret); 1025 goto fail; 1026 } 1027 1028 ret = get_clocks(pdev, gpu); 1029 if (ret) 1030 goto fail; 1031 1032 gpu->ebi1_clk = msm_clk_get(pdev, "bus"); 1033 DBG("ebi1_clk: %p", gpu->ebi1_clk); 1034 if (IS_ERR(gpu->ebi1_clk)) 1035 gpu->ebi1_clk = NULL; 1036 1037 /* Acquire regulators: */ 1038 gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd"); 1039 DBG("gpu_reg: %p", gpu->gpu_reg); 1040 if (IS_ERR(gpu->gpu_reg)) 1041 gpu->gpu_reg = NULL; 1042 1043 gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx"); 1044 DBG("gpu_cx: %p", gpu->gpu_cx); 1045 if (IS_ERR(gpu->gpu_cx)) 1046 gpu->gpu_cx = NULL; 1047 1048 platform_set_drvdata(pdev, &gpu->adreno_smmu); 1049 1050 msm_devfreq_init(gpu); 1051 1052 gpu->vm = gpu->funcs->create_vm(gpu, pdev); 1053 if (IS_ERR(gpu->vm)) { 1054 ret = PTR_ERR(gpu->vm); 1055 goto fail; 1056 } 1057 1058 memptrs = msm_gem_kernel_new(drm, 1059 sizeof(struct msm_rbmemptrs) * nr_rings, 1060 check_apriv(gpu, MSM_BO_WC), gpu->vm, &gpu->memptrs_bo, 1061 &memptrs_iova); 1062 1063 if (IS_ERR(memptrs)) { 1064 ret = PTR_ERR(memptrs); 1065 DRM_DEV_ERROR(drm->dev, "could not allocate memptrs: %d\n", ret); 1066 goto fail; 1067 } 1068 1069 msm_gem_object_set_name(gpu->memptrs_bo, "memptrs"); 1070 1071 if (nr_rings > ARRAY_SIZE(gpu->rb)) { 1072 DRM_DEV_INFO_ONCE(drm->dev, "Only creating %zu ringbuffers\n", 1073 ARRAY_SIZE(gpu->rb)); 1074 nr_rings = ARRAY_SIZE(gpu->rb); 1075 } 1076 1077 /* Create ringbuffer(s): */ 1078 for (i = 0; i < nr_rings; i++) { 1079 gpu->rb[i] = msm_ringbuffer_new(gpu, i, memptrs, memptrs_iova); 1080 1081 if (IS_ERR(gpu->rb[i])) { 1082 ret = PTR_ERR(gpu->rb[i]); 1083 DRM_DEV_ERROR(drm->dev, 1084 "could not create ringbuffer %d: %d\n", i, ret); 1085 goto fail; 1086 } 1087 1088 memptrs += sizeof(struct msm_rbmemptrs); 1089 memptrs_iova += sizeof(struct msm_rbmemptrs); 1090 } 1091 1092 gpu->nr_rings = nr_rings; 1093 1094 refcount_set(&gpu->sysprof_active, 1); 1095 1096 return 0; 1097 1098 fail: 1099 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 1100 msm_ringbuffer_destroy(gpu->rb[i]); 1101 gpu->rb[i] = NULL; 1102 } 1103 1104 msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm); 1105 1106 platform_set_drvdata(pdev, NULL); 1107 return ret; 1108 } 1109 1110 void msm_gpu_cleanup(struct msm_gpu *gpu) 1111 { 1112 int i; 1113 1114 DBG("%s", gpu->name); 1115 1116 for (i = 0; i < ARRAY_SIZE(gpu->rb); i++) { 1117 msm_ringbuffer_destroy(gpu->rb[i]); 1118 gpu->rb[i] = NULL; 1119 } 1120 1121 msm_gem_kernel_put(gpu->memptrs_bo, gpu->vm); 1122 1123 if (!IS_ERR_OR_NULL(gpu->vm)) { 1124 struct msm_mmu *mmu = to_msm_vm(gpu->vm)->mmu; 1125 mmu->funcs->detach(mmu); 1126 drm_gpuvm_put(gpu->vm); 1127 } 1128 1129 if (gpu->worker) { 1130 kthread_destroy_worker(gpu->worker); 1131 } 1132 1133 msm_devfreq_cleanup(gpu); 1134 1135 platform_set_drvdata(gpu->pdev, NULL); 1136 } 1137