1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_print.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/display/drm_dsc.h> 34 #include <drm/msm_drm.h> 35 #include <drm/drm_gem.h> 36 37 extern struct fault_attr fail_gem_alloc; 38 extern struct fault_attr fail_gem_iova; 39 40 struct drm_fb_helper; 41 struct drm_fb_helper_surface_size; 42 43 struct msm_kms; 44 struct msm_gpu; 45 struct msm_mmu; 46 struct msm_mdss; 47 struct msm_rd_state; 48 struct msm_gem_submit; 49 struct msm_fence_context; 50 struct msm_disp_state; 51 52 #define MAX_CRTCS 8 53 54 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 55 56 enum msm_dp_controller { 57 MSM_DP_CONTROLLER_0, 58 MSM_DP_CONTROLLER_1, 59 MSM_DP_CONTROLLER_2, 60 MSM_DP_CONTROLLER_3, 61 MSM_DP_CONTROLLER_COUNT, 62 }; 63 64 enum msm_dsi_controller { 65 MSM_DSI_CONTROLLER_0, 66 MSM_DSI_CONTROLLER_1, 67 MSM_DSI_CONTROLLER_COUNT, 68 }; 69 70 #define MSM_GPU_MAX_RINGS 4 71 72 struct msm_drm_private { 73 74 struct drm_device *dev; 75 76 struct msm_kms *kms; 77 int (*kms_init)(struct drm_device *dev); 78 79 /* subordinate devices, if present: */ 80 struct platform_device *gpu_pdev; 81 82 /* when we have more than one 'msm_gpu' these need to be an array: */ 83 struct msm_gpu *gpu; 84 85 /* gpu is only set on open(), but we need this info earlier */ 86 bool is_a2xx; 87 bool has_cached_coherent; 88 89 struct msm_rd_state *rd; /* debugfs to dump all submits */ 90 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 91 92 /** 93 * total_mem: Total/global amount of memory backing GEM objects. 94 */ 95 atomic64_t total_mem; 96 97 /** 98 * List of all GEM objects (mainly for debugfs, protected by obj_lock 99 * (acquire before per GEM object lock) 100 */ 101 struct list_head objects; 102 struct mutex obj_lock; 103 104 /** 105 * lru: 106 * 107 * The various LRU's that a GEM object is in at various stages of 108 * it's lifetime. Objects start out in the unbacked LRU. When 109 * pinned (for scannout or permanently mapped GPU buffers, like 110 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 111 * unpinned, it moves into willneed or dontneed LRU depending on 112 * madvise state. When backing pages are evicted (willneed) or 113 * purged (dontneed) it moves back into the unbacked LRU. 114 * 115 * The dontneed LRU is considered by the shrinker for objects 116 * that are candidate for purging, and the willneed LRU is 117 * considered for objects that could be evicted. 118 */ 119 struct { 120 /** 121 * unbacked: 122 * 123 * The LRU for GEM objects without backing pages allocated. 124 * This mostly exists so that objects are always is one 125 * LRU. 126 */ 127 struct drm_gem_lru unbacked; 128 129 /** 130 * pinned: 131 * 132 * The LRU for pinned GEM objects 133 */ 134 struct drm_gem_lru pinned; 135 136 /** 137 * willneed: 138 * 139 * The LRU for unpinned GEM objects which are in madvise 140 * WILLNEED state (ie. can be evicted) 141 */ 142 struct drm_gem_lru willneed; 143 144 /** 145 * dontneed: 146 * 147 * The LRU for unpinned GEM objects which are in madvise 148 * DONTNEED state (ie. can be purged) 149 */ 150 struct drm_gem_lru dontneed; 151 } lru; 152 153 struct notifier_block vmap_notifier; 154 struct shrinker *shrinker; 155 156 /** 157 * hangcheck_period: For hang detection, in ms 158 * 159 * Note that in practice, a submit/job will get at least two hangcheck 160 * periods, due to checking for progress being implemented as simply 161 * "have the CP position registers changed since last time?" 162 */ 163 unsigned int hangcheck_period; 164 165 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 166 struct devfreq_simple_ondemand_data gpu_devfreq_config; 167 168 /** 169 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 170 */ 171 bool gpu_clamp_to_idle; 172 173 /** 174 * disable_err_irq: 175 * 176 * Disable handling of GPU hw error interrupts, to force fallback to 177 * sw hangcheck timer. Written (via debugfs) by igt tests to test 178 * the sw hangcheck mechanism. 179 */ 180 bool disable_err_irq; 181 182 /** 183 * @fault_stall_lock: 184 * 185 * Serialize changes to stall-on-fault state. 186 */ 187 spinlock_t fault_stall_lock; 188 189 /** 190 * @fault_stall_reenable_time: 191 * 192 * If stall_enabled is false, when to reenable stall-on-fault. 193 * Protected by @fault_stall_lock. 194 */ 195 ktime_t stall_reenable_time; 196 197 /** 198 * @stall_enabled: 199 * 200 * Whether stall-on-fault is currently enabled. Protected by 201 * @fault_stall_lock. 202 */ 203 bool stall_enabled; 204 }; 205 206 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); 207 208 struct msm_pending_timer; 209 210 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 211 struct msm_kms *kms, int crtc_idx); 212 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 213 void msm_atomic_commit_tail(struct drm_atomic_commit *state); 214 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state); 215 struct drm_atomic_commit *msm_atomic_state_alloc(struct drm_device *dev); 216 217 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 218 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 219 220 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 221 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 222 223 struct drm_gpuvm *msm_kms_init_vm(struct drm_device *dev, struct device *mdss_dev); 224 bool msm_use_mmu(struct drm_device *dev); 225 226 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 227 struct drm_file *file); 228 int msm_ioctl_vm_bind(struct drm_device *dev, void *data, 229 struct drm_file *file); 230 231 int msm_perfcntr_resume(struct msm_gpu *gpu); 232 void msm_perfcntr_suspend(struct msm_gpu *gpu); 233 int msm_ioctl_perfcntr_config(struct drm_device *dev, void *data, 234 struct drm_file *file); 235 236 struct msm_perfcntr_state * msm_perfcntr_init(struct msm_gpu *gpu); 237 void msm_perfcntr_cleanup(struct msm_gpu *gpu); 238 239 #ifdef CONFIG_DEBUG_FS 240 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 241 #endif 242 243 int msm_gem_shrinker_init(struct drm_device *dev); 244 void msm_gem_shrinker_cleanup(struct drm_device *dev); 245 246 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 247 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 248 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 249 struct drm_gem_object *msm_gem_prime_import(struct drm_device *dev, struct dma_buf *buf); 250 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 251 struct dma_buf_attachment *attach, struct sg_table *sg); 252 struct dma_buf *msm_gem_prime_export(struct drm_gem_object *obj, int flags); 253 int msm_gem_prime_pin(struct drm_gem_object *obj); 254 void msm_gem_prime_unpin(struct drm_gem_object *obj); 255 256 int msm_framebuffer_prepare(struct drm_framebuffer *fb, bool needs_dirtyfb); 257 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, bool needed_dirtyfb); 258 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int plane); 259 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 260 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 261 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 262 struct drm_file *file, const struct drm_format_info *info, 263 const struct drm_mode_fb_cmd2 *mode_cmd); 264 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 265 int w, int h, int p, uint32_t format); 266 267 #ifdef CONFIG_DRM_MSM_KMS_FBDEV 268 int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, 269 struct drm_fb_helper_surface_size *sizes); 270 #define MSM_FBDEV_DRIVER_OPS \ 271 .fbdev_probe = msm_fbdev_driver_fbdev_probe 272 #else 273 #define MSM_FBDEV_DRIVER_OPS \ 274 .fbdev_probe = NULL 275 #endif 276 277 struct hdmi; 278 #ifdef CONFIG_DRM_MSM_HDMI 279 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 280 struct drm_encoder *encoder); 281 void __init msm_hdmi_register(void); 282 void __exit msm_hdmi_unregister(void); 283 #else 284 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 285 struct drm_encoder *encoder) 286 { 287 return -EINVAL; 288 } 289 static inline void __init msm_hdmi_register(void) {} 290 static inline void __exit msm_hdmi_unregister(void) {} 291 #endif 292 293 struct msm_dsi; 294 #ifdef CONFIG_DRM_MSM_DSI 295 int dsi_dev_attach(struct platform_device *pdev); 296 void dsi_dev_detach(struct platform_device *pdev); 297 void __init msm_dsi_register(void); 298 void __exit msm_dsi_unregister(void); 299 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 300 struct drm_encoder *encoder); 301 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 302 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 303 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 304 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 305 bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); 306 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 307 const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi); 308 #else 309 static inline void __init msm_dsi_register(void) 310 { 311 } 312 static inline void __exit msm_dsi_unregister(void) 313 { 314 } 315 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 316 struct drm_device *dev, 317 struct drm_encoder *encoder) 318 { 319 return -EINVAL; 320 } 321 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 322 { 323 } 324 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 325 { 326 return false; 327 } 328 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 329 { 330 return false; 331 } 332 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 333 { 334 return false; 335 } 336 static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) 337 { 338 return false; 339 } 340 341 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 342 { 343 return NULL; 344 } 345 346 static inline const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi) 347 { 348 return NULL; 349 } 350 #endif 351 352 struct msm_dp; 353 #ifdef CONFIG_DRM_MSM_DP 354 int __init msm_dp_register(void); 355 void __exit msm_dp_unregister(void); 356 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 357 struct drm_encoder *encoder, bool yuv_supported); 358 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 359 bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 360 const struct drm_display_mode *mode); 361 bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 362 const struct drm_display_mode *mode); 363 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 364 365 #else 366 static inline int __init msm_dp_register(void) 367 { 368 return -EINVAL; 369 } 370 static inline void __exit msm_dp_unregister(void) 371 { 372 } 373 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 374 struct drm_device *dev, 375 struct drm_encoder *encoder, 376 bool yuv_supported) 377 { 378 return -EINVAL; 379 } 380 381 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 382 { 383 } 384 385 static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 386 const struct drm_display_mode *mode) 387 { 388 return false; 389 } 390 391 static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 392 const struct drm_display_mode *mode) 393 { 394 return false; 395 } 396 397 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 398 { 399 return false; 400 } 401 402 #endif 403 404 #ifdef CONFIG_DRM_MSM_MDP4 405 void msm_mdp4_register(void); 406 void msm_mdp4_unregister(void); 407 #else 408 static inline void msm_mdp4_register(void) {} 409 static inline void msm_mdp4_unregister(void) {} 410 #endif 411 412 #ifdef CONFIG_DRM_MSM_MDP5 413 void msm_mdp_register(void); 414 void msm_mdp_unregister(void); 415 #else 416 static inline void msm_mdp_register(void) {} 417 static inline void msm_mdp_unregister(void) {} 418 #endif 419 420 #ifdef CONFIG_DRM_MSM_DPU 421 void msm_dpu_register(void); 422 void msm_dpu_unregister(void); 423 #else 424 static inline void msm_dpu_register(void) {} 425 static inline void msm_dpu_unregister(void) {} 426 #endif 427 428 #ifdef CONFIG_DRM_MSM_MDSS 429 void msm_mdss_register(void); 430 void msm_mdss_unregister(void); 431 #else 432 static inline void msm_mdss_register(void) {} 433 static inline void msm_mdss_unregister(void) {} 434 #endif 435 436 #ifdef CONFIG_DEBUG_FS 437 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 438 int msm_debugfs_late_init(struct drm_device *dev); 439 int msm_rd_debugfs_init(struct drm_minor *minor); 440 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 441 __printf(3, 4) 442 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 443 const char *fmt, ...); 444 #else 445 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 446 __printf(3, 4) 447 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 448 struct msm_gem_submit *submit, 449 const char *fmt, ...) {} 450 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 451 #endif 452 453 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 454 455 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 456 const char *name); 457 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 458 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 459 phys_addr_t *size); 460 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 461 void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, 462 struct platform_device *dev, 463 const char *name); 464 465 struct icc_path *msm_icc_get(struct device *dev, const char *name); 466 467 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 468 { 469 u32 val = readl(addr); 470 471 val &= ~mask; 472 writel(val | or, addr); 473 } 474 475 /** 476 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 477 * 478 * @timer: hrtimer to control when the kthread work is triggered 479 * @work: the kthread work 480 * @worker: the kthread worker the work will be scheduled on 481 */ 482 struct msm_hrtimer_work { 483 struct hrtimer timer; 484 struct kthread_work work; 485 struct kthread_worker *worker; 486 }; 487 488 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 489 ktime_t wakeup_time, 490 enum hrtimer_mode mode); 491 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 492 struct kthread_worker *worker, 493 kthread_work_func_t fn, 494 clockid_t clock_id, 495 enum hrtimer_mode mode); 496 497 /* Helper for returning a UABI error with optional logging which can make 498 * it easier for userspace to understand what it is doing wrong. 499 */ 500 #define UERR(err, drm, fmt, ...) \ 501 ({ DRM_DEV_DEBUG_DRIVER((drm)->dev, fmt, ##__VA_ARGS__); -(err); }) 502 503 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 504 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 505 506 static inline int align_pitch(int width, int bpp) 507 { 508 int bytespp = (bpp + 7) / 8; 509 /* adreno needs pitch aligned to 32 pixels: */ 510 return bytespp * ALIGN(width, 32); 511 } 512 513 /* for the generated headers: */ 514 #define INVALID_IDX(idx) ({BUG(); 0;}) 515 #define fui(x) ({BUG(); 0;}) 516 #define _mesa_float_to_half(x) ({BUG(); 0;}) 517 518 519 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 520 521 /* for conditionally setting boolean flag(s): */ 522 #define COND(bool, val) ((bool) ? (val) : 0) 523 524 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 525 { 526 ktime_t now = ktime_get(); 527 528 if (ktime_compare(*timeout, now) <= 0) 529 return 0; 530 531 ktime_t rem = ktime_sub(*timeout, now); 532 s64 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 533 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 534 } 535 536 /* Driver helpers */ 537 538 extern const struct component_master_ops msm_drm_ops; 539 540 int msm_kms_pm_prepare(struct device *dev); 541 void msm_kms_pm_complete(struct device *dev); 542 543 int msm_gpu_probe(struct platform_device *pdev, 544 const struct component_ops *ops); 545 void msm_gpu_remove(struct platform_device *pdev, 546 const struct component_ops *ops); 547 int msm_drv_probe(struct device *dev, 548 int (*kms_init)(struct drm_device *dev), 549 struct msm_kms *kms); 550 void msm_kms_shutdown(struct platform_device *pdev); 551 552 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); 553 554 bool msm_gpu_no_components(void); 555 556 #endif /* __MSM_DRV_H__ */ 557