1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/display/drm_dsc.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 #ifdef CONFIG_FAULT_INJECTION 37 extern struct fault_attr fail_gem_alloc; 38 extern struct fault_attr fail_gem_iova; 39 #else 40 # define should_fail(attr, size) 0 41 #endif 42 43 struct msm_kms; 44 struct msm_gpu; 45 struct msm_mmu; 46 struct msm_mdss; 47 struct msm_rd_state; 48 struct msm_perf_state; 49 struct msm_gem_submit; 50 struct msm_fence_context; 51 struct msm_gem_address_space; 52 struct msm_gem_vma; 53 struct msm_disp_state; 54 55 #define MAX_CRTCS 8 56 #define MAX_BRIDGES 8 57 58 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 59 60 enum msm_dp_controller { 61 MSM_DP_CONTROLLER_0, 62 MSM_DP_CONTROLLER_1, 63 MSM_DP_CONTROLLER_2, 64 MSM_DP_CONTROLLER_3, 65 MSM_DP_CONTROLLER_COUNT, 66 }; 67 68 #define MSM_GPU_MAX_RINGS 4 69 #define MAX_H_TILES_PER_DISPLAY 2 70 71 /** 72 * enum msm_event_wait - type of HW events to wait for 73 * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW 74 * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel 75 * @MSM_ENC_VBLANK - wait for the HW VBLANK event (for driver-internal waiters) 76 */ 77 enum msm_event_wait { 78 MSM_ENC_COMMIT_DONE = 0, 79 MSM_ENC_TX_COMPLETE, 80 MSM_ENC_VBLANK, 81 }; 82 83 /** 84 * struct msm_display_topology - defines a display topology pipeline 85 * @num_lm: number of layer mixers used 86 * @num_intf: number of interfaces the panel is mounted on 87 * @num_dspp: number of dspp blocks used 88 * @num_dsc: number of Display Stream Compression (DSC) blocks used 89 */ 90 struct msm_display_topology { 91 u32 num_lm; 92 u32 num_intf; 93 u32 num_dspp; 94 u32 num_dsc; 95 }; 96 97 /* Commit/Event thread specific structure */ 98 struct msm_drm_thread { 99 struct drm_device *dev; 100 unsigned int crtc_id; 101 struct kthread_worker *worker; 102 }; 103 104 struct msm_drm_private { 105 106 struct drm_device *dev; 107 108 struct msm_kms *kms; 109 int (*kms_init)(struct drm_device *dev); 110 111 /* subordinate devices, if present: */ 112 struct platform_device *gpu_pdev; 113 114 /* possibly this should be in the kms component, but it is 115 * shared by both mdp4 and mdp5.. 116 */ 117 struct hdmi *hdmi; 118 119 /* DSI is shared by mdp4 and mdp5 */ 120 struct msm_dsi *dsi[2]; 121 122 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 123 124 /* when we have more than one 'msm_gpu' these need to be an array: */ 125 struct msm_gpu *gpu; 126 127 /* gpu is only set on open(), but we need this info earlier */ 128 bool is_a2xx; 129 bool has_cached_coherent; 130 131 struct msm_rd_state *rd; /* debugfs to dump all submits */ 132 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 133 struct msm_perf_state *perf; 134 135 /** 136 * List of all GEM objects (mainly for debugfs, protected by obj_lock 137 * (acquire before per GEM object lock) 138 */ 139 struct list_head objects; 140 struct mutex obj_lock; 141 142 /** 143 * lru: 144 * 145 * The various LRU's that a GEM object is in at various stages of 146 * it's lifetime. Objects start out in the unbacked LRU. When 147 * pinned (for scannout or permanently mapped GPU buffers, like 148 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 149 * unpinned, it moves into willneed or dontneed LRU depending on 150 * madvise state. When backing pages are evicted (willneed) or 151 * purged (dontneed) it moves back into the unbacked LRU. 152 * 153 * The dontneed LRU is considered by the shrinker for objects 154 * that are candidate for purging, and the willneed LRU is 155 * considered for objects that could be evicted. 156 */ 157 struct { 158 /** 159 * unbacked: 160 * 161 * The LRU for GEM objects without backing pages allocated. 162 * This mostly exists so that objects are always is one 163 * LRU. 164 */ 165 struct drm_gem_lru unbacked; 166 167 /** 168 * pinned: 169 * 170 * The LRU for pinned GEM objects 171 */ 172 struct drm_gem_lru pinned; 173 174 /** 175 * willneed: 176 * 177 * The LRU for unpinned GEM objects which are in madvise 178 * WILLNEED state (ie. can be evicted) 179 */ 180 struct drm_gem_lru willneed; 181 182 /** 183 * dontneed: 184 * 185 * The LRU for unpinned GEM objects which are in madvise 186 * DONTNEED state (ie. can be purged) 187 */ 188 struct drm_gem_lru dontneed; 189 190 /** 191 * lock: 192 * 193 * Protects manipulation of all of the LRUs. 194 */ 195 struct mutex lock; 196 } lru; 197 198 struct workqueue_struct *wq; 199 200 unsigned int num_crtcs; 201 struct drm_crtc *crtcs[MAX_CRTCS]; 202 203 struct msm_drm_thread event_thread[MAX_CRTCS]; 204 205 unsigned int num_bridges; 206 struct drm_bridge *bridges[MAX_BRIDGES]; 207 208 /* VRAM carveout, used when no IOMMU: */ 209 struct { 210 unsigned long size; 211 dma_addr_t paddr; 212 /* NOTE: mm managed at the page level, size is in # of pages 213 * and position mm_node->start is in # of pages: 214 */ 215 struct drm_mm mm; 216 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 217 } vram; 218 219 struct notifier_block vmap_notifier; 220 struct shrinker shrinker; 221 222 struct drm_atomic_state *pm_state; 223 224 /** 225 * hangcheck_period: For hang detection, in ms 226 * 227 * Note that in practice, a submit/job will get at least two hangcheck 228 * periods, due to checking for progress being implemented as simply 229 * "have the CP position registers changed since last time?" 230 */ 231 unsigned int hangcheck_period; 232 233 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 234 struct devfreq_simple_ondemand_data gpu_devfreq_config; 235 236 /** 237 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 238 */ 239 bool gpu_clamp_to_idle; 240 241 /** 242 * disable_err_irq: 243 * 244 * Disable handling of GPU hw error interrupts, to force fallback to 245 * sw hangcheck timer. Written (via debugfs) by igt tests to test 246 * the sw hangcheck mechanism. 247 */ 248 bool disable_err_irq; 249 }; 250 251 struct msm_format { 252 uint32_t pixel_format; 253 }; 254 255 struct msm_pending_timer; 256 257 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 258 struct msm_kms *kms, int crtc_idx); 259 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 260 void msm_atomic_commit_tail(struct drm_atomic_state *state); 261 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 262 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 263 void msm_atomic_state_clear(struct drm_atomic_state *state); 264 void msm_atomic_state_free(struct drm_atomic_state *state); 265 266 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 267 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 268 269 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 270 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 271 272 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 273 bool msm_use_mmu(struct drm_device *dev); 274 275 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 276 struct drm_file *file); 277 278 #ifdef CONFIG_DEBUG_FS 279 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 280 #endif 281 282 void msm_gem_shrinker_init(struct drm_device *dev); 283 void msm_gem_shrinker_cleanup(struct drm_device *dev); 284 285 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 286 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 287 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 288 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 289 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 290 struct dma_buf_attachment *attach, struct sg_table *sg); 291 int msm_gem_prime_pin(struct drm_gem_object *obj); 292 void msm_gem_prime_unpin(struct drm_gem_object *obj); 293 294 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 295 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 296 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 297 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 298 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 299 struct msm_gem_address_space *aspace, int plane); 300 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 301 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 302 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 303 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 304 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 305 int w, int h, int p, uint32_t format); 306 307 #ifdef CONFIG_DRM_FBDEV_EMULATION 308 void msm_fbdev_setup(struct drm_device *dev); 309 #else 310 static inline void msm_fbdev_setup(struct drm_device *dev) 311 { 312 } 313 #endif 314 315 struct hdmi; 316 #ifdef CONFIG_DRM_MSM_HDMI 317 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 318 struct drm_encoder *encoder); 319 void __init msm_hdmi_register(void); 320 void __exit msm_hdmi_unregister(void); 321 #else 322 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 323 struct drm_encoder *encoder) 324 { 325 return -EINVAL; 326 } 327 static inline void __init msm_hdmi_register(void) {} 328 static inline void __exit msm_hdmi_unregister(void) {} 329 #endif 330 331 struct msm_dsi; 332 #ifdef CONFIG_DRM_MSM_DSI 333 int dsi_dev_attach(struct platform_device *pdev); 334 void dsi_dev_detach(struct platform_device *pdev); 335 void __init msm_dsi_register(void); 336 void __exit msm_dsi_unregister(void); 337 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 338 struct drm_encoder *encoder); 339 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 340 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 341 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 342 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 343 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 344 #else 345 static inline void __init msm_dsi_register(void) 346 { 347 } 348 static inline void __exit msm_dsi_unregister(void) 349 { 350 } 351 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 352 struct drm_device *dev, 353 struct drm_encoder *encoder) 354 { 355 return -EINVAL; 356 } 357 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 358 { 359 } 360 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 361 { 362 return false; 363 } 364 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 365 { 366 return false; 367 } 368 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 369 { 370 return false; 371 } 372 373 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 374 { 375 return NULL; 376 } 377 #endif 378 379 #ifdef CONFIG_DRM_MSM_DP 380 int __init msm_dp_register(void); 381 void __exit msm_dp_unregister(void); 382 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 383 struct drm_encoder *encoder); 384 void msm_dp_irq_postinstall(struct msm_dp *dp_display); 385 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 386 387 void msm_dp_debugfs_init(struct msm_dp *dp_display, struct drm_minor *minor); 388 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 389 390 #else 391 static inline int __init msm_dp_register(void) 392 { 393 return -EINVAL; 394 } 395 static inline void __exit msm_dp_unregister(void) 396 { 397 } 398 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 399 struct drm_device *dev, 400 struct drm_encoder *encoder) 401 { 402 return -EINVAL; 403 } 404 405 static inline void msm_dp_irq_postinstall(struct msm_dp *dp_display) 406 { 407 } 408 409 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 410 { 411 } 412 413 static inline void msm_dp_debugfs_init(struct msm_dp *dp_display, 414 struct drm_minor *minor) 415 { 416 } 417 418 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 419 { 420 return false; 421 } 422 423 #endif 424 425 #ifdef CONFIG_DRM_MSM_MDP4 426 void msm_mdp4_register(void); 427 void msm_mdp4_unregister(void); 428 #else 429 static inline void msm_mdp4_register(void) {} 430 static inline void msm_mdp4_unregister(void) {} 431 #endif 432 433 #ifdef CONFIG_DRM_MSM_MDP5 434 void msm_mdp_register(void); 435 void msm_mdp_unregister(void); 436 #else 437 static inline void msm_mdp_register(void) {} 438 static inline void msm_mdp_unregister(void) {} 439 #endif 440 441 #ifdef CONFIG_DRM_MSM_DPU 442 void msm_dpu_register(void); 443 void msm_dpu_unregister(void); 444 #else 445 static inline void msm_dpu_register(void) {} 446 static inline void msm_dpu_unregister(void) {} 447 #endif 448 449 #ifdef CONFIG_DRM_MSM_MDSS 450 void msm_mdss_register(void); 451 void msm_mdss_unregister(void); 452 #else 453 static inline void msm_mdss_register(void) {} 454 static inline void msm_mdss_unregister(void) {} 455 #endif 456 457 #ifdef CONFIG_DEBUG_FS 458 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 459 int msm_debugfs_late_init(struct drm_device *dev); 460 int msm_rd_debugfs_init(struct drm_minor *minor); 461 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 462 __printf(3, 4) 463 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 464 const char *fmt, ...); 465 int msm_perf_debugfs_init(struct drm_minor *minor); 466 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 467 #else 468 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 469 __printf(3, 4) 470 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 471 struct msm_gem_submit *submit, 472 const char *fmt, ...) {} 473 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 474 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 475 #endif 476 477 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 478 479 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 480 const char *name); 481 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 482 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 483 phys_addr_t *size); 484 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 485 486 struct icc_path *msm_icc_get(struct device *dev, const char *name); 487 488 #define msm_writel(data, addr) writel((data), (addr)) 489 #define msm_readl(addr) readl((addr)) 490 491 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 492 { 493 u32 val = msm_readl(addr); 494 495 val &= ~mask; 496 msm_writel(val | or, addr); 497 } 498 499 /** 500 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 501 * 502 * @timer: hrtimer to control when the kthread work is triggered 503 * @work: the kthread work 504 * @worker: the kthread worker the work will be scheduled on 505 */ 506 struct msm_hrtimer_work { 507 struct hrtimer timer; 508 struct kthread_work work; 509 struct kthread_worker *worker; 510 }; 511 512 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 513 ktime_t wakeup_time, 514 enum hrtimer_mode mode); 515 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 516 struct kthread_worker *worker, 517 kthread_work_func_t fn, 518 clockid_t clock_id, 519 enum hrtimer_mode mode); 520 521 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 522 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 523 524 static inline int align_pitch(int width, int bpp) 525 { 526 int bytespp = (bpp + 7) / 8; 527 /* adreno needs pitch aligned to 32 pixels: */ 528 return bytespp * ALIGN(width, 32); 529 } 530 531 /* for the generated headers: */ 532 #define INVALID_IDX(idx) ({BUG(); 0;}) 533 #define fui(x) ({BUG(); 0;}) 534 #define _mesa_float_to_half(x) ({BUG(); 0;}) 535 536 537 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 538 539 /* for conditionally setting boolean flag(s): */ 540 #define COND(bool, val) ((bool) ? (val) : 0) 541 542 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 543 { 544 ktime_t now = ktime_get(); 545 s64 remaining_jiffies; 546 547 if (ktime_compare(*timeout, now) < 0) { 548 remaining_jiffies = 0; 549 } else { 550 ktime_t rem = ktime_sub(*timeout, now); 551 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 552 } 553 554 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 555 } 556 557 /* Driver helpers */ 558 559 extern const struct component_master_ops msm_drm_ops; 560 561 int msm_pm_prepare(struct device *dev); 562 void msm_pm_complete(struct device *dev); 563 564 int msm_drv_probe(struct device *dev, 565 int (*kms_init)(struct drm_device *dev)); 566 void msm_drv_shutdown(struct platform_device *pdev); 567 568 569 #endif /* __MSM_DRV_H__ */ 570