1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/display/drm_dsc.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 extern struct fault_attr fail_gem_alloc; 37 extern struct fault_attr fail_gem_iova; 38 39 struct drm_fb_helper; 40 struct drm_fb_helper_surface_size; 41 42 struct msm_kms; 43 struct msm_gpu; 44 struct msm_mmu; 45 struct msm_mdss; 46 struct msm_rd_state; 47 struct msm_perf_state; 48 struct msm_gem_submit; 49 struct msm_fence_context; 50 struct msm_gem_address_space; 51 struct msm_gem_vma; 52 struct msm_disp_state; 53 54 #define MAX_CRTCS 8 55 56 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 57 58 enum msm_dp_controller { 59 MSM_DP_CONTROLLER_0, 60 MSM_DP_CONTROLLER_1, 61 MSM_DP_CONTROLLER_2, 62 MSM_DP_CONTROLLER_3, 63 MSM_DP_CONTROLLER_COUNT, 64 }; 65 66 enum msm_dsi_controller { 67 MSM_DSI_CONTROLLER_0, 68 MSM_DSI_CONTROLLER_1, 69 MSM_DSI_CONTROLLER_COUNT, 70 }; 71 72 #define MSM_GPU_MAX_RINGS 4 73 74 /* Commit/Event thread specific structure */ 75 struct msm_drm_thread { 76 struct drm_device *dev; 77 struct kthread_worker *worker; 78 }; 79 80 struct msm_drm_private { 81 82 struct drm_device *dev; 83 84 struct msm_kms *kms; 85 int (*kms_init)(struct drm_device *dev); 86 87 /* subordinate devices, if present: */ 88 struct platform_device *gpu_pdev; 89 90 /* possibly this should be in the kms component, but it is 91 * shared by both mdp4 and mdp5.. 92 */ 93 struct hdmi *hdmi; 94 95 /* DSI is shared by mdp4 and mdp5 */ 96 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; 97 98 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 99 100 /* when we have more than one 'msm_gpu' these need to be an array: */ 101 struct msm_gpu *gpu; 102 103 /* gpu is only set on open(), but we need this info earlier */ 104 bool is_a2xx; 105 bool has_cached_coherent; 106 107 struct msm_rd_state *rd; /* debugfs to dump all submits */ 108 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 109 struct msm_perf_state *perf; 110 111 /** 112 * total_mem: Total/global amount of memory backing GEM objects. 113 */ 114 atomic64_t total_mem; 115 116 /** 117 * List of all GEM objects (mainly for debugfs, protected by obj_lock 118 * (acquire before per GEM object lock) 119 */ 120 struct list_head objects; 121 struct mutex obj_lock; 122 123 /** 124 * lru: 125 * 126 * The various LRU's that a GEM object is in at various stages of 127 * it's lifetime. Objects start out in the unbacked LRU. When 128 * pinned (for scannout or permanently mapped GPU buffers, like 129 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 130 * unpinned, it moves into willneed or dontneed LRU depending on 131 * madvise state. When backing pages are evicted (willneed) or 132 * purged (dontneed) it moves back into the unbacked LRU. 133 * 134 * The dontneed LRU is considered by the shrinker for objects 135 * that are candidate for purging, and the willneed LRU is 136 * considered for objects that could be evicted. 137 */ 138 struct { 139 /** 140 * unbacked: 141 * 142 * The LRU for GEM objects without backing pages allocated. 143 * This mostly exists so that objects are always is one 144 * LRU. 145 */ 146 struct drm_gem_lru unbacked; 147 148 /** 149 * pinned: 150 * 151 * The LRU for pinned GEM objects 152 */ 153 struct drm_gem_lru pinned; 154 155 /** 156 * willneed: 157 * 158 * The LRU for unpinned GEM objects which are in madvise 159 * WILLNEED state (ie. can be evicted) 160 */ 161 struct drm_gem_lru willneed; 162 163 /** 164 * dontneed: 165 * 166 * The LRU for unpinned GEM objects which are in madvise 167 * DONTNEED state (ie. can be purged) 168 */ 169 struct drm_gem_lru dontneed; 170 171 /** 172 * lock: 173 * 174 * Protects manipulation of all of the LRUs. 175 */ 176 struct mutex lock; 177 } lru; 178 179 struct workqueue_struct *wq; 180 181 unsigned int num_crtcs; 182 183 struct msm_drm_thread event_thread[MAX_CRTCS]; 184 185 /* VRAM carveout, used when no IOMMU: */ 186 struct { 187 unsigned long size; 188 dma_addr_t paddr; 189 /* NOTE: mm managed at the page level, size is in # of pages 190 * and position mm_node->start is in # of pages: 191 */ 192 struct drm_mm mm; 193 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 194 } vram; 195 196 struct notifier_block vmap_notifier; 197 struct shrinker *shrinker; 198 199 /** 200 * hangcheck_period: For hang detection, in ms 201 * 202 * Note that in practice, a submit/job will get at least two hangcheck 203 * periods, due to checking for progress being implemented as simply 204 * "have the CP position registers changed since last time?" 205 */ 206 unsigned int hangcheck_period; 207 208 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 209 struct devfreq_simple_ondemand_data gpu_devfreq_config; 210 211 /** 212 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 213 */ 214 bool gpu_clamp_to_idle; 215 216 /** 217 * disable_err_irq: 218 * 219 * Disable handling of GPU hw error interrupts, to force fallback to 220 * sw hangcheck timer. Written (via debugfs) by igt tests to test 221 * the sw hangcheck mechanism. 222 */ 223 bool disable_err_irq; 224 }; 225 226 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); 227 228 struct msm_pending_timer; 229 230 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 231 struct msm_kms *kms, int crtc_idx); 232 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 233 void msm_atomic_commit_tail(struct drm_atomic_state *state); 234 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 235 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 236 237 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 238 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 239 240 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 241 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 242 243 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 244 bool msm_use_mmu(struct drm_device *dev); 245 246 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 247 struct drm_file *file); 248 249 #ifdef CONFIG_DEBUG_FS 250 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 251 #endif 252 253 int msm_gem_shrinker_init(struct drm_device *dev); 254 void msm_gem_shrinker_cleanup(struct drm_device *dev); 255 256 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 257 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 258 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 259 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 260 struct dma_buf_attachment *attach, struct sg_table *sg); 261 int msm_gem_prime_pin(struct drm_gem_object *obj); 262 void msm_gem_prime_unpin(struct drm_gem_object *obj); 263 264 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 265 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 266 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 267 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 268 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 269 struct msm_gem_address_space *aspace, int plane); 270 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 271 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 272 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 273 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 274 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 275 int w, int h, int p, uint32_t format); 276 277 #ifdef CONFIG_DRM_FBDEV_EMULATION 278 int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, 279 struct drm_fb_helper_surface_size *sizes); 280 #define MSM_FBDEV_DRIVER_OPS \ 281 .fbdev_probe = msm_fbdev_driver_fbdev_probe 282 #else 283 #define MSM_FBDEV_DRIVER_OPS \ 284 .fbdev_probe = NULL 285 #endif 286 287 struct hdmi; 288 #ifdef CONFIG_DRM_MSM_HDMI 289 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 290 struct drm_encoder *encoder); 291 void __init msm_hdmi_register(void); 292 void __exit msm_hdmi_unregister(void); 293 #else 294 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 295 struct drm_encoder *encoder) 296 { 297 return -EINVAL; 298 } 299 static inline void __init msm_hdmi_register(void) {} 300 static inline void __exit msm_hdmi_unregister(void) {} 301 #endif 302 303 struct msm_dsi; 304 #ifdef CONFIG_DRM_MSM_DSI 305 int dsi_dev_attach(struct platform_device *pdev); 306 void dsi_dev_detach(struct platform_device *pdev); 307 void __init msm_dsi_register(void); 308 void __exit msm_dsi_unregister(void); 309 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 310 struct drm_encoder *encoder); 311 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 312 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 313 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 314 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 315 bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); 316 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 317 const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi); 318 #else 319 static inline void __init msm_dsi_register(void) 320 { 321 } 322 static inline void __exit msm_dsi_unregister(void) 323 { 324 } 325 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 326 struct drm_device *dev, 327 struct drm_encoder *encoder) 328 { 329 return -EINVAL; 330 } 331 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 332 { 333 } 334 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 335 { 336 return false; 337 } 338 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 339 { 340 return false; 341 } 342 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 343 { 344 return false; 345 } 346 static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) 347 { 348 return false; 349 } 350 351 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 352 { 353 return NULL; 354 } 355 356 static inline const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi) 357 { 358 return NULL; 359 } 360 #endif 361 362 #ifdef CONFIG_DRM_MSM_DP 363 int __init msm_dp_register(void); 364 void __exit msm_dp_unregister(void); 365 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 366 struct drm_encoder *encoder, bool yuv_supported); 367 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 368 bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 369 const struct drm_display_mode *mode); 370 bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 371 const struct drm_display_mode *mode); 372 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 373 374 #else 375 static inline int __init msm_dp_register(void) 376 { 377 return -EINVAL; 378 } 379 static inline void __exit msm_dp_unregister(void) 380 { 381 } 382 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 383 struct drm_device *dev, 384 struct drm_encoder *encoder, 385 bool yuv_supported) 386 { 387 return -EINVAL; 388 } 389 390 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 391 { 392 } 393 394 static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 395 const struct drm_display_mode *mode) 396 { 397 return false; 398 } 399 400 static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 401 const struct drm_display_mode *mode) 402 { 403 return false; 404 } 405 406 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 407 { 408 return false; 409 } 410 411 #endif 412 413 #ifdef CONFIG_DRM_MSM_MDP4 414 void msm_mdp4_register(void); 415 void msm_mdp4_unregister(void); 416 #else 417 static inline void msm_mdp4_register(void) {} 418 static inline void msm_mdp4_unregister(void) {} 419 #endif 420 421 #ifdef CONFIG_DRM_MSM_MDP5 422 void msm_mdp_register(void); 423 void msm_mdp_unregister(void); 424 #else 425 static inline void msm_mdp_register(void) {} 426 static inline void msm_mdp_unregister(void) {} 427 #endif 428 429 #ifdef CONFIG_DRM_MSM_DPU 430 void msm_dpu_register(void); 431 void msm_dpu_unregister(void); 432 #else 433 static inline void msm_dpu_register(void) {} 434 static inline void msm_dpu_unregister(void) {} 435 #endif 436 437 #ifdef CONFIG_DRM_MSM_MDSS 438 void msm_mdss_register(void); 439 void msm_mdss_unregister(void); 440 #else 441 static inline void msm_mdss_register(void) {} 442 static inline void msm_mdss_unregister(void) {} 443 #endif 444 445 #ifdef CONFIG_DEBUG_FS 446 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 447 int msm_debugfs_late_init(struct drm_device *dev); 448 int msm_rd_debugfs_init(struct drm_minor *minor); 449 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 450 __printf(3, 4) 451 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 452 const char *fmt, ...); 453 int msm_perf_debugfs_init(struct drm_minor *minor); 454 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 455 #else 456 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 457 __printf(3, 4) 458 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 459 struct msm_gem_submit *submit, 460 const char *fmt, ...) {} 461 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 462 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 463 #endif 464 465 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 466 467 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 468 const char *name); 469 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 470 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 471 phys_addr_t *size); 472 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 473 void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, 474 struct platform_device *dev, 475 const char *name); 476 477 struct icc_path *msm_icc_get(struct device *dev, const char *name); 478 479 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 480 { 481 u32 val = readl(addr); 482 483 val &= ~mask; 484 writel(val | or, addr); 485 } 486 487 /** 488 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 489 * 490 * @timer: hrtimer to control when the kthread work is triggered 491 * @work: the kthread work 492 * @worker: the kthread worker the work will be scheduled on 493 */ 494 struct msm_hrtimer_work { 495 struct hrtimer timer; 496 struct kthread_work work; 497 struct kthread_worker *worker; 498 }; 499 500 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 501 ktime_t wakeup_time, 502 enum hrtimer_mode mode); 503 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 504 struct kthread_worker *worker, 505 kthread_work_func_t fn, 506 clockid_t clock_id, 507 enum hrtimer_mode mode); 508 509 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 510 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 511 512 static inline int align_pitch(int width, int bpp) 513 { 514 int bytespp = (bpp + 7) / 8; 515 /* adreno needs pitch aligned to 32 pixels: */ 516 return bytespp * ALIGN(width, 32); 517 } 518 519 /* for the generated headers: */ 520 #define INVALID_IDX(idx) ({BUG(); 0;}) 521 #define fui(x) ({BUG(); 0;}) 522 #define _mesa_float_to_half(x) ({BUG(); 0;}) 523 524 525 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 526 527 /* for conditionally setting boolean flag(s): */ 528 #define COND(bool, val) ((bool) ? (val) : 0) 529 530 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 531 { 532 ktime_t now = ktime_get(); 533 s64 remaining_jiffies; 534 535 if (ktime_compare(*timeout, now) < 0) { 536 remaining_jiffies = 0; 537 } else { 538 ktime_t rem = ktime_sub(*timeout, now); 539 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 540 } 541 542 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 543 } 544 545 /* Driver helpers */ 546 547 extern const struct component_master_ops msm_drm_ops; 548 549 int msm_kms_pm_prepare(struct device *dev); 550 void msm_kms_pm_complete(struct device *dev); 551 552 int msm_drv_probe(struct device *dev, 553 int (*kms_init)(struct drm_device *dev), 554 struct msm_kms *kms); 555 void msm_kms_shutdown(struct platform_device *pdev); 556 557 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); 558 559 #endif /* __MSM_DRV_H__ */ 560