1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/display/drm_dsc.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 #ifdef CONFIG_FAULT_INJECTION 37 extern struct fault_attr fail_gem_alloc; 38 extern struct fault_attr fail_gem_iova; 39 #else 40 # define should_fail(attr, size) 0 41 #endif 42 43 struct msm_kms; 44 struct msm_gpu; 45 struct msm_mmu; 46 struct msm_mdss; 47 struct msm_rd_state; 48 struct msm_perf_state; 49 struct msm_gem_submit; 50 struct msm_fence_context; 51 struct msm_gem_address_space; 52 struct msm_gem_vma; 53 struct msm_disp_state; 54 55 #define MAX_CRTCS 8 56 #define MAX_BRIDGES 8 57 58 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 59 60 enum msm_dp_controller { 61 MSM_DP_CONTROLLER_0, 62 MSM_DP_CONTROLLER_1, 63 MSM_DP_CONTROLLER_2, 64 MSM_DP_CONTROLLER_3, 65 MSM_DP_CONTROLLER_COUNT, 66 }; 67 68 enum msm_dsi_controller { 69 MSM_DSI_CONTROLLER_0, 70 MSM_DSI_CONTROLLER_1, 71 MSM_DSI_CONTROLLER_COUNT, 72 }; 73 74 #define MSM_GPU_MAX_RINGS 4 75 #define MAX_H_TILES_PER_DISPLAY 2 76 77 /** 78 * struct msm_display_topology - defines a display topology pipeline 79 * @num_lm: number of layer mixers used 80 * @num_intf: number of interfaces the panel is mounted on 81 * @num_dspp: number of dspp blocks used 82 * @num_dsc: number of Display Stream Compression (DSC) blocks used 83 * @needs_cdm: indicates whether cdm block is needed for this display topology 84 */ 85 struct msm_display_topology { 86 u32 num_lm; 87 u32 num_intf; 88 u32 num_dspp; 89 u32 num_dsc; 90 bool needs_cdm; 91 }; 92 93 /* Commit/Event thread specific structure */ 94 struct msm_drm_thread { 95 struct drm_device *dev; 96 struct kthread_worker *worker; 97 }; 98 99 struct msm_drm_private { 100 101 struct drm_device *dev; 102 103 struct msm_kms *kms; 104 int (*kms_init)(struct drm_device *dev); 105 106 /* subordinate devices, if present: */ 107 struct platform_device *gpu_pdev; 108 109 /* possibly this should be in the kms component, but it is 110 * shared by both mdp4 and mdp5.. 111 */ 112 struct hdmi *hdmi; 113 114 /* DSI is shared by mdp4 and mdp5 */ 115 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; 116 117 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 118 119 /* when we have more than one 'msm_gpu' these need to be an array: */ 120 struct msm_gpu *gpu; 121 122 /* gpu is only set on open(), but we need this info earlier */ 123 bool is_a2xx; 124 bool has_cached_coherent; 125 126 struct msm_rd_state *rd; /* debugfs to dump all submits */ 127 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 128 struct msm_perf_state *perf; 129 130 /** 131 * total_mem: Total/global amount of memory backing GEM objects. 132 */ 133 atomic64_t total_mem; 134 135 /** 136 * List of all GEM objects (mainly for debugfs, protected by obj_lock 137 * (acquire before per GEM object lock) 138 */ 139 struct list_head objects; 140 struct mutex obj_lock; 141 142 /** 143 * lru: 144 * 145 * The various LRU's that a GEM object is in at various stages of 146 * it's lifetime. Objects start out in the unbacked LRU. When 147 * pinned (for scannout or permanently mapped GPU buffers, like 148 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 149 * unpinned, it moves into willneed or dontneed LRU depending on 150 * madvise state. When backing pages are evicted (willneed) or 151 * purged (dontneed) it moves back into the unbacked LRU. 152 * 153 * The dontneed LRU is considered by the shrinker for objects 154 * that are candidate for purging, and the willneed LRU is 155 * considered for objects that could be evicted. 156 */ 157 struct { 158 /** 159 * unbacked: 160 * 161 * The LRU for GEM objects without backing pages allocated. 162 * This mostly exists so that objects are always is one 163 * LRU. 164 */ 165 struct drm_gem_lru unbacked; 166 167 /** 168 * pinned: 169 * 170 * The LRU for pinned GEM objects 171 */ 172 struct drm_gem_lru pinned; 173 174 /** 175 * willneed: 176 * 177 * The LRU for unpinned GEM objects which are in madvise 178 * WILLNEED state (ie. can be evicted) 179 */ 180 struct drm_gem_lru willneed; 181 182 /** 183 * dontneed: 184 * 185 * The LRU for unpinned GEM objects which are in madvise 186 * DONTNEED state (ie. can be purged) 187 */ 188 struct drm_gem_lru dontneed; 189 190 /** 191 * lock: 192 * 193 * Protects manipulation of all of the LRUs. 194 */ 195 struct mutex lock; 196 } lru; 197 198 struct workqueue_struct *wq; 199 200 unsigned int num_crtcs; 201 202 struct msm_drm_thread event_thread[MAX_CRTCS]; 203 204 /* VRAM carveout, used when no IOMMU: */ 205 struct { 206 unsigned long size; 207 dma_addr_t paddr; 208 /* NOTE: mm managed at the page level, size is in # of pages 209 * and position mm_node->start is in # of pages: 210 */ 211 struct drm_mm mm; 212 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 213 } vram; 214 215 struct notifier_block vmap_notifier; 216 struct shrinker *shrinker; 217 218 struct drm_atomic_state *pm_state; 219 220 /** 221 * hangcheck_period: For hang detection, in ms 222 * 223 * Note that in practice, a submit/job will get at least two hangcheck 224 * periods, due to checking for progress being implemented as simply 225 * "have the CP position registers changed since last time?" 226 */ 227 unsigned int hangcheck_period; 228 229 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 230 struct devfreq_simple_ondemand_data gpu_devfreq_config; 231 232 /** 233 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 234 */ 235 bool gpu_clamp_to_idle; 236 237 /** 238 * disable_err_irq: 239 * 240 * Disable handling of GPU hw error interrupts, to force fallback to 241 * sw hangcheck timer. Written (via debugfs) by igt tests to test 242 * the sw hangcheck mechanism. 243 */ 244 bool disable_err_irq; 245 }; 246 247 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); 248 249 struct msm_pending_timer; 250 251 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 252 struct msm_kms *kms, int crtc_idx); 253 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 254 void msm_atomic_commit_tail(struct drm_atomic_state *state); 255 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 256 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 257 void msm_atomic_state_clear(struct drm_atomic_state *state); 258 void msm_atomic_state_free(struct drm_atomic_state *state); 259 260 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 261 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 262 263 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 264 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 265 266 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 267 bool msm_use_mmu(struct drm_device *dev); 268 269 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 270 struct drm_file *file); 271 272 #ifdef CONFIG_DEBUG_FS 273 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 274 #endif 275 276 int msm_gem_shrinker_init(struct drm_device *dev); 277 void msm_gem_shrinker_cleanup(struct drm_device *dev); 278 279 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 280 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 281 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 282 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 283 struct dma_buf_attachment *attach, struct sg_table *sg); 284 int msm_gem_prime_pin(struct drm_gem_object *obj); 285 void msm_gem_prime_unpin(struct drm_gem_object *obj); 286 287 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 288 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 289 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 290 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 291 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 292 struct msm_gem_address_space *aspace, int plane); 293 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 294 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 295 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 296 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 297 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 298 int w, int h, int p, uint32_t format); 299 300 #ifdef CONFIG_DRM_FBDEV_EMULATION 301 void msm_fbdev_setup(struct drm_device *dev); 302 #else 303 static inline void msm_fbdev_setup(struct drm_device *dev) 304 { 305 } 306 #endif 307 308 struct hdmi; 309 #ifdef CONFIG_DRM_MSM_HDMI 310 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 311 struct drm_encoder *encoder); 312 void __init msm_hdmi_register(void); 313 void __exit msm_hdmi_unregister(void); 314 #else 315 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 316 struct drm_encoder *encoder) 317 { 318 return -EINVAL; 319 } 320 static inline void __init msm_hdmi_register(void) {} 321 static inline void __exit msm_hdmi_unregister(void) {} 322 #endif 323 324 struct msm_dsi; 325 #ifdef CONFIG_DRM_MSM_DSI 326 int dsi_dev_attach(struct platform_device *pdev); 327 void dsi_dev_detach(struct platform_device *pdev); 328 void __init msm_dsi_register(void); 329 void __exit msm_dsi_unregister(void); 330 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 331 struct drm_encoder *encoder); 332 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 333 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 334 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 335 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 336 bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); 337 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 338 #else 339 static inline void __init msm_dsi_register(void) 340 { 341 } 342 static inline void __exit msm_dsi_unregister(void) 343 { 344 } 345 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 346 struct drm_device *dev, 347 struct drm_encoder *encoder) 348 { 349 return -EINVAL; 350 } 351 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 352 { 353 } 354 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 355 { 356 return false; 357 } 358 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 359 { 360 return false; 361 } 362 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 363 { 364 return false; 365 } 366 static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) 367 { 368 return false; 369 } 370 371 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 372 { 373 return NULL; 374 } 375 #endif 376 377 #ifdef CONFIG_DRM_MSM_DP 378 int __init msm_dp_register(void); 379 void __exit msm_dp_unregister(void); 380 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 381 struct drm_encoder *encoder, bool yuv_supported); 382 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 383 bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 384 const struct drm_display_mode *mode); 385 bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 386 const struct drm_display_mode *mode); 387 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 388 389 #else 390 static inline int __init msm_dp_register(void) 391 { 392 return -EINVAL; 393 } 394 static inline void __exit msm_dp_unregister(void) 395 { 396 } 397 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 398 struct drm_device *dev, 399 struct drm_encoder *encoder, 400 bool yuv_supported) 401 { 402 return -EINVAL; 403 } 404 405 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 406 { 407 } 408 409 static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 410 const struct drm_display_mode *mode) 411 { 412 return false; 413 } 414 415 static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 416 const struct drm_display_mode *mode) 417 { 418 return false; 419 } 420 421 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 422 { 423 return false; 424 } 425 426 #endif 427 428 #ifdef CONFIG_DRM_MSM_MDP4 429 void msm_mdp4_register(void); 430 void msm_mdp4_unregister(void); 431 #else 432 static inline void msm_mdp4_register(void) {} 433 static inline void msm_mdp4_unregister(void) {} 434 #endif 435 436 #ifdef CONFIG_DRM_MSM_MDP5 437 void msm_mdp_register(void); 438 void msm_mdp_unregister(void); 439 #else 440 static inline void msm_mdp_register(void) {} 441 static inline void msm_mdp_unregister(void) {} 442 #endif 443 444 #ifdef CONFIG_DRM_MSM_DPU 445 void msm_dpu_register(void); 446 void msm_dpu_unregister(void); 447 #else 448 static inline void msm_dpu_register(void) {} 449 static inline void msm_dpu_unregister(void) {} 450 #endif 451 452 #ifdef CONFIG_DRM_MSM_MDSS 453 void msm_mdss_register(void); 454 void msm_mdss_unregister(void); 455 #else 456 static inline void msm_mdss_register(void) {} 457 static inline void msm_mdss_unregister(void) {} 458 #endif 459 460 #ifdef CONFIG_DEBUG_FS 461 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 462 int msm_debugfs_late_init(struct drm_device *dev); 463 int msm_rd_debugfs_init(struct drm_minor *minor); 464 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 465 __printf(3, 4) 466 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 467 const char *fmt, ...); 468 int msm_perf_debugfs_init(struct drm_minor *minor); 469 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 470 #else 471 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 472 __printf(3, 4) 473 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 474 struct msm_gem_submit *submit, 475 const char *fmt, ...) {} 476 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 477 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 478 #endif 479 480 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 481 482 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 483 const char *name); 484 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 485 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 486 phys_addr_t *size); 487 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 488 void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, 489 struct platform_device *dev, 490 const char *name); 491 492 struct icc_path *msm_icc_get(struct device *dev, const char *name); 493 494 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 495 { 496 u32 val = readl(addr); 497 498 val &= ~mask; 499 writel(val | or, addr); 500 } 501 502 /** 503 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 504 * 505 * @timer: hrtimer to control when the kthread work is triggered 506 * @work: the kthread work 507 * @worker: the kthread worker the work will be scheduled on 508 */ 509 struct msm_hrtimer_work { 510 struct hrtimer timer; 511 struct kthread_work work; 512 struct kthread_worker *worker; 513 }; 514 515 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 516 ktime_t wakeup_time, 517 enum hrtimer_mode mode); 518 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 519 struct kthread_worker *worker, 520 kthread_work_func_t fn, 521 clockid_t clock_id, 522 enum hrtimer_mode mode); 523 524 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 525 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 526 527 static inline int align_pitch(int width, int bpp) 528 { 529 int bytespp = (bpp + 7) / 8; 530 /* adreno needs pitch aligned to 32 pixels: */ 531 return bytespp * ALIGN(width, 32); 532 } 533 534 /* for the generated headers: */ 535 #define INVALID_IDX(idx) ({BUG(); 0;}) 536 #define fui(x) ({BUG(); 0;}) 537 #define _mesa_float_to_half(x) ({BUG(); 0;}) 538 539 540 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 541 542 /* for conditionally setting boolean flag(s): */ 543 #define COND(bool, val) ((bool) ? (val) : 0) 544 545 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 546 { 547 ktime_t now = ktime_get(); 548 s64 remaining_jiffies; 549 550 if (ktime_compare(*timeout, now) < 0) { 551 remaining_jiffies = 0; 552 } else { 553 ktime_t rem = ktime_sub(*timeout, now); 554 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 555 } 556 557 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 558 } 559 560 /* Driver helpers */ 561 562 extern const struct component_master_ops msm_drm_ops; 563 564 int msm_kms_pm_prepare(struct device *dev); 565 void msm_kms_pm_complete(struct device *dev); 566 567 int msm_drv_probe(struct device *dev, 568 int (*kms_init)(struct drm_device *dev), 569 struct msm_kms *kms); 570 void msm_kms_shutdown(struct platform_device *pdev); 571 572 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); 573 574 #endif /* __MSM_DRV_H__ */ 575