1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_print.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/display/drm_dsc.h> 34 #include <drm/msm_drm.h> 35 #include <drm/drm_gem.h> 36 37 extern struct fault_attr fail_gem_alloc; 38 extern struct fault_attr fail_gem_iova; 39 40 struct drm_fb_helper; 41 struct drm_fb_helper_surface_size; 42 43 struct msm_kms; 44 struct msm_gpu; 45 struct msm_mmu; 46 struct msm_mdss; 47 struct msm_rd_state; 48 struct msm_perf_state; 49 struct msm_gem_submit; 50 struct msm_fence_context; 51 struct msm_disp_state; 52 53 #define MAX_CRTCS 8 54 55 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 56 57 enum msm_dp_controller { 58 MSM_DP_CONTROLLER_0, 59 MSM_DP_CONTROLLER_1, 60 MSM_DP_CONTROLLER_2, 61 MSM_DP_CONTROLLER_3, 62 MSM_DP_CONTROLLER_COUNT, 63 }; 64 65 enum msm_dsi_controller { 66 MSM_DSI_CONTROLLER_0, 67 MSM_DSI_CONTROLLER_1, 68 MSM_DSI_CONTROLLER_COUNT, 69 }; 70 71 #define MSM_GPU_MAX_RINGS 4 72 73 struct msm_drm_private { 74 75 struct drm_device *dev; 76 77 struct msm_kms *kms; 78 int (*kms_init)(struct drm_device *dev); 79 80 /* subordinate devices, if present: */ 81 struct platform_device *gpu_pdev; 82 83 /* when we have more than one 'msm_gpu' these need to be an array: */ 84 struct msm_gpu *gpu; 85 86 /* gpu is only set on open(), but we need this info earlier */ 87 bool is_a2xx; 88 bool has_cached_coherent; 89 90 struct msm_rd_state *rd; /* debugfs to dump all submits */ 91 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 92 struct msm_perf_state *perf; 93 94 /** 95 * total_mem: Total/global amount of memory backing GEM objects. 96 */ 97 atomic64_t total_mem; 98 99 /** 100 * List of all GEM objects (mainly for debugfs, protected by obj_lock 101 * (acquire before per GEM object lock) 102 */ 103 struct list_head objects; 104 struct mutex obj_lock; 105 106 /** 107 * lru: 108 * 109 * The various LRU's that a GEM object is in at various stages of 110 * it's lifetime. Objects start out in the unbacked LRU. When 111 * pinned (for scannout or permanently mapped GPU buffers, like 112 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 113 * unpinned, it moves into willneed or dontneed LRU depending on 114 * madvise state. When backing pages are evicted (willneed) or 115 * purged (dontneed) it moves back into the unbacked LRU. 116 * 117 * The dontneed LRU is considered by the shrinker for objects 118 * that are candidate for purging, and the willneed LRU is 119 * considered for objects that could be evicted. 120 */ 121 struct { 122 /** 123 * unbacked: 124 * 125 * The LRU for GEM objects without backing pages allocated. 126 * This mostly exists so that objects are always is one 127 * LRU. 128 */ 129 struct drm_gem_lru unbacked; 130 131 /** 132 * pinned: 133 * 134 * The LRU for pinned GEM objects 135 */ 136 struct drm_gem_lru pinned; 137 138 /** 139 * willneed: 140 * 141 * The LRU for unpinned GEM objects which are in madvise 142 * WILLNEED state (ie. can be evicted) 143 */ 144 struct drm_gem_lru willneed; 145 146 /** 147 * dontneed: 148 * 149 * The LRU for unpinned GEM objects which are in madvise 150 * DONTNEED state (ie. can be purged) 151 */ 152 struct drm_gem_lru dontneed; 153 } lru; 154 155 struct notifier_block vmap_notifier; 156 struct shrinker *shrinker; 157 158 /** 159 * hangcheck_period: For hang detection, in ms 160 * 161 * Note that in practice, a submit/job will get at least two hangcheck 162 * periods, due to checking for progress being implemented as simply 163 * "have the CP position registers changed since last time?" 164 */ 165 unsigned int hangcheck_period; 166 167 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 168 struct devfreq_simple_ondemand_data gpu_devfreq_config; 169 170 /** 171 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 172 */ 173 bool gpu_clamp_to_idle; 174 175 /** 176 * disable_err_irq: 177 * 178 * Disable handling of GPU hw error interrupts, to force fallback to 179 * sw hangcheck timer. Written (via debugfs) by igt tests to test 180 * the sw hangcheck mechanism. 181 */ 182 bool disable_err_irq; 183 184 /** 185 * @fault_stall_lock: 186 * 187 * Serialize changes to stall-on-fault state. 188 */ 189 spinlock_t fault_stall_lock; 190 191 /** 192 * @fault_stall_reenable_time: 193 * 194 * If stall_enabled is false, when to reenable stall-on-fault. 195 * Protected by @fault_stall_lock. 196 */ 197 ktime_t stall_reenable_time; 198 199 /** 200 * @stall_enabled: 201 * 202 * Whether stall-on-fault is currently enabled. Protected by 203 * @fault_stall_lock. 204 */ 205 bool stall_enabled; 206 }; 207 208 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); 209 210 struct msm_pending_timer; 211 212 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 213 struct msm_kms *kms, int crtc_idx); 214 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 215 void msm_atomic_commit_tail(struct drm_atomic_state *state); 216 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 217 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 218 219 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 220 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 221 222 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 223 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 224 225 struct drm_gpuvm *msm_kms_init_vm(struct drm_device *dev, struct device *mdss_dev); 226 bool msm_use_mmu(struct drm_device *dev); 227 228 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 229 struct drm_file *file); 230 int msm_ioctl_vm_bind(struct drm_device *dev, void *data, 231 struct drm_file *file); 232 233 #ifdef CONFIG_DEBUG_FS 234 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 235 #endif 236 237 int msm_gem_shrinker_init(struct drm_device *dev); 238 void msm_gem_shrinker_cleanup(struct drm_device *dev); 239 240 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 241 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 242 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 243 struct drm_gem_object *msm_gem_prime_import(struct drm_device *dev, struct dma_buf *buf); 244 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 245 struct dma_buf_attachment *attach, struct sg_table *sg); 246 struct dma_buf *msm_gem_prime_export(struct drm_gem_object *obj, int flags); 247 int msm_gem_prime_pin(struct drm_gem_object *obj); 248 void msm_gem_prime_unpin(struct drm_gem_object *obj); 249 250 int msm_framebuffer_prepare(struct drm_framebuffer *fb, bool needs_dirtyfb); 251 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, bool needed_dirtyfb); 252 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int plane); 253 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 254 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 255 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 256 struct drm_file *file, const struct drm_format_info *info, 257 const struct drm_mode_fb_cmd2 *mode_cmd); 258 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 259 int w, int h, int p, uint32_t format); 260 261 #ifdef CONFIG_DRM_MSM_KMS_FBDEV 262 int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, 263 struct drm_fb_helper_surface_size *sizes); 264 #define MSM_FBDEV_DRIVER_OPS \ 265 .fbdev_probe = msm_fbdev_driver_fbdev_probe 266 #else 267 #define MSM_FBDEV_DRIVER_OPS \ 268 .fbdev_probe = NULL 269 #endif 270 271 struct hdmi; 272 #ifdef CONFIG_DRM_MSM_HDMI 273 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 274 struct drm_encoder *encoder); 275 void __init msm_hdmi_register(void); 276 void __exit msm_hdmi_unregister(void); 277 #else 278 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 279 struct drm_encoder *encoder) 280 { 281 return -EINVAL; 282 } 283 static inline void __init msm_hdmi_register(void) {} 284 static inline void __exit msm_hdmi_unregister(void) {} 285 #endif 286 287 struct msm_dsi; 288 #ifdef CONFIG_DRM_MSM_DSI 289 int dsi_dev_attach(struct platform_device *pdev); 290 void dsi_dev_detach(struct platform_device *pdev); 291 void __init msm_dsi_register(void); 292 void __exit msm_dsi_unregister(void); 293 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 294 struct drm_encoder *encoder); 295 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 296 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 297 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 298 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 299 bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); 300 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 301 const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi); 302 #else 303 static inline void __init msm_dsi_register(void) 304 { 305 } 306 static inline void __exit msm_dsi_unregister(void) 307 { 308 } 309 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 310 struct drm_device *dev, 311 struct drm_encoder *encoder) 312 { 313 return -EINVAL; 314 } 315 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 316 { 317 } 318 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 319 { 320 return false; 321 } 322 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 323 { 324 return false; 325 } 326 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 327 { 328 return false; 329 } 330 static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) 331 { 332 return false; 333 } 334 335 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 336 { 337 return NULL; 338 } 339 340 static inline const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi) 341 { 342 return NULL; 343 } 344 #endif 345 346 struct msm_dp; 347 #ifdef CONFIG_DRM_MSM_DP 348 int __init msm_dp_register(void); 349 void __exit msm_dp_unregister(void); 350 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 351 struct drm_encoder *encoder, bool yuv_supported); 352 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 353 bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 354 const struct drm_display_mode *mode); 355 bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 356 const struct drm_display_mode *mode); 357 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 358 359 #else 360 static inline int __init msm_dp_register(void) 361 { 362 return -EINVAL; 363 } 364 static inline void __exit msm_dp_unregister(void) 365 { 366 } 367 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 368 struct drm_device *dev, 369 struct drm_encoder *encoder, 370 bool yuv_supported) 371 { 372 return -EINVAL; 373 } 374 375 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 376 { 377 } 378 379 static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 380 const struct drm_display_mode *mode) 381 { 382 return false; 383 } 384 385 static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 386 const struct drm_display_mode *mode) 387 { 388 return false; 389 } 390 391 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 392 { 393 return false; 394 } 395 396 #endif 397 398 #ifdef CONFIG_DRM_MSM_MDP4 399 void msm_mdp4_register(void); 400 void msm_mdp4_unregister(void); 401 #else 402 static inline void msm_mdp4_register(void) {} 403 static inline void msm_mdp4_unregister(void) {} 404 #endif 405 406 #ifdef CONFIG_DRM_MSM_MDP5 407 void msm_mdp_register(void); 408 void msm_mdp_unregister(void); 409 #else 410 static inline void msm_mdp_register(void) {} 411 static inline void msm_mdp_unregister(void) {} 412 #endif 413 414 #ifdef CONFIG_DRM_MSM_DPU 415 void msm_dpu_register(void); 416 void msm_dpu_unregister(void); 417 #else 418 static inline void msm_dpu_register(void) {} 419 static inline void msm_dpu_unregister(void) {} 420 #endif 421 422 #ifdef CONFIG_DRM_MSM_MDSS 423 void msm_mdss_register(void); 424 void msm_mdss_unregister(void); 425 #else 426 static inline void msm_mdss_register(void) {} 427 static inline void msm_mdss_unregister(void) {} 428 #endif 429 430 #ifdef CONFIG_DEBUG_FS 431 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 432 int msm_debugfs_late_init(struct drm_device *dev); 433 int msm_rd_debugfs_init(struct drm_minor *minor); 434 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 435 __printf(3, 4) 436 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 437 const char *fmt, ...); 438 int msm_perf_debugfs_init(struct drm_minor *minor); 439 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 440 #else 441 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 442 __printf(3, 4) 443 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 444 struct msm_gem_submit *submit, 445 const char *fmt, ...) {} 446 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 447 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 448 #endif 449 450 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 451 452 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 453 const char *name); 454 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 455 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 456 phys_addr_t *size); 457 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 458 void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, 459 struct platform_device *dev, 460 const char *name); 461 462 struct icc_path *msm_icc_get(struct device *dev, const char *name); 463 464 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 465 { 466 u32 val = readl(addr); 467 468 val &= ~mask; 469 writel(val | or, addr); 470 } 471 472 /** 473 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 474 * 475 * @timer: hrtimer to control when the kthread work is triggered 476 * @work: the kthread work 477 * @worker: the kthread worker the work will be scheduled on 478 */ 479 struct msm_hrtimer_work { 480 struct hrtimer timer; 481 struct kthread_work work; 482 struct kthread_worker *worker; 483 }; 484 485 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 486 ktime_t wakeup_time, 487 enum hrtimer_mode mode); 488 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 489 struct kthread_worker *worker, 490 kthread_work_func_t fn, 491 clockid_t clock_id, 492 enum hrtimer_mode mode); 493 494 /* Helper for returning a UABI error with optional logging which can make 495 * it easier for userspace to understand what it is doing wrong. 496 */ 497 #define UERR(err, drm, fmt, ...) \ 498 ({ DRM_DEV_DEBUG_DRIVER((drm)->dev, fmt, ##__VA_ARGS__); -(err); }) 499 500 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 501 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 502 503 static inline int align_pitch(int width, int bpp) 504 { 505 int bytespp = (bpp + 7) / 8; 506 /* adreno needs pitch aligned to 32 pixels: */ 507 return bytespp * ALIGN(width, 32); 508 } 509 510 /* for the generated headers: */ 511 #define INVALID_IDX(idx) ({BUG(); 0;}) 512 #define fui(x) ({BUG(); 0;}) 513 #define _mesa_float_to_half(x) ({BUG(); 0;}) 514 515 516 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 517 518 /* for conditionally setting boolean flag(s): */ 519 #define COND(bool, val) ((bool) ? (val) : 0) 520 521 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 522 { 523 ktime_t now = ktime_get(); 524 525 if (ktime_compare(*timeout, now) <= 0) 526 return 0; 527 528 ktime_t rem = ktime_sub(*timeout, now); 529 s64 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 530 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 531 } 532 533 /* Driver helpers */ 534 535 extern const struct component_master_ops msm_drm_ops; 536 537 int msm_kms_pm_prepare(struct device *dev); 538 void msm_kms_pm_complete(struct device *dev); 539 540 int msm_gpu_probe(struct platform_device *pdev, 541 const struct component_ops *ops); 542 void msm_gpu_remove(struct platform_device *pdev, 543 const struct component_ops *ops); 544 int msm_drv_probe(struct device *dev, 545 int (*kms_init)(struct drm_device *dev), 546 struct msm_kms *kms); 547 void msm_kms_shutdown(struct platform_device *pdev); 548 549 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); 550 551 bool msm_gpu_no_components(void); 552 553 #endif /* __MSM_DRV_H__ */ 554