1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_print.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/display/drm_dsc.h> 34 #include <drm/msm_drm.h> 35 #include <drm/drm_gem.h> 36 37 extern struct fault_attr fail_gem_alloc; 38 extern struct fault_attr fail_gem_iova; 39 40 struct drm_fb_helper; 41 struct drm_fb_helper_surface_size; 42 43 struct msm_kms; 44 struct msm_gpu; 45 struct msm_mmu; 46 struct msm_mdss; 47 struct msm_rd_state; 48 struct msm_gem_submit; 49 struct msm_fence_context; 50 struct msm_disp_state; 51 52 #define MAX_CRTCS 8 53 54 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 55 56 enum msm_dp_controller { 57 MSM_DP_CONTROLLER_0, 58 MSM_DP_CONTROLLER_1, 59 MSM_DP_CONTROLLER_2, 60 MSM_DP_CONTROLLER_3, 61 MSM_DP_CONTROLLER_COUNT, 62 }; 63 64 enum msm_dsi_controller { 65 MSM_DSI_CONTROLLER_0, 66 MSM_DSI_CONTROLLER_1, 67 MSM_DSI_CONTROLLER_COUNT, 68 }; 69 70 #define MSM_GPU_MAX_RINGS 4 71 72 struct msm_drm_private { 73 74 struct drm_device *dev; 75 76 struct msm_kms *kms; 77 int (*kms_init)(struct drm_device *dev); 78 79 /* subordinate devices, if present: */ 80 struct platform_device *gpu_pdev; 81 82 /* when we have more than one 'msm_gpu' these need to be an array: */ 83 struct msm_gpu *gpu; 84 85 /* gpu is only set on open(), but we need this info earlier */ 86 bool is_a2xx; 87 bool has_cached_coherent; 88 89 struct msm_rd_state *rd; /* debugfs to dump all submits */ 90 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 91 92 /** 93 * total_mem: Total/global amount of memory backing GEM objects. 94 */ 95 atomic64_t total_mem; 96 97 /** 98 * List of all GEM objects (mainly for debugfs, protected by obj_lock 99 * (acquire before per GEM object lock) 100 */ 101 struct list_head objects; 102 struct mutex obj_lock; 103 104 /** 105 * lru: 106 * 107 * The various LRU's that a GEM object is in at various stages of 108 * it's lifetime. Objects start out in the unbacked LRU. When 109 * pinned (for scannout or permanently mapped GPU buffers, like 110 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 111 * unpinned, it moves into willneed or dontneed LRU depending on 112 * madvise state. When backing pages are evicted (willneed) or 113 * purged (dontneed) it moves back into the unbacked LRU. 114 * 115 * The dontneed LRU is considered by the shrinker for objects 116 * that are candidate for purging, and the willneed LRU is 117 * considered for objects that could be evicted. 118 */ 119 struct { 120 /** 121 * unbacked: 122 * 123 * The LRU for GEM objects without backing pages allocated. 124 * This mostly exists so that objects are always is one 125 * LRU. 126 */ 127 struct drm_gem_lru unbacked; 128 129 /** 130 * pinned: 131 * 132 * The LRU for pinned GEM objects 133 */ 134 struct drm_gem_lru pinned; 135 136 /** 137 * willneed: 138 * 139 * The LRU for unpinned GEM objects which are in madvise 140 * WILLNEED state (ie. can be evicted) 141 */ 142 struct drm_gem_lru willneed; 143 144 /** 145 * dontneed: 146 * 147 * The LRU for unpinned GEM objects which are in madvise 148 * DONTNEED state (ie. can be purged) 149 */ 150 struct drm_gem_lru dontneed; 151 } lru; 152 153 struct notifier_block vmap_notifier; 154 struct shrinker *shrinker; 155 156 /** 157 * hangcheck_period: For hang detection, in ms 158 * 159 * Note that in practice, a submit/job will get at least two hangcheck 160 * periods, due to checking for progress being implemented as simply 161 * "have the CP position registers changed since last time?" 162 */ 163 unsigned int hangcheck_period; 164 165 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 166 struct devfreq_simple_ondemand_data gpu_devfreq_config; 167 168 /** 169 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 170 */ 171 bool gpu_clamp_to_idle; 172 173 /** 174 * disable_err_irq: 175 * 176 * Disable handling of GPU hw error interrupts, to force fallback to 177 * sw hangcheck timer. Written (via debugfs) by igt tests to test 178 * the sw hangcheck mechanism. 179 */ 180 bool disable_err_irq; 181 182 /** 183 * @fault_stall_lock: 184 * 185 * Serialize changes to stall-on-fault state. 186 */ 187 spinlock_t fault_stall_lock; 188 189 /** 190 * @fault_stall_reenable_time: 191 * 192 * If stall_enabled is false, when to reenable stall-on-fault. 193 * Protected by @fault_stall_lock. 194 */ 195 ktime_t stall_reenable_time; 196 197 /** 198 * @stall_enabled: 199 * 200 * Whether stall-on-fault is currently enabled. Protected by 201 * @fault_stall_lock. 202 */ 203 bool stall_enabled; 204 }; 205 206 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); 207 208 struct msm_pending_timer; 209 210 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 211 struct msm_kms *kms, int crtc_idx); 212 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 213 void msm_atomic_commit_tail(struct drm_atomic_commit *state); 214 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_commit *state); 215 struct drm_atomic_commit *msm_atomic_state_alloc(struct drm_device *dev); 216 217 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 218 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 219 220 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 221 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 222 223 struct drm_gpuvm *msm_kms_init_vm(struct drm_device *dev, struct device *mdss_dev); 224 bool msm_use_mmu(struct drm_device *dev); 225 226 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 227 struct drm_file *file); 228 int msm_ioctl_vm_bind(struct drm_device *dev, void *data, 229 struct drm_file *file); 230 231 int msm_perfcntr_resume(struct msm_gpu *gpu); 232 void msm_perfcntr_suspend(struct msm_gpu *gpu); 233 int msm_ioctl_perfcntr_config(struct drm_device *dev, void *data, 234 struct drm_file *file); 235 236 struct msm_perfcntr_state * msm_perfcntr_init(struct msm_gpu *gpu); 237 void msm_perfcntr_cleanup(struct msm_gpu *gpu); 238 239 #ifdef CONFIG_DEBUG_FS 240 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 241 #endif 242 243 int msm_gem_shrinker_init(struct drm_device *dev); 244 void msm_gem_shrinker_cleanup(struct drm_device *dev); 245 246 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 247 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 248 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 249 struct drm_gem_object *msm_gem_prime_import(struct drm_device *dev, struct dma_buf *buf); 250 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 251 struct dma_buf_attachment *attach, struct sg_table *sg); 252 struct dma_buf *msm_gem_prime_export(struct drm_gem_object *obj, int flags); 253 int msm_gem_prime_pin(struct drm_gem_object *obj); 254 void msm_gem_prime_unpin(struct drm_gem_object *obj); 255 256 int msm_framebuffer_prepare(struct drm_framebuffer *fb, bool needs_dirtyfb); 257 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, bool needed_dirtyfb); 258 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int plane); 259 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 260 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 261 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 262 struct drm_file *file, const struct drm_format_info *info, 263 const struct drm_mode_fb_cmd2 *mode_cmd); 264 265 #ifdef CONFIG_DRM_MSM_KMS_FBDEV 266 int msm_fbdev_driver_fbdev_probe(struct drm_fb_helper *helper, 267 struct drm_fb_helper_surface_size *sizes); 268 #define MSM_FBDEV_DRIVER_OPS \ 269 .fbdev_probe = msm_fbdev_driver_fbdev_probe 270 #else 271 #define MSM_FBDEV_DRIVER_OPS \ 272 .fbdev_probe = NULL 273 #endif 274 275 struct hdmi; 276 #ifdef CONFIG_DRM_MSM_HDMI 277 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 278 struct drm_encoder *encoder); 279 void __init msm_hdmi_register(void); 280 void __exit msm_hdmi_unregister(void); 281 #else 282 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 283 struct drm_encoder *encoder) 284 { 285 return -EINVAL; 286 } 287 static inline void __init msm_hdmi_register(void) {} 288 static inline void __exit msm_hdmi_unregister(void) {} 289 #endif 290 291 struct msm_dsi; 292 #ifdef CONFIG_DRM_MSM_DSI 293 int dsi_dev_attach(struct platform_device *pdev); 294 void dsi_dev_detach(struct platform_device *pdev); 295 void __init msm_dsi_register(void); 296 void __exit msm_dsi_unregister(void); 297 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 298 struct drm_encoder *encoder); 299 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 300 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 301 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 302 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 303 bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); 304 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 305 const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi); 306 #else 307 static inline void __init msm_dsi_register(void) 308 { 309 } 310 static inline void __exit msm_dsi_unregister(void) 311 { 312 } 313 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 314 struct drm_device *dev, 315 struct drm_encoder *encoder) 316 { 317 return -EINVAL; 318 } 319 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 320 { 321 } 322 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 323 { 324 return false; 325 } 326 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 327 { 328 return false; 329 } 330 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 331 { 332 return false; 333 } 334 static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) 335 { 336 return false; 337 } 338 339 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 340 { 341 return NULL; 342 } 343 344 static inline const char *msm_dsi_get_te_source(struct msm_dsi *msm_dsi) 345 { 346 return NULL; 347 } 348 #endif 349 350 struct msm_dp; 351 #ifdef CONFIG_DRM_MSM_DP 352 int __init msm_dp_register(void); 353 void __exit msm_dp_unregister(void); 354 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 355 struct drm_encoder *encoder, bool yuv_supported); 356 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 357 bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 358 const struct drm_display_mode *mode); 359 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 360 361 #else 362 static inline int __init msm_dp_register(void) 363 { 364 return -EINVAL; 365 } 366 static inline void __exit msm_dp_unregister(void) 367 { 368 } 369 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 370 struct drm_device *dev, 371 struct drm_encoder *encoder, 372 bool yuv_supported) 373 { 374 return -EINVAL; 375 } 376 377 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 378 { 379 } 380 381 static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 382 const struct drm_display_mode *mode) 383 { 384 return false; 385 } 386 387 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 388 { 389 return false; 390 } 391 392 #endif 393 394 #ifdef CONFIG_DRM_MSM_MDP4 395 void msm_mdp4_register(void); 396 void msm_mdp4_unregister(void); 397 #else 398 static inline void msm_mdp4_register(void) {} 399 static inline void msm_mdp4_unregister(void) {} 400 #endif 401 402 #ifdef CONFIG_DRM_MSM_MDP5 403 void msm_mdp_register(void); 404 void msm_mdp_unregister(void); 405 #else 406 static inline void msm_mdp_register(void) {} 407 static inline void msm_mdp_unregister(void) {} 408 #endif 409 410 #ifdef CONFIG_DRM_MSM_DPU 411 void msm_dpu_register(void); 412 void msm_dpu_unregister(void); 413 #else 414 static inline void msm_dpu_register(void) {} 415 static inline void msm_dpu_unregister(void) {} 416 #endif 417 418 #ifdef CONFIG_DRM_MSM_MDSS 419 void msm_mdss_register(void); 420 void msm_mdss_unregister(void); 421 #else 422 static inline void msm_mdss_register(void) {} 423 static inline void msm_mdss_unregister(void) {} 424 #endif 425 426 #ifdef CONFIG_DEBUG_FS 427 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 428 int msm_debugfs_late_init(struct drm_device *dev); 429 int msm_rd_debugfs_init(struct drm_minor *minor); 430 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 431 __printf(3, 4) 432 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 433 const char *fmt, ...); 434 #else 435 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 436 __printf(3, 4) 437 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 438 struct msm_gem_submit *submit, 439 const char *fmt, ...) {} 440 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 441 #endif 442 443 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 444 445 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 446 const char *name); 447 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 448 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 449 phys_addr_t *size); 450 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 451 void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, 452 struct platform_device *dev, 453 const char *name); 454 455 struct icc_path *msm_icc_get(struct device *dev, const char *name); 456 457 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 458 { 459 u32 val = readl(addr); 460 461 val &= ~mask; 462 writel(val | or, addr); 463 } 464 465 /** 466 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 467 * 468 * @timer: hrtimer to control when the kthread work is triggered 469 * @work: the kthread work 470 * @worker: the kthread worker the work will be scheduled on 471 */ 472 struct msm_hrtimer_work { 473 struct hrtimer timer; 474 struct kthread_work work; 475 struct kthread_worker *worker; 476 }; 477 478 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 479 ktime_t wakeup_time, 480 enum hrtimer_mode mode); 481 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 482 struct kthread_worker *worker, 483 kthread_work_func_t fn, 484 clockid_t clock_id, 485 enum hrtimer_mode mode); 486 487 /* Helper for returning a UABI error with optional logging which can make 488 * it easier for userspace to understand what it is doing wrong. 489 */ 490 #define UERR(err, drm, fmt, ...) \ 491 ({ DRM_DEV_DEBUG_DRIVER((drm)->dev, fmt, ##__VA_ARGS__); -(err); }) 492 493 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 494 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 495 496 /* for the generated headers: */ 497 #define INVALID_IDX(idx) ({BUG(); 0;}) 498 #define fui(x) ({BUG(); 0;}) 499 #define _mesa_float_to_half(x) ({BUG(); 0;}) 500 501 502 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 503 504 /* for conditionally setting boolean flag(s): */ 505 #define COND(bool, val) ((bool) ? (val) : 0) 506 507 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 508 { 509 ktime_t now = ktime_get(); 510 511 if (ktime_compare(*timeout, now) <= 0) 512 return 0; 513 514 ktime_t rem = ktime_sub(*timeout, now); 515 s64 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 516 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 517 } 518 519 /* Driver helpers */ 520 521 extern const struct component_master_ops msm_drm_ops; 522 523 int msm_kms_pm_prepare(struct device *dev); 524 void msm_kms_pm_complete(struct device *dev); 525 526 int msm_gpu_probe(struct platform_device *pdev, 527 const struct component_ops *ops); 528 void msm_gpu_remove(struct platform_device *pdev, 529 const struct component_ops *ops); 530 int msm_drv_probe(struct device *dev, 531 int (*kms_init)(struct drm_device *dev), 532 struct msm_kms *kms); 533 void msm_kms_shutdown(struct platform_device *pdev); 534 535 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); 536 537 bool msm_gpu_no_components(void); 538 539 #endif /* __MSM_DRV_H__ */ 540