1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #ifndef __MSM_DRV_H__ 9 #define __MSM_DRV_H__ 10 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/cpufreq.h> 14 #include <linux/devfreq.h> 15 #include <linux/module.h> 16 #include <linux/component.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 #include <linux/list.h> 22 #include <linux/iommu.h> 23 #include <linux/types.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_device.h> 26 #include <linux/sizes.h> 27 #include <linux/kthread.h> 28 29 #include <drm/drm_atomic.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/display/drm_dsc.h> 33 #include <drm/msm_drm.h> 34 #include <drm/drm_gem.h> 35 36 #ifdef CONFIG_FAULT_INJECTION 37 extern struct fault_attr fail_gem_alloc; 38 extern struct fault_attr fail_gem_iova; 39 #else 40 # define should_fail(attr, size) 0 41 #endif 42 43 struct msm_kms; 44 struct msm_gpu; 45 struct msm_mmu; 46 struct msm_mdss; 47 struct msm_rd_state; 48 struct msm_perf_state; 49 struct msm_gem_submit; 50 struct msm_fence_context; 51 struct msm_gem_address_space; 52 struct msm_gem_vma; 53 struct msm_disp_state; 54 55 #define MAX_CRTCS 8 56 #define MAX_BRIDGES 8 57 58 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 59 60 enum msm_dp_controller { 61 MSM_DP_CONTROLLER_0, 62 MSM_DP_CONTROLLER_1, 63 MSM_DP_CONTROLLER_2, 64 MSM_DP_CONTROLLER_3, 65 MSM_DP_CONTROLLER_COUNT, 66 }; 67 68 enum msm_dsi_controller { 69 MSM_DSI_CONTROLLER_0, 70 MSM_DSI_CONTROLLER_1, 71 MSM_DSI_CONTROLLER_COUNT, 72 }; 73 74 #define MSM_GPU_MAX_RINGS 4 75 #define MAX_H_TILES_PER_DISPLAY 2 76 77 /** 78 * struct msm_display_topology - defines a display topology pipeline 79 * @num_lm: number of layer mixers used 80 * @num_intf: number of interfaces the panel is mounted on 81 * @num_dspp: number of dspp blocks used 82 * @num_dsc: number of Display Stream Compression (DSC) blocks used 83 * @needs_cdm: indicates whether cdm block is needed for this display topology 84 */ 85 struct msm_display_topology { 86 u32 num_lm; 87 u32 num_intf; 88 u32 num_dspp; 89 u32 num_dsc; 90 bool needs_cdm; 91 }; 92 93 /* Commit/Event thread specific structure */ 94 struct msm_drm_thread { 95 struct drm_device *dev; 96 struct kthread_worker *worker; 97 }; 98 99 struct msm_drm_private { 100 101 struct drm_device *dev; 102 103 struct msm_kms *kms; 104 int (*kms_init)(struct drm_device *dev); 105 106 /* subordinate devices, if present: */ 107 struct platform_device *gpu_pdev; 108 109 /* possibly this should be in the kms component, but it is 110 * shared by both mdp4 and mdp5.. 111 */ 112 struct hdmi *hdmi; 113 114 /* DSI is shared by mdp4 and mdp5 */ 115 struct msm_dsi *dsi[MSM_DSI_CONTROLLER_COUNT]; 116 117 struct msm_dp *dp[MSM_DP_CONTROLLER_COUNT]; 118 119 /* when we have more than one 'msm_gpu' these need to be an array: */ 120 struct msm_gpu *gpu; 121 122 /* gpu is only set on open(), but we need this info earlier */ 123 bool is_a2xx; 124 bool has_cached_coherent; 125 126 struct msm_rd_state *rd; /* debugfs to dump all submits */ 127 struct msm_rd_state *hangrd; /* debugfs to dump hanging submits */ 128 struct msm_perf_state *perf; 129 130 /** 131 * List of all GEM objects (mainly for debugfs, protected by obj_lock 132 * (acquire before per GEM object lock) 133 */ 134 struct list_head objects; 135 struct mutex obj_lock; 136 137 /** 138 * lru: 139 * 140 * The various LRU's that a GEM object is in at various stages of 141 * it's lifetime. Objects start out in the unbacked LRU. When 142 * pinned (for scannout or permanently mapped GPU buffers, like 143 * ringbuffer, memptr, fw, etc) it moves to the pinned LRU. When 144 * unpinned, it moves into willneed or dontneed LRU depending on 145 * madvise state. When backing pages are evicted (willneed) or 146 * purged (dontneed) it moves back into the unbacked LRU. 147 * 148 * The dontneed LRU is considered by the shrinker for objects 149 * that are candidate for purging, and the willneed LRU is 150 * considered for objects that could be evicted. 151 */ 152 struct { 153 /** 154 * unbacked: 155 * 156 * The LRU for GEM objects without backing pages allocated. 157 * This mostly exists so that objects are always is one 158 * LRU. 159 */ 160 struct drm_gem_lru unbacked; 161 162 /** 163 * pinned: 164 * 165 * The LRU for pinned GEM objects 166 */ 167 struct drm_gem_lru pinned; 168 169 /** 170 * willneed: 171 * 172 * The LRU for unpinned GEM objects which are in madvise 173 * WILLNEED state (ie. can be evicted) 174 */ 175 struct drm_gem_lru willneed; 176 177 /** 178 * dontneed: 179 * 180 * The LRU for unpinned GEM objects which are in madvise 181 * DONTNEED state (ie. can be purged) 182 */ 183 struct drm_gem_lru dontneed; 184 185 /** 186 * lock: 187 * 188 * Protects manipulation of all of the LRUs. 189 */ 190 struct mutex lock; 191 } lru; 192 193 struct workqueue_struct *wq; 194 195 unsigned int num_crtcs; 196 197 struct msm_drm_thread event_thread[MAX_CRTCS]; 198 199 /* VRAM carveout, used when no IOMMU: */ 200 struct { 201 unsigned long size; 202 dma_addr_t paddr; 203 /* NOTE: mm managed at the page level, size is in # of pages 204 * and position mm_node->start is in # of pages: 205 */ 206 struct drm_mm mm; 207 spinlock_t lock; /* Protects drm_mm node allocation/removal */ 208 } vram; 209 210 struct notifier_block vmap_notifier; 211 struct shrinker *shrinker; 212 213 struct drm_atomic_state *pm_state; 214 215 /** 216 * hangcheck_period: For hang detection, in ms 217 * 218 * Note that in practice, a submit/job will get at least two hangcheck 219 * periods, due to checking for progress being implemented as simply 220 * "have the CP position registers changed since last time?" 221 */ 222 unsigned int hangcheck_period; 223 224 /** gpu_devfreq_config: Devfreq tuning config for the GPU. */ 225 struct devfreq_simple_ondemand_data gpu_devfreq_config; 226 227 /** 228 * gpu_clamp_to_idle: Enable clamping to idle freq when inactive 229 */ 230 bool gpu_clamp_to_idle; 231 232 /** 233 * disable_err_irq: 234 * 235 * Disable handling of GPU hw error interrupts, to force fallback to 236 * sw hangcheck timer. Written (via debugfs) by igt tests to test 237 * the sw hangcheck mechanism. 238 */ 239 bool disable_err_irq; 240 }; 241 242 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); 243 244 struct msm_pending_timer; 245 246 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer, 247 struct msm_kms *kms, int crtc_idx); 248 void msm_atomic_destroy_pending_timer(struct msm_pending_timer *timer); 249 void msm_atomic_commit_tail(struct drm_atomic_state *state); 250 int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); 251 struct drm_atomic_state *msm_atomic_state_alloc(struct drm_device *dev); 252 void msm_atomic_state_clear(struct drm_atomic_state *state); 253 void msm_atomic_state_free(struct drm_atomic_state *state); 254 255 int msm_crtc_enable_vblank(struct drm_crtc *crtc); 256 void msm_crtc_disable_vblank(struct drm_crtc *crtc); 257 258 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 259 void msm_unregister_mmu(struct drm_device *dev, struct msm_mmu *mmu); 260 261 struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev); 262 bool msm_use_mmu(struct drm_device *dev); 263 264 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 265 struct drm_file *file); 266 267 #ifdef CONFIG_DEBUG_FS 268 unsigned long msm_gem_shrinker_shrink(struct drm_device *dev, unsigned long nr_to_scan); 269 #endif 270 271 int msm_gem_shrinker_init(struct drm_device *dev); 272 void msm_gem_shrinker_cleanup(struct drm_device *dev); 273 274 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 275 int msm_gem_prime_vmap(struct drm_gem_object *obj, struct iosys_map *map); 276 void msm_gem_prime_vunmap(struct drm_gem_object *obj, struct iosys_map *map); 277 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 278 struct dma_buf_attachment *attach, struct sg_table *sg); 279 int msm_gem_prime_pin(struct drm_gem_object *obj); 280 void msm_gem_prime_unpin(struct drm_gem_object *obj); 281 282 int msm_framebuffer_prepare(struct drm_framebuffer *fb, 283 struct msm_gem_address_space *aspace, bool needs_dirtyfb); 284 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, 285 struct msm_gem_address_space *aspace, bool needed_dirtyfb); 286 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, 287 struct msm_gem_address_space *aspace, int plane); 288 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 289 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 290 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 291 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 292 struct drm_framebuffer * msm_alloc_stolen_fb(struct drm_device *dev, 293 int w, int h, int p, uint32_t format); 294 295 #ifdef CONFIG_DRM_FBDEV_EMULATION 296 void msm_fbdev_setup(struct drm_device *dev); 297 #else 298 static inline void msm_fbdev_setup(struct drm_device *dev) 299 { 300 } 301 #endif 302 303 struct hdmi; 304 #ifdef CONFIG_DRM_MSM_HDMI 305 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 306 struct drm_encoder *encoder); 307 void __init msm_hdmi_register(void); 308 void __exit msm_hdmi_unregister(void); 309 #else 310 static inline int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 311 struct drm_encoder *encoder) 312 { 313 return -EINVAL; 314 } 315 static inline void __init msm_hdmi_register(void) {} 316 static inline void __exit msm_hdmi_unregister(void) {} 317 #endif 318 319 struct msm_dsi; 320 #ifdef CONFIG_DRM_MSM_DSI 321 int dsi_dev_attach(struct platform_device *pdev); 322 void dsi_dev_detach(struct platform_device *pdev); 323 void __init msm_dsi_register(void); 324 void __exit msm_dsi_unregister(void); 325 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 326 struct drm_encoder *encoder); 327 void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi); 328 bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi); 329 bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi); 330 bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi); 331 bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi); 332 struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi); 333 #else 334 static inline void __init msm_dsi_register(void) 335 { 336 } 337 static inline void __exit msm_dsi_unregister(void) 338 { 339 } 340 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 341 struct drm_device *dev, 342 struct drm_encoder *encoder) 343 { 344 return -EINVAL; 345 } 346 static inline void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi) 347 { 348 } 349 static inline bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi) 350 { 351 return false; 352 } 353 static inline bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi) 354 { 355 return false; 356 } 357 static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi) 358 { 359 return false; 360 } 361 static inline bool msm_dsi_wide_bus_enabled(struct msm_dsi *msm_dsi) 362 { 363 return false; 364 } 365 366 static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi) 367 { 368 return NULL; 369 } 370 #endif 371 372 #ifdef CONFIG_DRM_MSM_DP 373 int __init msm_dp_register(void); 374 void __exit msm_dp_unregister(void); 375 int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, 376 struct drm_encoder *encoder, bool yuv_supported); 377 void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); 378 bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 379 const struct drm_display_mode *mode); 380 bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 381 const struct drm_display_mode *mode); 382 bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); 383 384 #else 385 static inline int __init msm_dp_register(void) 386 { 387 return -EINVAL; 388 } 389 static inline void __exit msm_dp_unregister(void) 390 { 391 } 392 static inline int msm_dp_modeset_init(struct msm_dp *dp_display, 393 struct drm_device *dev, 394 struct drm_encoder *encoder, 395 bool yuv_supported) 396 { 397 return -EINVAL; 398 } 399 400 static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display) 401 { 402 } 403 404 static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, 405 const struct drm_display_mode *mode) 406 { 407 return false; 408 } 409 410 static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, 411 const struct drm_display_mode *mode) 412 { 413 return false; 414 } 415 416 static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) 417 { 418 return false; 419 } 420 421 #endif 422 423 #ifdef CONFIG_DRM_MSM_MDP4 424 void msm_mdp4_register(void); 425 void msm_mdp4_unregister(void); 426 #else 427 static inline void msm_mdp4_register(void) {} 428 static inline void msm_mdp4_unregister(void) {} 429 #endif 430 431 #ifdef CONFIG_DRM_MSM_MDP5 432 void msm_mdp_register(void); 433 void msm_mdp_unregister(void); 434 #else 435 static inline void msm_mdp_register(void) {} 436 static inline void msm_mdp_unregister(void) {} 437 #endif 438 439 #ifdef CONFIG_DRM_MSM_DPU 440 void msm_dpu_register(void); 441 void msm_dpu_unregister(void); 442 #else 443 static inline void msm_dpu_register(void) {} 444 static inline void msm_dpu_unregister(void) {} 445 #endif 446 447 #ifdef CONFIG_DRM_MSM_MDSS 448 void msm_mdss_register(void); 449 void msm_mdss_unregister(void); 450 #else 451 static inline void msm_mdss_register(void) {} 452 static inline void msm_mdss_unregister(void) {} 453 #endif 454 455 #ifdef CONFIG_DEBUG_FS 456 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 457 int msm_debugfs_late_init(struct drm_device *dev); 458 int msm_rd_debugfs_init(struct drm_minor *minor); 459 void msm_rd_debugfs_cleanup(struct msm_drm_private *priv); 460 __printf(3, 4) 461 void msm_rd_dump_submit(struct msm_rd_state *rd, struct msm_gem_submit *submit, 462 const char *fmt, ...); 463 int msm_perf_debugfs_init(struct drm_minor *minor); 464 void msm_perf_debugfs_cleanup(struct msm_drm_private *priv); 465 #else 466 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 467 __printf(3, 4) 468 static inline void msm_rd_dump_submit(struct msm_rd_state *rd, 469 struct msm_gem_submit *submit, 470 const char *fmt, ...) {} 471 static inline void msm_rd_debugfs_cleanup(struct msm_drm_private *priv) {} 472 static inline void msm_perf_debugfs_cleanup(struct msm_drm_private *priv) {} 473 #endif 474 475 struct clk *msm_clk_get(struct platform_device *pdev, const char *name); 476 477 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 478 const char *name); 479 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); 480 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 481 phys_addr_t *size); 482 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); 483 void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, 484 struct platform_device *dev, 485 const char *name); 486 487 struct icc_path *msm_icc_get(struct device *dev, const char *name); 488 489 static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or) 490 { 491 u32 val = readl(addr); 492 493 val &= ~mask; 494 writel(val | or, addr); 495 } 496 497 /** 498 * struct msm_hrtimer_work - a helper to combine an hrtimer with kthread_work 499 * 500 * @timer: hrtimer to control when the kthread work is triggered 501 * @work: the kthread work 502 * @worker: the kthread worker the work will be scheduled on 503 */ 504 struct msm_hrtimer_work { 505 struct hrtimer timer; 506 struct kthread_work work; 507 struct kthread_worker *worker; 508 }; 509 510 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 511 ktime_t wakeup_time, 512 enum hrtimer_mode mode); 513 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 514 struct kthread_worker *worker, 515 kthread_work_func_t fn, 516 clockid_t clock_id, 517 enum hrtimer_mode mode); 518 519 #define DBG(fmt, ...) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 520 #define VERB(fmt, ...) if (0) DRM_DEBUG_DRIVER(fmt"\n", ##__VA_ARGS__) 521 522 static inline int align_pitch(int width, int bpp) 523 { 524 int bytespp = (bpp + 7) / 8; 525 /* adreno needs pitch aligned to 32 pixels: */ 526 return bytespp * ALIGN(width, 32); 527 } 528 529 /* for the generated headers: */ 530 #define INVALID_IDX(idx) ({BUG(); 0;}) 531 #define fui(x) ({BUG(); 0;}) 532 #define _mesa_float_to_half(x) ({BUG(); 0;}) 533 534 535 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 536 537 /* for conditionally setting boolean flag(s): */ 538 #define COND(bool, val) ((bool) ? (val) : 0) 539 540 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 541 { 542 ktime_t now = ktime_get(); 543 s64 remaining_jiffies; 544 545 if (ktime_compare(*timeout, now) < 0) { 546 remaining_jiffies = 0; 547 } else { 548 ktime_t rem = ktime_sub(*timeout, now); 549 remaining_jiffies = ktime_divns(rem, NSEC_PER_SEC / HZ); 550 } 551 552 return clamp(remaining_jiffies, 1LL, (s64)INT_MAX); 553 } 554 555 /* Driver helpers */ 556 557 extern const struct component_master_ops msm_drm_ops; 558 559 int msm_kms_pm_prepare(struct device *dev); 560 void msm_kms_pm_complete(struct device *dev); 561 562 int msm_drv_probe(struct device *dev, 563 int (*kms_init)(struct drm_device *dev), 564 struct msm_kms *kms); 565 void msm_kms_shutdown(struct platform_device *pdev); 566 567 bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); 568 569 #endif /* __MSM_DRV_H__ */ 570