1 /* 2 * Copyright (C) 2013 Red Hat 3 * Author: Rob Clark <robdclark@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published by 7 * the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __MSM_DRV_H__ 19 #define __MSM_DRV_H__ 20 21 #include <linux/kernel.h> 22 #include <linux/clk.h> 23 #include <linux/cpufreq.h> 24 #include <linux/module.h> 25 #include <linux/component.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/slab.h> 30 #include <linux/list.h> 31 #include <linux/iommu.h> 32 #include <linux/types.h> 33 #include <linux/of_graph.h> 34 #include <linux/of_device.h> 35 #include <asm/sizes.h> 36 37 #include <drm/drmP.h> 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_plane_helper.h> 42 #include <drm/drm_fb_helper.h> 43 #include <drm/msm_drm.h> 44 #include <drm/drm_gem.h> 45 46 struct msm_kms; 47 struct msm_gpu; 48 struct msm_mmu; 49 struct msm_rd_state; 50 struct msm_perf_state; 51 struct msm_gem_submit; 52 struct msm_fence_context; 53 struct msm_fence_cb; 54 55 #define NUM_DOMAINS 2 /* one for KMS, then one per gpu core (?) */ 56 57 struct msm_file_private { 58 /* currently we don't do anything useful with this.. but when 59 * per-context address spaces are supported we'd keep track of 60 * the context's page-tables here. 61 */ 62 int dummy; 63 }; 64 65 enum msm_mdp_plane_property { 66 PLANE_PROP_ZPOS, 67 PLANE_PROP_ALPHA, 68 PLANE_PROP_PREMULTIPLIED, 69 PLANE_PROP_MAX_NUM 70 }; 71 72 struct msm_vblank_ctrl { 73 struct work_struct work; 74 struct list_head event_list; 75 spinlock_t lock; 76 }; 77 78 struct msm_drm_private { 79 80 struct msm_kms *kms; 81 82 /* subordinate devices, if present: */ 83 struct platform_device *gpu_pdev; 84 85 /* possibly this should be in the kms component, but it is 86 * shared by both mdp4 and mdp5.. 87 */ 88 struct hdmi *hdmi; 89 90 /* eDP is for mdp5 only, but kms has not been created 91 * when edp_bind() and edp_init() are called. Here is the only 92 * place to keep the edp instance. 93 */ 94 struct msm_edp *edp; 95 96 /* DSI is shared by mdp4 and mdp5 */ 97 struct msm_dsi *dsi[2]; 98 99 /* when we have more than one 'msm_gpu' these need to be an array: */ 100 struct msm_gpu *gpu; 101 struct msm_file_private *lastctx; 102 103 struct drm_fb_helper *fbdev; 104 105 struct msm_rd_state *rd; 106 struct msm_perf_state *perf; 107 108 /* list of GEM objects: */ 109 struct list_head inactive_list; 110 111 struct workqueue_struct *wq; 112 struct workqueue_struct *atomic_wq; 113 114 /* crtcs pending async atomic updates: */ 115 uint32_t pending_crtcs; 116 wait_queue_head_t pending_crtcs_event; 117 118 /* registered MMUs: */ 119 unsigned int num_mmus; 120 struct msm_mmu *mmus[NUM_DOMAINS]; 121 122 unsigned int num_planes; 123 struct drm_plane *planes[8]; 124 125 unsigned int num_crtcs; 126 struct drm_crtc *crtcs[8]; 127 128 unsigned int num_encoders; 129 struct drm_encoder *encoders[8]; 130 131 unsigned int num_bridges; 132 struct drm_bridge *bridges[8]; 133 134 unsigned int num_connectors; 135 struct drm_connector *connectors[8]; 136 137 /* Properties */ 138 struct drm_property *plane_property[PLANE_PROP_MAX_NUM]; 139 140 /* VRAM carveout, used when no IOMMU: */ 141 struct { 142 unsigned long size; 143 dma_addr_t paddr; 144 /* NOTE: mm managed at the page level, size is in # of pages 145 * and position mm_node->start is in # of pages: 146 */ 147 struct drm_mm mm; 148 } vram; 149 150 struct msm_vblank_ctrl vblank_ctrl; 151 }; 152 153 struct msm_format { 154 uint32_t pixel_format; 155 }; 156 157 int msm_atomic_check(struct drm_device *dev, 158 struct drm_atomic_state *state); 159 int msm_atomic_commit(struct drm_device *dev, 160 struct drm_atomic_state *state, bool nonblock); 161 162 int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu); 163 164 void msm_gem_submit_free(struct msm_gem_submit *submit); 165 int msm_ioctl_gem_submit(struct drm_device *dev, void *data, 166 struct drm_file *file); 167 168 int msm_gem_mmap_obj(struct drm_gem_object *obj, 169 struct vm_area_struct *vma); 170 int msm_gem_mmap(struct file *filp, struct vm_area_struct *vma); 171 int msm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); 172 uint64_t msm_gem_mmap_offset(struct drm_gem_object *obj); 173 int msm_gem_get_iova_locked(struct drm_gem_object *obj, int id, 174 uint32_t *iova); 175 int msm_gem_get_iova(struct drm_gem_object *obj, int id, uint32_t *iova); 176 uint32_t msm_gem_iova(struct drm_gem_object *obj, int id); 177 struct page **msm_gem_get_pages(struct drm_gem_object *obj); 178 void msm_gem_put_pages(struct drm_gem_object *obj); 179 void msm_gem_put_iova(struct drm_gem_object *obj, int id); 180 int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev, 181 struct drm_mode_create_dumb *args); 182 int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev, 183 uint32_t handle, uint64_t *offset); 184 struct sg_table *msm_gem_prime_get_sg_table(struct drm_gem_object *obj); 185 void *msm_gem_prime_vmap(struct drm_gem_object *obj); 186 void msm_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 187 int msm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 188 struct drm_gem_object *msm_gem_prime_import_sg_table(struct drm_device *dev, 189 struct dma_buf_attachment *attach, struct sg_table *sg); 190 int msm_gem_prime_pin(struct drm_gem_object *obj); 191 void msm_gem_prime_unpin(struct drm_gem_object *obj); 192 void *msm_gem_vaddr_locked(struct drm_gem_object *obj); 193 void *msm_gem_vaddr(struct drm_gem_object *obj); 194 int msm_gem_sync_object(struct drm_gem_object *obj, 195 struct msm_fence_context *fctx, bool exclusive); 196 void msm_gem_move_to_active(struct drm_gem_object *obj, 197 struct msm_gpu *gpu, bool exclusive, struct fence *fence); 198 void msm_gem_move_to_inactive(struct drm_gem_object *obj); 199 int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t *timeout); 200 int msm_gem_cpu_fini(struct drm_gem_object *obj); 201 void msm_gem_free_object(struct drm_gem_object *obj); 202 int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file, 203 uint32_t size, uint32_t flags, uint32_t *handle); 204 struct drm_gem_object *msm_gem_new(struct drm_device *dev, 205 uint32_t size, uint32_t flags); 206 struct drm_gem_object *msm_gem_import(struct drm_device *dev, 207 struct dma_buf *dmabuf, struct sg_table *sgt); 208 209 int msm_framebuffer_prepare(struct drm_framebuffer *fb, int id); 210 void msm_framebuffer_cleanup(struct drm_framebuffer *fb, int id); 211 uint32_t msm_framebuffer_iova(struct drm_framebuffer *fb, int id, int plane); 212 struct drm_gem_object *msm_framebuffer_bo(struct drm_framebuffer *fb, int plane); 213 const struct msm_format *msm_framebuffer_format(struct drm_framebuffer *fb); 214 struct drm_framebuffer *msm_framebuffer_init(struct drm_device *dev, 215 const struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **bos); 216 struct drm_framebuffer *msm_framebuffer_create(struct drm_device *dev, 217 struct drm_file *file, const struct drm_mode_fb_cmd2 *mode_cmd); 218 219 struct drm_fb_helper *msm_fbdev_init(struct drm_device *dev); 220 void msm_fbdev_free(struct drm_device *dev); 221 222 struct hdmi; 223 int msm_hdmi_modeset_init(struct hdmi *hdmi, struct drm_device *dev, 224 struct drm_encoder *encoder); 225 void __init msm_hdmi_register(void); 226 void __exit msm_hdmi_unregister(void); 227 228 struct msm_edp; 229 void __init msm_edp_register(void); 230 void __exit msm_edp_unregister(void); 231 int msm_edp_modeset_init(struct msm_edp *edp, struct drm_device *dev, 232 struct drm_encoder *encoder); 233 234 struct msm_dsi; 235 enum msm_dsi_encoder_id { 236 MSM_DSI_VIDEO_ENCODER_ID = 0, 237 MSM_DSI_CMD_ENCODER_ID = 1, 238 MSM_DSI_ENCODER_NUM = 2 239 }; 240 #ifdef CONFIG_DRM_MSM_DSI 241 void __init msm_dsi_register(void); 242 void __exit msm_dsi_unregister(void); 243 int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, 244 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]); 245 #else 246 static inline void __init msm_dsi_register(void) 247 { 248 } 249 static inline void __exit msm_dsi_unregister(void) 250 { 251 } 252 static inline int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, 253 struct drm_device *dev, 254 struct drm_encoder *encoders[MSM_DSI_ENCODER_NUM]) 255 { 256 return -EINVAL; 257 } 258 #endif 259 260 #ifdef CONFIG_DEBUG_FS 261 void msm_gem_describe(struct drm_gem_object *obj, struct seq_file *m); 262 void msm_gem_describe_objects(struct list_head *list, struct seq_file *m); 263 void msm_framebuffer_describe(struct drm_framebuffer *fb, struct seq_file *m); 264 int msm_debugfs_late_init(struct drm_device *dev); 265 int msm_rd_debugfs_init(struct drm_minor *minor); 266 void msm_rd_debugfs_cleanup(struct drm_minor *minor); 267 void msm_rd_dump_submit(struct msm_gem_submit *submit); 268 int msm_perf_debugfs_init(struct drm_minor *minor); 269 void msm_perf_debugfs_cleanup(struct drm_minor *minor); 270 #else 271 static inline int msm_debugfs_late_init(struct drm_device *dev) { return 0; } 272 static inline void msm_rd_dump_submit(struct msm_gem_submit *submit) {} 273 #endif 274 275 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 276 const char *dbgname); 277 void msm_writel(u32 data, void __iomem *addr); 278 u32 msm_readl(const void __iomem *addr); 279 280 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 281 #define VERB(fmt, ...) if (0) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 282 283 static inline int align_pitch(int width, int bpp) 284 { 285 int bytespp = (bpp + 7) / 8; 286 /* adreno needs pitch aligned to 32 pixels: */ 287 return bytespp * ALIGN(width, 32); 288 } 289 290 /* for the generated headers: */ 291 #define INVALID_IDX(idx) ({BUG(); 0;}) 292 #define fui(x) ({BUG(); 0;}) 293 #define util_float_to_half(x) ({BUG(); 0;}) 294 295 296 #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT) 297 298 /* for conditionally setting boolean flag(s): */ 299 #define COND(bool, val) ((bool) ? (val) : 0) 300 301 static inline unsigned long timeout_to_jiffies(const ktime_t *timeout) 302 { 303 ktime_t now = ktime_get(); 304 unsigned long remaining_jiffies; 305 306 if (ktime_compare(*timeout, now) < 0) { 307 remaining_jiffies = 0; 308 } else { 309 ktime_t rem = ktime_sub(*timeout, now); 310 struct timespec ts = ktime_to_timespec(rem); 311 remaining_jiffies = timespec_to_jiffies(&ts); 312 } 313 314 return remaining_jiffies; 315 } 316 317 #endif /* __MSM_DRV_H__ */ 318