1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/kthread.h> 10 #include <linux/sched/mm.h> 11 #include <linux/uaccess.h> 12 #include <uapi/linux/sched/types.h> 13 14 #include <drm/drm_drv.h> 15 #include <drm/drm_file.h> 16 #include <drm/drm_ioctl.h> 17 #include <drm/drm_prime.h> 18 #include <drm/drm_of.h> 19 #include <drm/drm_vblank.h> 20 21 #include "disp/msm_disp_snapshot.h" 22 #include "msm_drv.h" 23 #include "msm_debugfs.h" 24 #include "msm_fence.h" 25 #include "msm_gem.h" 26 #include "msm_gpu.h" 27 #include "msm_kms.h" 28 #include "adreno/adreno_gpu.h" 29 30 /* 31 * MSM driver version: 32 * - 1.0.0 - initial interface 33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers 34 * - 1.2.0 - adds explicit fence support for submit ioctl 35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + 36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for 37 * MSM_GEM_INFO ioctl. 38 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get 39 * GEM object's debug name 40 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl 41 * - 1.6.0 - Syncobj support 42 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count 43 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) 44 */ 45 #define MSM_VERSION_MAJOR 1 46 #define MSM_VERSION_MINOR 8 47 #define MSM_VERSION_PATCHLEVEL 0 48 49 static const struct drm_mode_config_funcs mode_config_funcs = { 50 .fb_create = msm_framebuffer_create, 51 .output_poll_changed = drm_fb_helper_output_poll_changed, 52 .atomic_check = drm_atomic_helper_check, 53 .atomic_commit = drm_atomic_helper_commit, 54 }; 55 56 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { 57 .atomic_commit_tail = msm_atomic_commit_tail, 58 }; 59 60 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING 61 static bool reglog; 62 MODULE_PARM_DESC(reglog, "Enable register read/write logging"); 63 module_param(reglog, bool, 0600); 64 #else 65 #define reglog 0 66 #endif 67 68 #ifdef CONFIG_DRM_FBDEV_EMULATION 69 static bool fbdev = true; 70 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); 71 module_param(fbdev, bool, 0600); 72 #endif 73 74 static char *vram = "16m"; 75 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); 76 module_param(vram, charp, 0); 77 78 bool dumpstate; 79 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); 80 module_param(dumpstate, bool, 0600); 81 82 static bool modeset = true; 83 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); 84 module_param(modeset, bool, 0600); 85 86 /* 87 * Util/helpers: 88 */ 89 90 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 91 const char *name) 92 { 93 int i; 94 char n[32]; 95 96 snprintf(n, sizeof(n), "%s_clk", name); 97 98 for (i = 0; bulk && i < count; i++) { 99 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n)) 100 return bulk[i].clk; 101 } 102 103 104 return NULL; 105 } 106 107 struct clk *msm_clk_get(struct platform_device *pdev, const char *name) 108 { 109 struct clk *clk; 110 char name2[32]; 111 112 clk = devm_clk_get(&pdev->dev, name); 113 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER) 114 return clk; 115 116 snprintf(name2, sizeof(name2), "%s_clk", name); 117 118 clk = devm_clk_get(&pdev->dev, name2); 119 if (!IS_ERR(clk)) 120 dev_warn(&pdev->dev, "Using legacy clk name binding. Use " 121 "\"%s\" instead of \"%s\"\n", name, name2); 122 123 return clk; 124 } 125 126 static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name, 127 const char *dbgname, bool quiet, phys_addr_t *psize) 128 { 129 struct resource *res; 130 unsigned long size; 131 void __iomem *ptr; 132 133 if (name) 134 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 135 else 136 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 137 138 if (!res) { 139 if (!quiet) 140 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name); 141 return ERR_PTR(-EINVAL); 142 } 143 144 size = resource_size(res); 145 146 ptr = devm_ioremap(&pdev->dev, res->start, size); 147 if (!ptr) { 148 if (!quiet) 149 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name); 150 return ERR_PTR(-ENOMEM); 151 } 152 153 if (reglog) 154 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); 155 156 if (psize) 157 *psize = size; 158 159 return ptr; 160 } 161 162 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 163 const char *dbgname) 164 { 165 return _msm_ioremap(pdev, name, dbgname, false, NULL); 166 } 167 168 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, 169 const char *dbgname) 170 { 171 return _msm_ioremap(pdev, name, dbgname, true, NULL); 172 } 173 174 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, 175 const char *dbgname, phys_addr_t *psize) 176 { 177 return _msm_ioremap(pdev, name, dbgname, false, psize); 178 } 179 180 void msm_writel(u32 data, void __iomem *addr) 181 { 182 if (reglog) 183 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); 184 writel(data, addr); 185 } 186 187 u32 msm_readl(const void __iomem *addr) 188 { 189 u32 val = readl(addr); 190 if (reglog) 191 pr_err("IO:R %p %08x\n", addr, val); 192 return val; 193 } 194 195 void msm_rmw(void __iomem *addr, u32 mask, u32 or) 196 { 197 u32 val = msm_readl(addr); 198 199 val &= ~mask; 200 msm_writel(val | or, addr); 201 } 202 203 static enum hrtimer_restart msm_hrtimer_worktimer(struct hrtimer *t) 204 { 205 struct msm_hrtimer_work *work = container_of(t, 206 struct msm_hrtimer_work, timer); 207 208 kthread_queue_work(work->worker, &work->work); 209 210 return HRTIMER_NORESTART; 211 } 212 213 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work, 214 ktime_t wakeup_time, 215 enum hrtimer_mode mode) 216 { 217 hrtimer_start(&work->timer, wakeup_time, mode); 218 } 219 220 void msm_hrtimer_work_init(struct msm_hrtimer_work *work, 221 struct kthread_worker *worker, 222 kthread_work_func_t fn, 223 clockid_t clock_id, 224 enum hrtimer_mode mode) 225 { 226 hrtimer_init(&work->timer, clock_id, mode); 227 work->timer.function = msm_hrtimer_worktimer; 228 work->worker = worker; 229 kthread_init_work(&work->work, fn); 230 } 231 232 static irqreturn_t msm_irq(int irq, void *arg) 233 { 234 struct drm_device *dev = arg; 235 struct msm_drm_private *priv = dev->dev_private; 236 struct msm_kms *kms = priv->kms; 237 238 BUG_ON(!kms); 239 240 return kms->funcs->irq(kms); 241 } 242 243 static void msm_irq_preinstall(struct drm_device *dev) 244 { 245 struct msm_drm_private *priv = dev->dev_private; 246 struct msm_kms *kms = priv->kms; 247 248 BUG_ON(!kms); 249 250 kms->funcs->irq_preinstall(kms); 251 } 252 253 static int msm_irq_postinstall(struct drm_device *dev) 254 { 255 struct msm_drm_private *priv = dev->dev_private; 256 struct msm_kms *kms = priv->kms; 257 258 BUG_ON(!kms); 259 260 if (kms->funcs->irq_postinstall) 261 return kms->funcs->irq_postinstall(kms); 262 263 return 0; 264 } 265 266 static int msm_irq_install(struct drm_device *dev, unsigned int irq) 267 { 268 int ret; 269 270 if (irq == IRQ_NOTCONNECTED) 271 return -ENOTCONN; 272 273 msm_irq_preinstall(dev); 274 275 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev); 276 if (ret) 277 return ret; 278 279 ret = msm_irq_postinstall(dev); 280 if (ret) { 281 free_irq(irq, dev); 282 return ret; 283 } 284 285 return 0; 286 } 287 288 static void msm_irq_uninstall(struct drm_device *dev) 289 { 290 struct msm_drm_private *priv = dev->dev_private; 291 struct msm_kms *kms = priv->kms; 292 293 kms->funcs->irq_uninstall(kms); 294 free_irq(kms->irq, dev); 295 } 296 297 struct msm_vblank_work { 298 struct work_struct work; 299 int crtc_id; 300 bool enable; 301 struct msm_drm_private *priv; 302 }; 303 304 static void vblank_ctrl_worker(struct work_struct *work) 305 { 306 struct msm_vblank_work *vbl_work = container_of(work, 307 struct msm_vblank_work, work); 308 struct msm_drm_private *priv = vbl_work->priv; 309 struct msm_kms *kms = priv->kms; 310 311 if (vbl_work->enable) 312 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 313 else 314 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 315 316 kfree(vbl_work); 317 } 318 319 static int vblank_ctrl_queue_work(struct msm_drm_private *priv, 320 int crtc_id, bool enable) 321 { 322 struct msm_vblank_work *vbl_work; 323 324 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC); 325 if (!vbl_work) 326 return -ENOMEM; 327 328 INIT_WORK(&vbl_work->work, vblank_ctrl_worker); 329 330 vbl_work->crtc_id = crtc_id; 331 vbl_work->enable = enable; 332 vbl_work->priv = priv; 333 334 queue_work(priv->wq, &vbl_work->work); 335 336 return 0; 337 } 338 339 static int msm_drm_uninit(struct device *dev) 340 { 341 struct platform_device *pdev = to_platform_device(dev); 342 struct msm_drm_private *priv = platform_get_drvdata(pdev); 343 struct drm_device *ddev = priv->dev; 344 struct msm_kms *kms = priv->kms; 345 int i; 346 347 /* 348 * Shutdown the hw if we're far enough along where things might be on. 349 * If we run this too early, we'll end up panicking in any variety of 350 * places. Since we don't register the drm device until late in 351 * msm_drm_init, drm_dev->registered is used as an indicator that the 352 * shutdown will be successful. 353 */ 354 if (ddev->registered) { 355 drm_dev_unregister(ddev); 356 drm_atomic_helper_shutdown(ddev); 357 } 358 359 /* We must cancel and cleanup any pending vblank enable/disable 360 * work before msm_irq_uninstall() to avoid work re-enabling an 361 * irq after uninstall has disabled it. 362 */ 363 364 flush_workqueue(priv->wq); 365 366 /* clean up event worker threads */ 367 for (i = 0; i < priv->num_crtcs; i++) { 368 if (priv->event_thread[i].worker) 369 kthread_destroy_worker(priv->event_thread[i].worker); 370 } 371 372 msm_gem_shrinker_cleanup(ddev); 373 374 drm_kms_helper_poll_fini(ddev); 375 376 msm_perf_debugfs_cleanup(priv); 377 msm_rd_debugfs_cleanup(priv); 378 379 #ifdef CONFIG_DRM_FBDEV_EMULATION 380 if (fbdev && priv->fbdev) 381 msm_fbdev_free(ddev); 382 #endif 383 384 msm_disp_snapshot_destroy(ddev); 385 386 drm_mode_config_cleanup(ddev); 387 388 pm_runtime_get_sync(dev); 389 msm_irq_uninstall(ddev); 390 pm_runtime_put_sync(dev); 391 392 if (kms && kms->funcs) 393 kms->funcs->destroy(kms); 394 395 if (priv->vram.paddr) { 396 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; 397 drm_mm_takedown(&priv->vram.mm); 398 dma_free_attrs(dev, priv->vram.size, NULL, 399 priv->vram.paddr, attrs); 400 } 401 402 component_unbind_all(dev, ddev); 403 404 ddev->dev_private = NULL; 405 drm_dev_put(ddev); 406 407 destroy_workqueue(priv->wq); 408 409 return 0; 410 } 411 412 #define KMS_MDP4 4 413 #define KMS_MDP5 5 414 #define KMS_DPU 3 415 416 static int get_mdp_ver(struct platform_device *pdev) 417 { 418 struct device *dev = &pdev->dev; 419 420 return (int) (unsigned long) of_device_get_match_data(dev); 421 } 422 423 #include <linux/of_address.h> 424 425 bool msm_use_mmu(struct drm_device *dev) 426 { 427 struct msm_drm_private *priv = dev->dev_private; 428 429 /* a2xx comes with its own MMU */ 430 return priv->is_a2xx || iommu_present(&platform_bus_type); 431 } 432 433 static int msm_init_vram(struct drm_device *dev) 434 { 435 struct msm_drm_private *priv = dev->dev_private; 436 struct device_node *node; 437 unsigned long size = 0; 438 int ret = 0; 439 440 /* In the device-tree world, we could have a 'memory-region' 441 * phandle, which gives us a link to our "vram". Allocating 442 * is all nicely abstracted behind the dma api, but we need 443 * to know the entire size to allocate it all in one go. There 444 * are two cases: 445 * 1) device with no IOMMU, in which case we need exclusive 446 * access to a VRAM carveout big enough for all gpu 447 * buffers 448 * 2) device with IOMMU, but where the bootloader puts up 449 * a splash screen. In this case, the VRAM carveout 450 * need only be large enough for fbdev fb. But we need 451 * exclusive access to the buffer to avoid the kernel 452 * using those pages for other purposes (which appears 453 * as corruption on screen before we have a chance to 454 * load and do initial modeset) 455 */ 456 457 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); 458 if (node) { 459 struct resource r; 460 ret = of_address_to_resource(node, 0, &r); 461 of_node_put(node); 462 if (ret) 463 return ret; 464 size = r.end - r.start + 1; 465 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); 466 467 /* if we have no IOMMU, then we need to use carveout allocator. 468 * Grab the entire CMA chunk carved out in early startup in 469 * mach-msm: 470 */ 471 } else if (!msm_use_mmu(dev)) { 472 DRM_INFO("using %s VRAM carveout\n", vram); 473 size = memparse(vram, NULL); 474 } 475 476 if (size) { 477 unsigned long attrs = 0; 478 void *p; 479 480 priv->vram.size = size; 481 482 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); 483 spin_lock_init(&priv->vram.lock); 484 485 attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 486 attrs |= DMA_ATTR_WRITE_COMBINE; 487 488 /* note that for no-kernel-mapping, the vaddr returned 489 * is bogus, but non-null if allocation succeeded: 490 */ 491 p = dma_alloc_attrs(dev->dev, size, 492 &priv->vram.paddr, GFP_KERNEL, attrs); 493 if (!p) { 494 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n"); 495 priv->vram.paddr = 0; 496 return -ENOMEM; 497 } 498 499 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n", 500 (uint32_t)priv->vram.paddr, 501 (uint32_t)(priv->vram.paddr + size)); 502 } 503 504 return ret; 505 } 506 507 static int msm_drm_init(struct device *dev, const struct drm_driver *drv) 508 { 509 struct platform_device *pdev = to_platform_device(dev); 510 struct msm_drm_private *priv = dev_get_drvdata(dev); 511 struct drm_device *ddev; 512 struct msm_kms *kms; 513 int ret, i; 514 515 ddev = drm_dev_alloc(drv, dev); 516 if (IS_ERR(ddev)) { 517 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); 518 return PTR_ERR(ddev); 519 } 520 ddev->dev_private = priv; 521 priv->dev = ddev; 522 523 priv->wq = alloc_ordered_workqueue("msm", 0); 524 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD; 525 526 INIT_LIST_HEAD(&priv->objects); 527 mutex_init(&priv->obj_lock); 528 529 INIT_LIST_HEAD(&priv->inactive_willneed); 530 INIT_LIST_HEAD(&priv->inactive_dontneed); 531 INIT_LIST_HEAD(&priv->inactive_unpinned); 532 mutex_init(&priv->mm_lock); 533 534 /* Teach lockdep about lock ordering wrt. shrinker: */ 535 fs_reclaim_acquire(GFP_KERNEL); 536 might_lock(&priv->mm_lock); 537 fs_reclaim_release(GFP_KERNEL); 538 539 drm_mode_config_init(ddev); 540 541 ret = msm_init_vram(ddev); 542 if (ret) 543 return ret; 544 545 /* Bind all our sub-components: */ 546 ret = component_bind_all(dev, ddev); 547 if (ret) 548 return ret; 549 550 dma_set_max_seg_size(dev, UINT_MAX); 551 552 msm_gem_shrinker_init(ddev); 553 554 switch (get_mdp_ver(pdev)) { 555 case KMS_MDP4: 556 kms = mdp4_kms_init(ddev); 557 priv->kms = kms; 558 break; 559 case KMS_MDP5: 560 kms = mdp5_kms_init(ddev); 561 break; 562 case KMS_DPU: 563 kms = dpu_kms_init(ddev); 564 priv->kms = kms; 565 break; 566 default: 567 /* valid only for the dummy headless case, where of_node=NULL */ 568 WARN_ON(dev->of_node); 569 kms = NULL; 570 break; 571 } 572 573 if (IS_ERR(kms)) { 574 DRM_DEV_ERROR(dev, "failed to load kms\n"); 575 ret = PTR_ERR(kms); 576 priv->kms = NULL; 577 goto err_msm_uninit; 578 } 579 580 /* Enable normalization of plane zpos */ 581 ddev->mode_config.normalize_zpos = true; 582 583 if (kms) { 584 kms->dev = ddev; 585 ret = kms->funcs->hw_init(kms); 586 if (ret) { 587 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret); 588 goto err_msm_uninit; 589 } 590 } 591 592 ddev->mode_config.funcs = &mode_config_funcs; 593 ddev->mode_config.helper_private = &mode_config_helper_funcs; 594 595 for (i = 0; i < priv->num_crtcs; i++) { 596 /* initialize event thread */ 597 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id; 598 priv->event_thread[i].dev = ddev; 599 priv->event_thread[i].worker = kthread_create_worker(0, 600 "crtc_event:%d", priv->event_thread[i].crtc_id); 601 if (IS_ERR(priv->event_thread[i].worker)) { 602 ret = PTR_ERR(priv->event_thread[i].worker); 603 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n"); 604 ret = PTR_ERR(priv->event_thread[i].worker); 605 goto err_msm_uninit; 606 } 607 608 sched_set_fifo(priv->event_thread[i].worker->task); 609 } 610 611 ret = drm_vblank_init(ddev, priv->num_crtcs); 612 if (ret < 0) { 613 DRM_DEV_ERROR(dev, "failed to initialize vblank\n"); 614 goto err_msm_uninit; 615 } 616 617 if (kms) { 618 pm_runtime_get_sync(dev); 619 ret = msm_irq_install(ddev, kms->irq); 620 pm_runtime_put_sync(dev); 621 if (ret < 0) { 622 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n"); 623 goto err_msm_uninit; 624 } 625 } 626 627 ret = drm_dev_register(ddev, 0); 628 if (ret) 629 goto err_msm_uninit; 630 631 if (kms) { 632 ret = msm_disp_snapshot_init(ddev); 633 if (ret) 634 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret); 635 } 636 drm_mode_config_reset(ddev); 637 638 #ifdef CONFIG_DRM_FBDEV_EMULATION 639 if (kms && fbdev) 640 priv->fbdev = msm_fbdev_init(ddev); 641 #endif 642 643 ret = msm_debugfs_late_init(ddev); 644 if (ret) 645 goto err_msm_uninit; 646 647 drm_kms_helper_poll_init(ddev); 648 649 return 0; 650 651 err_msm_uninit: 652 msm_drm_uninit(dev); 653 return ret; 654 } 655 656 /* 657 * DRM operations: 658 */ 659 660 static void load_gpu(struct drm_device *dev) 661 { 662 static DEFINE_MUTEX(init_lock); 663 struct msm_drm_private *priv = dev->dev_private; 664 665 mutex_lock(&init_lock); 666 667 if (!priv->gpu) 668 priv->gpu = adreno_load_gpu(dev); 669 670 mutex_unlock(&init_lock); 671 } 672 673 static int context_init(struct drm_device *dev, struct drm_file *file) 674 { 675 static atomic_t ident = ATOMIC_INIT(0); 676 struct msm_drm_private *priv = dev->dev_private; 677 struct msm_file_private *ctx; 678 679 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 680 if (!ctx) 681 return -ENOMEM; 682 683 INIT_LIST_HEAD(&ctx->submitqueues); 684 rwlock_init(&ctx->queuelock); 685 686 kref_init(&ctx->ref); 687 msm_submitqueue_init(dev, ctx); 688 689 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); 690 file->driver_priv = ctx; 691 692 ctx->seqno = atomic_inc_return(&ident); 693 694 return 0; 695 } 696 697 static int msm_open(struct drm_device *dev, struct drm_file *file) 698 { 699 /* For now, load gpu on open.. to avoid the requirement of having 700 * firmware in the initrd. 701 */ 702 load_gpu(dev); 703 704 return context_init(dev, file); 705 } 706 707 static void context_close(struct msm_file_private *ctx) 708 { 709 msm_submitqueue_close(ctx); 710 msm_file_private_put(ctx); 711 } 712 713 static void msm_postclose(struct drm_device *dev, struct drm_file *file) 714 { 715 struct msm_file_private *ctx = file->driver_priv; 716 717 context_close(ctx); 718 } 719 720 int msm_crtc_enable_vblank(struct drm_crtc *crtc) 721 { 722 struct drm_device *dev = crtc->dev; 723 unsigned int pipe = crtc->index; 724 struct msm_drm_private *priv = dev->dev_private; 725 struct msm_kms *kms = priv->kms; 726 if (!kms) 727 return -ENXIO; 728 drm_dbg_vbl(dev, "crtc=%u", pipe); 729 return vblank_ctrl_queue_work(priv, pipe, true); 730 } 731 732 void msm_crtc_disable_vblank(struct drm_crtc *crtc) 733 { 734 struct drm_device *dev = crtc->dev; 735 unsigned int pipe = crtc->index; 736 struct msm_drm_private *priv = dev->dev_private; 737 struct msm_kms *kms = priv->kms; 738 if (!kms) 739 return; 740 drm_dbg_vbl(dev, "crtc=%u", pipe); 741 vblank_ctrl_queue_work(priv, pipe, false); 742 } 743 744 /* 745 * DRM ioctls: 746 */ 747 748 static int msm_ioctl_get_param(struct drm_device *dev, void *data, 749 struct drm_file *file) 750 { 751 struct msm_drm_private *priv = dev->dev_private; 752 struct drm_msm_param *args = data; 753 struct msm_gpu *gpu; 754 755 /* for now, we just have 3d pipe.. eventually this would need to 756 * be more clever to dispatch to appropriate gpu module: 757 */ 758 if (args->pipe != MSM_PIPE_3D0) 759 return -EINVAL; 760 761 gpu = priv->gpu; 762 763 if (!gpu) 764 return -ENXIO; 765 766 return gpu->funcs->get_param(gpu, args->param, &args->value); 767 } 768 769 static int msm_ioctl_gem_new(struct drm_device *dev, void *data, 770 struct drm_file *file) 771 { 772 struct drm_msm_gem_new *args = data; 773 774 if (args->flags & ~MSM_BO_FLAGS) { 775 DRM_ERROR("invalid flags: %08x\n", args->flags); 776 return -EINVAL; 777 } 778 779 return msm_gem_new_handle(dev, file, args->size, 780 args->flags, &args->handle, NULL); 781 } 782 783 static inline ktime_t to_ktime(struct drm_msm_timespec timeout) 784 { 785 return ktime_set(timeout.tv_sec, timeout.tv_nsec); 786 } 787 788 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 789 struct drm_file *file) 790 { 791 struct drm_msm_gem_cpu_prep *args = data; 792 struct drm_gem_object *obj; 793 ktime_t timeout = to_ktime(args->timeout); 794 int ret; 795 796 if (args->op & ~MSM_PREP_FLAGS) { 797 DRM_ERROR("invalid op: %08x\n", args->op); 798 return -EINVAL; 799 } 800 801 obj = drm_gem_object_lookup(file, args->handle); 802 if (!obj) 803 return -ENOENT; 804 805 ret = msm_gem_cpu_prep(obj, args->op, &timeout); 806 807 drm_gem_object_put(obj); 808 809 return ret; 810 } 811 812 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 813 struct drm_file *file) 814 { 815 struct drm_msm_gem_cpu_fini *args = data; 816 struct drm_gem_object *obj; 817 int ret; 818 819 obj = drm_gem_object_lookup(file, args->handle); 820 if (!obj) 821 return -ENOENT; 822 823 ret = msm_gem_cpu_fini(obj); 824 825 drm_gem_object_put(obj); 826 827 return ret; 828 } 829 830 static int msm_ioctl_gem_info_iova(struct drm_device *dev, 831 struct drm_file *file, struct drm_gem_object *obj, 832 uint64_t *iova) 833 { 834 struct msm_drm_private *priv = dev->dev_private; 835 struct msm_file_private *ctx = file->driver_priv; 836 837 if (!priv->gpu) 838 return -EINVAL; 839 840 /* 841 * Don't pin the memory here - just get an address so that userspace can 842 * be productive 843 */ 844 return msm_gem_get_iova(obj, ctx->aspace, iova); 845 } 846 847 static int msm_ioctl_gem_info(struct drm_device *dev, void *data, 848 struct drm_file *file) 849 { 850 struct drm_msm_gem_info *args = data; 851 struct drm_gem_object *obj; 852 struct msm_gem_object *msm_obj; 853 int i, ret = 0; 854 855 if (args->pad) 856 return -EINVAL; 857 858 switch (args->info) { 859 case MSM_INFO_GET_OFFSET: 860 case MSM_INFO_GET_IOVA: 861 /* value returned as immediate, not pointer, so len==0: */ 862 if (args->len) 863 return -EINVAL; 864 break; 865 case MSM_INFO_SET_NAME: 866 case MSM_INFO_GET_NAME: 867 break; 868 default: 869 return -EINVAL; 870 } 871 872 obj = drm_gem_object_lookup(file, args->handle); 873 if (!obj) 874 return -ENOENT; 875 876 msm_obj = to_msm_bo(obj); 877 878 switch (args->info) { 879 case MSM_INFO_GET_OFFSET: 880 args->value = msm_gem_mmap_offset(obj); 881 break; 882 case MSM_INFO_GET_IOVA: 883 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); 884 break; 885 case MSM_INFO_SET_NAME: 886 /* length check should leave room for terminating null: */ 887 if (args->len >= sizeof(msm_obj->name)) { 888 ret = -EINVAL; 889 break; 890 } 891 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), 892 args->len)) { 893 msm_obj->name[0] = '\0'; 894 ret = -EFAULT; 895 break; 896 } 897 msm_obj->name[args->len] = '\0'; 898 for (i = 0; i < args->len; i++) { 899 if (!isprint(msm_obj->name[i])) { 900 msm_obj->name[i] = '\0'; 901 break; 902 } 903 } 904 break; 905 case MSM_INFO_GET_NAME: 906 if (args->value && (args->len < strlen(msm_obj->name))) { 907 ret = -EINVAL; 908 break; 909 } 910 args->len = strlen(msm_obj->name); 911 if (args->value) { 912 if (copy_to_user(u64_to_user_ptr(args->value), 913 msm_obj->name, args->len)) 914 ret = -EFAULT; 915 } 916 break; 917 } 918 919 drm_gem_object_put(obj); 920 921 return ret; 922 } 923 924 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, 925 ktime_t timeout) 926 { 927 struct dma_fence *fence; 928 int ret; 929 930 if (fence_after(fence_id, queue->last_fence)) { 931 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n", 932 fence_id, queue->last_fence); 933 return -EINVAL; 934 } 935 936 /* 937 * Map submitqueue scoped "seqno" (which is actually an idr key) 938 * back to underlying dma-fence 939 * 940 * The fence is removed from the fence_idr when the submit is 941 * retired, so if the fence is not found it means there is nothing 942 * to wait for 943 */ 944 ret = mutex_lock_interruptible(&queue->lock); 945 if (ret) 946 return ret; 947 fence = idr_find(&queue->fence_idr, fence_id); 948 if (fence) 949 fence = dma_fence_get_rcu(fence); 950 mutex_unlock(&queue->lock); 951 952 if (!fence) 953 return 0; 954 955 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); 956 if (ret == 0) { 957 ret = -ETIMEDOUT; 958 } else if (ret != -ERESTARTSYS) { 959 ret = 0; 960 } 961 962 dma_fence_put(fence); 963 964 return ret; 965 } 966 967 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, 968 struct drm_file *file) 969 { 970 struct msm_drm_private *priv = dev->dev_private; 971 struct drm_msm_wait_fence *args = data; 972 struct msm_gpu_submitqueue *queue; 973 int ret; 974 975 if (args->pad) { 976 DRM_ERROR("invalid pad: %08x\n", args->pad); 977 return -EINVAL; 978 } 979 980 if (!priv->gpu) 981 return 0; 982 983 queue = msm_submitqueue_get(file->driver_priv, args->queueid); 984 if (!queue) 985 return -ENOENT; 986 987 ret = wait_fence(queue, args->fence, to_ktime(args->timeout)); 988 989 msm_submitqueue_put(queue); 990 991 return ret; 992 } 993 994 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, 995 struct drm_file *file) 996 { 997 struct drm_msm_gem_madvise *args = data; 998 struct drm_gem_object *obj; 999 int ret; 1000 1001 switch (args->madv) { 1002 case MSM_MADV_DONTNEED: 1003 case MSM_MADV_WILLNEED: 1004 break; 1005 default: 1006 return -EINVAL; 1007 } 1008 1009 obj = drm_gem_object_lookup(file, args->handle); 1010 if (!obj) { 1011 return -ENOENT; 1012 } 1013 1014 ret = msm_gem_madvise(obj, args->madv); 1015 if (ret >= 0) { 1016 args->retained = ret; 1017 ret = 0; 1018 } 1019 1020 drm_gem_object_put(obj); 1021 1022 return ret; 1023 } 1024 1025 1026 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, 1027 struct drm_file *file) 1028 { 1029 struct drm_msm_submitqueue *args = data; 1030 1031 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) 1032 return -EINVAL; 1033 1034 return msm_submitqueue_create(dev, file->driver_priv, args->prio, 1035 args->flags, &args->id); 1036 } 1037 1038 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, 1039 struct drm_file *file) 1040 { 1041 return msm_submitqueue_query(dev, file->driver_priv, data); 1042 } 1043 1044 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, 1045 struct drm_file *file) 1046 { 1047 u32 id = *(u32 *) data; 1048 1049 return msm_submitqueue_remove(file->driver_priv, id); 1050 } 1051 1052 static const struct drm_ioctl_desc msm_ioctls[] = { 1053 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), 1054 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), 1055 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), 1056 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), 1057 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), 1058 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), 1059 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), 1060 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), 1061 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), 1062 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), 1063 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), 1064 }; 1065 1066 DEFINE_DRM_GEM_FOPS(fops); 1067 1068 static const struct drm_driver msm_driver = { 1069 .driver_features = DRIVER_GEM | 1070 DRIVER_RENDER | 1071 DRIVER_ATOMIC | 1072 DRIVER_MODESET | 1073 DRIVER_SYNCOBJ, 1074 .open = msm_open, 1075 .postclose = msm_postclose, 1076 .lastclose = drm_fb_helper_lastclose, 1077 .dumb_create = msm_gem_dumb_create, 1078 .dumb_map_offset = msm_gem_dumb_map_offset, 1079 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1080 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1081 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 1082 .gem_prime_mmap = drm_gem_prime_mmap, 1083 #ifdef CONFIG_DEBUG_FS 1084 .debugfs_init = msm_debugfs_init, 1085 #endif 1086 .ioctls = msm_ioctls, 1087 .num_ioctls = ARRAY_SIZE(msm_ioctls), 1088 .fops = &fops, 1089 .name = "msm", 1090 .desc = "MSM Snapdragon DRM", 1091 .date = "20130625", 1092 .major = MSM_VERSION_MAJOR, 1093 .minor = MSM_VERSION_MINOR, 1094 .patchlevel = MSM_VERSION_PATCHLEVEL, 1095 }; 1096 1097 static int __maybe_unused msm_runtime_suspend(struct device *dev) 1098 { 1099 struct msm_drm_private *priv = dev_get_drvdata(dev); 1100 struct msm_mdss *mdss = priv->mdss; 1101 1102 DBG(""); 1103 1104 if (mdss && mdss->funcs) 1105 return mdss->funcs->disable(mdss); 1106 1107 return 0; 1108 } 1109 1110 static int __maybe_unused msm_runtime_resume(struct device *dev) 1111 { 1112 struct msm_drm_private *priv = dev_get_drvdata(dev); 1113 struct msm_mdss *mdss = priv->mdss; 1114 1115 DBG(""); 1116 1117 if (mdss && mdss->funcs) 1118 return mdss->funcs->enable(mdss); 1119 1120 return 0; 1121 } 1122 1123 static int __maybe_unused msm_pm_suspend(struct device *dev) 1124 { 1125 1126 if (pm_runtime_suspended(dev)) 1127 return 0; 1128 1129 return msm_runtime_suspend(dev); 1130 } 1131 1132 static int __maybe_unused msm_pm_resume(struct device *dev) 1133 { 1134 if (pm_runtime_suspended(dev)) 1135 return 0; 1136 1137 return msm_runtime_resume(dev); 1138 } 1139 1140 static int __maybe_unused msm_pm_prepare(struct device *dev) 1141 { 1142 struct msm_drm_private *priv = dev_get_drvdata(dev); 1143 struct drm_device *ddev = priv ? priv->dev : NULL; 1144 1145 if (!priv || !priv->kms) 1146 return 0; 1147 1148 return drm_mode_config_helper_suspend(ddev); 1149 } 1150 1151 static void __maybe_unused msm_pm_complete(struct device *dev) 1152 { 1153 struct msm_drm_private *priv = dev_get_drvdata(dev); 1154 struct drm_device *ddev = priv ? priv->dev : NULL; 1155 1156 if (!priv || !priv->kms) 1157 return; 1158 1159 drm_mode_config_helper_resume(ddev); 1160 } 1161 1162 static const struct dev_pm_ops msm_pm_ops = { 1163 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) 1164 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL) 1165 .prepare = msm_pm_prepare, 1166 .complete = msm_pm_complete, 1167 }; 1168 1169 /* 1170 * Componentized driver support: 1171 */ 1172 1173 /* 1174 * NOTE: duplication of the same code as exynos or imx (or probably any other). 1175 * so probably some room for some helpers 1176 */ 1177 static int compare_of(struct device *dev, void *data) 1178 { 1179 return dev->of_node == data; 1180 } 1181 1182 /* 1183 * Identify what components need to be added by parsing what remote-endpoints 1184 * our MDP output ports are connected to. In the case of LVDS on MDP4, there 1185 * is no external component that we need to add since LVDS is within MDP4 1186 * itself. 1187 */ 1188 static int add_components_mdp(struct device *mdp_dev, 1189 struct component_match **matchptr) 1190 { 1191 struct device_node *np = mdp_dev->of_node; 1192 struct device_node *ep_node; 1193 struct device *master_dev; 1194 1195 /* 1196 * on MDP4 based platforms, the MDP platform device is the component 1197 * master that adds other display interface components to itself. 1198 * 1199 * on MDP5 based platforms, the MDSS platform device is the component 1200 * master that adds MDP5 and other display interface components to 1201 * itself. 1202 */ 1203 if (of_device_is_compatible(np, "qcom,mdp4")) 1204 master_dev = mdp_dev; 1205 else 1206 master_dev = mdp_dev->parent; 1207 1208 for_each_endpoint_of_node(np, ep_node) { 1209 struct device_node *intf; 1210 struct of_endpoint ep; 1211 int ret; 1212 1213 ret = of_graph_parse_endpoint(ep_node, &ep); 1214 if (ret) { 1215 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n"); 1216 of_node_put(ep_node); 1217 return ret; 1218 } 1219 1220 /* 1221 * The LCDC/LVDS port on MDP4 is a speacial case where the 1222 * remote-endpoint isn't a component that we need to add 1223 */ 1224 if (of_device_is_compatible(np, "qcom,mdp4") && 1225 ep.port == 0) 1226 continue; 1227 1228 /* 1229 * It's okay if some of the ports don't have a remote endpoint 1230 * specified. It just means that the port isn't connected to 1231 * any external interface. 1232 */ 1233 intf = of_graph_get_remote_port_parent(ep_node); 1234 if (!intf) 1235 continue; 1236 1237 if (of_device_is_available(intf)) 1238 drm_of_component_match_add(master_dev, matchptr, 1239 compare_of, intf); 1240 1241 of_node_put(intf); 1242 } 1243 1244 return 0; 1245 } 1246 1247 static int find_mdp_node(struct device *dev, void *data) 1248 { 1249 return of_match_node(dpu_dt_match, dev->of_node) || 1250 of_match_node(mdp5_dt_match, dev->of_node); 1251 } 1252 1253 static int add_display_components(struct platform_device *pdev, 1254 struct component_match **matchptr) 1255 { 1256 struct device *mdp_dev; 1257 struct device *dev = &pdev->dev; 1258 int ret; 1259 1260 /* 1261 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 1262 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 1263 * Populate the children devices, find the MDP5/DPU node, and then add 1264 * the interfaces to our components list. 1265 */ 1266 switch (get_mdp_ver(pdev)) { 1267 case KMS_MDP5: 1268 case KMS_DPU: 1269 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 1270 if (ret) { 1271 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 1272 return ret; 1273 } 1274 1275 mdp_dev = device_find_child(dev, NULL, find_mdp_node); 1276 if (!mdp_dev) { 1277 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n"); 1278 of_platform_depopulate(dev); 1279 return -ENODEV; 1280 } 1281 1282 put_device(mdp_dev); 1283 1284 /* add the MDP component itself */ 1285 drm_of_component_match_add(dev, matchptr, compare_of, 1286 mdp_dev->of_node); 1287 break; 1288 case KMS_MDP4: 1289 /* MDP4 */ 1290 mdp_dev = dev; 1291 break; 1292 } 1293 1294 ret = add_components_mdp(mdp_dev, matchptr); 1295 if (ret) 1296 of_platform_depopulate(dev); 1297 1298 return ret; 1299 } 1300 1301 /* 1302 * We don't know what's the best binding to link the gpu with the drm device. 1303 * Fow now, we just hunt for all the possible gpus that we support, and add them 1304 * as components. 1305 */ 1306 static const struct of_device_id msm_gpu_match[] = { 1307 { .compatible = "qcom,adreno" }, 1308 { .compatible = "qcom,adreno-3xx" }, 1309 { .compatible = "amd,imageon" }, 1310 { .compatible = "qcom,kgsl-3d0" }, 1311 { }, 1312 }; 1313 1314 static int add_gpu_components(struct device *dev, 1315 struct component_match **matchptr) 1316 { 1317 struct device_node *np; 1318 1319 np = of_find_matching_node(NULL, msm_gpu_match); 1320 if (!np) 1321 return 0; 1322 1323 if (of_device_is_available(np)) 1324 drm_of_component_match_add(dev, matchptr, compare_of, np); 1325 1326 of_node_put(np); 1327 1328 return 0; 1329 } 1330 1331 static int msm_drm_bind(struct device *dev) 1332 { 1333 return msm_drm_init(dev, &msm_driver); 1334 } 1335 1336 static void msm_drm_unbind(struct device *dev) 1337 { 1338 msm_drm_uninit(dev); 1339 } 1340 1341 static const struct component_master_ops msm_drm_ops = { 1342 .bind = msm_drm_bind, 1343 .unbind = msm_drm_unbind, 1344 }; 1345 1346 /* 1347 * Platform driver: 1348 */ 1349 1350 static int msm_pdev_probe(struct platform_device *pdev) 1351 { 1352 struct component_match *match = NULL; 1353 struct msm_drm_private *priv; 1354 int ret; 1355 1356 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1357 if (!priv) 1358 return -ENOMEM; 1359 1360 platform_set_drvdata(pdev, priv); 1361 1362 switch (get_mdp_ver(pdev)) { 1363 case KMS_MDP5: 1364 ret = mdp5_mdss_init(pdev); 1365 break; 1366 case KMS_DPU: 1367 ret = dpu_mdss_init(pdev); 1368 break; 1369 default: 1370 ret = 0; 1371 break; 1372 } 1373 if (ret) { 1374 platform_set_drvdata(pdev, NULL); 1375 return ret; 1376 } 1377 1378 if (get_mdp_ver(pdev)) { 1379 ret = add_display_components(pdev, &match); 1380 if (ret) 1381 goto fail; 1382 } 1383 1384 ret = add_gpu_components(&pdev->dev, &match); 1385 if (ret) 1386 goto fail; 1387 1388 /* on all devices that I am aware of, iommu's which can map 1389 * any address the cpu can see are used: 1390 */ 1391 ret = dma_set_mask_and_coherent(&pdev->dev, ~0); 1392 if (ret) 1393 goto fail; 1394 1395 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); 1396 if (ret) 1397 goto fail; 1398 1399 return 0; 1400 1401 fail: 1402 of_platform_depopulate(&pdev->dev); 1403 1404 if (priv->mdss && priv->mdss->funcs) 1405 priv->mdss->funcs->destroy(priv->mdss); 1406 1407 return ret; 1408 } 1409 1410 static int msm_pdev_remove(struct platform_device *pdev) 1411 { 1412 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1413 struct msm_mdss *mdss = priv->mdss; 1414 1415 component_master_del(&pdev->dev, &msm_drm_ops); 1416 of_platform_depopulate(&pdev->dev); 1417 1418 if (mdss && mdss->funcs) 1419 mdss->funcs->destroy(mdss); 1420 1421 return 0; 1422 } 1423 1424 static void msm_pdev_shutdown(struct platform_device *pdev) 1425 { 1426 struct msm_drm_private *priv = platform_get_drvdata(pdev); 1427 struct drm_device *drm = priv ? priv->dev : NULL; 1428 1429 if (!priv || !priv->kms) 1430 return; 1431 1432 drm_atomic_helper_shutdown(drm); 1433 } 1434 1435 static const struct of_device_id dt_match[] = { 1436 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, 1437 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, 1438 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU }, 1439 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU }, 1440 { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU }, 1441 { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU }, 1442 { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU }, 1443 {} 1444 }; 1445 MODULE_DEVICE_TABLE(of, dt_match); 1446 1447 static struct platform_driver msm_platform_driver = { 1448 .probe = msm_pdev_probe, 1449 .remove = msm_pdev_remove, 1450 .shutdown = msm_pdev_shutdown, 1451 .driver = { 1452 .name = "msm", 1453 .of_match_table = dt_match, 1454 .pm = &msm_pm_ops, 1455 }, 1456 }; 1457 1458 static int __init msm_drm_register(void) 1459 { 1460 if (!modeset) 1461 return -EINVAL; 1462 1463 DBG("init"); 1464 msm_mdp_register(); 1465 msm_dpu_register(); 1466 msm_dsi_register(); 1467 msm_hdmi_register(); 1468 msm_dp_register(); 1469 adreno_register(); 1470 return platform_driver_register(&msm_platform_driver); 1471 } 1472 1473 static void __exit msm_drm_unregister(void) 1474 { 1475 DBG("fini"); 1476 platform_driver_unregister(&msm_platform_driver); 1477 msm_dp_unregister(); 1478 msm_hdmi_unregister(); 1479 adreno_unregister(); 1480 msm_dsi_unregister(); 1481 msm_mdp_unregister(); 1482 msm_dpu_unregister(); 1483 } 1484 1485 module_init(msm_drm_register); 1486 module_exit(msm_drm_unregister); 1487 1488 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1489 MODULE_DESCRIPTION("MSM DRM Driver"); 1490 MODULE_LICENSE("GPL"); 1491