1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/fault-inject.h> 10 #include <linux/of_address.h> 11 #include <linux/uaccess.h> 12 13 #include <drm/drm_drv.h> 14 #include <drm/drm_file.h> 15 #include <drm/drm_ioctl.h> 16 #include <drm/drm_of.h> 17 18 #include "msm_drv.h" 19 #include "msm_debugfs.h" 20 #include "msm_kms.h" 21 #include "adreno/adreno_gpu.h" 22 23 /* 24 * MSM driver version: 25 * - 1.0.0 - initial interface 26 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers 27 * - 1.2.0 - adds explicit fence support for submit ioctl 28 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + 29 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for 30 * MSM_GEM_INFO ioctl. 31 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get 32 * GEM object's debug name 33 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl 34 * - 1.6.0 - Syncobj support 35 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count 36 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx) 37 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN 38 * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT 39 * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST) 40 */ 41 #define MSM_VERSION_MAJOR 1 42 #define MSM_VERSION_MINOR 10 43 #define MSM_VERSION_PATCHLEVEL 0 44 45 static void msm_deinit_vram(struct drm_device *ddev); 46 47 static char *vram = "16m"; 48 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); 49 module_param(vram, charp, 0); 50 51 bool dumpstate; 52 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); 53 module_param(dumpstate, bool, 0600); 54 55 static bool modeset = true; 56 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); 57 module_param(modeset, bool, 0600); 58 59 #ifdef CONFIG_FAULT_INJECTION 60 DECLARE_FAULT_ATTR(fail_gem_alloc); 61 DECLARE_FAULT_ATTR(fail_gem_iova); 62 #endif 63 64 static int msm_drm_uninit(struct device *dev) 65 { 66 struct platform_device *pdev = to_platform_device(dev); 67 struct msm_drm_private *priv = platform_get_drvdata(pdev); 68 struct drm_device *ddev = priv->dev; 69 70 /* 71 * Shutdown the hw if we're far enough along where things might be on. 72 * If we run this too early, we'll end up panicking in any variety of 73 * places. Since we don't register the drm device until late in 74 * msm_drm_init, drm_dev->registered is used as an indicator that the 75 * shutdown will be successful. 76 */ 77 if (ddev->registered) { 78 drm_dev_unregister(ddev); 79 if (priv->kms) 80 drm_atomic_helper_shutdown(ddev); 81 } 82 83 /* We must cancel and cleanup any pending vblank enable/disable 84 * work before msm_irq_uninstall() to avoid work re-enabling an 85 * irq after uninstall has disabled it. 86 */ 87 88 flush_workqueue(priv->wq); 89 90 msm_gem_shrinker_cleanup(ddev); 91 92 msm_perf_debugfs_cleanup(priv); 93 msm_rd_debugfs_cleanup(priv); 94 95 if (priv->kms) 96 msm_drm_kms_uninit(dev); 97 98 msm_deinit_vram(ddev); 99 100 component_unbind_all(dev, ddev); 101 102 ddev->dev_private = NULL; 103 drm_dev_put(ddev); 104 105 destroy_workqueue(priv->wq); 106 107 return 0; 108 } 109 110 bool msm_use_mmu(struct drm_device *dev) 111 { 112 struct msm_drm_private *priv = dev->dev_private; 113 114 /* 115 * a2xx comes with its own MMU 116 * On other platforms IOMMU can be declared specified either for the 117 * MDP/DPU device or for its parent, MDSS device. 118 */ 119 return priv->is_a2xx || 120 device_iommu_mapped(dev->dev) || 121 device_iommu_mapped(dev->dev->parent); 122 } 123 124 static int msm_init_vram(struct drm_device *dev) 125 { 126 struct msm_drm_private *priv = dev->dev_private; 127 struct device_node *node; 128 unsigned long size = 0; 129 int ret = 0; 130 131 /* In the device-tree world, we could have a 'memory-region' 132 * phandle, which gives us a link to our "vram". Allocating 133 * is all nicely abstracted behind the dma api, but we need 134 * to know the entire size to allocate it all in one go. There 135 * are two cases: 136 * 1) device with no IOMMU, in which case we need exclusive 137 * access to a VRAM carveout big enough for all gpu 138 * buffers 139 * 2) device with IOMMU, but where the bootloader puts up 140 * a splash screen. In this case, the VRAM carveout 141 * need only be large enough for fbdev fb. But we need 142 * exclusive access to the buffer to avoid the kernel 143 * using those pages for other purposes (which appears 144 * as corruption on screen before we have a chance to 145 * load and do initial modeset) 146 */ 147 148 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); 149 if (node) { 150 struct resource r; 151 ret = of_address_to_resource(node, 0, &r); 152 of_node_put(node); 153 if (ret) 154 return ret; 155 size = r.end - r.start + 1; 156 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); 157 158 /* if we have no IOMMU, then we need to use carveout allocator. 159 * Grab the entire DMA chunk carved out in early startup in 160 * mach-msm: 161 */ 162 } else if (!msm_use_mmu(dev)) { 163 DRM_INFO("using %s VRAM carveout\n", vram); 164 size = memparse(vram, NULL); 165 } 166 167 if (size) { 168 unsigned long attrs = 0; 169 void *p; 170 171 priv->vram.size = size; 172 173 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); 174 spin_lock_init(&priv->vram.lock); 175 176 attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 177 attrs |= DMA_ATTR_WRITE_COMBINE; 178 179 /* note that for no-kernel-mapping, the vaddr returned 180 * is bogus, but non-null if allocation succeeded: 181 */ 182 p = dma_alloc_attrs(dev->dev, size, 183 &priv->vram.paddr, GFP_KERNEL, attrs); 184 if (!p) { 185 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n"); 186 priv->vram.paddr = 0; 187 return -ENOMEM; 188 } 189 190 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n", 191 (uint32_t)priv->vram.paddr, 192 (uint32_t)(priv->vram.paddr + size)); 193 } 194 195 return ret; 196 } 197 198 static void msm_deinit_vram(struct drm_device *ddev) 199 { 200 struct msm_drm_private *priv = ddev->dev_private; 201 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; 202 203 if (!priv->vram.paddr) 204 return; 205 206 drm_mm_takedown(&priv->vram.mm); 207 dma_free_attrs(ddev->dev, priv->vram.size, NULL, priv->vram.paddr, 208 attrs); 209 } 210 211 static int msm_drm_init(struct device *dev, const struct drm_driver *drv) 212 { 213 struct msm_drm_private *priv = dev_get_drvdata(dev); 214 struct drm_device *ddev; 215 int ret; 216 217 if (drm_firmware_drivers_only()) 218 return -ENODEV; 219 220 ddev = drm_dev_alloc(drv, dev); 221 if (IS_ERR(ddev)) { 222 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); 223 return PTR_ERR(ddev); 224 } 225 ddev->dev_private = priv; 226 priv->dev = ddev; 227 228 priv->wq = alloc_ordered_workqueue("msm", 0); 229 if (!priv->wq) { 230 ret = -ENOMEM; 231 goto err_put_dev; 232 } 233 234 INIT_LIST_HEAD(&priv->objects); 235 mutex_init(&priv->obj_lock); 236 237 /* 238 * Initialize the LRUs: 239 */ 240 mutex_init(&priv->lru.lock); 241 drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock); 242 drm_gem_lru_init(&priv->lru.pinned, &priv->lru.lock); 243 drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock); 244 drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock); 245 246 /* Teach lockdep about lock ordering wrt. shrinker: */ 247 fs_reclaim_acquire(GFP_KERNEL); 248 might_lock(&priv->lru.lock); 249 fs_reclaim_release(GFP_KERNEL); 250 251 if (priv->kms_init) { 252 ret = drmm_mode_config_init(ddev); 253 if (ret) 254 goto err_destroy_wq; 255 } 256 257 ret = msm_init_vram(ddev); 258 if (ret) 259 goto err_destroy_wq; 260 261 dma_set_max_seg_size(dev, UINT_MAX); 262 263 /* Bind all our sub-components: */ 264 ret = component_bind_all(dev, ddev); 265 if (ret) 266 goto err_deinit_vram; 267 268 ret = msm_gem_shrinker_init(ddev); 269 if (ret) 270 goto err_msm_uninit; 271 272 if (priv->kms_init) { 273 ret = msm_drm_kms_init(dev, drv); 274 if (ret) 275 goto err_msm_uninit; 276 } else { 277 /* valid only for the dummy headless case, where of_node=NULL */ 278 WARN_ON(dev->of_node); 279 ddev->driver_features &= ~DRIVER_MODESET; 280 ddev->driver_features &= ~DRIVER_ATOMIC; 281 } 282 283 ret = drm_dev_register(ddev, 0); 284 if (ret) 285 goto err_msm_uninit; 286 287 ret = msm_debugfs_late_init(ddev); 288 if (ret) 289 goto err_msm_uninit; 290 291 drm_kms_helper_poll_init(ddev); 292 293 if (priv->kms_init) { 294 drm_kms_helper_poll_init(ddev); 295 msm_fbdev_setup(ddev); 296 } 297 298 return 0; 299 300 err_msm_uninit: 301 msm_drm_uninit(dev); 302 303 return ret; 304 305 err_deinit_vram: 306 msm_deinit_vram(ddev); 307 err_destroy_wq: 308 destroy_workqueue(priv->wq); 309 err_put_dev: 310 drm_dev_put(ddev); 311 312 return ret; 313 } 314 315 /* 316 * DRM operations: 317 */ 318 319 static void load_gpu(struct drm_device *dev) 320 { 321 static DEFINE_MUTEX(init_lock); 322 struct msm_drm_private *priv = dev->dev_private; 323 324 mutex_lock(&init_lock); 325 326 if (!priv->gpu) 327 priv->gpu = adreno_load_gpu(dev); 328 329 mutex_unlock(&init_lock); 330 } 331 332 static int context_init(struct drm_device *dev, struct drm_file *file) 333 { 334 static atomic_t ident = ATOMIC_INIT(0); 335 struct msm_drm_private *priv = dev->dev_private; 336 struct msm_file_private *ctx; 337 338 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 339 if (!ctx) 340 return -ENOMEM; 341 342 INIT_LIST_HEAD(&ctx->submitqueues); 343 rwlock_init(&ctx->queuelock); 344 345 kref_init(&ctx->ref); 346 msm_submitqueue_init(dev, ctx); 347 348 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); 349 file->driver_priv = ctx; 350 351 ctx->seqno = atomic_inc_return(&ident); 352 353 return 0; 354 } 355 356 static int msm_open(struct drm_device *dev, struct drm_file *file) 357 { 358 /* For now, load gpu on open.. to avoid the requirement of having 359 * firmware in the initrd. 360 */ 361 load_gpu(dev); 362 363 return context_init(dev, file); 364 } 365 366 static void context_close(struct msm_file_private *ctx) 367 { 368 msm_submitqueue_close(ctx); 369 msm_file_private_put(ctx); 370 } 371 372 static void msm_postclose(struct drm_device *dev, struct drm_file *file) 373 { 374 struct msm_drm_private *priv = dev->dev_private; 375 struct msm_file_private *ctx = file->driver_priv; 376 377 /* 378 * It is not possible to set sysprof param to non-zero if gpu 379 * is not initialized: 380 */ 381 if (priv->gpu) 382 msm_file_private_set_sysprof(ctx, priv->gpu, 0); 383 384 context_close(ctx); 385 } 386 387 /* 388 * DRM ioctls: 389 */ 390 391 static int msm_ioctl_get_param(struct drm_device *dev, void *data, 392 struct drm_file *file) 393 { 394 struct msm_drm_private *priv = dev->dev_private; 395 struct drm_msm_param *args = data; 396 struct msm_gpu *gpu; 397 398 /* for now, we just have 3d pipe.. eventually this would need to 399 * be more clever to dispatch to appropriate gpu module: 400 */ 401 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 402 return -EINVAL; 403 404 gpu = priv->gpu; 405 406 if (!gpu) 407 return -ENXIO; 408 409 return gpu->funcs->get_param(gpu, file->driver_priv, 410 args->param, &args->value, &args->len); 411 } 412 413 static int msm_ioctl_set_param(struct drm_device *dev, void *data, 414 struct drm_file *file) 415 { 416 struct msm_drm_private *priv = dev->dev_private; 417 struct drm_msm_param *args = data; 418 struct msm_gpu *gpu; 419 420 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0)) 421 return -EINVAL; 422 423 gpu = priv->gpu; 424 425 if (!gpu) 426 return -ENXIO; 427 428 return gpu->funcs->set_param(gpu, file->driver_priv, 429 args->param, args->value, args->len); 430 } 431 432 static int msm_ioctl_gem_new(struct drm_device *dev, void *data, 433 struct drm_file *file) 434 { 435 struct drm_msm_gem_new *args = data; 436 uint32_t flags = args->flags; 437 438 if (args->flags & ~MSM_BO_FLAGS) { 439 DRM_ERROR("invalid flags: %08x\n", args->flags); 440 return -EINVAL; 441 } 442 443 /* 444 * Uncached CPU mappings are deprecated, as of: 445 * 446 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)") 447 * 448 * So promote them to WC. 449 */ 450 if (flags & MSM_BO_UNCACHED) { 451 flags &= ~MSM_BO_CACHED; 452 flags |= MSM_BO_WC; 453 } 454 455 if (should_fail(&fail_gem_alloc, args->size)) 456 return -ENOMEM; 457 458 return msm_gem_new_handle(dev, file, args->size, 459 args->flags, &args->handle, NULL); 460 } 461 462 static inline ktime_t to_ktime(struct drm_msm_timespec timeout) 463 { 464 return ktime_set(timeout.tv_sec, timeout.tv_nsec); 465 } 466 467 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 468 struct drm_file *file) 469 { 470 struct drm_msm_gem_cpu_prep *args = data; 471 struct drm_gem_object *obj; 472 ktime_t timeout = to_ktime(args->timeout); 473 int ret; 474 475 if (args->op & ~MSM_PREP_FLAGS) { 476 DRM_ERROR("invalid op: %08x\n", args->op); 477 return -EINVAL; 478 } 479 480 obj = drm_gem_object_lookup(file, args->handle); 481 if (!obj) 482 return -ENOENT; 483 484 ret = msm_gem_cpu_prep(obj, args->op, &timeout); 485 486 drm_gem_object_put(obj); 487 488 return ret; 489 } 490 491 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 492 struct drm_file *file) 493 { 494 struct drm_msm_gem_cpu_fini *args = data; 495 struct drm_gem_object *obj; 496 int ret; 497 498 obj = drm_gem_object_lookup(file, args->handle); 499 if (!obj) 500 return -ENOENT; 501 502 ret = msm_gem_cpu_fini(obj); 503 504 drm_gem_object_put(obj); 505 506 return ret; 507 } 508 509 static int msm_ioctl_gem_info_iova(struct drm_device *dev, 510 struct drm_file *file, struct drm_gem_object *obj, 511 uint64_t *iova) 512 { 513 struct msm_drm_private *priv = dev->dev_private; 514 struct msm_file_private *ctx = file->driver_priv; 515 516 if (!priv->gpu) 517 return -EINVAL; 518 519 if (should_fail(&fail_gem_iova, obj->size)) 520 return -ENOMEM; 521 522 /* 523 * Don't pin the memory here - just get an address so that userspace can 524 * be productive 525 */ 526 return msm_gem_get_iova(obj, ctx->aspace, iova); 527 } 528 529 static int msm_ioctl_gem_info_set_iova(struct drm_device *dev, 530 struct drm_file *file, struct drm_gem_object *obj, 531 uint64_t iova) 532 { 533 struct msm_drm_private *priv = dev->dev_private; 534 struct msm_file_private *ctx = file->driver_priv; 535 536 if (!priv->gpu) 537 return -EINVAL; 538 539 /* Only supported if per-process address space is supported: */ 540 if (priv->gpu->aspace == ctx->aspace) 541 return -EOPNOTSUPP; 542 543 if (should_fail(&fail_gem_iova, obj->size)) 544 return -ENOMEM; 545 546 return msm_gem_set_iova(obj, ctx->aspace, iova); 547 } 548 549 static int msm_ioctl_gem_info(struct drm_device *dev, void *data, 550 struct drm_file *file) 551 { 552 struct drm_msm_gem_info *args = data; 553 struct drm_gem_object *obj; 554 struct msm_gem_object *msm_obj; 555 int i, ret = 0; 556 557 if (args->pad) 558 return -EINVAL; 559 560 switch (args->info) { 561 case MSM_INFO_GET_OFFSET: 562 case MSM_INFO_GET_IOVA: 563 case MSM_INFO_SET_IOVA: 564 case MSM_INFO_GET_FLAGS: 565 /* value returned as immediate, not pointer, so len==0: */ 566 if (args->len) 567 return -EINVAL; 568 break; 569 case MSM_INFO_SET_NAME: 570 case MSM_INFO_GET_NAME: 571 break; 572 default: 573 return -EINVAL; 574 } 575 576 obj = drm_gem_object_lookup(file, args->handle); 577 if (!obj) 578 return -ENOENT; 579 580 msm_obj = to_msm_bo(obj); 581 582 switch (args->info) { 583 case MSM_INFO_GET_OFFSET: 584 args->value = msm_gem_mmap_offset(obj); 585 break; 586 case MSM_INFO_GET_IOVA: 587 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); 588 break; 589 case MSM_INFO_SET_IOVA: 590 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value); 591 break; 592 case MSM_INFO_GET_FLAGS: 593 if (obj->import_attach) { 594 ret = -EINVAL; 595 break; 596 } 597 /* Hide internal kernel-only flags: */ 598 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS; 599 ret = 0; 600 break; 601 case MSM_INFO_SET_NAME: 602 /* length check should leave room for terminating null: */ 603 if (args->len >= sizeof(msm_obj->name)) { 604 ret = -EINVAL; 605 break; 606 } 607 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), 608 args->len)) { 609 msm_obj->name[0] = '\0'; 610 ret = -EFAULT; 611 break; 612 } 613 msm_obj->name[args->len] = '\0'; 614 for (i = 0; i < args->len; i++) { 615 if (!isprint(msm_obj->name[i])) { 616 msm_obj->name[i] = '\0'; 617 break; 618 } 619 } 620 break; 621 case MSM_INFO_GET_NAME: 622 if (args->value && (args->len < strlen(msm_obj->name))) { 623 ret = -EINVAL; 624 break; 625 } 626 args->len = strlen(msm_obj->name); 627 if (args->value) { 628 if (copy_to_user(u64_to_user_ptr(args->value), 629 msm_obj->name, args->len)) 630 ret = -EFAULT; 631 } 632 break; 633 } 634 635 drm_gem_object_put(obj); 636 637 return ret; 638 } 639 640 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id, 641 ktime_t timeout, uint32_t flags) 642 { 643 struct dma_fence *fence; 644 int ret; 645 646 if (fence_after(fence_id, queue->last_fence)) { 647 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n", 648 fence_id, queue->last_fence); 649 return -EINVAL; 650 } 651 652 /* 653 * Map submitqueue scoped "seqno" (which is actually an idr key) 654 * back to underlying dma-fence 655 * 656 * The fence is removed from the fence_idr when the submit is 657 * retired, so if the fence is not found it means there is nothing 658 * to wait for 659 */ 660 spin_lock(&queue->idr_lock); 661 fence = idr_find(&queue->fence_idr, fence_id); 662 if (fence) 663 fence = dma_fence_get_rcu(fence); 664 spin_unlock(&queue->idr_lock); 665 666 if (!fence) 667 return 0; 668 669 if (flags & MSM_WAIT_FENCE_BOOST) 670 dma_fence_set_deadline(fence, ktime_get()); 671 672 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout)); 673 if (ret == 0) { 674 ret = -ETIMEDOUT; 675 } else if (ret != -ERESTARTSYS) { 676 ret = 0; 677 } 678 679 dma_fence_put(fence); 680 681 return ret; 682 } 683 684 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, 685 struct drm_file *file) 686 { 687 struct msm_drm_private *priv = dev->dev_private; 688 struct drm_msm_wait_fence *args = data; 689 struct msm_gpu_submitqueue *queue; 690 int ret; 691 692 if (args->flags & ~MSM_WAIT_FENCE_FLAGS) { 693 DRM_ERROR("invalid flags: %08x\n", args->flags); 694 return -EINVAL; 695 } 696 697 if (!priv->gpu) 698 return 0; 699 700 queue = msm_submitqueue_get(file->driver_priv, args->queueid); 701 if (!queue) 702 return -ENOENT; 703 704 ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags); 705 706 msm_submitqueue_put(queue); 707 708 return ret; 709 } 710 711 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, 712 struct drm_file *file) 713 { 714 struct drm_msm_gem_madvise *args = data; 715 struct drm_gem_object *obj; 716 int ret; 717 718 switch (args->madv) { 719 case MSM_MADV_DONTNEED: 720 case MSM_MADV_WILLNEED: 721 break; 722 default: 723 return -EINVAL; 724 } 725 726 obj = drm_gem_object_lookup(file, args->handle); 727 if (!obj) { 728 return -ENOENT; 729 } 730 731 ret = msm_gem_madvise(obj, args->madv); 732 if (ret >= 0) { 733 args->retained = ret; 734 ret = 0; 735 } 736 737 drm_gem_object_put(obj); 738 739 return ret; 740 } 741 742 743 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, 744 struct drm_file *file) 745 { 746 struct drm_msm_submitqueue *args = data; 747 748 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) 749 return -EINVAL; 750 751 return msm_submitqueue_create(dev, file->driver_priv, args->prio, 752 args->flags, &args->id); 753 } 754 755 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, 756 struct drm_file *file) 757 { 758 return msm_submitqueue_query(dev, file->driver_priv, data); 759 } 760 761 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, 762 struct drm_file *file) 763 { 764 u32 id = *(u32 *) data; 765 766 return msm_submitqueue_remove(file->driver_priv, id); 767 } 768 769 static const struct drm_ioctl_desc msm_ioctls[] = { 770 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), 771 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW), 772 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), 773 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), 774 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), 775 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), 776 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), 777 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), 778 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), 779 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), 780 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), 781 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), 782 }; 783 784 static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file) 785 { 786 struct drm_device *dev = file->minor->dev; 787 struct msm_drm_private *priv = dev->dev_private; 788 789 if (!priv->gpu) 790 return; 791 792 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p); 793 794 drm_show_memory_stats(p, file); 795 } 796 797 static const struct file_operations fops = { 798 .owner = THIS_MODULE, 799 DRM_GEM_FOPS, 800 .show_fdinfo = drm_show_fdinfo, 801 }; 802 803 static const struct drm_driver msm_driver = { 804 .driver_features = DRIVER_GEM | 805 DRIVER_RENDER | 806 DRIVER_ATOMIC | 807 DRIVER_MODESET | 808 DRIVER_SYNCOBJ, 809 .open = msm_open, 810 .postclose = msm_postclose, 811 .dumb_create = msm_gem_dumb_create, 812 .dumb_map_offset = msm_gem_dumb_map_offset, 813 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 814 #ifdef CONFIG_DEBUG_FS 815 .debugfs_init = msm_debugfs_init, 816 #endif 817 .show_fdinfo = msm_show_fdinfo, 818 .ioctls = msm_ioctls, 819 .num_ioctls = ARRAY_SIZE(msm_ioctls), 820 .fops = &fops, 821 .name = "msm", 822 .desc = "MSM Snapdragon DRM", 823 .date = "20130625", 824 .major = MSM_VERSION_MAJOR, 825 .minor = MSM_VERSION_MINOR, 826 .patchlevel = MSM_VERSION_PATCHLEVEL, 827 }; 828 829 /* 830 * Componentized driver support: 831 */ 832 833 /* 834 * Identify what components need to be added by parsing what remote-endpoints 835 * our MDP output ports are connected to. In the case of LVDS on MDP4, there 836 * is no external component that we need to add since LVDS is within MDP4 837 * itself. 838 */ 839 static int add_components_mdp(struct device *master_dev, 840 struct component_match **matchptr) 841 { 842 struct device_node *np = master_dev->of_node; 843 struct device_node *ep_node; 844 845 for_each_endpoint_of_node(np, ep_node) { 846 struct device_node *intf; 847 struct of_endpoint ep; 848 int ret; 849 850 ret = of_graph_parse_endpoint(ep_node, &ep); 851 if (ret) { 852 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n"); 853 of_node_put(ep_node); 854 return ret; 855 } 856 857 /* 858 * The LCDC/LVDS port on MDP4 is a speacial case where the 859 * remote-endpoint isn't a component that we need to add 860 */ 861 if (of_device_is_compatible(np, "qcom,mdp4") && 862 ep.port == 0) 863 continue; 864 865 /* 866 * It's okay if some of the ports don't have a remote endpoint 867 * specified. It just means that the port isn't connected to 868 * any external interface. 869 */ 870 intf = of_graph_get_remote_port_parent(ep_node); 871 if (!intf) 872 continue; 873 874 if (of_device_is_available(intf)) 875 drm_of_component_match_add(master_dev, matchptr, 876 component_compare_of, intf); 877 878 of_node_put(intf); 879 } 880 881 return 0; 882 } 883 884 /* 885 * We don't know what's the best binding to link the gpu with the drm device. 886 * Fow now, we just hunt for all the possible gpus that we support, and add them 887 * as components. 888 */ 889 static const struct of_device_id msm_gpu_match[] = { 890 { .compatible = "qcom,adreno" }, 891 { .compatible = "qcom,adreno-3xx" }, 892 { .compatible = "amd,imageon" }, 893 { .compatible = "qcom,kgsl-3d0" }, 894 { }, 895 }; 896 897 static int add_gpu_components(struct device *dev, 898 struct component_match **matchptr) 899 { 900 struct device_node *np; 901 902 np = of_find_matching_node(NULL, msm_gpu_match); 903 if (!np) 904 return 0; 905 906 if (of_device_is_available(np)) 907 drm_of_component_match_add(dev, matchptr, component_compare_of, np); 908 909 of_node_put(np); 910 911 return 0; 912 } 913 914 static int msm_drm_bind(struct device *dev) 915 { 916 return msm_drm_init(dev, &msm_driver); 917 } 918 919 static void msm_drm_unbind(struct device *dev) 920 { 921 msm_drm_uninit(dev); 922 } 923 924 const struct component_master_ops msm_drm_ops = { 925 .bind = msm_drm_bind, 926 .unbind = msm_drm_unbind, 927 }; 928 929 int msm_drv_probe(struct device *master_dev, 930 int (*kms_init)(struct drm_device *dev), 931 struct msm_kms *kms) 932 { 933 struct msm_drm_private *priv; 934 struct component_match *match = NULL; 935 int ret; 936 937 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL); 938 if (!priv) 939 return -ENOMEM; 940 941 priv->kms = kms; 942 priv->kms_init = kms_init; 943 dev_set_drvdata(master_dev, priv); 944 945 /* Add mdp components if we have KMS. */ 946 if (kms_init) { 947 ret = add_components_mdp(master_dev, &match); 948 if (ret) 949 return ret; 950 } 951 952 ret = add_gpu_components(master_dev, &match); 953 if (ret) 954 return ret; 955 956 /* on all devices that I am aware of, iommu's which can map 957 * any address the cpu can see are used: 958 */ 959 ret = dma_set_mask_and_coherent(master_dev, ~0); 960 if (ret) 961 return ret; 962 963 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match); 964 if (ret) 965 return ret; 966 967 return 0; 968 } 969 970 /* 971 * Platform driver: 972 * Used only for headlesss GPU instances 973 */ 974 975 static int msm_pdev_probe(struct platform_device *pdev) 976 { 977 return msm_drv_probe(&pdev->dev, NULL, NULL); 978 } 979 980 static void msm_pdev_remove(struct platform_device *pdev) 981 { 982 component_master_del(&pdev->dev, &msm_drm_ops); 983 } 984 985 static struct platform_driver msm_platform_driver = { 986 .probe = msm_pdev_probe, 987 .remove_new = msm_pdev_remove, 988 .driver = { 989 .name = "msm", 990 }, 991 }; 992 993 static int __init msm_drm_register(void) 994 { 995 if (!modeset) 996 return -EINVAL; 997 998 DBG("init"); 999 msm_mdp_register(); 1000 msm_dpu_register(); 1001 msm_dsi_register(); 1002 msm_hdmi_register(); 1003 msm_dp_register(); 1004 adreno_register(); 1005 msm_mdp4_register(); 1006 msm_mdss_register(); 1007 return platform_driver_register(&msm_platform_driver); 1008 } 1009 1010 static void __exit msm_drm_unregister(void) 1011 { 1012 DBG("fini"); 1013 platform_driver_unregister(&msm_platform_driver); 1014 msm_mdss_unregister(); 1015 msm_mdp4_unregister(); 1016 msm_dp_unregister(); 1017 msm_hdmi_unregister(); 1018 adreno_unregister(); 1019 msm_dsi_unregister(); 1020 msm_mdp_unregister(); 1021 msm_dpu_unregister(); 1022 } 1023 1024 module_init(msm_drm_register); 1025 module_exit(msm_drm_unregister); 1026 1027 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1028 MODULE_DESCRIPTION("MSM DRM Driver"); 1029 MODULE_LICENSE("GPL"); 1030