1*caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2c8afe684SRob Clark /*
3c8afe684SRob Clark * Copyright (C) 2013 Red Hat
4c8afe684SRob Clark * Author: Rob Clark <robdclark@gmail.com>
5c8afe684SRob Clark */
6c8afe684SRob Clark
7c8afe684SRob Clark #include "hdmi.h"
8c8afe684SRob Clark
9c8afe684SRob Clark struct hdmi_i2c_adapter {
10c8afe684SRob Clark struct i2c_adapter base;
11c8afe684SRob Clark struct hdmi *hdmi;
12c8afe684SRob Clark bool sw_done;
13c8afe684SRob Clark wait_queue_head_t ddc_event;
14c8afe684SRob Clark };
15c8afe684SRob Clark #define to_hdmi_i2c_adapter(x) container_of(x, struct hdmi_i2c_adapter, base)
16c8afe684SRob Clark
init_ddc(struct hdmi_i2c_adapter * hdmi_i2c)17c8afe684SRob Clark static void init_ddc(struct hdmi_i2c_adapter *hdmi_i2c)
18c8afe684SRob Clark {
19c8afe684SRob Clark struct hdmi *hdmi = hdmi_i2c->hdmi;
20c8afe684SRob Clark
21c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
22c8afe684SRob Clark HDMI_DDC_CTRL_SW_STATUS_RESET);
23c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
24c8afe684SRob Clark HDMI_DDC_CTRL_SOFT_RESET);
25c8afe684SRob Clark
26c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_SPEED,
27c8afe684SRob Clark HDMI_DDC_SPEED_THRESHOLD(2) |
28c8afe684SRob Clark HDMI_DDC_SPEED_PRESCALE(10));
29c8afe684SRob Clark
30c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_SETUP,
31c8afe684SRob Clark HDMI_DDC_SETUP_TIMEOUT(0xff));
32c8afe684SRob Clark
33c8afe684SRob Clark /* enable reference timer for 27us */
34c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_REF,
35c8afe684SRob Clark HDMI_DDC_REF_REFTIMER_ENABLE |
36c8afe684SRob Clark HDMI_DDC_REF_REFTIMER(27));
37c8afe684SRob Clark }
38c8afe684SRob Clark
ddc_clear_irq(struct hdmi_i2c_adapter * hdmi_i2c)39c8afe684SRob Clark static int ddc_clear_irq(struct hdmi_i2c_adapter *hdmi_i2c)
40c8afe684SRob Clark {
41c8afe684SRob Clark struct hdmi *hdmi = hdmi_i2c->hdmi;
42c8afe684SRob Clark struct drm_device *dev = hdmi->dev;
43c8afe684SRob Clark uint32_t retry = 0xffff;
44c8afe684SRob Clark uint32_t ddc_int_ctrl;
45c8afe684SRob Clark
46c8afe684SRob Clark do {
47c8afe684SRob Clark --retry;
48c8afe684SRob Clark
49c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
50c8afe684SRob Clark HDMI_DDC_INT_CTRL_SW_DONE_ACK |
51c8afe684SRob Clark HDMI_DDC_INT_CTRL_SW_DONE_MASK);
52c8afe684SRob Clark
53c8afe684SRob Clark ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
54c8afe684SRob Clark
55c8afe684SRob Clark } while ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT) && retry);
56c8afe684SRob Clark
57c8afe684SRob Clark if (!retry) {
586a41da17SMamta Shukla DRM_DEV_ERROR(dev->dev, "timeout waiting for DDC\n");
59c8afe684SRob Clark return -ETIMEDOUT;
60c8afe684SRob Clark }
61c8afe684SRob Clark
62c8afe684SRob Clark hdmi_i2c->sw_done = false;
63c8afe684SRob Clark
64c8afe684SRob Clark return 0;
65c8afe684SRob Clark }
66c8afe684SRob Clark
67c8afe684SRob Clark #define MAX_TRANSACTIONS 4
68c8afe684SRob Clark
sw_done(struct hdmi_i2c_adapter * hdmi_i2c)69c8afe684SRob Clark static bool sw_done(struct hdmi_i2c_adapter *hdmi_i2c)
70c8afe684SRob Clark {
71c8afe684SRob Clark struct hdmi *hdmi = hdmi_i2c->hdmi;
72c8afe684SRob Clark
73c8afe684SRob Clark if (!hdmi_i2c->sw_done) {
74c8afe684SRob Clark uint32_t ddc_int_ctrl;
75c8afe684SRob Clark
76c8afe684SRob Clark ddc_int_ctrl = hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL);
77c8afe684SRob Clark
78c8afe684SRob Clark if ((ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_MASK) &&
79c8afe684SRob Clark (ddc_int_ctrl & HDMI_DDC_INT_CTRL_SW_DONE_INT)) {
80c8afe684SRob Clark hdmi_i2c->sw_done = true;
81c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_INT_CTRL,
82c8afe684SRob Clark HDMI_DDC_INT_CTRL_SW_DONE_ACK);
83c8afe684SRob Clark }
84c8afe684SRob Clark }
85c8afe684SRob Clark
86c8afe684SRob Clark return hdmi_i2c->sw_done;
87c8afe684SRob Clark }
88c8afe684SRob Clark
msm_hdmi_i2c_xfer(struct i2c_adapter * i2c,struct i2c_msg * msgs,int num)89fcda50c8SArnd Bergmann static int msm_hdmi_i2c_xfer(struct i2c_adapter *i2c,
90c8afe684SRob Clark struct i2c_msg *msgs, int num)
91c8afe684SRob Clark {
92c8afe684SRob Clark struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
93c8afe684SRob Clark struct hdmi *hdmi = hdmi_i2c->hdmi;
94c8afe684SRob Clark struct drm_device *dev = hdmi->dev;
95c8afe684SRob Clark static const uint32_t nack[] = {
96c8afe684SRob Clark HDMI_DDC_SW_STATUS_NACK0, HDMI_DDC_SW_STATUS_NACK1,
97c8afe684SRob Clark HDMI_DDC_SW_STATUS_NACK2, HDMI_DDC_SW_STATUS_NACK3,
98c8afe684SRob Clark };
99c8afe684SRob Clark int indices[MAX_TRANSACTIONS];
100c8afe684SRob Clark int ret, i, j, index = 0;
101c8afe684SRob Clark uint32_t ddc_status, ddc_data, i2c_trans;
102c8afe684SRob Clark
103c8afe684SRob Clark num = min(num, MAX_TRANSACTIONS);
104c8afe684SRob Clark
105c8afe684SRob Clark WARN_ON(!(hdmi_read(hdmi, REG_HDMI_CTRL) & HDMI_CTRL_ENABLE));
106c8afe684SRob Clark
107c8afe684SRob Clark if (num == 0)
108c8afe684SRob Clark return num;
109c8afe684SRob Clark
110c8afe684SRob Clark init_ddc(hdmi_i2c);
111c8afe684SRob Clark
112c8afe684SRob Clark ret = ddc_clear_irq(hdmi_i2c);
113c8afe684SRob Clark if (ret)
114c8afe684SRob Clark return ret;
115c8afe684SRob Clark
116c8afe684SRob Clark for (i = 0; i < num; i++) {
117c8afe684SRob Clark struct i2c_msg *p = &msgs[i];
118c8afe684SRob Clark uint32_t raw_addr = p->addr << 1;
119c8afe684SRob Clark
120c8afe684SRob Clark if (p->flags & I2C_M_RD)
121c8afe684SRob Clark raw_addr |= 1;
122c8afe684SRob Clark
123c8afe684SRob Clark ddc_data = HDMI_DDC_DATA_DATA(raw_addr) |
124c8afe684SRob Clark HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
125c8afe684SRob Clark
126c8afe684SRob Clark if (i == 0) {
127c8afe684SRob Clark ddc_data |= HDMI_DDC_DATA_INDEX(0) |
128c8afe684SRob Clark HDMI_DDC_DATA_INDEX_WRITE;
129c8afe684SRob Clark }
130c8afe684SRob Clark
131c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
132c8afe684SRob Clark index++;
133c8afe684SRob Clark
134c8afe684SRob Clark indices[i] = index;
135c8afe684SRob Clark
136c8afe684SRob Clark if (p->flags & I2C_M_RD) {
137c8afe684SRob Clark index += p->len;
138c8afe684SRob Clark } else {
139c8afe684SRob Clark for (j = 0; j < p->len; j++) {
140c8afe684SRob Clark ddc_data = HDMI_DDC_DATA_DATA(p->buf[j]) |
141c8afe684SRob Clark HDMI_DDC_DATA_DATA_RW(DDC_WRITE);
142c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
143c8afe684SRob Clark index++;
144c8afe684SRob Clark }
145c8afe684SRob Clark }
146c8afe684SRob Clark
147c8afe684SRob Clark i2c_trans = HDMI_I2C_TRANSACTION_REG_CNT(p->len) |
148c8afe684SRob Clark HDMI_I2C_TRANSACTION_REG_RW(
149c8afe684SRob Clark (p->flags & I2C_M_RD) ? DDC_READ : DDC_WRITE) |
150c8afe684SRob Clark HDMI_I2C_TRANSACTION_REG_START;
151c8afe684SRob Clark
152c8afe684SRob Clark if (i == (num - 1))
153c8afe684SRob Clark i2c_trans |= HDMI_I2C_TRANSACTION_REG_STOP;
154c8afe684SRob Clark
155c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_I2C_TRANSACTION(i), i2c_trans);
156c8afe684SRob Clark }
157c8afe684SRob Clark
158c8afe684SRob Clark /* trigger the transfer: */
159c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_CTRL,
160c8afe684SRob Clark HDMI_DDC_CTRL_TRANSACTION_CNT(num - 1) |
161c8afe684SRob Clark HDMI_DDC_CTRL_GO);
162c8afe684SRob Clark
163c8afe684SRob Clark ret = wait_event_timeout(hdmi_i2c->ddc_event, sw_done(hdmi_i2c), HZ/4);
164c8afe684SRob Clark if (ret <= 0) {
165c8afe684SRob Clark if (ret == 0)
166c8afe684SRob Clark ret = -ETIMEDOUT;
167c8afe684SRob Clark dev_warn(dev->dev, "DDC timeout: %d\n", ret);
168c8afe684SRob Clark DBG("sw_status=%08x, hw_status=%08x, int_ctrl=%08x",
169c8afe684SRob Clark hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS),
170c8afe684SRob Clark hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS),
171c8afe684SRob Clark hdmi_read(hdmi, REG_HDMI_DDC_INT_CTRL));
172c8afe684SRob Clark return ret;
173c8afe684SRob Clark }
174c8afe684SRob Clark
175c8afe684SRob Clark ddc_status = hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS);
176c8afe684SRob Clark
177c8afe684SRob Clark /* read back results of any read transactions: */
178c8afe684SRob Clark for (i = 0; i < num; i++) {
179c8afe684SRob Clark struct i2c_msg *p = &msgs[i];
180c8afe684SRob Clark
181c8afe684SRob Clark if (!(p->flags & I2C_M_RD))
182c8afe684SRob Clark continue;
183c8afe684SRob Clark
184c8afe684SRob Clark /* check for NACK: */
185c8afe684SRob Clark if (ddc_status & nack[i]) {
186c8afe684SRob Clark DBG("ddc_status=%08x", ddc_status);
187c8afe684SRob Clark break;
188c8afe684SRob Clark }
189c8afe684SRob Clark
190c8afe684SRob Clark ddc_data = HDMI_DDC_DATA_DATA_RW(DDC_READ) |
191c8afe684SRob Clark HDMI_DDC_DATA_INDEX(indices[i]) |
192c8afe684SRob Clark HDMI_DDC_DATA_INDEX_WRITE;
193c8afe684SRob Clark
194c8afe684SRob Clark hdmi_write(hdmi, REG_HDMI_DDC_DATA, ddc_data);
195c8afe684SRob Clark
196c8afe684SRob Clark /* discard first byte: */
197c8afe684SRob Clark hdmi_read(hdmi, REG_HDMI_DDC_DATA);
198c8afe684SRob Clark
199c8afe684SRob Clark for (j = 0; j < p->len; j++) {
200c8afe684SRob Clark ddc_data = hdmi_read(hdmi, REG_HDMI_DDC_DATA);
201c8afe684SRob Clark p->buf[j] = FIELD(ddc_data, HDMI_DDC_DATA_DATA);
202c8afe684SRob Clark }
203c8afe684SRob Clark }
204c8afe684SRob Clark
205c8afe684SRob Clark return i;
206c8afe684SRob Clark }
207c8afe684SRob Clark
msm_hdmi_i2c_func(struct i2c_adapter * adapter)208fcda50c8SArnd Bergmann static u32 msm_hdmi_i2c_func(struct i2c_adapter *adapter)
209c8afe684SRob Clark {
210c8afe684SRob Clark return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
211c8afe684SRob Clark }
212c8afe684SRob Clark
213fcda50c8SArnd Bergmann static const struct i2c_algorithm msm_hdmi_i2c_algorithm = {
214fcda50c8SArnd Bergmann .master_xfer = msm_hdmi_i2c_xfer,
215fcda50c8SArnd Bergmann .functionality = msm_hdmi_i2c_func,
216c8afe684SRob Clark };
217c8afe684SRob Clark
msm_hdmi_i2c_irq(struct i2c_adapter * i2c)218fcda50c8SArnd Bergmann void msm_hdmi_i2c_irq(struct i2c_adapter *i2c)
219c8afe684SRob Clark {
220c8afe684SRob Clark struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
221c8afe684SRob Clark
222c8afe684SRob Clark if (sw_done(hdmi_i2c))
223c8afe684SRob Clark wake_up_all(&hdmi_i2c->ddc_event);
224c8afe684SRob Clark }
225c8afe684SRob Clark
msm_hdmi_i2c_destroy(struct i2c_adapter * i2c)226fcda50c8SArnd Bergmann void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c)
227c8afe684SRob Clark {
228c8afe684SRob Clark struct hdmi_i2c_adapter *hdmi_i2c = to_hdmi_i2c_adapter(i2c);
229c8afe684SRob Clark i2c_del_adapter(i2c);
230c8afe684SRob Clark kfree(hdmi_i2c);
231c8afe684SRob Clark }
232c8afe684SRob Clark
msm_hdmi_i2c_init(struct hdmi * hdmi)233fcda50c8SArnd Bergmann struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi)
234c8afe684SRob Clark {
235c8afe684SRob Clark struct hdmi_i2c_adapter *hdmi_i2c;
236c8afe684SRob Clark struct i2c_adapter *i2c = NULL;
237c8afe684SRob Clark int ret;
238c8afe684SRob Clark
239c8afe684SRob Clark hdmi_i2c = kzalloc(sizeof(*hdmi_i2c), GFP_KERNEL);
240c8afe684SRob Clark if (!hdmi_i2c) {
241c8afe684SRob Clark ret = -ENOMEM;
242c8afe684SRob Clark goto fail;
243c8afe684SRob Clark }
244c8afe684SRob Clark
245c8afe684SRob Clark i2c = &hdmi_i2c->base;
246c8afe684SRob Clark
247c8afe684SRob Clark hdmi_i2c->hdmi = hdmi;
248c8afe684SRob Clark init_waitqueue_head(&hdmi_i2c->ddc_event);
249c8afe684SRob Clark
250c8afe684SRob Clark
251c8afe684SRob Clark i2c->owner = THIS_MODULE;
252c8afe684SRob Clark snprintf(i2c->name, sizeof(i2c->name), "msm hdmi i2c");
253c8afe684SRob Clark i2c->dev.parent = &hdmi->pdev->dev;
254fcda50c8SArnd Bergmann i2c->algo = &msm_hdmi_i2c_algorithm;
255c8afe684SRob Clark
256c8afe684SRob Clark ret = i2c_add_adapter(i2c);
2570e54543cSWolfram Sang if (ret)
258c8afe684SRob Clark goto fail;
259c8afe684SRob Clark
260c8afe684SRob Clark return i2c;
261c8afe684SRob Clark
262c8afe684SRob Clark fail:
263c8afe684SRob Clark if (i2c)
264fcda50c8SArnd Bergmann msm_hdmi_i2c_destroy(i2c);
265c8afe684SRob Clark return ERR_PTR(ret);
266c8afe684SRob Clark }
267