1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. 3 */ 4 5 #include "hdmi.h" 6 #include <linux/firmware/qcom/qcom_scm.h> 7 8 #define HDCP_REG_ENABLE 0x01 9 #define HDCP_REG_DISABLE 0x00 10 #define HDCP_PORT_ADDR 0x74 11 12 #define HDCP_INT_STATUS_MASK ( \ 13 HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT | \ 14 HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT | \ 15 HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT | \ 16 HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT) 17 18 #define AUTH_WORK_RETRIES_TIME 100 19 #define AUTH_RETRIES_TIME 30 20 21 /* QFPROM Registers for HDMI/HDCP */ 22 #define QFPROM_RAW_FEAT_CONFIG_ROW0_LSB 0x000000F8 23 #define QFPROM_RAW_FEAT_CONFIG_ROW0_MSB 0x000000FC 24 #define HDCP_KSV_LSB 0x000060D8 25 #define HDCP_KSV_MSB 0x000060DC 26 27 enum DS_TYPE { /* type of downstream device */ 28 DS_UNKNOWN, 29 DS_RECEIVER, 30 DS_REPEATER, 31 }; 32 33 enum hdmi_hdcp_state { 34 HDCP_STATE_NO_AKSV, 35 HDCP_STATE_INACTIVE, 36 HDCP_STATE_AUTHENTICATING, 37 HDCP_STATE_AUTHENTICATED, 38 HDCP_STATE_AUTH_FAILED 39 }; 40 41 struct hdmi_hdcp_reg_data { 42 u32 reg_id; 43 u32 off; 44 char *name; 45 u32 reg_val; 46 }; 47 48 struct hdmi_hdcp_ctrl { 49 struct hdmi *hdmi; 50 u32 auth_retries; 51 bool tz_hdcp; 52 enum hdmi_hdcp_state hdcp_state; 53 struct work_struct hdcp_auth_work; 54 struct work_struct hdcp_reauth_work; 55 56 #define AUTH_ABORT_EV 1 57 #define AUTH_RESULT_RDY_EV 2 58 unsigned long auth_event; 59 wait_queue_head_t auth_event_queue; 60 61 u32 ksv_fifo_w_index; 62 /* 63 * store aksv from qfprom 64 */ 65 u32 aksv_lsb; 66 u32 aksv_msb; 67 bool aksv_valid; 68 u32 ds_type; 69 u32 bksv_lsb; 70 u32 bksv_msb; 71 u8 dev_count; 72 u8 depth; 73 u8 ksv_list[5 * 127]; 74 bool max_cascade_exceeded; 75 bool max_dev_exceeded; 76 }; 77 78 static int msm_hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset, 79 u8 *data, u16 data_len) 80 { 81 int rc; 82 int retry = 5; 83 struct i2c_msg msgs[] = { 84 { 85 .addr = addr >> 1, 86 .flags = 0, 87 .len = 1, 88 .buf = &offset, 89 }, { 90 .addr = addr >> 1, 91 .flags = I2C_M_RD, 92 .len = data_len, 93 .buf = data, 94 } 95 }; 96 97 DBG("Start DDC read"); 98 retry: 99 rc = i2c_transfer(hdmi->i2c, msgs, 2); 100 101 retry--; 102 if (rc == 2) 103 rc = 0; 104 else if (retry > 0) 105 goto retry; 106 else 107 rc = -EIO; 108 109 DBG("End DDC read %d", rc); 110 111 return rc; 112 } 113 114 #define HDCP_DDC_WRITE_MAX_BYTE_NUM 32 115 116 static int msm_hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset, 117 u8 *data, u16 data_len) 118 { 119 int rc; 120 int retry = 10; 121 u8 buf[HDCP_DDC_WRITE_MAX_BYTE_NUM]; 122 struct i2c_msg msgs[] = { 123 { 124 .addr = addr >> 1, 125 .flags = 0, 126 .len = 1, 127 } 128 }; 129 130 DBG("Start DDC write"); 131 if (data_len > (HDCP_DDC_WRITE_MAX_BYTE_NUM - 1)) { 132 pr_err("%s: write size too big\n", __func__); 133 return -ERANGE; 134 } 135 136 buf[0] = offset; 137 memcpy(&buf[1], data, data_len); 138 msgs[0].buf = buf; 139 msgs[0].len = data_len + 1; 140 retry: 141 rc = i2c_transfer(hdmi->i2c, msgs, 1); 142 143 retry--; 144 if (rc == 1) 145 rc = 0; 146 else if (retry > 0) 147 goto retry; 148 else 149 rc = -EIO; 150 151 DBG("End DDC write %d", rc); 152 153 return rc; 154 } 155 156 static int msm_hdmi_hdcp_scm_wr(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 *preg, 157 u32 *pdata, u32 count) 158 { 159 struct hdmi *hdmi = hdcp_ctrl->hdmi; 160 struct qcom_scm_hdcp_req scm_buf[QCOM_SCM_HDCP_MAX_REQ_CNT]; 161 u32 resp, phy_addr, idx = 0; 162 int i, ret = 0; 163 164 WARN_ON(!pdata || !preg || (count == 0)); 165 166 if (hdcp_ctrl->tz_hdcp) { 167 phy_addr = (u32)hdmi->mmio_phy_addr; 168 169 while (count) { 170 memset(scm_buf, 0, sizeof(scm_buf)); 171 for (i = 0; i < count && i < QCOM_SCM_HDCP_MAX_REQ_CNT; 172 i++) { 173 scm_buf[i].addr = phy_addr + preg[idx]; 174 scm_buf[i].val = pdata[idx]; 175 idx++; 176 } 177 ret = qcom_scm_hdcp_req(scm_buf, i, &resp); 178 179 if (ret || resp) { 180 pr_err("%s: error: scm_call ret=%d resp=%u\n", 181 __func__, ret, resp); 182 ret = -EINVAL; 183 break; 184 } 185 186 count -= i; 187 } 188 } else { 189 for (i = 0; i < count; i++) 190 hdmi_write(hdmi, preg[i], pdata[i]); 191 } 192 193 return ret; 194 } 195 196 void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) 197 { 198 struct hdmi *hdmi = hdcp_ctrl->hdmi; 199 u32 reg_val, hdcp_int_status; 200 unsigned long flags; 201 202 spin_lock_irqsave(&hdmi->reg_lock, flags); 203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); 204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; 205 if (!hdcp_int_status) { 206 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 207 return; 208 } 209 /* Clear Interrupts */ 210 reg_val |= hdcp_int_status << 1; 211 /* Clear AUTH_FAIL_INFO as well */ 212 if (hdcp_int_status & HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT) 213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; 214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); 215 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 216 217 DBG("hdcp irq %x", hdcp_int_status); 218 219 if (hdcp_int_status & HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT) { 220 pr_info("%s:AUTH_SUCCESS_INT received\n", __func__); 221 if (HDCP_STATE_AUTHENTICATING == hdcp_ctrl->hdcp_state) { 222 set_bit(AUTH_RESULT_RDY_EV, &hdcp_ctrl->auth_event); 223 wake_up_all(&hdcp_ctrl->auth_event_queue); 224 } 225 } 226 227 if (hdcp_int_status & HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT) { 228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 229 pr_info("%s: AUTH_FAIL_INT rcvd, LINK0_STATUS=0x%08x\n", 230 __func__, reg_val); 231 if (HDCP_STATE_AUTHENTICATED == hdcp_ctrl->hdcp_state) 232 queue_work(hdmi->workq, &hdcp_ctrl->hdcp_reauth_work); 233 else if (HDCP_STATE_AUTHENTICATING == 234 hdcp_ctrl->hdcp_state) { 235 set_bit(AUTH_RESULT_RDY_EV, &hdcp_ctrl->auth_event); 236 wake_up_all(&hdcp_ctrl->auth_event_queue); 237 } 238 } 239 } 240 241 static int msm_hdmi_hdcp_msleep(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 ms, u32 ev) 242 { 243 int rc; 244 245 rc = wait_event_timeout(hdcp_ctrl->auth_event_queue, 246 !!test_bit(ev, &hdcp_ctrl->auth_event), 247 msecs_to_jiffies(ms)); 248 if (rc) { 249 pr_info("%s: msleep is canceled by event %d\n", 250 __func__, ev); 251 clear_bit(ev, &hdcp_ctrl->auth_event); 252 return -ECANCELED; 253 } 254 255 return 0; 256 } 257 258 static int msm_hdmi_hdcp_read_validate_aksv(struct hdmi_hdcp_ctrl *hdcp_ctrl) 259 { 260 struct hdmi *hdmi = hdcp_ctrl->hdmi; 261 262 /* Fetch aksv from QFPROM, this info should be public. */ 263 hdcp_ctrl->aksv_lsb = hdmi_qfprom_read(hdmi, HDCP_KSV_LSB); 264 hdcp_ctrl->aksv_msb = hdmi_qfprom_read(hdmi, HDCP_KSV_MSB); 265 266 /* check there are 20 ones in AKSV */ 267 if ((hweight32(hdcp_ctrl->aksv_lsb) + hweight32(hdcp_ctrl->aksv_msb)) 268 != 20) { 269 pr_err("%s: AKSV QFPROM doesn't have 20 1's, 20 0's\n", 270 __func__); 271 pr_err("%s: QFPROM AKSV chk failed (AKSV=%02x%08x)\n", 272 __func__, hdcp_ctrl->aksv_msb, 273 hdcp_ctrl->aksv_lsb); 274 return -EINVAL; 275 } 276 DBG("AKSV=%02x%08x", hdcp_ctrl->aksv_msb, hdcp_ctrl->aksv_lsb); 277 278 return 0; 279 } 280 281 static int msm_reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl) 282 { 283 struct hdmi *hdmi = hdcp_ctrl->hdmi; 284 u32 reg_val, failure, nack0; 285 int rc = 0; 286 287 /* Check for any DDC transfer failures */ 288 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); 289 failure = reg_val & HDMI_HDCP_DDC_STATUS_FAILED; 290 nack0 = reg_val & HDMI_HDCP_DDC_STATUS_NACK0; 291 DBG("HDCP_DDC_STATUS=0x%x, FAIL=%d, NACK0=%d", 292 reg_val, failure, nack0); 293 294 if (failure) { 295 /* 296 * Indicates that the last HDCP HW DDC transfer failed. 297 * This occurs when a transfer is attempted with HDCP DDC 298 * disabled (HDCP_DDC_DISABLE=1) or the number of retries 299 * matches HDCP_DDC_RETRY_CNT. 300 * Failure occurred, let's clear it. 301 */ 302 DBG("DDC failure detected"); 303 304 /* First, Disable DDC */ 305 hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_0, 306 HDMI_HDCP_DDC_CTRL_0_DISABLE); 307 308 /* ACK the Failure to Clear it */ 309 hdmi_update_bits(hdmi, REG_HDMI_HDCP_DDC_CTRL_1, 310 HDMI_HDCP_DDC_CTRL_1_FAILED_ACK, 311 HDMI_HDCP_DDC_CTRL_1_FAILED_ACK); 312 313 /* Check if the FAILURE got Cleared */ 314 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); 315 if (reg_val & HDMI_HDCP_DDC_STATUS_FAILED) 316 pr_info("%s: Unable to clear HDCP DDC Failure\n", 317 __func__); 318 319 /* Re-Enable HDCP DDC */ 320 hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_0, 0); 321 } 322 323 if (nack0) { 324 DBG("Before: HDMI_DDC_SW_STATUS=0x%08x", 325 hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS)); 326 /* Reset HDMI DDC software status */ 327 hdmi_update_bits(hdmi, REG_HDMI_DDC_CTRL, HDMI_DDC_CTRL_SW_STATUS_RESET, 328 HDMI_DDC_CTRL_SW_STATUS_RESET); 329 330 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 331 332 hdmi_clear_bits(hdmi, REG_HDMI_DDC_CTRL, HDMI_DDC_CTRL_SW_STATUS_RESET); 333 334 /* Reset HDMI DDC Controller */ 335 hdmi_update_bits(hdmi, REG_HDMI_DDC_CTRL, HDMI_DDC_CTRL_SOFT_RESET, 336 HDMI_DDC_CTRL_SOFT_RESET); 337 338 /* If previous msleep is aborted, skip this msleep */ 339 if (!rc) 340 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 341 342 hdmi_clear_bits(hdmi, REG_HDMI_DDC_CTRL, HDMI_DDC_CTRL_SOFT_RESET); 343 DBG("After: HDMI_DDC_SW_STATUS=0x%08x", 344 hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS)); 345 } 346 347 return rc; 348 } 349 350 static int msm_hdmi_hdcp_hw_ddc_clean(struct hdmi_hdcp_ctrl *hdcp_ctrl) 351 { 352 int rc; 353 u32 hdcp_ddc_status, ddc_hw_status; 354 u32 xfer_done, xfer_req, hw_done; 355 bool hw_not_ready; 356 u32 timeout_count; 357 struct hdmi *hdmi = hdcp_ctrl->hdmi; 358 359 if (hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS) == 0) 360 return 0; 361 362 /* Wait to be clean on DDC HW engine */ 363 timeout_count = 100; 364 do { 365 hdcp_ddc_status = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); 366 ddc_hw_status = hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS); 367 368 xfer_done = hdcp_ddc_status & HDMI_HDCP_DDC_STATUS_XFER_DONE; 369 xfer_req = hdcp_ddc_status & HDMI_HDCP_DDC_STATUS_XFER_REQ; 370 hw_done = ddc_hw_status & HDMI_DDC_HW_STATUS_DONE; 371 hw_not_ready = !xfer_done || xfer_req || !hw_done; 372 373 if (hw_not_ready) 374 break; 375 376 timeout_count--; 377 if (!timeout_count) { 378 pr_warn("%s: hw_ddc_clean failed\n", __func__); 379 return -ETIMEDOUT; 380 } 381 382 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 383 if (rc) 384 return rc; 385 } while (1); 386 387 return 0; 388 } 389 390 static void msm_hdmi_hdcp_reauth_work(struct work_struct *work) 391 { 392 struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(work, 393 struct hdmi_hdcp_ctrl, hdcp_reauth_work); 394 struct hdmi *hdmi = hdcp_ctrl->hdmi; 395 unsigned long flags; 396 397 DBG("HDCP REAUTH WORK"); 398 /* 399 * Disable HPD circuitry. 400 * This is needed to reset the HDCP cipher engine so that when we 401 * attempt a re-authentication, HW would clear the AN0_READY and 402 * AN1_READY bits in HDMI_HDCP_LINK0_STATUS register 403 */ 404 spin_lock_irqsave(&hdmi->reg_lock, flags); 405 hdmi_clear_bits(hdmi, REG_HDMI_HPD_CTRL, HDMI_HPD_CTRL_ENABLE); 406 407 /* Disable HDCP interrupts */ 408 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, 0); 409 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 410 411 hdmi_write(hdmi, REG_HDMI_HDCP_RESET, 412 HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE); 413 414 /* Wait to be clean on DDC HW engine */ 415 if (msm_hdmi_hdcp_hw_ddc_clean(hdcp_ctrl)) { 416 pr_info("%s: reauth work aborted\n", __func__); 417 return; 418 } 419 420 /* Disable encryption and disable the HDCP block */ 421 hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, 0); 422 423 /* Enable HPD circuitry */ 424 spin_lock_irqsave(&hdmi->reg_lock, flags); 425 hdmi_update_bits(hdmi, REG_HDMI_HPD_CTRL, HDMI_HPD_CTRL_ENABLE, 426 HDMI_HPD_CTRL_ENABLE); 427 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 428 429 /* 430 * Only retry defined times then abort current authenticating process 431 */ 432 if (++hdcp_ctrl->auth_retries == AUTH_RETRIES_TIME) { 433 hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE; 434 hdcp_ctrl->auth_retries = 0; 435 pr_info("%s: abort reauthentication!\n", __func__); 436 437 return; 438 } 439 440 DBG("Queue AUTH WORK"); 441 hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATING; 442 queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work); 443 } 444 445 static int msm_hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl) 446 { 447 struct hdmi *hdmi = hdcp_ctrl->hdmi; 448 u32 link0_status; 449 unsigned long flags; 450 int rc; 451 452 if (!hdcp_ctrl->aksv_valid) { 453 rc = msm_hdmi_hdcp_read_validate_aksv(hdcp_ctrl); 454 if (rc) { 455 pr_err("%s: ASKV validation failed\n", __func__); 456 hdcp_ctrl->hdcp_state = HDCP_STATE_NO_AKSV; 457 return -ENOTSUPP; 458 } 459 hdcp_ctrl->aksv_valid = true; 460 } 461 462 spin_lock_irqsave(&hdmi->reg_lock, flags); 463 /* disable HDMI Encrypt */ 464 hdmi_clear_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED); 465 466 /* Enabling Software DDC */ 467 hdmi_clear_bits(hdmi, REG_HDMI_DDC_ARBITRATION, 468 HDMI_DDC_ARBITRATION_HW_ARBITRATION); 469 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 470 471 /* 472 * Write AKSV read from QFPROM to the HDCP registers. 473 * This step is needed for HDCP authentication and must be 474 * written before enabling HDCP. 475 */ 476 hdmi_write(hdmi, REG_HDMI_HDCP_SW_LOWER_AKSV, hdcp_ctrl->aksv_lsb); 477 hdmi_write(hdmi, REG_HDMI_HDCP_SW_UPPER_AKSV, hdcp_ctrl->aksv_msb); 478 479 /* 480 * HDCP setup prior to enabling HDCP_CTRL. 481 * Setup seed values for random number An. 482 */ 483 hdmi_write(hdmi, REG_HDMI_HDCP_ENTROPY_CTRL0, 0xB1FFB0FF); 484 hdmi_write(hdmi, REG_HDMI_HDCP_ENTROPY_CTRL1, 0xF00DFACE); 485 486 /* Disable the RngCipher state */ 487 hdmi_clear_bits(hdmi, REG_HDMI_HDCP_DEBUG_CTRL, 488 HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER); 489 DBG("HDCP_DEBUG_CTRL=0x%08x", 490 hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL)); 491 492 /* 493 * Ensure that all register writes are completed before 494 * enabling HDCP cipher 495 */ 496 wmb(); 497 498 /* 499 * Enable HDCP 500 * This needs to be done as early as possible in order for the 501 * hardware to make An available to read 502 */ 503 hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, HDMI_HDCP_CTRL_ENABLE); 504 505 /* 506 * If we had stale values for the An ready bit, it should most 507 * likely be cleared now after enabling HDCP cipher 508 */ 509 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 510 DBG("After enabling HDCP Link0_Status=0x%08x", link0_status); 511 if (!(link0_status & 512 (HDMI_HDCP_LINK0_STATUS_AN_0_READY | 513 HDMI_HDCP_LINK0_STATUS_AN_1_READY))) 514 DBG("An not ready after enabling HDCP"); 515 516 /* Clear any DDC failures from previous tries before enable HDCP*/ 517 rc = msm_reset_hdcp_ddc_failures(hdcp_ctrl); 518 519 return rc; 520 } 521 522 static void msm_hdmi_hdcp_auth_fail(struct hdmi_hdcp_ctrl *hdcp_ctrl) 523 { 524 struct hdmi *hdmi = hdcp_ctrl->hdmi; 525 unsigned long flags; 526 527 DBG("hdcp auth failed, queue reauth work"); 528 /* clear HDMI Encrypt */ 529 spin_lock_irqsave(&hdmi->reg_lock, flags); 530 hdmi_clear_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED); 531 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 532 533 hdcp_ctrl->hdcp_state = HDCP_STATE_AUTH_FAILED; 534 queue_work(hdmi->workq, &hdcp_ctrl->hdcp_reauth_work); 535 } 536 537 static void msm_hdmi_hdcp_auth_done(struct hdmi_hdcp_ctrl *hdcp_ctrl) 538 { 539 struct hdmi *hdmi = hdcp_ctrl->hdmi; 540 unsigned long flags; 541 542 /* 543 * Disable software DDC before going into part3 to make sure 544 * there is no Arbitration between software and hardware for DDC 545 */ 546 spin_lock_irqsave(&hdmi->reg_lock, flags); 547 hdmi_update_bits(hdmi, REG_HDMI_DDC_ARBITRATION, 548 HDMI_DDC_ARBITRATION_HW_ARBITRATION, 549 HDMI_DDC_ARBITRATION_HW_ARBITRATION); 550 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 551 552 /* enable HDMI Encrypt */ 553 spin_lock_irqsave(&hdmi->reg_lock, flags); 554 hdmi_update_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED, 555 HDMI_CTRL_ENCRYPTED); 556 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 557 558 hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATED; 559 hdcp_ctrl->auth_retries = 0; 560 } 561 562 /* 563 * hdcp authenticating part 1 564 * Wait Key/An ready 565 * Read BCAPS from sink 566 * Write BCAPS and AKSV into HDCP engine 567 * Write An and AKSV to sink 568 * Read BKSV from sink and write into HDCP engine 569 */ 570 static int msm_hdmi_hdcp_wait_key_an_ready(struct hdmi_hdcp_ctrl *hdcp_ctrl) 571 { 572 int rc; 573 struct hdmi *hdmi = hdcp_ctrl->hdmi; 574 u32 link0_status, keys_state; 575 u32 timeout_count; 576 bool an_ready; 577 578 /* Wait for HDCP keys to be checked and validated */ 579 timeout_count = 100; 580 do { 581 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 582 keys_state = (link0_status >> 28) & 0x7; 583 if (keys_state == HDCP_KEYS_STATE_VALID) 584 break; 585 586 DBG("Keys not ready(%d). s=%d, l0=%0x08x", 587 timeout_count, keys_state, link0_status); 588 589 timeout_count--; 590 if (!timeout_count) { 591 pr_err("%s: Wait key state timedout", __func__); 592 return -ETIMEDOUT; 593 } 594 595 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 596 if (rc) 597 return rc; 598 } while (1); 599 600 timeout_count = 100; 601 do { 602 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 603 an_ready = (link0_status & HDMI_HDCP_LINK0_STATUS_AN_0_READY) 604 && (link0_status & HDMI_HDCP_LINK0_STATUS_AN_1_READY); 605 if (an_ready) 606 break; 607 608 DBG("An not ready(%d). l0_status=0x%08x", 609 timeout_count, link0_status); 610 611 timeout_count--; 612 if (!timeout_count) { 613 pr_err("%s: Wait An timedout", __func__); 614 return -ETIMEDOUT; 615 } 616 617 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 618 if (rc) 619 return rc; 620 } while (1); 621 622 return 0; 623 } 624 625 static int msm_hdmi_hdcp_send_aksv_an(struct hdmi_hdcp_ctrl *hdcp_ctrl) 626 { 627 int rc = 0; 628 struct hdmi *hdmi = hdcp_ctrl->hdmi; 629 u32 link0_aksv_0, link0_aksv_1; 630 u32 link0_an[2]; 631 u8 aksv[5]; 632 633 /* Read An0 and An1 */ 634 link0_an[0] = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA5); 635 link0_an[1] = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA6); 636 637 /* Read AKSV */ 638 link0_aksv_0 = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA3); 639 link0_aksv_1 = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA4); 640 641 DBG("Link ASKV=%08x%08x", link0_aksv_0, link0_aksv_1); 642 /* Copy An and AKSV to byte arrays for transmission */ 643 aksv[0] = link0_aksv_0 & 0xFF; 644 aksv[1] = (link0_aksv_0 >> 8) & 0xFF; 645 aksv[2] = (link0_aksv_0 >> 16) & 0xFF; 646 aksv[3] = (link0_aksv_0 >> 24) & 0xFF; 647 aksv[4] = link0_aksv_1 & 0xFF; 648 649 /* Write An to offset 0x18 */ 650 rc = msm_hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x18, (u8 *)link0_an, 651 (u16)sizeof(link0_an)); 652 if (rc) { 653 pr_err("%s:An write failed\n", __func__); 654 return rc; 655 } 656 DBG("Link0-An=%08x%08x", link0_an[0], link0_an[1]); 657 658 /* Write AKSV to offset 0x10 */ 659 rc = msm_hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x10, aksv, 5); 660 if (rc) { 661 pr_err("%s:AKSV write failed\n", __func__); 662 return rc; 663 } 664 DBG("Link0-AKSV=%02x%08x", link0_aksv_1 & 0xFF, link0_aksv_0); 665 666 return 0; 667 } 668 669 static int msm_hdmi_hdcp_recv_bksv(struct hdmi_hdcp_ctrl *hdcp_ctrl) 670 { 671 int rc = 0; 672 struct hdmi *hdmi = hdcp_ctrl->hdmi; 673 u8 bksv[5]; 674 u32 reg[2], data[2]; 675 676 /* Read BKSV at offset 0x00 */ 677 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x00, bksv, 5); 678 if (rc) { 679 pr_err("%s:BKSV read failed\n", __func__); 680 return rc; 681 } 682 683 hdcp_ctrl->bksv_lsb = bksv[0] | (bksv[1] << 8) | 684 (bksv[2] << 16) | (bksv[3] << 24); 685 hdcp_ctrl->bksv_msb = bksv[4]; 686 DBG(":BKSV=%02x%08x", hdcp_ctrl->bksv_msb, hdcp_ctrl->bksv_lsb); 687 688 /* check there are 20 ones in BKSV */ 689 if ((hweight32(hdcp_ctrl->bksv_lsb) + hweight32(hdcp_ctrl->bksv_msb)) 690 != 20) { 691 pr_err(": BKSV doesn't have 20 1's and 20 0's\n"); 692 pr_err(": BKSV chk fail. BKSV=%02x%02x%02x%02x%02x\n", 693 bksv[4], bksv[3], bksv[2], bksv[1], bksv[0]); 694 return -EINVAL; 695 } 696 697 /* Write BKSV read from sink to HDCP registers */ 698 reg[0] = REG_HDMI_HDCP_RCVPORT_DATA0; 699 data[0] = hdcp_ctrl->bksv_lsb; 700 reg[1] = REG_HDMI_HDCP_RCVPORT_DATA1; 701 data[1] = hdcp_ctrl->bksv_msb; 702 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2); 703 704 return rc; 705 } 706 707 static int msm_hdmi_hdcp_recv_bcaps(struct hdmi_hdcp_ctrl *hdcp_ctrl) 708 { 709 int rc = 0; 710 struct hdmi *hdmi = hdcp_ctrl->hdmi; 711 u32 reg, data; 712 u8 bcaps; 713 714 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1); 715 if (rc) { 716 pr_err("%s:BCAPS read failed\n", __func__); 717 return rc; 718 } 719 DBG("BCAPS=%02x", bcaps); 720 721 /* receiver (0), repeater (1) */ 722 hdcp_ctrl->ds_type = (bcaps & BIT(6)) ? DS_REPEATER : DS_RECEIVER; 723 724 /* Write BCAPS to the hardware */ 725 reg = REG_HDMI_HDCP_RCVPORT_DATA12; 726 data = (u32)bcaps; 727 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, ®, &data, 1); 728 729 return rc; 730 } 731 732 static int msm_hdmi_hdcp_auth_part1_key_exchange(struct hdmi_hdcp_ctrl *hdcp_ctrl) 733 { 734 struct hdmi *hdmi = hdcp_ctrl->hdmi; 735 unsigned long flags; 736 int rc; 737 738 /* Wait for AKSV key and An ready */ 739 rc = msm_hdmi_hdcp_wait_key_an_ready(hdcp_ctrl); 740 if (rc) { 741 pr_err("%s: wait key and an ready failed\n", __func__); 742 return rc; 743 } 744 745 /* Read BCAPS and send to HDCP engine */ 746 rc = msm_hdmi_hdcp_recv_bcaps(hdcp_ctrl); 747 if (rc) { 748 pr_err("%s: read bcaps error, abort\n", __func__); 749 return rc; 750 } 751 752 /* 753 * 1.1_Features turned off by default. 754 * No need to write AInfo since 1.1_Features is disabled. 755 */ 756 hdmi_write(hdmi, REG_HDMI_HDCP_RCVPORT_DATA4, 0); 757 758 /* Send AKSV and An to sink */ 759 rc = msm_hdmi_hdcp_send_aksv_an(hdcp_ctrl); 760 if (rc) { 761 pr_err("%s:An/Aksv write failed\n", __func__); 762 return rc; 763 } 764 765 /* Read BKSV and send to HDCP engine*/ 766 rc = msm_hdmi_hdcp_recv_bksv(hdcp_ctrl); 767 if (rc) { 768 pr_err("%s:BKSV Process failed\n", __func__); 769 return rc; 770 } 771 772 /* Enable HDCP interrupts and ack/clear any stale interrupts */ 773 spin_lock_irqsave(&hdmi->reg_lock, flags); 774 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, 775 HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK | 776 HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK | 777 HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK | 778 HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK | 779 HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK); 780 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 781 782 return 0; 783 } 784 785 /* read R0' from sink and pass it to HDCP engine */ 786 static int msm_hdmi_hdcp_auth_part1_recv_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl) 787 { 788 struct hdmi *hdmi = hdcp_ctrl->hdmi; 789 int rc = 0; 790 u8 buf[2]; 791 792 /* 793 * HDCP Compliance Test case 1A-01: 794 * Wait here at least 100ms before reading R0' 795 */ 796 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 125, AUTH_ABORT_EV); 797 if (rc) 798 return rc; 799 800 /* Read R0' at offset 0x08 */ 801 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x08, buf, 2); 802 if (rc) { 803 pr_err("%s:R0' read failed\n", __func__); 804 return rc; 805 } 806 DBG("R0'=%02x%02x", buf[1], buf[0]); 807 808 /* Write R0' to HDCP registers and check to see if it is a match */ 809 hdmi_write(hdmi, REG_HDMI_HDCP_RCVPORT_DATA2_0, 810 (((u32)buf[1]) << 8) | buf[0]); 811 812 return 0; 813 } 814 815 /* Wait for authenticating result: R0/R0' are matched or not */ 816 static int msm_hdmi_hdcp_auth_part1_verify_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl) 817 { 818 struct hdmi *hdmi = hdcp_ctrl->hdmi; 819 u32 link0_status; 820 int rc; 821 822 /* wait for hdcp irq, 10 sec should be long enough */ 823 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 10000, AUTH_RESULT_RDY_EV); 824 if (!rc) { 825 pr_err("%s: Wait Auth IRQ timeout\n", __func__); 826 return -ETIMEDOUT; 827 } 828 829 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 830 if (!(link0_status & HDMI_HDCP_LINK0_STATUS_RI_MATCHES)) { 831 pr_err("%s: Authentication Part I failed\n", __func__); 832 return -EINVAL; 833 } 834 835 /* Enable HDCP Encryption */ 836 hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, 837 HDMI_HDCP_CTRL_ENABLE | 838 HDMI_HDCP_CTRL_ENCRYPTION_ENABLE); 839 840 return 0; 841 } 842 843 static int msm_hdmi_hdcp_recv_check_bstatus(struct hdmi_hdcp_ctrl *hdcp_ctrl, 844 u16 *pbstatus) 845 { 846 int rc; 847 struct hdmi *hdmi = hdcp_ctrl->hdmi; 848 bool max_devs_exceeded = false, max_cascade_exceeded = false; 849 u32 repeater_cascade_depth = 0, down_stream_devices = 0; 850 u16 bstatus; 851 u8 buf[2]; 852 853 /* Read BSTATUS at offset 0x41 */ 854 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x41, buf, 2); 855 if (rc) { 856 pr_err("%s: BSTATUS read failed\n", __func__); 857 goto error; 858 } 859 *pbstatus = bstatus = (buf[1] << 8) | buf[0]; 860 861 862 down_stream_devices = bstatus & 0x7F; 863 repeater_cascade_depth = (bstatus >> 8) & 0x7; 864 max_devs_exceeded = (bstatus & BIT(7)) ? true : false; 865 max_cascade_exceeded = (bstatus & BIT(11)) ? true : false; 866 867 if (down_stream_devices == 0) { 868 /* 869 * If no downstream devices are attached to the repeater 870 * then part II fails. 871 * todo: The other approach would be to continue PART II. 872 */ 873 pr_err("%s: No downstream devices\n", __func__); 874 rc = -EINVAL; 875 goto error; 876 } 877 878 /* 879 * HDCP Compliance 1B-05: 880 * Check if no. of devices connected to repeater 881 * exceed max_devices_connected from bit 7 of Bstatus. 882 */ 883 if (max_devs_exceeded) { 884 pr_err("%s: no. of devs connected exceeds max allowed", 885 __func__); 886 rc = -EINVAL; 887 goto error; 888 } 889 890 /* 891 * HDCP Compliance 1B-06: 892 * Check if no. of cascade connected to repeater 893 * exceed max_cascade_connected from bit 11 of Bstatus. 894 */ 895 if (max_cascade_exceeded) { 896 pr_err("%s: no. of cascade conn exceeds max allowed", 897 __func__); 898 rc = -EINVAL; 899 goto error; 900 } 901 902 error: 903 hdcp_ctrl->dev_count = down_stream_devices; 904 hdcp_ctrl->max_cascade_exceeded = max_cascade_exceeded; 905 hdcp_ctrl->max_dev_exceeded = max_devs_exceeded; 906 hdcp_ctrl->depth = repeater_cascade_depth; 907 return rc; 908 } 909 910 static int msm_hdmi_hdcp_auth_part2_wait_ksv_fifo_ready( 911 struct hdmi_hdcp_ctrl *hdcp_ctrl) 912 { 913 int rc; 914 struct hdmi *hdmi = hdcp_ctrl->hdmi; 915 u32 reg, data; 916 u32 timeout_count; 917 u16 bstatus; 918 u8 bcaps; 919 920 /* 921 * Wait until READY bit is set in BCAPS, as per HDCP specifications 922 * maximum permitted time to check for READY bit is five seconds. 923 */ 924 timeout_count = 100; 925 do { 926 /* Read BCAPS at offset 0x40 */ 927 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1); 928 if (rc) { 929 pr_err("%s: BCAPS read failed\n", __func__); 930 return rc; 931 } 932 933 if (bcaps & BIT(5)) 934 break; 935 936 timeout_count--; 937 if (!timeout_count) { 938 pr_err("%s: Wait KSV fifo ready timedout", __func__); 939 return -ETIMEDOUT; 940 } 941 942 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 943 if (rc) 944 return rc; 945 } while (1); 946 947 rc = msm_hdmi_hdcp_recv_check_bstatus(hdcp_ctrl, &bstatus); 948 if (rc) { 949 pr_err("%s: bstatus error\n", __func__); 950 return rc; 951 } 952 953 /* Write BSTATUS and BCAPS to HDCP registers */ 954 reg = REG_HDMI_HDCP_RCVPORT_DATA12; 955 data = bcaps | (bstatus << 8); 956 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, ®, &data, 1); 957 if (rc) { 958 pr_err("%s: BSTATUS write failed\n", __func__); 959 return rc; 960 } 961 962 return 0; 963 } 964 965 /* 966 * hdcp authenticating part 2: 2nd 967 * read ksv fifo from sink 968 * transfer V' from sink to HDCP engine 969 * reset SHA engine 970 */ 971 static int msm_hdmi_hdcp_transfer_v_h(struct hdmi_hdcp_ctrl *hdcp_ctrl) 972 { 973 struct hdmi *hdmi = hdcp_ctrl->hdmi; 974 int rc = 0; 975 struct hdmi_hdcp_reg_data reg_data[] = { 976 {REG_HDMI_HDCP_RCVPORT_DATA7, 0x20, "V' H0"}, 977 {REG_HDMI_HDCP_RCVPORT_DATA8, 0x24, "V' H1"}, 978 {REG_HDMI_HDCP_RCVPORT_DATA9, 0x28, "V' H2"}, 979 {REG_HDMI_HDCP_RCVPORT_DATA10, 0x2C, "V' H3"}, 980 {REG_HDMI_HDCP_RCVPORT_DATA11, 0x30, "V' H4"}, 981 }; 982 struct hdmi_hdcp_reg_data *rd; 983 u32 size = ARRAY_SIZE(reg_data); 984 u32 reg[ARRAY_SIZE(reg_data)]; 985 u32 data[ARRAY_SIZE(reg_data)]; 986 int i; 987 988 for (i = 0; i < size; i++) { 989 rd = ®_data[i]; 990 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 991 rd->off, (u8 *)&data[i], (u16)sizeof(data[i])); 992 if (rc) { 993 pr_err("%s: Read %s failed\n", __func__, rd->name); 994 goto error; 995 } 996 997 DBG("%s =%x", rd->name, data[i]); 998 reg[i] = reg_data[i].reg_id; 999 } 1000 1001 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, size); 1002 1003 error: 1004 return rc; 1005 } 1006 1007 static int msm_hdmi_hdcp_recv_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1008 { 1009 int rc; 1010 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1011 u32 ksv_bytes; 1012 1013 ksv_bytes = 5 * hdcp_ctrl->dev_count; 1014 1015 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x43, 1016 hdcp_ctrl->ksv_list, ksv_bytes); 1017 if (rc) 1018 pr_err("%s: KSV FIFO read failed\n", __func__); 1019 1020 return rc; 1021 } 1022 1023 static int msm_hdmi_hdcp_reset_sha_engine(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1024 { 1025 u32 reg[2], data[2]; 1026 u32 rc = 0; 1027 1028 reg[0] = REG_HDMI_HDCP_SHA_CTRL; 1029 data[0] = HDCP_REG_ENABLE; 1030 reg[1] = REG_HDMI_HDCP_SHA_CTRL; 1031 data[1] = HDCP_REG_DISABLE; 1032 1033 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2); 1034 1035 return rc; 1036 } 1037 1038 static int msm_hdmi_hdcp_auth_part2_recv_ksv_fifo( 1039 struct hdmi_hdcp_ctrl *hdcp_ctrl) 1040 { 1041 int rc; 1042 u32 timeout_count; 1043 1044 /* 1045 * Read KSV FIFO over DDC 1046 * Key Selection vector FIFO Used to pull downstream KSVs 1047 * from HDCP Repeaters. 1048 * All bytes (DEVICE_COUNT * 5) must be read in a single, 1049 * auto incrementing access. 1050 * All bytes read as 0x00 for HDCP Receivers that are not 1051 * HDCP Repeaters (REPEATER == 0). 1052 */ 1053 timeout_count = 100; 1054 do { 1055 rc = msm_hdmi_hdcp_recv_ksv_fifo(hdcp_ctrl); 1056 if (!rc) 1057 break; 1058 1059 timeout_count--; 1060 if (!timeout_count) { 1061 pr_err("%s: Recv ksv fifo timedout", __func__); 1062 return -ETIMEDOUT; 1063 } 1064 1065 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 25, AUTH_ABORT_EV); 1066 if (rc) 1067 return rc; 1068 } while (1); 1069 1070 rc = msm_hdmi_hdcp_transfer_v_h(hdcp_ctrl); 1071 if (rc) { 1072 pr_err("%s: transfer V failed\n", __func__); 1073 return rc; 1074 } 1075 1076 /* reset SHA engine before write ksv fifo */ 1077 rc = msm_hdmi_hdcp_reset_sha_engine(hdcp_ctrl); 1078 if (rc) { 1079 pr_err("%s: fail to reset sha engine\n", __func__); 1080 return rc; 1081 } 1082 1083 return 0; 1084 } 1085 1086 /* 1087 * Write KSV FIFO to HDCP_SHA_DATA. 1088 * This is done 1 byte at time starting with the LSB. 1089 * Once 64 bytes have been written, we need to poll for 1090 * HDCP_SHA_BLOCK_DONE before writing any further 1091 * If the last byte is written, we need to poll for 1092 * HDCP_SHA_COMP_DONE to wait until HW finish 1093 */ 1094 static int msm_hdmi_hdcp_write_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1095 { 1096 int i; 1097 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1098 u32 ksv_bytes, last_byte = 0; 1099 u8 *ksv_fifo = NULL; 1100 u32 reg_val, data, reg; 1101 u32 rc = 0; 1102 1103 ksv_bytes = 5 * hdcp_ctrl->dev_count; 1104 1105 /* Check if need to wait for HW completion */ 1106 if (hdcp_ctrl->ksv_fifo_w_index) { 1107 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_SHA_STATUS); 1108 DBG("HDCP_SHA_STATUS=%08x", reg_val); 1109 if (hdcp_ctrl->ksv_fifo_w_index == ksv_bytes) { 1110 /* check COMP_DONE if last write */ 1111 if (reg_val & HDMI_HDCP_SHA_STATUS_COMP_DONE) { 1112 DBG("COMP_DONE"); 1113 return 0; 1114 } else { 1115 return -EAGAIN; 1116 } 1117 } else { 1118 /* check BLOCK_DONE if not last write */ 1119 if (!(reg_val & HDMI_HDCP_SHA_STATUS_BLOCK_DONE)) 1120 return -EAGAIN; 1121 1122 DBG("BLOCK_DONE"); 1123 } 1124 } 1125 1126 ksv_bytes -= hdcp_ctrl->ksv_fifo_w_index; 1127 if (ksv_bytes <= 64) 1128 last_byte = 1; 1129 else 1130 ksv_bytes = 64; 1131 1132 ksv_fifo = hdcp_ctrl->ksv_list; 1133 ksv_fifo += hdcp_ctrl->ksv_fifo_w_index; 1134 1135 for (i = 0; i < ksv_bytes; i++) { 1136 /* Write KSV byte and set DONE bit[0] for last byte*/ 1137 reg_val = ksv_fifo[i] << 16; 1138 if ((i == (ksv_bytes - 1)) && last_byte) 1139 reg_val |= HDMI_HDCP_SHA_DATA_DONE; 1140 1141 reg = REG_HDMI_HDCP_SHA_DATA; 1142 data = reg_val; 1143 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, ®, &data, 1); 1144 1145 if (rc) 1146 return rc; 1147 } 1148 1149 hdcp_ctrl->ksv_fifo_w_index += ksv_bytes; 1150 1151 /* 1152 *return -EAGAIN to notify caller to wait for COMP_DONE or BLOCK_DONE 1153 */ 1154 return -EAGAIN; 1155 } 1156 1157 /* write ksv fifo into HDCP engine */ 1158 static int msm_hdmi_hdcp_auth_part2_write_ksv_fifo( 1159 struct hdmi_hdcp_ctrl *hdcp_ctrl) 1160 { 1161 int rc; 1162 u32 timeout_count; 1163 1164 hdcp_ctrl->ksv_fifo_w_index = 0; 1165 timeout_count = 100; 1166 do { 1167 rc = msm_hdmi_hdcp_write_ksv_fifo(hdcp_ctrl); 1168 if (!rc) 1169 break; 1170 1171 if (rc != -EAGAIN) 1172 return rc; 1173 1174 timeout_count--; 1175 if (!timeout_count) { 1176 pr_err("%s: Write KSV fifo timedout", __func__); 1177 return -ETIMEDOUT; 1178 } 1179 1180 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 1181 if (rc) 1182 return rc; 1183 } while (1); 1184 1185 return 0; 1186 } 1187 1188 static int msm_hdmi_hdcp_auth_part2_check_v_match(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1189 { 1190 int rc = 0; 1191 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1192 u32 link0_status; 1193 u32 timeout_count = 100; 1194 1195 do { 1196 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 1197 if (link0_status & HDMI_HDCP_LINK0_STATUS_V_MATCHES) 1198 break; 1199 1200 timeout_count--; 1201 if (!timeout_count) { 1202 pr_err("%s: HDCP V Match timedout", __func__); 1203 return -ETIMEDOUT; 1204 } 1205 1206 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 1207 if (rc) 1208 return rc; 1209 } while (1); 1210 1211 return 0; 1212 } 1213 1214 static void msm_hdmi_hdcp_auth_work(struct work_struct *work) 1215 { 1216 struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(work, 1217 struct hdmi_hdcp_ctrl, hdcp_auth_work); 1218 int rc; 1219 1220 rc = msm_hdmi_hdcp_auth_prepare(hdcp_ctrl); 1221 if (rc) { 1222 pr_err("%s: auth prepare failed %d\n", __func__, rc); 1223 goto end; 1224 } 1225 1226 /* HDCP PartI */ 1227 rc = msm_hdmi_hdcp_auth_part1_key_exchange(hdcp_ctrl); 1228 if (rc) { 1229 pr_err("%s: key exchange failed %d\n", __func__, rc); 1230 goto end; 1231 } 1232 1233 rc = msm_hdmi_hdcp_auth_part1_recv_r0(hdcp_ctrl); 1234 if (rc) { 1235 pr_err("%s: receive r0 failed %d\n", __func__, rc); 1236 goto end; 1237 } 1238 1239 rc = msm_hdmi_hdcp_auth_part1_verify_r0(hdcp_ctrl); 1240 if (rc) { 1241 pr_err("%s: verify r0 failed %d\n", __func__, rc); 1242 goto end; 1243 } 1244 pr_info("%s: Authentication Part I successful\n", __func__); 1245 if (hdcp_ctrl->ds_type == DS_RECEIVER) 1246 goto end; 1247 1248 /* HDCP PartII */ 1249 rc = msm_hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(hdcp_ctrl); 1250 if (rc) { 1251 pr_err("%s: wait ksv fifo ready failed %d\n", __func__, rc); 1252 goto end; 1253 } 1254 1255 rc = msm_hdmi_hdcp_auth_part2_recv_ksv_fifo(hdcp_ctrl); 1256 if (rc) { 1257 pr_err("%s: recv ksv fifo failed %d\n", __func__, rc); 1258 goto end; 1259 } 1260 1261 rc = msm_hdmi_hdcp_auth_part2_write_ksv_fifo(hdcp_ctrl); 1262 if (rc) { 1263 pr_err("%s: write ksv fifo failed %d\n", __func__, rc); 1264 goto end; 1265 } 1266 1267 rc = msm_hdmi_hdcp_auth_part2_check_v_match(hdcp_ctrl); 1268 if (rc) 1269 pr_err("%s: check v match failed %d\n", __func__, rc); 1270 1271 end: 1272 if (rc == -ECANCELED) { 1273 pr_info("%s: hdcp authentication canceled\n", __func__); 1274 } else if (rc == -ENOTSUPP) { 1275 pr_info("%s: hdcp is not supported\n", __func__); 1276 } else if (rc) { 1277 pr_err("%s: hdcp authentication failed\n", __func__); 1278 msm_hdmi_hdcp_auth_fail(hdcp_ctrl); 1279 } else { 1280 msm_hdmi_hdcp_auth_done(hdcp_ctrl); 1281 } 1282 } 1283 1284 void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1285 { 1286 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1287 unsigned long flags; 1288 1289 if ((HDCP_STATE_INACTIVE != hdcp_ctrl->hdcp_state) || 1290 (HDCP_STATE_NO_AKSV == hdcp_ctrl->hdcp_state)) { 1291 DBG("still active or activating or no askv. returning"); 1292 return; 1293 } 1294 1295 /* clear HDMI Encrypt */ 1296 spin_lock_irqsave(&hdmi->reg_lock, flags); 1297 hdmi_clear_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED); 1298 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 1299 1300 hdcp_ctrl->auth_event = 0; 1301 hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATING; 1302 hdcp_ctrl->auth_retries = 0; 1303 queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work); 1304 } 1305 1306 void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1307 { 1308 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1309 unsigned long flags; 1310 1311 if ((HDCP_STATE_INACTIVE == hdcp_ctrl->hdcp_state) || 1312 (HDCP_STATE_NO_AKSV == hdcp_ctrl->hdcp_state)) { 1313 DBG("hdcp inactive or no aksv. returning"); 1314 return; 1315 } 1316 1317 /* 1318 * Disable HPD circuitry. 1319 * This is needed to reset the HDCP cipher engine so that when we 1320 * attempt a re-authentication, HW would clear the AN0_READY and 1321 * AN1_READY bits in HDMI_HDCP_LINK0_STATUS register 1322 */ 1323 spin_lock_irqsave(&hdmi->reg_lock, flags); 1324 hdmi_clear_bits(hdmi, REG_HDMI_HPD_CTRL, HDMI_HPD_CTRL_ENABLE); 1325 1326 /* 1327 * Disable HDCP interrupts. 1328 * Also, need to set the state to inactive here so that any ongoing 1329 * reauth works will know that the HDCP session has been turned off. 1330 */ 1331 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, 0); 1332 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 1333 1334 /* 1335 * Cancel any pending auth/reauth attempts. 1336 * If one is ongoing, this will wait for it to finish. 1337 * No more reauthentication attempts will be scheduled since we 1338 * set the current state to inactive. 1339 */ 1340 set_bit(AUTH_ABORT_EV, &hdcp_ctrl->auth_event); 1341 wake_up_all(&hdcp_ctrl->auth_event_queue); 1342 cancel_work_sync(&hdcp_ctrl->hdcp_auth_work); 1343 cancel_work_sync(&hdcp_ctrl->hdcp_reauth_work); 1344 1345 hdmi_write(hdmi, REG_HDMI_HDCP_RESET, 1346 HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE); 1347 1348 /* Disable encryption and disable the HDCP block */ 1349 hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, 0); 1350 1351 spin_lock_irqsave(&hdmi->reg_lock, flags); 1352 hdmi_clear_bits(hdmi, REG_HDMI_CTRL, HDMI_CTRL_ENCRYPTED); 1353 1354 /* Enable HPD circuitry */ 1355 hdmi_update_bits(hdmi, REG_HDMI_HPD_CTRL, HDMI_HPD_CTRL_ENABLE, 1356 HDMI_HPD_CTRL_ENABLE); 1357 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 1358 1359 hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE; 1360 1361 DBG("HDCP: Off"); 1362 } 1363 1364 struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi) 1365 { 1366 struct hdmi_hdcp_ctrl *hdcp_ctrl = NULL; 1367 1368 if (!hdmi->qfprom_mmio) { 1369 pr_err("%s: HDCP is not supported without qfprom\n", 1370 __func__); 1371 return ERR_PTR(-EINVAL); 1372 } 1373 1374 hdcp_ctrl = kzalloc_obj(*hdcp_ctrl); 1375 if (!hdcp_ctrl) 1376 return ERR_PTR(-ENOMEM); 1377 1378 INIT_WORK(&hdcp_ctrl->hdcp_auth_work, msm_hdmi_hdcp_auth_work); 1379 INIT_WORK(&hdcp_ctrl->hdcp_reauth_work, msm_hdmi_hdcp_reauth_work); 1380 init_waitqueue_head(&hdcp_ctrl->auth_event_queue); 1381 hdcp_ctrl->hdmi = hdmi; 1382 hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE; 1383 hdcp_ctrl->aksv_valid = false; 1384 1385 if (qcom_scm_hdcp_available()) 1386 hdcp_ctrl->tz_hdcp = true; 1387 else 1388 hdcp_ctrl->tz_hdcp = false; 1389 1390 return hdcp_ctrl; 1391 } 1392 1393 void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) 1394 { 1395 if (hdmi) { 1396 kfree(hdmi->hdcp_ctrl); 1397 hdmi->hdcp_ctrl = NULL; 1398 } 1399 } 1400