1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/delay.h> 8 #include <drm/drm_bridge_connector.h> 9 #include <drm/drm_edid.h> 10 #include <drm/display/drm_hdmi_helper.h> 11 #include <drm/display/drm_hdmi_state_helper.h> 12 13 #include "msm_kms.h" 14 #include "hdmi.h" 15 16 static void msm_hdmi_power_on(struct drm_bridge *bridge) 17 { 18 struct drm_device *dev = bridge->dev; 19 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 20 struct hdmi *hdmi = hdmi_bridge->hdmi; 21 int ret; 22 23 pm_runtime_resume_and_get(&hdmi->pdev->dev); 24 25 if (hdmi->extp_clk) { 26 DBG("pixclock: %lu", hdmi->pixclock); 27 ret = clk_set_rate(hdmi->extp_clk, hdmi->pixclock); 28 if (ret) 29 DRM_DEV_ERROR(dev->dev, "failed to set extp clk rate: %d\n", ret); 30 31 ret = clk_prepare_enable(hdmi->extp_clk); 32 if (ret) 33 DRM_DEV_ERROR(dev->dev, "failed to enable extp clk: %d\n", ret); 34 } 35 } 36 37 static void power_off(struct drm_bridge *bridge) 38 { 39 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 40 struct hdmi *hdmi = hdmi_bridge->hdmi; 41 42 /* TODO do we need to wait for final vblank somewhere before 43 * cutting the clocks? 44 */ 45 mdelay(16 + 4); 46 47 if (hdmi->extp_clk) 48 clk_disable_unprepare(hdmi->extp_clk); 49 50 pm_runtime_put(&hdmi->pdev->dev); 51 } 52 53 #define AVI_IFRAME_LINE_NUMBER 1 54 #define SPD_IFRAME_LINE_NUMBER 1 55 #define VENSPEC_IFRAME_LINE_NUMBER 3 56 57 static int msm_hdmi_bridge_clear_avi_infoframe(struct drm_bridge *bridge) 58 { 59 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 60 struct hdmi *hdmi = hdmi_bridge->hdmi; 61 u32 val; 62 63 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL0); 64 val &= ~(HDMI_INFOFRAME_CTRL0_AVI_SEND | 65 HDMI_INFOFRAME_CTRL0_AVI_CONT); 66 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, val); 67 68 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1); 69 val &= ~HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK; 70 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val); 71 72 return 0; 73 } 74 75 static int msm_hdmi_bridge_clear_audio_infoframe(struct drm_bridge *bridge) 76 { 77 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 78 struct hdmi *hdmi = hdmi_bridge->hdmi; 79 u32 val; 80 81 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL0); 82 val &= ~(HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND | 83 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT | 84 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE | 85 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE); 86 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, val); 87 88 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1); 89 val &= ~HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK; 90 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val); 91 92 return 0; 93 } 94 95 static int msm_hdmi_bridge_clear_spd_infoframe(struct drm_bridge *bridge) 96 { 97 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 98 struct hdmi *hdmi = hdmi_bridge->hdmi; 99 u32 val; 100 101 val = hdmi_read(hdmi, REG_HDMI_GEN_PKT_CTRL); 102 val &= ~(HDMI_GEN_PKT_CTRL_GENERIC1_SEND | 103 HDMI_GEN_PKT_CTRL_GENERIC1_CONT | 104 HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK); 105 hdmi_write(hdmi, REG_HDMI_GEN_PKT_CTRL, val); 106 107 return 0; 108 } 109 110 static int msm_hdmi_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) 111 { 112 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 113 struct hdmi *hdmi = hdmi_bridge->hdmi; 114 u32 val; 115 116 val = hdmi_read(hdmi, REG_HDMI_GEN_PKT_CTRL); 117 val &= ~(HDMI_GEN_PKT_CTRL_GENERIC0_SEND | 118 HDMI_GEN_PKT_CTRL_GENERIC0_CONT | 119 HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE | 120 HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK); 121 hdmi_write(hdmi, REG_HDMI_GEN_PKT_CTRL, val); 122 123 return 0; 124 } 125 126 static int msm_hdmi_bridge_write_avi_infoframe(struct drm_bridge *bridge, 127 const u8 *buffer, size_t len) 128 { 129 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 130 struct hdmi *hdmi = hdmi_bridge->hdmi; 131 u32 buf[4] = {}; 132 u32 val; 133 int i; 134 135 if (len != HDMI_INFOFRAME_SIZE(AVI) || len - 3 > sizeof(buf)) { 136 DRM_DEV_ERROR(&hdmi->pdev->dev, 137 "failed to configure avi infoframe\n"); 138 return -EINVAL; 139 } 140 141 msm_hdmi_bridge_clear_avi_infoframe(bridge); 142 143 /* 144 * the AVI_INFOx registers don't map exactly to how the AVI infoframes 145 * are packed according to the spec. The checksum from the header is 146 * written to the LSB byte of AVI_INFO0 and the version is written to 147 * the third byte from the LSB of AVI_INFO3 148 */ 149 memcpy(buf, &buffer[3], len - 3); 150 151 buf[3] |= buffer[1] << 24; 152 153 for (i = 0; i < ARRAY_SIZE(buf); i++) 154 hdmi_write(hdmi, REG_HDMI_AVI_INFO(i), buf[i]); 155 156 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1); 157 val |= HDMI_INFOFRAME_CTRL0_AVI_SEND | 158 HDMI_INFOFRAME_CTRL0_AVI_CONT; 159 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, val); 160 161 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1); 162 val &= ~HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK; 163 val |= HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER); 164 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val); 165 166 return 0; 167 } 168 169 static int msm_hdmi_bridge_write_audio_infoframe(struct drm_bridge *bridge, 170 const u8 *buffer, size_t len) 171 { 172 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 173 struct hdmi *hdmi = hdmi_bridge->hdmi; 174 u32 val; 175 176 if (len != HDMI_INFOFRAME_SIZE(AUDIO)) { 177 DRM_DEV_ERROR(&hdmi->pdev->dev, 178 "failed to configure audio infoframe\n"); 179 return -EINVAL; 180 } 181 182 msm_hdmi_bridge_clear_audio_infoframe(bridge); 183 184 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO0, 185 buffer[3] | 186 buffer[4] << 8 | 187 buffer[5] << 16 | 188 buffer[6] << 24); 189 190 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO1, 191 buffer[7] | 192 buffer[8] << 8 | 193 buffer[9] << 16 | 194 buffer[10] << 24); 195 196 val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1); 197 val |= HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND | 198 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT | 199 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE | 200 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE; 201 hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0, val); 202 203 return 0; 204 } 205 206 static int msm_hdmi_bridge_write_spd_infoframe(struct drm_bridge *bridge, 207 const u8 *buffer, size_t len) 208 { 209 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 210 struct hdmi *hdmi = hdmi_bridge->hdmi; 211 u32 buf[7] = {}; 212 u32 val; 213 int i; 214 215 if (len != HDMI_INFOFRAME_SIZE(SPD) || len - 3 > sizeof(buf)) { 216 DRM_DEV_ERROR(&hdmi->pdev->dev, 217 "failed to configure SPD infoframe\n"); 218 return -EINVAL; 219 } 220 221 msm_hdmi_bridge_clear_spd_infoframe(bridge); 222 223 /* checksum gets written together with the body of the frame */ 224 hdmi_write(hdmi, REG_HDMI_GENERIC1_HDR, 225 buffer[0] | 226 buffer[1] << 8 | 227 buffer[2] << 16); 228 229 memcpy(buf, &buffer[3], len - 3); 230 231 for (i = 0; i < ARRAY_SIZE(buf); i++) 232 hdmi_write(hdmi, REG_HDMI_GENERIC1(i), buf[i]); 233 234 val = hdmi_read(hdmi, REG_HDMI_GEN_PKT_CTRL); 235 val |= HDMI_GEN_PKT_CTRL_GENERIC1_SEND | 236 HDMI_GEN_PKT_CTRL_GENERIC1_CONT | 237 HDMI_GEN_PKT_CTRL_GENERIC1_LINE(SPD_IFRAME_LINE_NUMBER); 238 hdmi_write(hdmi, REG_HDMI_GEN_PKT_CTRL, val); 239 240 return 0; 241 } 242 243 static int msm_hdmi_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, 244 const u8 *buffer, size_t len) 245 { 246 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 247 struct hdmi *hdmi = hdmi_bridge->hdmi; 248 u32 buf[7] = {}; 249 u32 val; 250 int i; 251 252 if (len < HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_SIZE || 253 len - 3 > sizeof(buf)) { 254 DRM_DEV_ERROR(&hdmi->pdev->dev, 255 "failed to configure HDMI infoframe\n"); 256 return -EINVAL; 257 } 258 259 msm_hdmi_bridge_clear_hdmi_infoframe(bridge); 260 261 /* checksum gets written together with the body of the frame */ 262 hdmi_write(hdmi, REG_HDMI_GENERIC0_HDR, 263 buffer[0] | 264 buffer[1] << 8 | 265 buffer[2] << 16); 266 267 memcpy(buf, &buffer[3], len - 3); 268 269 for (i = 0; i < ARRAY_SIZE(buf); i++) 270 hdmi_write(hdmi, REG_HDMI_GENERIC0(i), buf[i]); 271 272 val = hdmi_read(hdmi, REG_HDMI_GEN_PKT_CTRL); 273 val |= HDMI_GEN_PKT_CTRL_GENERIC0_SEND | 274 HDMI_GEN_PKT_CTRL_GENERIC0_CONT | 275 HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE | 276 HDMI_GEN_PKT_CTRL_GENERIC0_LINE(VENSPEC_IFRAME_LINE_NUMBER); 277 hdmi_write(hdmi, REG_HDMI_GEN_PKT_CTRL, val); 278 279 return 0; 280 } 281 282 static void msm_hdmi_set_timings(struct hdmi *hdmi, 283 const struct drm_display_mode *mode); 284 285 static void msm_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 286 struct drm_atomic_state *state) 287 { 288 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 289 struct hdmi *hdmi = hdmi_bridge->hdmi; 290 struct hdmi_phy *phy = hdmi->phy; 291 struct drm_encoder *encoder = bridge->encoder; 292 struct drm_connector *connector; 293 struct drm_connector_state *conn_state; 294 struct drm_crtc_state *crtc_state; 295 296 DBG("power up"); 297 298 connector = drm_atomic_get_new_connector_for_encoder(state, encoder); 299 conn_state = drm_atomic_get_new_connector_state(state, connector); 300 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 301 302 hdmi->pixclock = conn_state->hdmi.tmds_char_rate; 303 304 msm_hdmi_set_timings(hdmi, &crtc_state->adjusted_mode); 305 306 mutex_lock(&hdmi->state_mutex); 307 if (!hdmi->power_on) { 308 msm_hdmi_phy_resource_enable(phy); 309 msm_hdmi_power_on(bridge); 310 hdmi->power_on = true; 311 } 312 mutex_unlock(&hdmi->state_mutex); 313 314 if (connector->display_info.is_hdmi) 315 msm_hdmi_audio_update(hdmi); 316 317 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 318 319 msm_hdmi_phy_powerup(phy, hdmi->pixclock); 320 321 msm_hdmi_set_mode(hdmi, true); 322 323 if (hdmi->hdcp_ctrl) 324 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl); 325 } 326 327 static void msm_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge, 328 struct drm_atomic_state *state) 329 { 330 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 331 struct hdmi *hdmi = hdmi_bridge->hdmi; 332 struct hdmi_phy *phy = hdmi->phy; 333 334 if (hdmi->hdcp_ctrl) 335 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl); 336 337 DBG("power down"); 338 339 /* Keep the HDMI enabled if the HPD is enabled */ 340 mutex_lock(&hdmi->state_mutex); 341 msm_hdmi_set_mode(hdmi, hdmi->hpd_enabled); 342 343 msm_hdmi_phy_powerdown(phy); 344 345 if (hdmi->power_on) { 346 power_off(bridge); 347 hdmi->power_on = false; 348 if (hdmi->connector->display_info.is_hdmi) 349 msm_hdmi_audio_update(hdmi); 350 msm_hdmi_phy_resource_disable(phy); 351 } 352 mutex_unlock(&hdmi->state_mutex); 353 } 354 355 static void msm_hdmi_set_timings(struct hdmi *hdmi, 356 const struct drm_display_mode *mode) 357 { 358 int hstart, hend, vstart, vend; 359 uint32_t frame_ctrl; 360 361 hstart = mode->htotal - mode->hsync_start; 362 hend = mode->htotal - mode->hsync_start + mode->hdisplay; 363 364 vstart = mode->vtotal - mode->vsync_start - 1; 365 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1; 366 367 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d", 368 mode->htotal, mode->vtotal, hstart, hend, vstart, vend); 369 370 hdmi_write(hdmi, REG_HDMI_TOTAL, 371 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) | 372 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1)); 373 374 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC, 375 HDMI_ACTIVE_HSYNC_START(hstart) | 376 HDMI_ACTIVE_HSYNC_END(hend)); 377 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC, 378 HDMI_ACTIVE_VSYNC_START(vstart) | 379 HDMI_ACTIVE_VSYNC_END(vend)); 380 381 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 382 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2, 383 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal)); 384 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2, 385 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) | 386 HDMI_VSYNC_ACTIVE_F2_END(vend + 1)); 387 } else { 388 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2, 389 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0)); 390 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2, 391 HDMI_VSYNC_ACTIVE_F2_START(0) | 392 HDMI_VSYNC_ACTIVE_F2_END(0)); 393 } 394 395 frame_ctrl = 0; 396 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 397 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW; 398 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 399 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW; 400 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 401 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN; 402 DBG("frame_ctrl=%08x", frame_ctrl); 403 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl); 404 } 405 406 static const struct drm_edid *msm_hdmi_bridge_edid_read(struct drm_bridge *bridge, 407 struct drm_connector *connector) 408 { 409 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 410 struct hdmi *hdmi = hdmi_bridge->hdmi; 411 const struct drm_edid *drm_edid; 412 uint32_t hdmi_ctrl; 413 414 hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); 415 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); 416 417 drm_edid = drm_edid_read_ddc(connector, hdmi->i2c); 418 419 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); 420 421 return drm_edid; 422 } 423 424 static enum drm_mode_status msm_hdmi_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge, 425 const struct drm_display_mode *mode, 426 unsigned long long tmds_rate) 427 { 428 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 429 struct hdmi *hdmi = hdmi_bridge->hdmi; 430 struct msm_drm_private *priv = bridge->dev->dev_private; 431 struct msm_kms *kms = priv->kms; 432 long actual; 433 434 /* for mdp5/apq8074, we manage our own pixel clk (as opposed to 435 * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder 436 * instead): 437 */ 438 if (kms->funcs->round_pixclk) 439 actual = kms->funcs->round_pixclk(kms, 440 tmds_rate, 441 hdmi_bridge->hdmi->encoder); 442 else if (hdmi->extp_clk) 443 actual = clk_round_rate(hdmi->extp_clk, tmds_rate); 444 else 445 actual = tmds_rate; 446 447 DBG("requested=%lld, actual=%ld", tmds_rate, actual); 448 449 if (actual != tmds_rate) 450 return MODE_CLOCK_RANGE; 451 452 return 0; 453 } 454 455 static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = { 456 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 457 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 458 .atomic_reset = drm_atomic_helper_bridge_reset, 459 .atomic_pre_enable = msm_hdmi_bridge_atomic_pre_enable, 460 .atomic_post_disable = msm_hdmi_bridge_atomic_post_disable, 461 .edid_read = msm_hdmi_bridge_edid_read, 462 .detect = msm_hdmi_bridge_detect, 463 .hpd_enable = msm_hdmi_hpd_enable, 464 .hpd_disable = msm_hdmi_hpd_disable, 465 .hdmi_tmds_char_rate_valid = msm_hdmi_bridge_tmds_char_rate_valid, 466 .hdmi_clear_audio_infoframe = msm_hdmi_bridge_clear_audio_infoframe, 467 .hdmi_write_audio_infoframe = msm_hdmi_bridge_write_audio_infoframe, 468 .hdmi_clear_avi_infoframe = msm_hdmi_bridge_clear_avi_infoframe, 469 .hdmi_write_avi_infoframe = msm_hdmi_bridge_write_avi_infoframe, 470 .hdmi_clear_spd_infoframe = msm_hdmi_bridge_clear_spd_infoframe, 471 .hdmi_write_spd_infoframe = msm_hdmi_bridge_write_spd_infoframe, 472 .hdmi_clear_hdmi_infoframe = msm_hdmi_bridge_clear_hdmi_infoframe, 473 .hdmi_write_hdmi_infoframe = msm_hdmi_bridge_write_hdmi_infoframe, 474 .hdmi_audio_prepare = msm_hdmi_bridge_audio_prepare, 475 .hdmi_audio_shutdown = msm_hdmi_bridge_audio_shutdown, 476 }; 477 478 static void 479 msm_hdmi_hotplug_work(struct work_struct *work) 480 { 481 struct hdmi_bridge *hdmi_bridge = 482 container_of(work, struct hdmi_bridge, hpd_work); 483 struct drm_bridge *bridge = &hdmi_bridge->base; 484 485 drm_bridge_hpd_notify(bridge, drm_bridge_detect(bridge, hdmi_bridge->hdmi->connector)); 486 } 487 488 /* initialize bridge */ 489 int msm_hdmi_bridge_init(struct hdmi *hdmi) 490 { 491 struct drm_bridge *bridge = NULL; 492 struct hdmi_bridge *hdmi_bridge; 493 int ret; 494 495 hdmi_bridge = devm_drm_bridge_alloc(hdmi->dev->dev, struct hdmi_bridge, base, 496 &msm_hdmi_bridge_funcs); 497 if (IS_ERR(hdmi_bridge)) 498 return PTR_ERR(hdmi_bridge); 499 500 hdmi_bridge->hdmi = hdmi; 501 INIT_WORK(&hdmi_bridge->hpd_work, msm_hdmi_hotplug_work); 502 503 bridge = &hdmi_bridge->base; 504 bridge->ddc = hdmi->i2c; 505 bridge->type = DRM_MODE_CONNECTOR_HDMIA; 506 bridge->vendor = "Qualcomm"; 507 bridge->product = "Snapdragon"; 508 bridge->ops = DRM_BRIDGE_OP_HPD | 509 DRM_BRIDGE_OP_DETECT | 510 DRM_BRIDGE_OP_HDMI | 511 DRM_BRIDGE_OP_HDMI_AUDIO | 512 DRM_BRIDGE_OP_EDID; 513 bridge->hdmi_audio_max_i2s_playback_channels = 8; 514 bridge->hdmi_audio_dev = &hdmi->pdev->dev; 515 bridge->hdmi_audio_dai_port = -1; 516 517 ret = devm_drm_bridge_add(hdmi->dev->dev, bridge); 518 if (ret) 519 return ret; 520 521 ret = drm_bridge_attach(hdmi->encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 522 if (ret) 523 return ret; 524 525 hdmi->bridge = bridge; 526 527 return 0; 528 } 529