1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/delay.h> 8 #include <drm/drm_bridge_connector.h> 9 #include <drm/drm_edid.h> 10 #include <drm/display/drm_hdmi_helper.h> 11 #include <drm/display/drm_hdmi_state_helper.h> 12 13 #include "msm_kms.h" 14 #include "hdmi.h" 15 16 static void msm_hdmi_power_on(struct drm_bridge *bridge) 17 { 18 struct drm_device *dev = bridge->dev; 19 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 20 struct hdmi *hdmi = hdmi_bridge->hdmi; 21 int ret; 22 23 pm_runtime_resume_and_get(&hdmi->pdev->dev); 24 25 if (hdmi->extp_clk) { 26 DBG("pixclock: %lu", hdmi->pixclock); 27 ret = clk_set_rate(hdmi->extp_clk, hdmi->pixclock); 28 if (ret) 29 DRM_DEV_ERROR(dev->dev, "failed to set extp clk rate: %d\n", ret); 30 31 ret = clk_prepare_enable(hdmi->extp_clk); 32 if (ret) 33 DRM_DEV_ERROR(dev->dev, "failed to enable extp clk: %d\n", ret); 34 } 35 } 36 37 static void power_off(struct drm_bridge *bridge) 38 { 39 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 40 struct hdmi *hdmi = hdmi_bridge->hdmi; 41 42 /* TODO do we need to wait for final vblank somewhere before 43 * cutting the clocks? 44 */ 45 mdelay(16 + 4); 46 47 if (hdmi->extp_clk) 48 clk_disable_unprepare(hdmi->extp_clk); 49 50 pm_runtime_put(&hdmi->pdev->dev); 51 } 52 53 #define AVI_IFRAME_LINE_NUMBER 1 54 #define SPD_IFRAME_LINE_NUMBER 1 55 #define VENSPEC_IFRAME_LINE_NUMBER 3 56 57 static int msm_hdmi_bridge_clear_avi_infoframe(struct drm_bridge *bridge) 58 { 59 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 60 struct hdmi *hdmi = hdmi_bridge->hdmi; 61 62 hdmi_clear_bits(hdmi, REG_HDMI_INFOFRAME_CTRL0, 63 HDMI_INFOFRAME_CTRL0_AVI_SEND | 64 HDMI_INFOFRAME_CTRL0_AVI_CONT); 65 66 hdmi_clear_bits(hdmi, REG_HDMI_INFOFRAME_CTRL1, 67 HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK); 68 69 return 0; 70 } 71 72 static int msm_hdmi_bridge_clear_audio_infoframe(struct drm_bridge *bridge) 73 { 74 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 75 struct hdmi *hdmi = hdmi_bridge->hdmi; 76 77 hdmi_clear_bits(hdmi, REG_HDMI_INFOFRAME_CTRL0, 78 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND | 79 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT | 80 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE | 81 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE); 82 83 hdmi_clear_bits(hdmi, REG_HDMI_INFOFRAME_CTRL1, 84 HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK); 85 86 return 0; 87 } 88 89 static int msm_hdmi_bridge_clear_spd_infoframe(struct drm_bridge *bridge) 90 { 91 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 92 struct hdmi *hdmi = hdmi_bridge->hdmi; 93 94 hdmi_clear_bits(hdmi, REG_HDMI_GEN_PKT_CTRL, 95 HDMI_GEN_PKT_CTRL_GENERIC1_SEND | 96 HDMI_GEN_PKT_CTRL_GENERIC1_CONT | 97 HDMI_GEN_PKT_CTRL_GENERIC1_LINE__MASK); 98 99 return 0; 100 } 101 102 static int msm_hdmi_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) 103 { 104 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 105 struct hdmi *hdmi = hdmi_bridge->hdmi; 106 107 hdmi_clear_bits(hdmi, REG_HDMI_GEN_PKT_CTRL, 108 HDMI_GEN_PKT_CTRL_GENERIC0_SEND | 109 HDMI_GEN_PKT_CTRL_GENERIC0_CONT | 110 HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE | 111 HDMI_GEN_PKT_CTRL_GENERIC0_LINE__MASK); 112 113 return 0; 114 } 115 116 static int msm_hdmi_bridge_write_avi_infoframe(struct drm_bridge *bridge, 117 const u8 *buffer, size_t len) 118 { 119 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 120 struct hdmi *hdmi = hdmi_bridge->hdmi; 121 u32 buf[4] = {}; 122 int i; 123 124 if (len != HDMI_INFOFRAME_SIZE(AVI) || len - 3 > sizeof(buf)) { 125 DRM_DEV_ERROR(&hdmi->pdev->dev, 126 "failed to configure avi infoframe\n"); 127 return -EINVAL; 128 } 129 130 msm_hdmi_bridge_clear_avi_infoframe(bridge); 131 132 /* 133 * the AVI_INFOx registers don't map exactly to how the AVI infoframes 134 * are packed according to the spec. The checksum from the header is 135 * written to the LSB byte of AVI_INFO0 and the version is written to 136 * the third byte from the LSB of AVI_INFO3 137 */ 138 memcpy(buf, &buffer[3], len - 3); 139 140 buf[3] |= buffer[1] << 24; 141 142 for (i = 0; i < ARRAY_SIZE(buf); i++) 143 hdmi_write(hdmi, REG_HDMI_AVI_INFO(i), buf[i]); 144 145 hdmi_update_bits(hdmi, REG_HDMI_INFOFRAME_CTRL0, 146 HDMI_INFOFRAME_CTRL0_AVI_SEND | HDMI_INFOFRAME_CTRL0_AVI_CONT, 147 HDMI_INFOFRAME_CTRL0_AVI_SEND | HDMI_INFOFRAME_CTRL0_AVI_CONT); 148 149 hdmi_update_bits(hdmi, REG_HDMI_INFOFRAME_CTRL1, 150 HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK, 151 HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER)); 152 153 return 0; 154 } 155 156 static int msm_hdmi_bridge_write_audio_infoframe(struct drm_bridge *bridge, 157 const u8 *buffer, size_t len) 158 { 159 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 160 struct hdmi *hdmi = hdmi_bridge->hdmi; 161 u32 val; 162 163 if (len != HDMI_INFOFRAME_SIZE(AUDIO)) { 164 DRM_DEV_ERROR(&hdmi->pdev->dev, 165 "failed to configure audio infoframe\n"); 166 return -EINVAL; 167 } 168 169 msm_hdmi_bridge_clear_audio_infoframe(bridge); 170 171 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO0, 172 buffer[3] | 173 buffer[4] << 8 | 174 buffer[5] << 16 | 175 buffer[6] << 24); 176 177 hdmi_write(hdmi, REG_HDMI_AUDIO_INFO1, 178 buffer[7] | 179 buffer[8] << 8 | 180 buffer[9] << 16 | 181 buffer[10] << 24); 182 183 val = HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SEND | 184 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_CONT | 185 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE | 186 HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE; 187 hdmi_update_bits(hdmi, REG_HDMI_INFOFRAME_CTRL0, val, val); 188 189 return 0; 190 } 191 192 static int msm_hdmi_bridge_write_spd_infoframe(struct drm_bridge *bridge, 193 const u8 *buffer, size_t len) 194 { 195 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 196 struct hdmi *hdmi = hdmi_bridge->hdmi; 197 u32 buf[7] = {}; 198 u32 val; 199 int i; 200 201 if (len != HDMI_INFOFRAME_SIZE(SPD) || len - 3 > sizeof(buf)) { 202 DRM_DEV_ERROR(&hdmi->pdev->dev, 203 "failed to configure SPD infoframe\n"); 204 return -EINVAL; 205 } 206 207 msm_hdmi_bridge_clear_spd_infoframe(bridge); 208 209 /* checksum gets written together with the body of the frame */ 210 hdmi_write(hdmi, REG_HDMI_GENERIC1_HDR, 211 buffer[0] | 212 buffer[1] << 8 | 213 buffer[2] << 16); 214 215 memcpy(buf, &buffer[3], len - 3); 216 217 for (i = 0; i < ARRAY_SIZE(buf); i++) 218 hdmi_write(hdmi, REG_HDMI_GENERIC1(i), buf[i]); 219 220 val = HDMI_GEN_PKT_CTRL_GENERIC1_SEND | 221 HDMI_GEN_PKT_CTRL_GENERIC1_CONT | 222 HDMI_GEN_PKT_CTRL_GENERIC1_LINE(SPD_IFRAME_LINE_NUMBER); 223 hdmi_update_bits(hdmi, REG_HDMI_GEN_PKT_CTRL, val, val); 224 225 return 0; 226 } 227 228 static int msm_hdmi_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, 229 const u8 *buffer, size_t len) 230 { 231 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 232 struct hdmi *hdmi = hdmi_bridge->hdmi; 233 u32 buf[7] = {}; 234 u32 val; 235 int i; 236 237 if (len < HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_SIZE || 238 len - 3 > sizeof(buf)) { 239 DRM_DEV_ERROR(&hdmi->pdev->dev, 240 "failed to configure HDMI infoframe\n"); 241 return -EINVAL; 242 } 243 244 msm_hdmi_bridge_clear_hdmi_infoframe(bridge); 245 246 /* checksum gets written together with the body of the frame */ 247 hdmi_write(hdmi, REG_HDMI_GENERIC0_HDR, 248 buffer[0] | 249 buffer[1] << 8 | 250 buffer[2] << 16); 251 252 memcpy(buf, &buffer[3], len - 3); 253 254 for (i = 0; i < ARRAY_SIZE(buf); i++) 255 hdmi_write(hdmi, REG_HDMI_GENERIC0(i), buf[i]); 256 257 val = HDMI_GEN_PKT_CTRL_GENERIC0_SEND | 258 HDMI_GEN_PKT_CTRL_GENERIC0_CONT | 259 HDMI_GEN_PKT_CTRL_GENERIC0_UPDATE | 260 HDMI_GEN_PKT_CTRL_GENERIC0_LINE(VENSPEC_IFRAME_LINE_NUMBER); 261 hdmi_update_bits(hdmi, REG_HDMI_GEN_PKT_CTRL, val, val); 262 263 return 0; 264 } 265 266 static void msm_hdmi_set_timings(struct hdmi *hdmi, 267 const struct drm_display_mode *mode); 268 269 static void msm_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 270 struct drm_atomic_commit *state) 271 { 272 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 273 struct hdmi *hdmi = hdmi_bridge->hdmi; 274 struct hdmi_phy *phy = hdmi->phy; 275 struct drm_encoder *encoder = bridge->encoder; 276 struct drm_connector *connector; 277 struct drm_connector_state *conn_state; 278 struct drm_crtc_state *crtc_state; 279 280 DBG("power up"); 281 282 connector = drm_atomic_get_new_connector_for_encoder(state, encoder); 283 conn_state = drm_atomic_get_new_connector_state(state, connector); 284 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 285 286 hdmi->pixclock = conn_state->hdmi.tmds_char_rate; 287 288 msm_hdmi_set_timings(hdmi, &crtc_state->adjusted_mode); 289 290 mutex_lock(&hdmi->state_mutex); 291 if (!hdmi->power_on) { 292 msm_hdmi_phy_resource_enable(phy); 293 msm_hdmi_power_on(bridge); 294 hdmi->power_on = true; 295 } 296 mutex_unlock(&hdmi->state_mutex); 297 298 if (connector->display_info.is_hdmi) 299 msm_hdmi_audio_update(hdmi); 300 301 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 302 303 msm_hdmi_phy_powerup(phy, hdmi->pixclock); 304 305 msm_hdmi_set_mode(hdmi, true); 306 307 if (hdmi->hdcp_ctrl) 308 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl); 309 } 310 311 static void msm_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge, 312 struct drm_atomic_commit *state) 313 { 314 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 315 struct hdmi *hdmi = hdmi_bridge->hdmi; 316 struct hdmi_phy *phy = hdmi->phy; 317 318 if (hdmi->hdcp_ctrl) 319 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl); 320 321 DBG("power down"); 322 323 /* Keep the HDMI enabled if the HPD is enabled */ 324 mutex_lock(&hdmi->state_mutex); 325 msm_hdmi_set_mode(hdmi, hdmi->hpd_enabled); 326 327 msm_hdmi_phy_powerdown(phy); 328 329 if (hdmi->power_on) { 330 power_off(bridge); 331 hdmi->power_on = false; 332 if (hdmi->connector->display_info.is_hdmi) 333 msm_hdmi_audio_update(hdmi); 334 msm_hdmi_phy_resource_disable(phy); 335 } 336 mutex_unlock(&hdmi->state_mutex); 337 } 338 339 static void msm_hdmi_set_timings(struct hdmi *hdmi, 340 const struct drm_display_mode *mode) 341 { 342 int hstart, hend, vstart, vend; 343 u32 frame_ctrl; 344 345 hstart = mode->htotal - mode->hsync_start; 346 hend = mode->htotal - mode->hsync_start + mode->hdisplay; 347 348 vstart = mode->vtotal - mode->vsync_start - 1; 349 vend = mode->vtotal - mode->vsync_start + mode->vdisplay - 1; 350 351 DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d", 352 mode->htotal, mode->vtotal, hstart, hend, vstart, vend); 353 354 hdmi_write(hdmi, REG_HDMI_TOTAL, 355 HDMI_TOTAL_H_TOTAL(mode->htotal - 1) | 356 HDMI_TOTAL_V_TOTAL(mode->vtotal - 1)); 357 358 hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC, 359 HDMI_ACTIVE_HSYNC_START(hstart) | 360 HDMI_ACTIVE_HSYNC_END(hend)); 361 hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC, 362 HDMI_ACTIVE_VSYNC_START(vstart) | 363 HDMI_ACTIVE_VSYNC_END(vend)); 364 365 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 366 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2, 367 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal)); 368 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2, 369 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) | 370 HDMI_VSYNC_ACTIVE_F2_END(vend + 1)); 371 } else { 372 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2, 373 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0)); 374 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2, 375 HDMI_VSYNC_ACTIVE_F2_START(0) | 376 HDMI_VSYNC_ACTIVE_F2_END(0)); 377 } 378 379 frame_ctrl = 0; 380 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 381 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW; 382 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 383 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW; 384 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 385 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN; 386 DBG("frame_ctrl=%08x", frame_ctrl); 387 hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl); 388 } 389 390 static const struct drm_edid *msm_hdmi_bridge_edid_read(struct drm_bridge *bridge, 391 struct drm_connector *connector) 392 { 393 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 394 struct hdmi *hdmi = hdmi_bridge->hdmi; 395 const struct drm_edid *drm_edid; 396 u32 hdmi_ctrl; 397 398 hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); 399 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); 400 401 drm_edid = drm_edid_read_ddc(connector, hdmi->i2c); 402 403 hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); 404 405 return drm_edid; 406 } 407 408 static enum drm_mode_status msm_hdmi_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge, 409 const struct drm_display_mode *mode, 410 unsigned long long tmds_rate) 411 { 412 struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); 413 struct hdmi *hdmi = hdmi_bridge->hdmi; 414 struct msm_drm_private *priv = bridge->dev->dev_private; 415 struct msm_kms *kms = priv->kms; 416 long actual; 417 418 /* for mdp5/apq8074, we manage our own pixel clk (as opposed to 419 * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder 420 * instead): 421 */ 422 if (kms->funcs->round_pixclk) 423 actual = kms->funcs->round_pixclk(kms, 424 tmds_rate, 425 hdmi_bridge->hdmi->encoder); 426 else if (hdmi->extp_clk) 427 actual = clk_round_rate(hdmi->extp_clk, tmds_rate); 428 else 429 actual = tmds_rate; 430 431 DBG("requested=%lld, actual=%ld", tmds_rate, actual); 432 433 if (actual != tmds_rate) 434 return MODE_CLOCK_RANGE; 435 436 return 0; 437 } 438 439 static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = { 440 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 441 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 442 .atomic_create_state = drm_atomic_helper_bridge_create_state, 443 .atomic_pre_enable = msm_hdmi_bridge_atomic_pre_enable, 444 .atomic_post_disable = msm_hdmi_bridge_atomic_post_disable, 445 .edid_read = msm_hdmi_bridge_edid_read, 446 .detect = msm_hdmi_bridge_detect, 447 .hpd_enable = msm_hdmi_hpd_enable, 448 .hpd_disable = msm_hdmi_hpd_disable, 449 .hdmi_tmds_char_rate_valid = msm_hdmi_bridge_tmds_char_rate_valid, 450 .hdmi_clear_audio_infoframe = msm_hdmi_bridge_clear_audio_infoframe, 451 .hdmi_write_audio_infoframe = msm_hdmi_bridge_write_audio_infoframe, 452 .hdmi_clear_avi_infoframe = msm_hdmi_bridge_clear_avi_infoframe, 453 .hdmi_write_avi_infoframe = msm_hdmi_bridge_write_avi_infoframe, 454 .hdmi_clear_spd_infoframe = msm_hdmi_bridge_clear_spd_infoframe, 455 .hdmi_write_spd_infoframe = msm_hdmi_bridge_write_spd_infoframe, 456 .hdmi_clear_hdmi_infoframe = msm_hdmi_bridge_clear_hdmi_infoframe, 457 .hdmi_write_hdmi_infoframe = msm_hdmi_bridge_write_hdmi_infoframe, 458 .hdmi_audio_prepare = msm_hdmi_bridge_audio_prepare, 459 .hdmi_audio_shutdown = msm_hdmi_bridge_audio_shutdown, 460 }; 461 462 static void 463 msm_hdmi_hotplug_work(struct work_struct *work) 464 { 465 struct hdmi_bridge *hdmi_bridge = 466 container_of(work, struct hdmi_bridge, hpd_work); 467 struct drm_bridge *bridge = &hdmi_bridge->base; 468 469 drm_bridge_hpd_notify(bridge, drm_bridge_detect(bridge, hdmi_bridge->hdmi->connector)); 470 } 471 472 /* initialize bridge */ 473 int msm_hdmi_bridge_init(struct hdmi *hdmi) 474 { 475 struct drm_bridge *bridge = NULL; 476 struct hdmi_bridge *hdmi_bridge; 477 int ret; 478 479 hdmi_bridge = devm_drm_bridge_alloc(hdmi->dev->dev, struct hdmi_bridge, base, 480 &msm_hdmi_bridge_funcs); 481 if (IS_ERR(hdmi_bridge)) 482 return PTR_ERR(hdmi_bridge); 483 484 hdmi_bridge->hdmi = hdmi; 485 INIT_WORK(&hdmi_bridge->hpd_work, msm_hdmi_hotplug_work); 486 487 bridge = &hdmi_bridge->base; 488 bridge->ddc = hdmi->i2c; 489 bridge->type = DRM_MODE_CONNECTOR_HDMIA; 490 bridge->vendor = "Qualcomm"; 491 bridge->product = "Snapdragon"; 492 bridge->ops = DRM_BRIDGE_OP_HPD | 493 DRM_BRIDGE_OP_DETECT | 494 DRM_BRIDGE_OP_HDMI | 495 DRM_BRIDGE_OP_HDMI_AUDIO | 496 DRM_BRIDGE_OP_EDID; 497 bridge->hdmi_audio_max_i2s_playback_channels = 8; 498 bridge->hdmi_audio_dev = &hdmi->pdev->dev; 499 bridge->hdmi_audio_dai_port = -1; 500 501 ret = devm_drm_bridge_add(hdmi->dev->dev, bridge); 502 if (ret) 503 return ret; 504 505 ret = drm_bridge_attach(hdmi->encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 506 if (ret) 507 return ret; 508 509 hdmi->bridge = bridge; 510 511 return 0; 512 } 513