xref: /linux/drivers/gpu/drm/msm/hdmi/hdmi.h (revision 2dbc0838bcf24ca59cabc3130cf3b1d6809cdcd4)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Red Hat
4  * Author: Rob Clark <robdclark@gmail.com>
5  */
6 
7 #ifndef __HDMI_CONNECTOR_H__
8 #define __HDMI_CONNECTOR_H__
9 
10 #include <linux/i2c.h>
11 #include <linux/clk.h>
12 #include <linux/platform_device.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/hdmi.h>
15 
16 #include "msm_drv.h"
17 #include "hdmi.xml.h"
18 
19 #define HDMI_MAX_NUM_GPIO	6
20 
21 struct hdmi_phy;
22 struct hdmi_platform_config;
23 
24 struct hdmi_gpio_data {
25 	int num;
26 	bool output;
27 	int value;
28 	const char *label;
29 };
30 
31 struct hdmi_audio {
32 	bool enabled;
33 	struct hdmi_audio_infoframe infoframe;
34 	int rate;
35 };
36 
37 struct hdmi_hdcp_ctrl;
38 
39 struct hdmi {
40 	struct drm_device *dev;
41 	struct platform_device *pdev;
42 	struct platform_device *audio_pdev;
43 
44 	const struct hdmi_platform_config *config;
45 
46 	/* audio state: */
47 	struct hdmi_audio audio;
48 
49 	/* video state: */
50 	bool power_on;
51 	unsigned long int pixclock;
52 
53 	void __iomem *mmio;
54 	void __iomem *qfprom_mmio;
55 	phys_addr_t mmio_phy_addr;
56 
57 	struct regulator **hpd_regs;
58 	struct regulator **pwr_regs;
59 	struct clk **hpd_clks;
60 	struct clk **pwr_clks;
61 
62 	struct hdmi_phy *phy;
63 	struct device *phy_dev;
64 
65 	struct i2c_adapter *i2c;
66 	struct drm_connector *connector;
67 	struct drm_bridge *bridge;
68 
69 	/* the encoder we are hooked to (outside of hdmi block) */
70 	struct drm_encoder *encoder;
71 
72 	bool hdmi_mode;               /* are we in hdmi mode? */
73 
74 	int irq;
75 	struct workqueue_struct *workq;
76 
77 	struct hdmi_hdcp_ctrl *hdcp_ctrl;
78 
79 	/*
80 	* spinlock to protect registers shared by different execution
81 	* REG_HDMI_CTRL
82 	* REG_HDMI_DDC_ARBITRATION
83 	* REG_HDMI_HDCP_INT_CTRL
84 	* REG_HDMI_HPD_CTRL
85 	*/
86 	spinlock_t reg_lock;
87 };
88 
89 /* platform config data (ie. from DT, or pdata) */
90 struct hdmi_platform_config {
91 	const char *mmio_name;
92 	const char *qfprom_mmio_name;
93 
94 	/* regulators that need to be on for hpd: */
95 	const char **hpd_reg_names;
96 	int hpd_reg_cnt;
97 
98 	/* regulators that need to be on for screen pwr: */
99 	const char **pwr_reg_names;
100 	int pwr_reg_cnt;
101 
102 	/* clks that need to be on for hpd: */
103 	const char **hpd_clk_names;
104 	const long unsigned *hpd_freq;
105 	int hpd_clk_cnt;
106 
107 	/* clks that need to be on for screen pwr (ie pixel clk): */
108 	const char **pwr_clk_names;
109 	int pwr_clk_cnt;
110 
111 	/* gpio's: */
112 	struct hdmi_gpio_data gpios[HDMI_MAX_NUM_GPIO];
113 };
114 
115 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on);
116 
117 static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
118 {
119 	msm_writel(data, hdmi->mmio + reg);
120 }
121 
122 static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
123 {
124 	return msm_readl(hdmi->mmio + reg);
125 }
126 
127 static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
128 {
129 	return msm_readl(hdmi->qfprom_mmio + reg);
130 }
131 
132 /*
133  * hdmi phy:
134  */
135 
136 enum hdmi_phy_type {
137 	MSM_HDMI_PHY_8x60,
138 	MSM_HDMI_PHY_8960,
139 	MSM_HDMI_PHY_8x74,
140 	MSM_HDMI_PHY_8996,
141 	MSM_HDMI_PHY_MAX,
142 };
143 
144 struct hdmi_phy_cfg {
145 	enum hdmi_phy_type type;
146 	void (*powerup)(struct hdmi_phy *phy, unsigned long int pixclock);
147 	void (*powerdown)(struct hdmi_phy *phy);
148 	const char * const *reg_names;
149 	int num_regs;
150 	const char * const *clk_names;
151 	int num_clks;
152 };
153 
154 extern const struct hdmi_phy_cfg msm_hdmi_phy_8x60_cfg;
155 extern const struct hdmi_phy_cfg msm_hdmi_phy_8960_cfg;
156 extern const struct hdmi_phy_cfg msm_hdmi_phy_8x74_cfg;
157 extern const struct hdmi_phy_cfg msm_hdmi_phy_8996_cfg;
158 
159 struct hdmi_phy {
160 	struct platform_device *pdev;
161 	void __iomem *mmio;
162 	struct hdmi_phy_cfg *cfg;
163 	const struct hdmi_phy_funcs *funcs;
164 	struct regulator **regs;
165 	struct clk **clks;
166 };
167 
168 static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
169 {
170 	msm_writel(data, phy->mmio + reg);
171 }
172 
173 static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
174 {
175 	return msm_readl(phy->mmio + reg);
176 }
177 
178 int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
179 void msm_hdmi_phy_resource_disable(struct hdmi_phy *phy);
180 void msm_hdmi_phy_powerup(struct hdmi_phy *phy, unsigned long int pixclock);
181 void msm_hdmi_phy_powerdown(struct hdmi_phy *phy);
182 void __init msm_hdmi_phy_driver_register(void);
183 void __exit msm_hdmi_phy_driver_unregister(void);
184 
185 #ifdef CONFIG_COMMON_CLK
186 int msm_hdmi_pll_8960_init(struct platform_device *pdev);
187 int msm_hdmi_pll_8996_init(struct platform_device *pdev);
188 #else
189 static inline int msm_hdmi_pll_8960_init(struct platform_device *pdev)
190 {
191 	return -ENODEV;
192 }
193 
194 static inline int msm_hdmi_pll_8996_init(struct platform_device *pdev)
195 {
196 	return -ENODEV;
197 }
198 #endif
199 
200 /*
201  * audio:
202  */
203 /* Supported HDMI Audio channels and rates */
204 #define	MSM_HDMI_AUDIO_CHANNEL_2	0
205 #define	MSM_HDMI_AUDIO_CHANNEL_4	1
206 #define	MSM_HDMI_AUDIO_CHANNEL_6	2
207 #define	MSM_HDMI_AUDIO_CHANNEL_8	3
208 
209 #define	HDMI_SAMPLE_RATE_32KHZ		0
210 #define	HDMI_SAMPLE_RATE_44_1KHZ	1
211 #define	HDMI_SAMPLE_RATE_48KHZ		2
212 #define	HDMI_SAMPLE_RATE_88_2KHZ	3
213 #define	HDMI_SAMPLE_RATE_96KHZ		4
214 #define	HDMI_SAMPLE_RATE_176_4KHZ	5
215 #define	HDMI_SAMPLE_RATE_192KHZ		6
216 
217 int msm_hdmi_audio_update(struct hdmi *hdmi);
218 int msm_hdmi_audio_info_setup(struct hdmi *hdmi, bool enabled,
219 	uint32_t num_of_channels, uint32_t channel_allocation,
220 	uint32_t level_shift, bool down_mix);
221 void msm_hdmi_audio_set_sample_rate(struct hdmi *hdmi, int rate);
222 
223 
224 /*
225  * hdmi bridge:
226  */
227 
228 struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi);
229 void msm_hdmi_bridge_destroy(struct drm_bridge *bridge);
230 
231 /*
232  * hdmi connector:
233  */
234 
235 void msm_hdmi_connector_irq(struct drm_connector *connector);
236 struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi);
237 int msm_hdmi_hpd_enable(struct drm_connector *connector);
238 
239 /*
240  * i2c adapter for ddc:
241  */
242 
243 void msm_hdmi_i2c_irq(struct i2c_adapter *i2c);
244 void msm_hdmi_i2c_destroy(struct i2c_adapter *i2c);
245 struct i2c_adapter *msm_hdmi_i2c_init(struct hdmi *hdmi);
246 
247 /*
248  * hdcp
249  */
250 #ifdef CONFIG_DRM_MSM_HDMI_HDCP
251 struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi);
252 void msm_hdmi_hdcp_destroy(struct hdmi *hdmi);
253 void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl);
254 void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl);
255 void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl);
256 #else
257 static inline struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi)
258 {
259 	return ERR_PTR(-ENXIO);
260 }
261 static inline void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) {}
262 static inline void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
263 static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
264 static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {}
265 #endif
266 
267 #endif /* __HDMI_CONNECTOR_H__ */
268