1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 11 #include "dsi_phy.h" 12 #include "dsi.xml.h" 13 #include "dsi_phy_14nm.xml.h" 14 15 #define PHY_14NM_CKLN_IDX 4 16 17 /* 18 * DSI PLL 14nm - clock diagram (eg: DSI0): 19 * 20 * dsi0n1_postdiv_clk 21 * | 22 * | 23 * +----+ | +----+ 24 * dsi0vco_clk ---| n1 |--o--| /8 |-- dsi0pllbyte 25 * +----+ | +----+ 26 * | dsi0n1_postdivby2_clk 27 * | +----+ | 28 * o---| /2 |--o--|\ 29 * | +----+ | \ +----+ 30 * | | |--| n2 |-- dsi0pll 31 * o--------------| / +----+ 32 * |/ 33 */ 34 35 #define POLL_MAX_READS 15 36 #define POLL_TIMEOUT_US 1000 37 38 #define VCO_REF_CLK_RATE 19200000 39 #define VCO_MIN_RATE 1300000000UL 40 #define VCO_MAX_RATE 2600000000UL 41 42 struct dsi_pll_config { 43 u64 vco_current_rate; 44 45 u32 ssc_en; /* SSC enable/disable */ 46 47 /* fixed params */ 48 u32 plllock_cnt; 49 u32 ssc_center; 50 u32 ssc_adj_period; 51 u32 ssc_spread; 52 u32 ssc_freq; 53 54 /* calculated */ 55 u32 dec_start; 56 u32 div_frac_start; 57 u32 ssc_period; 58 u32 ssc_step_size; 59 u32 plllock_cmp; 60 u32 pll_vco_div_ref; 61 u32 pll_vco_count; 62 u32 pll_kvco_div_ref; 63 u32 pll_kvco_count; 64 }; 65 66 struct pll_14nm_cached_state { 67 unsigned long vco_rate; 68 u8 n2postdiv; 69 u8 n1postdiv; 70 }; 71 72 struct dsi_pll_14nm { 73 struct clk_hw clk_hw; 74 75 struct msm_dsi_phy *phy; 76 77 /* protects REG_DSI_14nm_PHY_CMN_CLK_CFG0 register */ 78 spinlock_t postdiv_lock; 79 80 struct pll_14nm_cached_state cached_state; 81 82 struct dsi_pll_14nm *slave; 83 }; 84 85 #define to_pll_14nm(x) container_of(x, struct dsi_pll_14nm, clk_hw) 86 87 /* 88 * Private struct for N1/N2 post-divider clocks. These clocks are similar to 89 * the generic clk_divider class of clocks. The only difference is that it 90 * also sets the slave DSI PLL's post-dividers if in bonded DSI mode 91 */ 92 struct dsi_pll_14nm_postdiv { 93 struct clk_hw hw; 94 95 /* divider params */ 96 u8 shift; 97 u8 width; 98 u8 flags; /* same flags as used by clk_divider struct */ 99 100 struct dsi_pll_14nm *pll; 101 }; 102 103 #define to_pll_14nm_postdiv(_hw) container_of(_hw, struct dsi_pll_14nm_postdiv, hw) 104 105 /* 106 * Global list of private DSI PLL struct pointers. We need this for bonded DSI 107 * mode, where the master PLL's clk_ops needs access the slave's private data 108 */ 109 static struct dsi_pll_14nm *pll_14nm_list[DSI_MAX]; 110 111 static bool pll_14nm_poll_for_ready(struct dsi_pll_14nm *pll_14nm, 112 u32 nb_tries, u32 timeout_us) 113 { 114 bool pll_locked = false, pll_ready = false; 115 void __iomem *base = pll_14nm->phy->pll_base; 116 u32 tries, val; 117 118 tries = nb_tries; 119 while (tries--) { 120 val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); 121 pll_locked = !!(val & BIT(5)); 122 123 if (pll_locked) 124 break; 125 126 udelay(timeout_us); 127 } 128 129 if (!pll_locked) 130 goto out; 131 132 tries = nb_tries; 133 while (tries--) { 134 val = readl(base + REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS); 135 pll_ready = !!(val & BIT(0)); 136 137 if (pll_ready) 138 break; 139 140 udelay(timeout_us); 141 } 142 143 out: 144 DBG("DSI PLL is %slocked, %sready", pll_locked ? "" : "*not* ", pll_ready ? "" : "*not* "); 145 146 return pll_locked && pll_ready; 147 } 148 149 static void dsi_pll_14nm_config_init(struct dsi_pll_config *pconf) 150 { 151 /* fixed input */ 152 pconf->plllock_cnt = 1; 153 154 /* 155 * SSC is enabled by default. We might need DT props for configuring 156 * some SSC params like PPM and center/down spread etc. 157 */ 158 pconf->ssc_en = 1; 159 pconf->ssc_center = 0; /* down spread by default */ 160 pconf->ssc_spread = 5; /* PPM / 1000 */ 161 pconf->ssc_freq = 31500; /* default recommended */ 162 pconf->ssc_adj_period = 37; 163 } 164 165 #define CEIL(x, y) (((x) + ((y) - 1)) / (y)) 166 167 static void pll_14nm_ssc_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 168 { 169 u32 period, ssc_period; 170 u32 ref, rem; 171 u64 step_size; 172 173 DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE); 174 175 ssc_period = pconf->ssc_freq / 500; 176 period = (u32)VCO_REF_CLK_RATE / 1000; 177 ssc_period = CEIL(period, ssc_period); 178 ssc_period -= 1; 179 pconf->ssc_period = ssc_period; 180 181 DBG("ssc freq=%d spread=%d period=%d", pconf->ssc_freq, 182 pconf->ssc_spread, pconf->ssc_period); 183 184 step_size = (u32)pconf->vco_current_rate; 185 ref = VCO_REF_CLK_RATE; 186 ref /= 1000; 187 step_size = div_u64(step_size, ref); 188 step_size <<= 20; 189 step_size = div_u64(step_size, 1000); 190 step_size *= pconf->ssc_spread; 191 step_size = div_u64(step_size, 1000); 192 step_size *= (pconf->ssc_adj_period + 1); 193 194 rem = 0; 195 step_size = div_u64_rem(step_size, ssc_period + 1, &rem); 196 if (rem) 197 step_size++; 198 199 DBG("step_size=%lld", step_size); 200 201 step_size &= 0x0ffff; /* take lower 16 bits */ 202 203 pconf->ssc_step_size = step_size; 204 } 205 206 static void pll_14nm_dec_frac_calc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 207 { 208 u64 multiplier = BIT(20); 209 u64 dec_start_multiple, dec_start, pll_comp_val; 210 u32 duration, div_frac_start; 211 u64 vco_clk_rate = pconf->vco_current_rate; 212 u64 fref = VCO_REF_CLK_RATE; 213 214 DBG("vco_clk_rate=%lld ref_clk_rate=%lld", vco_clk_rate, fref); 215 216 dec_start_multiple = div_u64(vco_clk_rate * multiplier, fref); 217 dec_start = div_u64_rem(dec_start_multiple, multiplier, &div_frac_start); 218 219 pconf->dec_start = (u32)dec_start; 220 pconf->div_frac_start = div_frac_start; 221 222 if (pconf->plllock_cnt == 0) 223 duration = 1024; 224 else if (pconf->plllock_cnt == 1) 225 duration = 256; 226 else if (pconf->plllock_cnt == 2) 227 duration = 128; 228 else 229 duration = 32; 230 231 pll_comp_val = duration * dec_start_multiple; 232 pll_comp_val = div_u64(pll_comp_val, multiplier); 233 do_div(pll_comp_val, 10); 234 235 pconf->plllock_cmp = (u32)pll_comp_val; 236 } 237 238 static u32 pll_14nm_kvco_slop(u32 vrate) 239 { 240 u32 slop = 0; 241 242 if (vrate > VCO_MIN_RATE && vrate <= 1800000000UL) 243 slop = 600; 244 else if (vrate > 1800000000UL && vrate < 2300000000UL) 245 slop = 400; 246 else if (vrate > 2300000000UL && vrate < VCO_MAX_RATE) 247 slop = 280; 248 249 return slop; 250 } 251 252 static void pll_14nm_calc_vco_count(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 253 { 254 u64 vco_clk_rate = pconf->vco_current_rate; 255 u64 fref = VCO_REF_CLK_RATE; 256 u32 vco_measure_time = 5; 257 u32 kvco_measure_time = 5; 258 u64 data; 259 u32 cnt; 260 261 data = fref * vco_measure_time; 262 do_div(data, 1000000); 263 data &= 0x03ff; /* 10 bits */ 264 data -= 2; 265 pconf->pll_vco_div_ref = data; 266 267 data = div_u64(vco_clk_rate, 1000000); /* unit is Mhz */ 268 data *= vco_measure_time; 269 do_div(data, 10); 270 pconf->pll_vco_count = data; 271 272 data = fref * kvco_measure_time; 273 do_div(data, 1000000); 274 data &= 0x03ff; /* 10 bits */ 275 data -= 1; 276 pconf->pll_kvco_div_ref = data; 277 278 cnt = pll_14nm_kvco_slop(vco_clk_rate); 279 cnt *= 2; 280 cnt /= 100; 281 cnt *= kvco_measure_time; 282 pconf->pll_kvco_count = cnt; 283 } 284 285 static void pll_db_commit_ssc(struct dsi_pll_14nm *pll, struct dsi_pll_config *pconf) 286 { 287 void __iomem *base = pll->phy->pll_base; 288 u8 data; 289 290 data = pconf->ssc_adj_period; 291 data &= 0x0ff; 292 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1); 293 data = (pconf->ssc_adj_period >> 8); 294 data &= 0x03; 295 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2); 296 297 data = pconf->ssc_period; 298 data &= 0x0ff; 299 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER1); 300 data = (pconf->ssc_period >> 8); 301 data &= 0x0ff; 302 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_PER2); 303 304 data = pconf->ssc_step_size; 305 data &= 0x0ff; 306 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1); 307 data = (pconf->ssc_step_size >> 8); 308 data &= 0x0ff; 309 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2); 310 311 data = (pconf->ssc_center & 0x01); 312 data <<= 1; 313 data |= 0x01; /* enable */ 314 writel(data, base + REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER); 315 316 wmb(); /* make sure register committed */ 317 } 318 319 static void pll_db_commit_common(struct dsi_pll_14nm *pll, 320 struct dsi_pll_config *pconf) 321 { 322 void __iomem *base = pll->phy->pll_base; 323 u8 data; 324 325 /* confgiure the non frequency dependent pll registers */ 326 data = 0; 327 writel(data, base + REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET); 328 329 writel(1, base + REG_DSI_14nm_PHY_PLL_TXCLK_EN); 330 331 writel(48, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL); 332 /* bandgap_timer */ 333 writel(4 << 3, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2); 334 /* pll_wakeup_timer */ 335 writel(5, base + REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5); 336 337 data = pconf->pll_vco_div_ref & 0xff; 338 writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1); 339 data = (pconf->pll_vco_div_ref >> 8) & 0x3; 340 writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2); 341 342 data = pconf->pll_kvco_div_ref & 0xff; 343 writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1); 344 data = (pconf->pll_kvco_div_ref >> 8) & 0x3; 345 writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2); 346 347 writel(16, base + REG_DSI_14nm_PHY_PLL_PLL_MISC1); 348 349 writel(4, base + REG_DSI_14nm_PHY_PLL_IE_TRIM); 350 351 writel(4, base + REG_DSI_14nm_PHY_PLL_IP_TRIM); 352 353 writel(1 << 3 | 1, base + REG_DSI_14nm_PHY_PLL_CP_SET_CUR); 354 355 writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPCSET); 356 357 writel(0 << 3 | 0, base + REG_DSI_14nm_PHY_PLL_PLL_ICPMSET); 358 359 writel(4 << 3 | 4, base + REG_DSI_14nm_PHY_PLL_PLL_ICP_SET); 360 361 writel(1 << 4 | 11, base + REG_DSI_14nm_PHY_PLL_PLL_LPF1); 362 363 writel(7, base + REG_DSI_14nm_PHY_PLL_IPTAT_TRIM); 364 365 writel(1 << 4 | 2, base + REG_DSI_14nm_PHY_PLL_PLL_CRCTRL); 366 } 367 368 static void pll_14nm_software_reset(struct dsi_pll_14nm *pll_14nm) 369 { 370 void __iomem *cmn_base = pll_14nm->phy->base; 371 372 /* de assert pll start and apply pll sw reset */ 373 374 /* stop pll */ 375 writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); 376 377 /* pll sw reset */ 378 writel(0x20, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1); 379 udelay(10); 380 wmb(); /* make sure register committed */ 381 382 writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1); 383 wmb(); /* make sure register committed */ 384 } 385 386 static void pll_db_commit_14nm(struct dsi_pll_14nm *pll, 387 struct dsi_pll_config *pconf) 388 { 389 void __iomem *base = pll->phy->pll_base; 390 void __iomem *cmn_base = pll->phy->base; 391 u8 data; 392 393 DBG("DSI%d PLL", pll->phy->id); 394 395 writel(0x3c, cmn_base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL); 396 397 pll_db_commit_common(pll, pconf); 398 399 pll_14nm_software_reset(pll); 400 401 /* Use the /2 path in Mux */ 402 writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG1); 403 404 data = 0xff; /* data, clk, pll normal operation */ 405 writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_0); 406 407 /* configure the frequency dependent pll registers */ 408 data = pconf->dec_start; 409 writel(data, base + REG_DSI_14nm_PHY_PLL_DEC_START); 410 411 data = pconf->div_frac_start & 0xff; 412 writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1); 413 data = (pconf->div_frac_start >> 8) & 0xff; 414 writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2); 415 data = (pconf->div_frac_start >> 16) & 0xf; 416 writel(data, base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3); 417 418 data = pconf->plllock_cmp & 0xff; 419 writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1); 420 421 data = (pconf->plllock_cmp >> 8) & 0xff; 422 writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2); 423 424 data = (pconf->plllock_cmp >> 16) & 0x3; 425 writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3); 426 427 data = pconf->plllock_cnt << 1 | 0 << 3; /* plllock_rng */ 428 writel(data, base + REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN); 429 430 data = pconf->pll_vco_count & 0xff; 431 writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT1); 432 data = (pconf->pll_vco_count >> 8) & 0xff; 433 writel(data, base + REG_DSI_14nm_PHY_PLL_VCO_COUNT2); 434 435 data = pconf->pll_kvco_count & 0xff; 436 writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT1); 437 data = (pconf->pll_kvco_count >> 8) & 0x3; 438 writel(data, base + REG_DSI_14nm_PHY_PLL_KVCO_COUNT2); 439 440 /* 441 * High nibble configures the post divider internal to the VCO. It's 442 * fixed to divide by 1 for now. 443 * 444 * 0: divided by 1 445 * 1: divided by 2 446 * 2: divided by 4 447 * 3: divided by 8 448 */ 449 writel(0 << 4 | 3, base + REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV); 450 451 if (pconf->ssc_en) 452 pll_db_commit_ssc(pll, pconf); 453 454 wmb(); /* make sure register committed */ 455 } 456 457 /* 458 * VCO clock Callbacks 459 */ 460 static int dsi_pll_14nm_vco_set_rate(struct clk_hw *hw, unsigned long rate, 461 unsigned long parent_rate) 462 { 463 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 464 struct dsi_pll_config conf; 465 466 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_14nm->phy->id, rate, 467 parent_rate); 468 469 dsi_pll_14nm_config_init(&conf); 470 conf.vco_current_rate = rate; 471 472 pll_14nm_dec_frac_calc(pll_14nm, &conf); 473 474 if (conf.ssc_en) 475 pll_14nm_ssc_calc(pll_14nm, &conf); 476 477 pll_14nm_calc_vco_count(pll_14nm, &conf); 478 479 /* commit the slave DSI PLL registers if we're master. Note that we 480 * don't lock the slave PLL. We just ensure that the PLL/PHY registers 481 * of the master and slave are identical 482 */ 483 if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { 484 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; 485 486 pll_db_commit_14nm(pll_14nm_slave, &conf); 487 } 488 489 pll_db_commit_14nm(pll_14nm, &conf); 490 491 return 0; 492 } 493 494 static unsigned long dsi_pll_14nm_vco_recalc_rate(struct clk_hw *hw, 495 unsigned long parent_rate) 496 { 497 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 498 void __iomem *base = pll_14nm->phy->pll_base; 499 u64 vco_rate, multiplier = BIT(20); 500 u32 div_frac_start; 501 u32 dec_start; 502 u64 ref_clk = parent_rate; 503 504 dec_start = readl(base + REG_DSI_14nm_PHY_PLL_DEC_START); 505 dec_start &= 0x0ff; 506 507 DBG("dec_start = %x", dec_start); 508 509 div_frac_start = (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) 510 & 0xf) << 16; 511 div_frac_start |= (readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2) 512 & 0xff) << 8; 513 div_frac_start |= readl(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1) 514 & 0xff; 515 516 DBG("div_frac_start = %x", div_frac_start); 517 518 vco_rate = ref_clk * dec_start; 519 520 vco_rate += ((ref_clk * div_frac_start) / multiplier); 521 522 /* 523 * Recalculating the rate from dec_start and frac_start doesn't end up 524 * the rate we originally set. Convert the freq to KHz, round it up and 525 * convert it back to MHz. 526 */ 527 vco_rate = DIV_ROUND_UP_ULL(vco_rate, 1000) * 1000; 528 529 DBG("returning vco rate = %lu", (unsigned long)vco_rate); 530 531 return (unsigned long)vco_rate; 532 } 533 534 static int dsi_pll_14nm_vco_prepare(struct clk_hw *hw) 535 { 536 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 537 void __iomem *base = pll_14nm->phy->pll_base; 538 void __iomem *cmn_base = pll_14nm->phy->base; 539 bool locked; 540 541 DBG(""); 542 543 if (unlikely(pll_14nm->phy->pll_on)) 544 return 0; 545 546 if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0) 547 dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE); 548 549 writel(0x10, base + REG_DSI_14nm_PHY_PLL_VREF_CFG1); 550 writel(1, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); 551 552 locked = pll_14nm_poll_for_ready(pll_14nm, POLL_MAX_READS, 553 POLL_TIMEOUT_US); 554 555 if (unlikely(!locked)) { 556 DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, "DSI PLL lock failed\n"); 557 return -EINVAL; 558 } 559 560 DBG("DSI PLL lock success"); 561 pll_14nm->phy->pll_on = true; 562 563 return 0; 564 } 565 566 static void dsi_pll_14nm_vco_unprepare(struct clk_hw *hw) 567 { 568 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 569 void __iomem *cmn_base = pll_14nm->phy->base; 570 571 DBG(""); 572 573 if (unlikely(!pll_14nm->phy->pll_on)) 574 return; 575 576 writel(0, cmn_base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); 577 578 pll_14nm->phy->pll_on = false; 579 } 580 581 static long dsi_pll_14nm_clk_round_rate(struct clk_hw *hw, 582 unsigned long rate, unsigned long *parent_rate) 583 { 584 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(hw); 585 586 if (rate < pll_14nm->phy->cfg->min_pll_rate) 587 return pll_14nm->phy->cfg->min_pll_rate; 588 else if (rate > pll_14nm->phy->cfg->max_pll_rate) 589 return pll_14nm->phy->cfg->max_pll_rate; 590 else 591 return rate; 592 } 593 594 static const struct clk_ops clk_ops_dsi_pll_14nm_vco = { 595 .round_rate = dsi_pll_14nm_clk_round_rate, 596 .set_rate = dsi_pll_14nm_vco_set_rate, 597 .recalc_rate = dsi_pll_14nm_vco_recalc_rate, 598 .prepare = dsi_pll_14nm_vco_prepare, 599 .unprepare = dsi_pll_14nm_vco_unprepare, 600 }; 601 602 /* 603 * N1 and N2 post-divider clock callbacks 604 */ 605 #define div_mask(width) ((1 << (width)) - 1) 606 static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw, 607 unsigned long parent_rate) 608 { 609 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 610 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 611 void __iomem *base = pll_14nm->phy->base; 612 u8 shift = postdiv->shift; 613 u8 width = postdiv->width; 614 u32 val; 615 616 DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, parent_rate); 617 618 val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0) >> shift; 619 val &= div_mask(width); 620 621 return divider_recalc_rate(hw, parent_rate, val, NULL, 622 postdiv->flags, width); 623 } 624 625 static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw, 626 unsigned long rate, 627 unsigned long *prate) 628 { 629 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 630 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 631 632 DBG("DSI%d PLL parent rate=%lu", pll_14nm->phy->id, rate); 633 634 return divider_round_rate(hw, rate, prate, NULL, 635 postdiv->width, 636 postdiv->flags); 637 } 638 639 static int dsi_pll_14nm_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, 640 unsigned long parent_rate) 641 { 642 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); 643 struct dsi_pll_14nm *pll_14nm = postdiv->pll; 644 void __iomem *base = pll_14nm->phy->base; 645 spinlock_t *lock = &pll_14nm->postdiv_lock; 646 u8 shift = postdiv->shift; 647 u8 width = postdiv->width; 648 unsigned int value; 649 unsigned long flags = 0; 650 u32 val; 651 652 DBG("DSI%d PLL parent rate=%lu parent rate %lu", pll_14nm->phy->id, rate, 653 parent_rate); 654 655 value = divider_get_val(rate, parent_rate, NULL, postdiv->width, 656 postdiv->flags); 657 658 spin_lock_irqsave(lock, flags); 659 660 val = readl(base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 661 val &= ~(div_mask(width) << shift); 662 663 val |= value << shift; 664 writel(val, base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 665 666 /* If we're master in bonded DSI mode, then the slave PLL's post-dividers 667 * follow the master's post dividers 668 */ 669 if (pll_14nm->phy->usecase == MSM_DSI_PHY_MASTER) { 670 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; 671 void __iomem *slave_base = pll_14nm_slave->phy->base; 672 673 writel(val, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 674 } 675 676 spin_unlock_irqrestore(lock, flags); 677 678 return 0; 679 } 680 681 static const struct clk_ops clk_ops_dsi_pll_14nm_postdiv = { 682 .recalc_rate = dsi_pll_14nm_postdiv_recalc_rate, 683 .round_rate = dsi_pll_14nm_postdiv_round_rate, 684 .set_rate = dsi_pll_14nm_postdiv_set_rate, 685 }; 686 687 /* 688 * PLL Callbacks 689 */ 690 691 static void dsi_14nm_pll_save_state(struct msm_dsi_phy *phy) 692 { 693 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); 694 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; 695 void __iomem *cmn_base = pll_14nm->phy->base; 696 u32 data; 697 698 data = readl(cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 699 700 cached_state->n1postdiv = data & 0xf; 701 cached_state->n2postdiv = (data >> 4) & 0xf; 702 703 DBG("DSI%d PLL save state %x %x", pll_14nm->phy->id, 704 cached_state->n1postdiv, cached_state->n2postdiv); 705 706 cached_state->vco_rate = clk_hw_get_rate(phy->vco_hw); 707 } 708 709 static int dsi_14nm_pll_restore_state(struct msm_dsi_phy *phy) 710 { 711 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); 712 struct pll_14nm_cached_state *cached_state = &pll_14nm->cached_state; 713 void __iomem *cmn_base = pll_14nm->phy->base; 714 u32 data; 715 int ret; 716 717 ret = dsi_pll_14nm_vco_set_rate(phy->vco_hw, 718 cached_state->vco_rate, 0); 719 if (ret) { 720 DRM_DEV_ERROR(&pll_14nm->phy->pdev->dev, 721 "restore vco rate failed. ret=%d\n", ret); 722 return ret; 723 } 724 725 data = cached_state->n1postdiv | (cached_state->n2postdiv << 4); 726 727 DBG("DSI%d PLL restore state %x %x", pll_14nm->phy->id, 728 cached_state->n1postdiv, cached_state->n2postdiv); 729 730 writel(data, cmn_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 731 732 /* also restore post-dividers for slave DSI PLL */ 733 if (phy->usecase == MSM_DSI_PHY_MASTER) { 734 struct dsi_pll_14nm *pll_14nm_slave = pll_14nm->slave; 735 void __iomem *slave_base = pll_14nm_slave->phy->base; 736 737 writel(data, slave_base + REG_DSI_14nm_PHY_CMN_CLK_CFG0); 738 } 739 740 return 0; 741 } 742 743 static int dsi_14nm_set_usecase(struct msm_dsi_phy *phy) 744 { 745 struct dsi_pll_14nm *pll_14nm = to_pll_14nm(phy->vco_hw); 746 void __iomem *base = phy->pll_base; 747 u32 clkbuflr_en, bandgap = 0; 748 749 switch (phy->usecase) { 750 case MSM_DSI_PHY_STANDALONE: 751 clkbuflr_en = 0x1; 752 break; 753 case MSM_DSI_PHY_MASTER: 754 clkbuflr_en = 0x3; 755 pll_14nm->slave = pll_14nm_list[(pll_14nm->phy->id + 1) % DSI_MAX]; 756 break; 757 case MSM_DSI_PHY_SLAVE: 758 clkbuflr_en = 0x0; 759 bandgap = 0x3; 760 break; 761 default: 762 return -EINVAL; 763 } 764 765 writel(clkbuflr_en, base + REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN); 766 if (bandgap) 767 writel(bandgap, base + REG_DSI_14nm_PHY_PLL_PLL_BANDGAP); 768 769 return 0; 770 } 771 772 static struct clk_hw *pll_14nm_postdiv_register(struct dsi_pll_14nm *pll_14nm, 773 const char *name, 774 const struct clk_hw *parent_hw, 775 unsigned long flags, 776 u8 shift) 777 { 778 struct dsi_pll_14nm_postdiv *pll_postdiv; 779 struct device *dev = &pll_14nm->phy->pdev->dev; 780 struct clk_init_data postdiv_init = { 781 .parent_hws = (const struct clk_hw *[]) { parent_hw }, 782 .num_parents = 1, 783 .name = name, 784 .flags = flags, 785 .ops = &clk_ops_dsi_pll_14nm_postdiv, 786 }; 787 int ret; 788 789 pll_postdiv = devm_kzalloc(dev, sizeof(*pll_postdiv), GFP_KERNEL); 790 if (!pll_postdiv) 791 return ERR_PTR(-ENOMEM); 792 793 pll_postdiv->pll = pll_14nm; 794 pll_postdiv->shift = shift; 795 /* both N1 and N2 postdividers are 4 bits wide */ 796 pll_postdiv->width = 4; 797 /* range of each divider is from 1 to 15 */ 798 pll_postdiv->flags = CLK_DIVIDER_ONE_BASED; 799 pll_postdiv->hw.init = &postdiv_init; 800 801 ret = devm_clk_hw_register(dev, &pll_postdiv->hw); 802 if (ret) 803 return ERR_PTR(ret); 804 805 return &pll_postdiv->hw; 806 } 807 808 static int pll_14nm_register(struct dsi_pll_14nm *pll_14nm, struct clk_hw **provided_clocks) 809 { 810 char clk_name[32]; 811 struct clk_init_data vco_init = { 812 .parent_data = &(const struct clk_parent_data) { 813 .fw_name = "ref", 814 }, 815 .num_parents = 1, 816 .name = clk_name, 817 .flags = CLK_IGNORE_UNUSED, 818 .ops = &clk_ops_dsi_pll_14nm_vco, 819 }; 820 struct device *dev = &pll_14nm->phy->pdev->dev; 821 struct clk_hw *hw, *n1_postdiv, *n1_postdivby2; 822 int ret; 823 824 DBG("DSI%d", pll_14nm->phy->id); 825 826 snprintf(clk_name, sizeof(clk_name), "dsi%dvco_clk", pll_14nm->phy->id); 827 pll_14nm->clk_hw.init = &vco_init; 828 829 ret = devm_clk_hw_register(dev, &pll_14nm->clk_hw); 830 if (ret) 831 return ret; 832 833 snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdiv_clk", pll_14nm->phy->id); 834 835 /* N1 postdiv, bits 0-3 in REG_DSI_14nm_PHY_CMN_CLK_CFG0 */ 836 n1_postdiv = pll_14nm_postdiv_register(pll_14nm, clk_name, 837 &pll_14nm->clk_hw, CLK_SET_RATE_PARENT, 0); 838 if (IS_ERR(n1_postdiv)) 839 return PTR_ERR(n1_postdiv); 840 841 snprintf(clk_name, sizeof(clk_name), "dsi%dpllbyte", pll_14nm->phy->id); 842 843 /* DSI Byte clock = VCO_CLK / N1 / 8 */ 844 hw = devm_clk_hw_register_fixed_factor_parent_hw(dev, clk_name, 845 n1_postdiv, CLK_SET_RATE_PARENT, 1, 8); 846 if (IS_ERR(hw)) 847 return PTR_ERR(hw); 848 849 provided_clocks[DSI_BYTE_PLL_CLK] = hw; 850 851 snprintf(clk_name, sizeof(clk_name), "dsi%dn1_postdivby2_clk", pll_14nm->phy->id); 852 853 /* 854 * Skip the mux for now, force DSICLK_SEL to 1, Add a /2 divider 855 * on the way. Don't let it set parent. 856 */ 857 n1_postdivby2 = devm_clk_hw_register_fixed_factor_parent_hw(dev, 858 clk_name, n1_postdiv, 0, 1, 2); 859 if (IS_ERR(n1_postdivby2)) 860 return PTR_ERR(n1_postdivby2); 861 862 snprintf(clk_name, sizeof(clk_name), "dsi%dpll", pll_14nm->phy->id); 863 864 /* DSI pixel clock = VCO_CLK / N1 / 2 / N2 865 * This is the output of N2 post-divider, bits 4-7 in 866 * REG_DSI_14nm_PHY_CMN_CLK_CFG0. Don't let it set parent. 867 */ 868 hw = pll_14nm_postdiv_register(pll_14nm, clk_name, n1_postdivby2, 869 0, 4); 870 if (IS_ERR(hw)) 871 return PTR_ERR(hw); 872 873 provided_clocks[DSI_PIXEL_PLL_CLK] = hw; 874 875 return 0; 876 } 877 878 static int dsi_pll_14nm_init(struct msm_dsi_phy *phy) 879 { 880 struct platform_device *pdev = phy->pdev; 881 struct dsi_pll_14nm *pll_14nm; 882 int ret; 883 884 if (!pdev) 885 return -ENODEV; 886 887 pll_14nm = devm_kzalloc(&pdev->dev, sizeof(*pll_14nm), GFP_KERNEL); 888 if (!pll_14nm) 889 return -ENOMEM; 890 891 DBG("PLL%d", phy->id); 892 893 pll_14nm_list[phy->id] = pll_14nm; 894 895 spin_lock_init(&pll_14nm->postdiv_lock); 896 897 pll_14nm->phy = phy; 898 899 ret = pll_14nm_register(pll_14nm, phy->provided_clocks->hws); 900 if (ret) { 901 DRM_DEV_ERROR(&pdev->dev, "failed to register PLL: %d\n", ret); 902 return ret; 903 } 904 905 phy->vco_hw = &pll_14nm->clk_hw; 906 907 return 0; 908 } 909 910 static void dsi_14nm_dphy_set_timing(struct msm_dsi_phy *phy, 911 struct msm_dsi_dphy_timing *timing, 912 int lane_idx) 913 { 914 void __iomem *base = phy->lane_base; 915 bool clk_ln = (lane_idx == PHY_14NM_CKLN_IDX); 916 u32 zero = clk_ln ? timing->clk_zero : timing->hs_zero; 917 u32 prepare = clk_ln ? timing->clk_prepare : timing->hs_prepare; 918 u32 trail = clk_ln ? timing->clk_trail : timing->hs_trail; 919 u32 rqst = clk_ln ? timing->hs_rqst_ckln : timing->hs_rqst; 920 u32 prep_dly = clk_ln ? timing->hs_prep_dly_ckln : timing->hs_prep_dly; 921 u32 halfbyte_en = clk_ln ? timing->hs_halfbyte_en_ckln : 922 timing->hs_halfbyte_en; 923 924 writel(DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), 925 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(lane_idx)); 926 writel(DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(zero), 927 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(lane_idx)); 928 writel(DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(prepare), 929 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(lane_idx)); 930 writel(DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(trail), 931 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(lane_idx)); 932 writel(DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(rqst), 933 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(lane_idx)); 934 writel(DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(prep_dly), 935 base + REG_DSI_14nm_PHY_LN_CFG0(lane_idx)); 936 writel(halfbyte_en ? DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN : 0, 937 base + REG_DSI_14nm_PHY_LN_CFG1(lane_idx)); 938 writel(DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(timing->ta_go) | 939 DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(timing->ta_sure), 940 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(lane_idx)); 941 writel(DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(timing->ta_get), 942 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(lane_idx)); 943 writel(DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(0xa0), 944 base + REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(lane_idx)); 945 } 946 947 static int dsi_14nm_phy_enable(struct msm_dsi_phy *phy, 948 struct msm_dsi_phy_clk_request *clk_req) 949 { 950 struct msm_dsi_dphy_timing *timing = &phy->timing; 951 u32 data; 952 int i; 953 int ret; 954 void __iomem *base = phy->base; 955 void __iomem *lane_base = phy->lane_base; 956 u32 glbl_test_ctrl; 957 958 if (msm_dsi_dphy_timing_calc_v2(timing, clk_req)) { 959 DRM_DEV_ERROR(&phy->pdev->dev, 960 "%s: D-PHY timing calculation failed\n", 961 __func__); 962 return -EINVAL; 963 } 964 965 data = 0x1c; 966 if (phy->usecase != MSM_DSI_PHY_STANDALONE) 967 data |= DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(32); 968 writel(data, base + REG_DSI_14nm_PHY_CMN_LDO_CNTRL); 969 970 writel(0x1, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); 971 972 /* 4 data lanes + 1 clk lane configuration */ 973 for (i = 0; i < 5; i++) { 974 writel(0x1d, lane_base + REG_DSI_14nm_PHY_LN_VREG_CNTRL(i)); 975 976 writel(0xff, lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(i)); 977 writel(i == PHY_14NM_CKLN_IDX ? 0x00 : 0x06, 978 lane_base + REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(i)); 979 980 writel(i == PHY_14NM_CKLN_IDX ? 0x8f : 0x0f, 981 lane_base + REG_DSI_14nm_PHY_LN_CFG3(i)); 982 writel(0x10, lane_base + REG_DSI_14nm_PHY_LN_CFG2(i)); 983 writel(0, lane_base + REG_DSI_14nm_PHY_LN_TEST_DATAPATH(i)); 984 writel(0x88, lane_base + REG_DSI_14nm_PHY_LN_TEST_STR(i)); 985 986 dsi_14nm_dphy_set_timing(phy, timing, i); 987 } 988 989 /* Make sure PLL is not start */ 990 writel(0x00, base + REG_DSI_14nm_PHY_CMN_PLL_CNTRL); 991 992 wmb(); /* make sure everything is written before reset and enable */ 993 994 /* reset digital block */ 995 writel(0x80, base + REG_DSI_14nm_PHY_CMN_CTRL_1); 996 wmb(); /* ensure reset is asserted */ 997 udelay(100); 998 writel(0x00, base + REG_DSI_14nm_PHY_CMN_CTRL_1); 999 1000 glbl_test_ctrl = readl(base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); 1001 if (phy->id == DSI_1 && phy->usecase == MSM_DSI_PHY_SLAVE) 1002 glbl_test_ctrl |= DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; 1003 else 1004 glbl_test_ctrl &= ~DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL; 1005 writel(glbl_test_ctrl, base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); 1006 ret = dsi_14nm_set_usecase(phy); 1007 if (ret) { 1008 DRM_DEV_ERROR(&phy->pdev->dev, "%s: set pll usecase failed, %d\n", 1009 __func__, ret); 1010 return ret; 1011 } 1012 1013 /* Remove power down from PLL and all lanes */ 1014 writel(0xff, base + REG_DSI_14nm_PHY_CMN_CTRL_0); 1015 1016 return 0; 1017 } 1018 1019 static void dsi_14nm_phy_disable(struct msm_dsi_phy *phy) 1020 { 1021 writel(0, phy->base + REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL); 1022 writel(0, phy->base + REG_DSI_14nm_PHY_CMN_CTRL_0); 1023 1024 /* ensure that the phy is completely disabled */ 1025 wmb(); 1026 } 1027 1028 static const struct regulator_bulk_data dsi_phy_14nm_17mA_regulators[] = { 1029 { .supply = "vcca", .init_load_uA = 17000 }, 1030 }; 1031 1032 static const struct regulator_bulk_data dsi_phy_14nm_73p4mA_regulators[] = { 1033 { .supply = "vcca", .init_load_uA = 73400 }, 1034 }; 1035 1036 static const struct regulator_bulk_data dsi_phy_14nm_36mA_regulators[] = { 1037 { .supply = "vdda", .init_load_uA = 36000 }, 1038 }; 1039 1040 const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { 1041 .has_phy_lane = true, 1042 .regulator_data = dsi_phy_14nm_17mA_regulators, 1043 .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators), 1044 .ops = { 1045 .enable = dsi_14nm_phy_enable, 1046 .disable = dsi_14nm_phy_disable, 1047 .pll_init = dsi_pll_14nm_init, 1048 .save_pll_state = dsi_14nm_pll_save_state, 1049 .restore_pll_state = dsi_14nm_pll_restore_state, 1050 }, 1051 .min_pll_rate = VCO_MIN_RATE, 1052 .max_pll_rate = VCO_MAX_RATE, 1053 .io_start = { 0x994400, 0x996400 }, 1054 .num_dsi_phy = 2, 1055 }; 1056 1057 const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { 1058 .has_phy_lane = true, 1059 .regulator_data = dsi_phy_14nm_73p4mA_regulators, 1060 .num_regulators = ARRAY_SIZE(dsi_phy_14nm_73p4mA_regulators), 1061 .ops = { 1062 .enable = dsi_14nm_phy_enable, 1063 .disable = dsi_14nm_phy_disable, 1064 .pll_init = dsi_pll_14nm_init, 1065 .save_pll_state = dsi_14nm_pll_save_state, 1066 .restore_pll_state = dsi_14nm_pll_restore_state, 1067 }, 1068 .min_pll_rate = VCO_MIN_RATE, 1069 .max_pll_rate = VCO_MAX_RATE, 1070 .io_start = { 0xc994400, 0xc996400 }, 1071 .num_dsi_phy = 2, 1072 }; 1073 1074 const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { 1075 .has_phy_lane = true, 1076 .regulator_data = dsi_phy_14nm_17mA_regulators, 1077 .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators), 1078 .ops = { 1079 .enable = dsi_14nm_phy_enable, 1080 .disable = dsi_14nm_phy_disable, 1081 .pll_init = dsi_pll_14nm_init, 1082 .save_pll_state = dsi_14nm_pll_save_state, 1083 .restore_pll_state = dsi_14nm_pll_restore_state, 1084 }, 1085 .min_pll_rate = VCO_MIN_RATE, 1086 .max_pll_rate = VCO_MAX_RATE, 1087 .io_start = { 0x1a94400, 0x1a96400 }, 1088 .num_dsi_phy = 2, 1089 }; 1090 1091 const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = { 1092 .has_phy_lane = true, 1093 .ops = { 1094 .enable = dsi_14nm_phy_enable, 1095 .disable = dsi_14nm_phy_disable, 1096 .pll_init = dsi_pll_14nm_init, 1097 .save_pll_state = dsi_14nm_pll_save_state, 1098 .restore_pll_state = dsi_14nm_pll_restore_state, 1099 }, 1100 .min_pll_rate = VCO_MIN_RATE, 1101 .max_pll_rate = VCO_MAX_RATE, 1102 .io_start = { 0x5e94400 }, 1103 .num_dsi_phy = 1, 1104 }; 1105 1106 const struct msm_dsi_phy_cfg dsi_phy_14nm_6150_cfgs = { 1107 .has_phy_lane = true, 1108 .regulator_data = dsi_phy_14nm_36mA_regulators, 1109 .num_regulators = ARRAY_SIZE(dsi_phy_14nm_36mA_regulators), 1110 .ops = { 1111 .enable = dsi_14nm_phy_enable, 1112 .disable = dsi_14nm_phy_disable, 1113 .pll_init = dsi_pll_14nm_init, 1114 .save_pll_state = dsi_14nm_pll_save_state, 1115 .restore_pll_state = dsi_14nm_pll_restore_state, 1116 }, 1117 .min_pll_rate = VCO_MIN_RATE, 1118 .max_pll_rate = VCO_MAX_RATE, 1119 .io_start = { 0xae94400 }, 1120 .num_dsi_phy = 1, 1121 }; 1122