1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of.h> 13 #include <linux/of_graph.h> 14 #include <linux/of_irq.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/pm_opp.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spinlock.h> 20 21 #include <video/mipi_display.h> 22 23 #include <drm/display/drm_dsc_helper.h> 24 #include <drm/drm_of.h> 25 26 #include "dsi.h" 27 #include "dsi.xml.h" 28 #include "sfpb.xml.h" 29 #include "dsi_cfg.h" 30 #include "msm_dsc_helper.h" 31 #include "msm_kms.h" 32 #include "msm_gem.h" 33 #include "phy/dsi_phy.h" 34 35 #define DSI_RESET_TOGGLE_DELAY_MS 20 36 37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 38 39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 40 { 41 u32 ver; 42 43 if (!major || !minor) 44 return -EINVAL; 45 46 /* 47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 48 * makes all other registers 4-byte shifted down. 49 * 50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 51 * older, we read the DSI_VERSION register without any shift(offset 52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 53 * the case of DSI6G, this has to be zero (the offset points to a 54 * scratch register which we never touch) 55 */ 56 57 ver = readl(base + REG_DSI_VERSION); 58 if (ver) { 59 /* older dsi host, there is no register shift */ 60 ver = FIELD(ver, DSI_VERSION_MAJOR); 61 if (ver <= MSM_DSI_VER_MAJOR_V2) { 62 /* old versions */ 63 *major = ver; 64 *minor = 0; 65 return 0; 66 } else { 67 return -EINVAL; 68 } 69 } else { 70 /* 71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 72 * registers are shifted down, read DSI_VERSION again with 73 * the shifted offset 74 */ 75 ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 76 ver = FIELD(ver, DSI_VERSION_MAJOR); 77 if (ver == MSM_DSI_VER_MAJOR_6G) { 78 /* 6G version */ 79 *major = ver; 80 *minor = readl(base + REG_DSI_6G_HW_VERSION); 81 return 0; 82 } else { 83 return -EINVAL; 84 } 85 } 86 } 87 88 #define DSI_ERR_STATE_ACK 0x0000 89 #define DSI_ERR_STATE_TIMEOUT 0x0001 90 #define DSI_ERR_STATE_DLN0_PHY 0x0002 91 #define DSI_ERR_STATE_FIFO 0x0004 92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 95 96 #define DSI_CLK_CTRL_ENABLE_CLKS \ 97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 101 102 struct msm_dsi_host { 103 struct mipi_dsi_host base; 104 105 struct platform_device *pdev; 106 struct drm_device *dev; 107 108 int id; 109 110 void __iomem *ctrl_base; 111 phys_addr_t ctrl_size; 112 struct regulator_bulk_data *supplies; 113 114 int num_bus_clks; 115 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 116 117 struct clk *byte_clk; 118 struct clk *esc_clk; 119 struct clk *pixel_clk; 120 struct clk *byte_intf_clk; 121 122 unsigned long byte_clk_rate; 123 unsigned long byte_intf_clk_rate; 124 unsigned long pixel_clk_rate; 125 unsigned long esc_clk_rate; 126 127 /* DSI v2 specific clocks */ 128 struct clk *src_clk; 129 130 unsigned long src_clk_rate; 131 132 const struct msm_dsi_cfg_handler *cfg_hnd; 133 134 struct completion dma_comp; 135 struct completion video_comp; 136 struct mutex dev_mutex; 137 struct mutex cmd_mutex; 138 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 139 140 u32 err_work_state; 141 struct work_struct err_work; 142 struct workqueue_struct *workqueue; 143 144 /* DSI 6G TX buffer*/ 145 struct drm_gem_object *tx_gem_obj; 146 struct msm_gem_address_space *aspace; 147 148 /* DSI v2 TX buffer */ 149 void *tx_buf; 150 dma_addr_t tx_buf_paddr; 151 152 int tx_size; 153 154 u8 *rx_buf; 155 156 struct regmap *sfpb; 157 158 struct drm_display_mode *mode; 159 struct drm_dsc_config *dsc; 160 161 /* connected device info */ 162 unsigned int channel; 163 unsigned int lanes; 164 enum mipi_dsi_pixel_format format; 165 unsigned long mode_flags; 166 167 /* lane data parsed via DT */ 168 int dlane_swap; 169 int num_data_lanes; 170 171 /* from phy DT */ 172 bool cphy_mode; 173 174 u32 dma_cmd_ctrl_restore; 175 176 bool registered; 177 bool power_on; 178 bool enabled; 179 int irq; 180 }; 181 182 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 183 { 184 return readl(msm_host->ctrl_base + reg); 185 } 186 187 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 188 { 189 writel(data, msm_host->ctrl_base + reg); 190 } 191 192 static const struct msm_dsi_cfg_handler * 193 dsi_get_config(struct msm_dsi_host *msm_host) 194 { 195 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 196 struct device *dev = &msm_host->pdev->dev; 197 struct clk *ahb_clk; 198 int ret; 199 u32 major = 0, minor = 0; 200 201 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 202 if (IS_ERR(ahb_clk)) { 203 dev_err_probe(dev, PTR_ERR(ahb_clk), "%s: cannot get interface clock\n", 204 __func__); 205 goto exit; 206 } 207 208 pm_runtime_get_sync(dev); 209 210 ret = clk_prepare_enable(ahb_clk); 211 if (ret) { 212 dev_err_probe(dev, ret, "%s: unable to enable ahb_clk\n", __func__); 213 goto runtime_put; 214 } 215 216 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 217 if (ret) { 218 dev_err_probe(dev, ret, "%s: Invalid version\n", __func__); 219 goto disable_clks; 220 } 221 222 cfg_hnd = msm_dsi_cfg_get(major, minor); 223 224 DBG("%s: Version %x:%x\n", __func__, major, minor); 225 226 disable_clks: 227 clk_disable_unprepare(ahb_clk); 228 runtime_put: 229 pm_runtime_put_sync(dev); 230 exit: 231 return cfg_hnd; 232 } 233 234 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 235 { 236 return container_of(host, struct msm_dsi_host, base); 237 } 238 239 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 240 { 241 struct platform_device *pdev = msm_host->pdev; 242 int ret = 0; 243 244 msm_host->src_clk = msm_clk_get(pdev, "src"); 245 246 if (IS_ERR(msm_host->src_clk)) { 247 ret = PTR_ERR(msm_host->src_clk); 248 pr_err("%s: can't find src clock. ret=%d\n", 249 __func__, ret); 250 msm_host->src_clk = NULL; 251 return ret; 252 } 253 254 return ret; 255 } 256 257 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 258 { 259 struct platform_device *pdev = msm_host->pdev; 260 int ret = 0; 261 262 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 263 if (IS_ERR(msm_host->byte_intf_clk)) { 264 ret = PTR_ERR(msm_host->byte_intf_clk); 265 pr_err("%s: can't find byte_intf clock. ret=%d\n", 266 __func__, ret); 267 } 268 269 return ret; 270 } 271 272 static int dsi_clk_init(struct msm_dsi_host *msm_host) 273 { 274 struct platform_device *pdev = msm_host->pdev; 275 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 276 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 277 int i, ret = 0; 278 279 /* get bus clocks */ 280 for (i = 0; i < cfg->num_bus_clks; i++) 281 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 282 msm_host->num_bus_clks = cfg->num_bus_clks; 283 284 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 285 if (ret < 0) 286 return dev_err_probe(&pdev->dev, ret, "Unable to get clocks\n"); 287 288 /* get link and source clocks */ 289 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 290 if (IS_ERR(msm_host->byte_clk)) 291 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->byte_clk), 292 "%s: can't find dsi_byte clock\n", 293 __func__); 294 295 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 296 if (IS_ERR(msm_host->pixel_clk)) 297 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->pixel_clk), 298 "%s: can't find dsi_pixel clock\n", 299 __func__); 300 301 msm_host->esc_clk = msm_clk_get(pdev, "core"); 302 if (IS_ERR(msm_host->esc_clk)) 303 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->esc_clk), 304 "%s: can't find dsi_esc clock\n", 305 __func__); 306 307 if (cfg_hnd->ops->clk_init_ver) 308 ret = cfg_hnd->ops->clk_init_ver(msm_host); 309 310 return ret; 311 } 312 313 int msm_dsi_runtime_suspend(struct device *dev) 314 { 315 struct platform_device *pdev = to_platform_device(dev); 316 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 317 struct mipi_dsi_host *host = msm_dsi->host; 318 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 319 320 if (!msm_host->cfg_hnd) 321 return 0; 322 323 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 324 325 return 0; 326 } 327 328 int msm_dsi_runtime_resume(struct device *dev) 329 { 330 struct platform_device *pdev = to_platform_device(dev); 331 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 332 struct mipi_dsi_host *host = msm_dsi->host; 333 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 334 335 if (!msm_host->cfg_hnd) 336 return 0; 337 338 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 339 } 340 341 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 342 { 343 int ret; 344 345 DBG("Set clk rates: pclk=%lu, byteclk=%lu", 346 msm_host->pixel_clk_rate, msm_host->byte_clk_rate); 347 348 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 349 msm_host->byte_clk_rate); 350 if (ret) { 351 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 352 return ret; 353 } 354 355 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 356 if (ret) { 357 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 358 return ret; 359 } 360 361 if (msm_host->byte_intf_clk) { 362 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); 363 if (ret) { 364 pr_err("%s: Failed to set rate byte intf clk, %d\n", 365 __func__, ret); 366 return ret; 367 } 368 } 369 370 return 0; 371 } 372 373 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 374 { 375 int ret; 376 377 ret = clk_prepare_enable(msm_host->esc_clk); 378 if (ret) { 379 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 380 goto error; 381 } 382 383 ret = clk_prepare_enable(msm_host->byte_clk); 384 if (ret) { 385 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 386 goto byte_clk_err; 387 } 388 389 ret = clk_prepare_enable(msm_host->pixel_clk); 390 if (ret) { 391 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 392 goto pixel_clk_err; 393 } 394 395 ret = clk_prepare_enable(msm_host->byte_intf_clk); 396 if (ret) { 397 pr_err("%s: Failed to enable byte intf clk\n", 398 __func__); 399 goto byte_intf_clk_err; 400 } 401 402 return 0; 403 404 byte_intf_clk_err: 405 clk_disable_unprepare(msm_host->pixel_clk); 406 pixel_clk_err: 407 clk_disable_unprepare(msm_host->byte_clk); 408 byte_clk_err: 409 clk_disable_unprepare(msm_host->esc_clk); 410 error: 411 return ret; 412 } 413 414 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 415 { 416 int ret; 417 418 DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 419 msm_host->pixel_clk_rate, msm_host->byte_clk_rate, 420 msm_host->esc_clk_rate, msm_host->src_clk_rate); 421 422 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 423 if (ret) { 424 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 425 return ret; 426 } 427 428 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 429 if (ret) { 430 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 431 return ret; 432 } 433 434 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 435 if (ret) { 436 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 437 return ret; 438 } 439 440 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 441 if (ret) { 442 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 443 return ret; 444 } 445 446 return 0; 447 } 448 449 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 450 { 451 int ret; 452 453 ret = clk_prepare_enable(msm_host->byte_clk); 454 if (ret) { 455 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 456 goto error; 457 } 458 459 ret = clk_prepare_enable(msm_host->esc_clk); 460 if (ret) { 461 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 462 goto esc_clk_err; 463 } 464 465 ret = clk_prepare_enable(msm_host->src_clk); 466 if (ret) { 467 pr_err("%s: Failed to enable dsi src clk\n", __func__); 468 goto src_clk_err; 469 } 470 471 ret = clk_prepare_enable(msm_host->pixel_clk); 472 if (ret) { 473 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 474 goto pixel_clk_err; 475 } 476 477 return 0; 478 479 pixel_clk_err: 480 clk_disable_unprepare(msm_host->src_clk); 481 src_clk_err: 482 clk_disable_unprepare(msm_host->esc_clk); 483 esc_clk_err: 484 clk_disable_unprepare(msm_host->byte_clk); 485 error: 486 return ret; 487 } 488 489 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 490 { 491 /* Drop the performance state vote */ 492 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 493 clk_disable_unprepare(msm_host->esc_clk); 494 clk_disable_unprepare(msm_host->pixel_clk); 495 clk_disable_unprepare(msm_host->byte_intf_clk); 496 clk_disable_unprepare(msm_host->byte_clk); 497 } 498 499 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 500 { 501 clk_disable_unprepare(msm_host->pixel_clk); 502 clk_disable_unprepare(msm_host->src_clk); 503 clk_disable_unprepare(msm_host->esc_clk); 504 clk_disable_unprepare(msm_host->byte_clk); 505 } 506 507 /** 508 * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case 509 * @mode: The selected mode for the DSI output 510 * @dsc: DRM DSC configuration for this DSI output 511 * 512 * Adjust the pclk rate by calculating a new hdisplay proportional to 513 * the compression ratio such that: 514 * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp 515 * 516 * Porches do not need to be adjusted: 517 * - For VIDEO mode they are not compressed by DSC and are passed as is. 518 * - For CMD mode there are no actual porches. Instead these fields 519 * currently represent the overhead to the image data transfer. As such, they 520 * are calculated for the final mode parameters (after the compression) and 521 * are not to be adjusted too. 522 * 523 * FIXME: Reconsider this if/when CMD mode handling is rewritten to use 524 * transfer time and data overhead as a starting point of the calculations. 525 */ 526 static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, 527 const struct drm_dsc_config *dsc) 528 { 529 int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc), 530 dsc->bits_per_component * 3); 531 532 int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; 533 534 return mult_frac(mode->clock * 1000u, new_htotal, mode->htotal); 535 } 536 537 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, 538 const struct drm_dsc_config *dsc, bool is_bonded_dsi) 539 { 540 unsigned long pclk_rate; 541 542 pclk_rate = mode->clock * 1000u; 543 544 if (dsc) 545 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc); 546 547 /* 548 * For bonded DSI mode, the current DRM mode has the complete width of the 549 * panel. Since, the complete panel is driven by two DSI controllers, 550 * the clock rates have to be split between the two dsi controllers. 551 * Adjust the byte and pixel clock rates for each dsi host accordingly. 552 */ 553 if (is_bonded_dsi) 554 pclk_rate /= 2; 555 556 return pclk_rate; 557 } 558 559 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 560 const struct drm_display_mode *mode) 561 { 562 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 563 u8 lanes = msm_host->lanes; 564 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 565 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); 566 unsigned long pclk_bpp; 567 568 if (lanes == 0) { 569 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 570 lanes = 1; 571 } 572 573 /* CPHY "byte_clk" is in units of 16 bits */ 574 if (msm_host->cphy_mode) 575 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); 576 else 577 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); 578 579 return pclk_bpp; 580 } 581 582 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 583 { 584 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); 585 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 586 msm_host->mode); 587 588 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 589 msm_host->byte_clk_rate); 590 } 591 592 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 593 { 594 if (!msm_host->mode) { 595 pr_err("%s: mode not set\n", __func__); 596 return -EINVAL; 597 } 598 599 dsi_calc_pclk(msm_host, is_bonded_dsi); 600 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 601 return 0; 602 } 603 604 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 605 { 606 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 607 unsigned int esc_mhz, esc_div; 608 unsigned long byte_mhz; 609 610 dsi_calc_pclk(msm_host, is_bonded_dsi); 611 612 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); 613 614 /* 615 * esc clock is byte clock followed by a 4 bit divider, 616 * we need to find an escape clock frequency within the 617 * mipi DSI spec range within the maximum divider limit 618 * We iterate here between an escape clock frequencey 619 * between 20 Mhz to 5 Mhz and pick up the first one 620 * that can be supported by our divider 621 */ 622 623 byte_mhz = msm_host->byte_clk_rate / 1000000; 624 625 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 626 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 627 628 /* 629 * TODO: Ideally, we shouldn't know what sort of divider 630 * is available in mmss_cc, we're just assuming that 631 * it'll always be a 4 bit divider. Need to come up with 632 * a better way here. 633 */ 634 if (esc_div >= 1 && esc_div <= 16) 635 break; 636 } 637 638 if (esc_mhz < 5) 639 return -EINVAL; 640 641 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 642 643 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 644 msm_host->src_clk_rate); 645 646 return 0; 647 } 648 649 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 650 { 651 u32 intr; 652 unsigned long flags; 653 654 spin_lock_irqsave(&msm_host->intr_lock, flags); 655 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 656 657 if (enable) 658 intr |= mask; 659 else 660 intr &= ~mask; 661 662 DBG("intr=%x enable=%d", intr, enable); 663 664 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 665 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 666 } 667 668 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 669 { 670 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 671 return BURST_MODE; 672 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 673 return NON_BURST_SYNCH_PULSE; 674 675 return NON_BURST_SYNCH_EVENT; 676 } 677 678 static inline enum dsi_vid_dst_format 679 dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 680 { 681 switch (mipi_fmt) { 682 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 683 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 684 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 685 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 686 default: return VID_DST_FORMAT_RGB888; 687 } 688 } 689 690 static inline enum dsi_cmd_dst_format 691 dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 692 { 693 switch (mipi_fmt) { 694 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 695 case MIPI_DSI_FMT_RGB666_PACKED: 696 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 697 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 698 default: return CMD_DST_FORMAT_RGB888; 699 } 700 } 701 702 static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) 703 { 704 dsi_write(msm_host, REG_DSI_CTRL, 0); 705 } 706 707 bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host) 708 { 709 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 710 711 return msm_host->dsc && 712 (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && 713 msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0); 714 } 715 716 static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, 717 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 718 { 719 u32 flags = msm_host->mode_flags; 720 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 721 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 722 u32 data = 0, lane_ctrl = 0; 723 724 if (flags & MIPI_DSI_MODE_VIDEO) { 725 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 726 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 727 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 728 data |= DSI_VID_CFG0_HFP_POWER_STOP; 729 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 730 data |= DSI_VID_CFG0_HBP_POWER_STOP; 731 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 732 data |= DSI_VID_CFG0_HSA_POWER_STOP; 733 /* Always set low power stop mode for BLLP 734 * to let command engine send packets 735 */ 736 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 737 DSI_VID_CFG0_BLLP_POWER_STOP; 738 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 739 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 740 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 741 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 742 data |= DSI_VID_CFG0_DATABUS_WIDEN; 743 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 744 745 /* Do not swap RGB colors */ 746 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 747 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 748 } else { 749 /* Do not swap RGB colors */ 750 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 751 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 752 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 753 754 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 755 DSI_CMD_CFG1_WR_MEM_CONTINUE( 756 MIPI_DCS_WRITE_MEMORY_CONTINUE); 757 /* Always insert DCS command */ 758 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 759 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 760 761 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 762 data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); 763 764 if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) 765 data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; 766 767 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 768 data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; 769 770 dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); 771 } 772 } 773 774 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 775 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 776 DSI_CMD_DMA_CTRL_LOW_POWER); 777 778 data = 0; 779 /* Always assume dedicated TE pin */ 780 data |= DSI_TRIG_CTRL_TE; 781 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 782 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 783 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 784 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 785 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 786 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 787 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 788 789 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 790 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 791 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 792 793 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 794 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 795 phy_shared_timings->clk_pre_inc_by_2) 796 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 797 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 798 799 data = 0; 800 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 801 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 802 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 803 804 /* allow only ack-err-status to generate interrupt */ 805 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 806 807 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 808 809 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 810 811 data = DSI_CTRL_CLK_EN; 812 813 DBG("lane number=%d", msm_host->lanes); 814 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 815 816 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 817 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 818 819 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 820 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 821 822 if (msm_dsi_phy_set_continuous_clock(phy, true)) 823 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 824 825 dsi_write(msm_host, REG_DSI_LANE_CTRL, 826 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 827 } 828 829 data |= DSI_CTRL_ENABLE; 830 831 dsi_write(msm_host, REG_DSI_CTRL, data); 832 833 if (msm_host->cphy_mode) 834 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 835 } 836 837 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode) 838 { 839 struct drm_dsc_config *dsc = msm_host->dsc; 840 u32 reg, reg_ctrl, reg_ctrl2; 841 u32 slice_per_intf, total_bytes_per_intf; 842 u32 pkt_per_line; 843 u32 eol_byte_num; 844 u32 bytes_per_pkt; 845 846 /* first calculate dsc parameters and then program 847 * compress mode registers 848 */ 849 slice_per_intf = dsc->slice_count; 850 851 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 852 bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ 853 854 eol_byte_num = total_bytes_per_intf % 3; 855 856 /* 857 * Typically, pkt_per_line = slice_per_intf * slice_per_pkt. 858 * 859 * Since the current driver only supports slice_per_pkt = 1, 860 * pkt_per_line will be equal to slice per intf for now. 861 */ 862 pkt_per_line = slice_per_intf; 863 864 if (is_cmd_mode) /* packet data type */ 865 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 866 else 867 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 868 869 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 870 * registers have similar offsets, so for below common code use 871 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 872 * 873 * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) 874 */ 875 if (pkt_per_line > 4) 876 drm_warn_once(msm_host->dev, "pkt_per_line too big"); 877 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 878 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 879 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 880 881 if (is_cmd_mode) { 882 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 883 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 884 885 reg_ctrl &= ~0xffff; 886 reg_ctrl |= reg; 887 888 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 889 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 890 891 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 892 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 893 } else { 894 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); 895 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 896 } 897 } 898 899 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 900 { 901 struct drm_display_mode *mode = msm_host->mode; 902 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 903 u32 h_total = mode->htotal; 904 u32 v_total = mode->vtotal; 905 u32 hs_end = mode->hsync_end - mode->hsync_start; 906 u32 vs_end = mode->vsync_end - mode->vsync_start; 907 u32 ha_start = h_total - mode->hsync_start; 908 u32 ha_end = ha_start + mode->hdisplay; 909 u32 va_start = v_total - mode->vsync_start; 910 u32 va_end = va_start + mode->vdisplay; 911 u32 hdisplay = mode->hdisplay; 912 u32 wc; 913 int ret; 914 bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base); 915 916 DBG(""); 917 918 /* 919 * For bonded DSI mode, the current DRM mode has 920 * the complete width of the panel. Since, the complete 921 * panel is driven by two DSI controllers, the horizontal 922 * timings have to be split between the two dsi controllers. 923 * Adjust the DSI host timing values accordingly. 924 */ 925 if (is_bonded_dsi) { 926 h_total /= 2; 927 hs_end /= 2; 928 ha_start /= 2; 929 ha_end /= 2; 930 hdisplay /= 2; 931 } 932 933 if (msm_host->dsc) { 934 struct drm_dsc_config *dsc = msm_host->dsc; 935 u32 bytes_per_pclk; 936 937 /* update dsc params with timing params */ 938 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 939 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 940 mode->hdisplay, mode->vdisplay); 941 return; 942 } 943 944 dsc->pic_width = mode->hdisplay; 945 dsc->pic_height = mode->vdisplay; 946 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 947 948 /* we do the calculations for dsc parameters here so that 949 * panel can use these parameters 950 */ 951 ret = dsi_populate_dsc_params(msm_host, dsc); 952 if (ret) 953 return; 954 955 /* 956 * DPU sends 3 bytes per pclk cycle to DSI. If widebus is 957 * enabled, bus width is extended to 6 bytes. 958 * 959 * Calculate the number of pclks needed to transmit one line of 960 * the compressed data. 961 962 * The back/font porch and pulse width are kept intact. For 963 * VIDEO mode they represent timing parameters rather than 964 * actual data transfer, see the documentation for 965 * dsi_adjust_pclk_for_compression(). For CMD mode they are 966 * unused anyway. 967 */ 968 h_total -= hdisplay; 969 if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 970 bytes_per_pclk = 6; 971 else 972 bytes_per_pclk = 3; 973 974 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk); 975 976 h_total += hdisplay; 977 ha_end = ha_start + hdisplay; 978 } 979 980 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 981 if (msm_host->dsc) 982 dsi_update_dsc_timing(msm_host, false); 983 984 dsi_write(msm_host, REG_DSI_ACTIVE_H, 985 DSI_ACTIVE_H_START(ha_start) | 986 DSI_ACTIVE_H_END(ha_end)); 987 dsi_write(msm_host, REG_DSI_ACTIVE_V, 988 DSI_ACTIVE_V_START(va_start) | 989 DSI_ACTIVE_V_END(va_end)); 990 dsi_write(msm_host, REG_DSI_TOTAL, 991 DSI_TOTAL_H_TOTAL(h_total - 1) | 992 DSI_TOTAL_V_TOTAL(v_total - 1)); 993 994 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 995 DSI_ACTIVE_HSYNC_START(hs_start) | 996 DSI_ACTIVE_HSYNC_END(hs_end)); 997 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 998 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 999 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1000 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1001 } else { /* command mode */ 1002 if (msm_host->dsc) 1003 dsi_update_dsc_timing(msm_host, true); 1004 1005 /* image data and 1 byte write_memory_start cmd */ 1006 if (!msm_host->dsc) 1007 wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; 1008 else 1009 /* 1010 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. 1011 * Currently, the driver only supports default value of slice_per_pkt = 1 1012 * 1013 * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info 1014 * and adjust DSC math to account for slice_per_pkt. 1015 */ 1016 wc = msm_host->dsc->slice_chunk_size + 1; 1017 1018 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1019 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1020 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1021 msm_host->channel) | 1022 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1023 MIPI_DSI_DCS_LONG_WRITE)); 1024 1025 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1026 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1027 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1028 } 1029 } 1030 1031 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1032 { 1033 u32 ctrl; 1034 1035 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1036 1037 if (ctrl & DSI_CTRL_ENABLE) { 1038 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1039 /* 1040 * dsi controller need to be disabled before 1041 * clocks turned on 1042 */ 1043 wmb(); 1044 } 1045 1046 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1047 wmb(); /* clocks need to be enabled before reset */ 1048 1049 /* dsi controller can only be reset while clocks are running */ 1050 dsi_write(msm_host, REG_DSI_RESET, 1); 1051 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1052 dsi_write(msm_host, REG_DSI_RESET, 0); 1053 wmb(); /* controller out of reset */ 1054 1055 if (ctrl & DSI_CTRL_ENABLE) { 1056 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1057 wmb(); /* make sure dsi controller enabled again */ 1058 } 1059 } 1060 1061 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1062 bool video_mode, bool enable) 1063 { 1064 u32 dsi_ctrl; 1065 1066 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1067 1068 if (!enable) { 1069 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1070 DSI_CTRL_CMD_MODE_EN); 1071 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1072 DSI_IRQ_MASK_VIDEO_DONE, 0); 1073 } else { 1074 if (video_mode) { 1075 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1076 } else { /* command mode */ 1077 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1078 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1079 } 1080 dsi_ctrl |= DSI_CTRL_ENABLE; 1081 } 1082 1083 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1084 } 1085 1086 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1087 { 1088 u32 data; 1089 1090 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1091 1092 if (mode == 0) 1093 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1094 else 1095 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1096 1097 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1098 } 1099 1100 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1101 { 1102 u32 ret = 0; 1103 struct device *dev = &msm_host->pdev->dev; 1104 1105 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1106 1107 reinit_completion(&msm_host->video_comp); 1108 1109 ret = wait_for_completion_timeout(&msm_host->video_comp, 1110 msecs_to_jiffies(70)); 1111 1112 if (ret == 0) 1113 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1114 1115 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1116 } 1117 1118 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1119 { 1120 u32 data; 1121 1122 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1123 return; 1124 1125 data = dsi_read(msm_host, REG_DSI_STATUS0); 1126 1127 /* if video mode engine is not busy, its because 1128 * either timing engine was not turned on or the 1129 * DSI controller has finished transmitting the video 1130 * data already, so no need to wait in those cases 1131 */ 1132 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1133 return; 1134 1135 if (msm_host->power_on && msm_host->enabled) { 1136 dsi_wait4video_done(msm_host); 1137 /* delay 4 ms to skip BLLP */ 1138 usleep_range(2000, 4000); 1139 } 1140 } 1141 1142 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1143 { 1144 struct drm_device *dev = msm_host->dev; 1145 struct msm_drm_private *priv = dev->dev_private; 1146 uint64_t iova; 1147 u8 *data; 1148 1149 msm_host->aspace = msm_gem_address_space_get(priv->kms->aspace); 1150 1151 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1152 msm_host->aspace, 1153 &msm_host->tx_gem_obj, &iova); 1154 1155 if (IS_ERR(data)) { 1156 msm_host->tx_gem_obj = NULL; 1157 return PTR_ERR(data); 1158 } 1159 1160 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1161 1162 msm_host->tx_size = msm_host->tx_gem_obj->size; 1163 1164 return 0; 1165 } 1166 1167 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1168 { 1169 struct drm_device *dev = msm_host->dev; 1170 1171 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1172 &msm_host->tx_buf_paddr, GFP_KERNEL); 1173 if (!msm_host->tx_buf) 1174 return -ENOMEM; 1175 1176 msm_host->tx_size = size; 1177 1178 return 0; 1179 } 1180 1181 void msm_dsi_tx_buf_free(struct mipi_dsi_host *host) 1182 { 1183 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1184 struct drm_device *dev = msm_host->dev; 1185 1186 /* 1187 * This is possible if we're tearing down before we've had a chance to 1188 * fully initialize. A very real possibility if our probe is deferred, 1189 * in which case we'll hit msm_dsi_host_destroy() without having run 1190 * through the dsi_tx_buf_alloc(). 1191 */ 1192 if (!dev) 1193 return; 1194 1195 if (msm_host->tx_gem_obj) { 1196 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->aspace); 1197 msm_gem_address_space_put(msm_host->aspace); 1198 msm_host->tx_gem_obj = NULL; 1199 msm_host->aspace = NULL; 1200 } 1201 1202 if (msm_host->tx_buf) 1203 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1204 msm_host->tx_buf_paddr); 1205 } 1206 1207 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1208 { 1209 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1210 } 1211 1212 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1213 { 1214 return msm_host->tx_buf; 1215 } 1216 1217 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1218 { 1219 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1220 } 1221 1222 /* 1223 * prepare cmd buffer to be txed 1224 */ 1225 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1226 const struct mipi_dsi_msg *msg) 1227 { 1228 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1229 struct mipi_dsi_packet packet; 1230 int len; 1231 int ret; 1232 u8 *data; 1233 1234 ret = mipi_dsi_create_packet(&packet, msg); 1235 if (ret) { 1236 pr_err("%s: create packet failed, %d\n", __func__, ret); 1237 return ret; 1238 } 1239 len = (packet.size + 3) & (~0x3); 1240 1241 if (len > msm_host->tx_size) { 1242 pr_err("%s: packet size is too big\n", __func__); 1243 return -EINVAL; 1244 } 1245 1246 data = cfg_hnd->ops->tx_buf_get(msm_host); 1247 if (IS_ERR(data)) { 1248 ret = PTR_ERR(data); 1249 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1250 return ret; 1251 } 1252 1253 /* MSM specific command format in memory */ 1254 data[0] = packet.header[1]; 1255 data[1] = packet.header[2]; 1256 data[2] = packet.header[0]; 1257 data[3] = BIT(7); /* Last packet */ 1258 if (mipi_dsi_packet_format_is_long(msg->type)) 1259 data[3] |= BIT(6); 1260 if (msg->rx_buf && msg->rx_len) 1261 data[3] |= BIT(5); 1262 1263 /* Long packet */ 1264 if (packet.payload && packet.payload_length) 1265 memcpy(data + 4, packet.payload, packet.payload_length); 1266 1267 /* Append 0xff to the end */ 1268 if (packet.size < len) 1269 memset(data + packet.size, 0xff, len - packet.size); 1270 1271 if (cfg_hnd->ops->tx_buf_put) 1272 cfg_hnd->ops->tx_buf_put(msm_host); 1273 1274 return len; 1275 } 1276 1277 /* 1278 * dsi_short_read1_resp: 1 parameter 1279 */ 1280 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1281 { 1282 u8 *data = msg->rx_buf; 1283 1284 if (data && (msg->rx_len >= 1)) { 1285 *data = buf[1]; /* strip out dcs type */ 1286 return 1; 1287 } 1288 1289 pr_err("%s: read data does not match with rx_buf len %zu\n", 1290 __func__, msg->rx_len); 1291 return -EINVAL; 1292 } 1293 1294 /* 1295 * dsi_short_read2_resp: 2 parameter 1296 */ 1297 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1298 { 1299 u8 *data = msg->rx_buf; 1300 1301 if (data && (msg->rx_len >= 2)) { 1302 data[0] = buf[1]; /* strip out dcs type */ 1303 data[1] = buf[2]; 1304 return 2; 1305 } 1306 1307 pr_err("%s: read data does not match with rx_buf len %zu\n", 1308 __func__, msg->rx_len); 1309 return -EINVAL; 1310 } 1311 1312 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1313 { 1314 /* strip out 4 byte dcs header */ 1315 if (msg->rx_buf && msg->rx_len) 1316 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1317 1318 return msg->rx_len; 1319 } 1320 1321 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1322 { 1323 struct drm_device *dev = msm_host->dev; 1324 struct msm_drm_private *priv = dev->dev_private; 1325 1326 if (!dma_base) 1327 return -EINVAL; 1328 1329 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1330 priv->kms->aspace, dma_base); 1331 } 1332 1333 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1334 { 1335 if (!dma_base) 1336 return -EINVAL; 1337 1338 *dma_base = msm_host->tx_buf_paddr; 1339 return 0; 1340 } 1341 1342 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1343 { 1344 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1345 int ret; 1346 uint64_t dma_base; 1347 bool triggered; 1348 1349 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1350 if (ret) { 1351 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1352 return ret; 1353 } 1354 1355 reinit_completion(&msm_host->dma_comp); 1356 1357 dsi_wait4video_eng_busy(msm_host); 1358 1359 triggered = msm_dsi_manager_cmd_xfer_trigger( 1360 msm_host->id, dma_base, len); 1361 if (triggered) { 1362 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1363 msecs_to_jiffies(200)); 1364 DBG("ret=%d", ret); 1365 if (ret == 0) 1366 ret = -ETIMEDOUT; 1367 else 1368 ret = len; 1369 } else { 1370 ret = len; 1371 } 1372 1373 return ret; 1374 } 1375 1376 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1377 u8 *buf, int rx_byte, int pkt_size) 1378 { 1379 u32 *temp, data; 1380 int i, j = 0, cnt; 1381 u32 read_cnt; 1382 u8 reg[16]; 1383 int repeated_bytes = 0; 1384 int buf_offset = buf - msm_host->rx_buf; 1385 1386 temp = (u32 *)reg; 1387 cnt = (rx_byte + 3) >> 2; 1388 if (cnt > 4) 1389 cnt = 4; /* 4 x 32 bits registers only */ 1390 1391 if (rx_byte == 4) 1392 read_cnt = 4; 1393 else 1394 read_cnt = pkt_size + 6; 1395 1396 /* 1397 * In case of multiple reads from the panel, after the first read, there 1398 * is possibility that there are some bytes in the payload repeating in 1399 * the RDBK_DATA registers. Since we read all the parameters from the 1400 * panel right from the first byte for every pass. We need to skip the 1401 * repeating bytes and then append the new parameters to the rx buffer. 1402 */ 1403 if (read_cnt > 16) { 1404 int bytes_shifted; 1405 /* Any data more than 16 bytes will be shifted out. 1406 * The temp read buffer should already contain these bytes. 1407 * The remaining bytes in read buffer are the repeated bytes. 1408 */ 1409 bytes_shifted = read_cnt - 16; 1410 repeated_bytes = buf_offset - bytes_shifted; 1411 } 1412 1413 for (i = cnt - 1; i >= 0; i--) { 1414 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1415 *temp++ = ntohl(data); /* to host byte order */ 1416 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1417 } 1418 1419 for (i = repeated_bytes; i < 16; i++) 1420 buf[j++] = reg[i]; 1421 1422 return j; 1423 } 1424 1425 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1426 const struct mipi_dsi_msg *msg) 1427 { 1428 int len, ret; 1429 int bllp_len = msm_host->mode->hdisplay * 1430 mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; 1431 1432 len = dsi_cmd_dma_add(msm_host, msg); 1433 if (len < 0) { 1434 pr_err("%s: failed to add cmd type = 0x%x\n", 1435 __func__, msg->type); 1436 return len; 1437 } 1438 1439 /* 1440 * for video mode, do not send cmds more than 1441 * one pixel line, since it only transmit it 1442 * during BLLP. 1443 * 1444 * TODO: if the command is sent in LP mode, the bit rate is only 1445 * half of esc clk rate. In this case, if the video is already 1446 * actively streaming, we need to check more carefully if the 1447 * command can be fit into one BLLP. 1448 */ 1449 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1450 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1451 __func__, len); 1452 return -EINVAL; 1453 } 1454 1455 ret = dsi_cmd_dma_tx(msm_host, len); 1456 if (ret < 0) { 1457 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1458 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1459 return ret; 1460 } else if (ret < len) { 1461 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1462 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1463 return -EIO; 1464 } 1465 1466 return len; 1467 } 1468 1469 static void dsi_err_worker(struct work_struct *work) 1470 { 1471 struct msm_dsi_host *msm_host = 1472 container_of(work, struct msm_dsi_host, err_work); 1473 u32 status = msm_host->err_work_state; 1474 1475 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1476 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1477 dsi_sw_reset(msm_host); 1478 1479 /* It is safe to clear here because error irq is disabled. */ 1480 msm_host->err_work_state = 0; 1481 1482 /* enable dsi error interrupt */ 1483 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1484 } 1485 1486 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1487 { 1488 u32 status; 1489 1490 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1491 1492 if (status) { 1493 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1494 /* Writing of an extra 0 needed to clear error bits */ 1495 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1496 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1497 } 1498 } 1499 1500 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1501 { 1502 u32 status; 1503 1504 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1505 1506 if (status) { 1507 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1508 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1509 } 1510 } 1511 1512 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1513 { 1514 u32 status; 1515 1516 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1517 1518 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1519 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1520 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1521 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1522 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1523 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1524 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1525 } 1526 } 1527 1528 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1529 { 1530 u32 status; 1531 1532 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1533 1534 /* fifo underflow, overflow */ 1535 if (status) { 1536 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1537 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1538 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1539 msm_host->err_work_state |= 1540 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1541 } 1542 } 1543 1544 static void dsi_status(struct msm_dsi_host *msm_host) 1545 { 1546 u32 status; 1547 1548 status = dsi_read(msm_host, REG_DSI_STATUS0); 1549 1550 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1551 dsi_write(msm_host, REG_DSI_STATUS0, status); 1552 msm_host->err_work_state |= 1553 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1554 } 1555 } 1556 1557 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1558 { 1559 u32 status; 1560 1561 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1562 1563 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1564 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1565 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1566 } 1567 } 1568 1569 static void dsi_error(struct msm_dsi_host *msm_host) 1570 { 1571 /* disable dsi error interrupt */ 1572 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1573 1574 dsi_clk_status(msm_host); 1575 dsi_fifo_status(msm_host); 1576 dsi_ack_err_status(msm_host); 1577 dsi_timeout_status(msm_host); 1578 dsi_status(msm_host); 1579 dsi_dln0_phy_err(msm_host); 1580 1581 queue_work(msm_host->workqueue, &msm_host->err_work); 1582 } 1583 1584 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1585 { 1586 struct msm_dsi_host *msm_host = ptr; 1587 u32 isr; 1588 unsigned long flags; 1589 1590 if (!msm_host->ctrl_base) 1591 return IRQ_HANDLED; 1592 1593 spin_lock_irqsave(&msm_host->intr_lock, flags); 1594 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1595 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1596 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1597 1598 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1599 1600 if (isr & DSI_IRQ_ERROR) 1601 dsi_error(msm_host); 1602 1603 if (isr & DSI_IRQ_VIDEO_DONE) 1604 complete(&msm_host->video_comp); 1605 1606 if (isr & DSI_IRQ_CMD_DMA_DONE) 1607 complete(&msm_host->dma_comp); 1608 1609 return IRQ_HANDLED; 1610 } 1611 1612 static int dsi_host_attach(struct mipi_dsi_host *host, 1613 struct mipi_dsi_device *dsi) 1614 { 1615 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1616 int ret; 1617 1618 if (dsi->lanes > msm_host->num_data_lanes) 1619 return -EINVAL; 1620 1621 msm_host->channel = dsi->channel; 1622 msm_host->lanes = dsi->lanes; 1623 msm_host->format = dsi->format; 1624 msm_host->mode_flags = dsi->mode_flags; 1625 if (dsi->dsc) 1626 msm_host->dsc = dsi->dsc; 1627 1628 ret = dsi_dev_attach(msm_host->pdev); 1629 if (ret) 1630 return ret; 1631 1632 DBG("id=%d", msm_host->id); 1633 1634 return 0; 1635 } 1636 1637 static int dsi_host_detach(struct mipi_dsi_host *host, 1638 struct mipi_dsi_device *dsi) 1639 { 1640 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1641 1642 dsi_dev_detach(msm_host->pdev); 1643 1644 DBG("id=%d", msm_host->id); 1645 1646 return 0; 1647 } 1648 1649 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1650 const struct mipi_dsi_msg *msg) 1651 { 1652 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1653 int ret; 1654 1655 if (!msg || !msm_host->power_on) 1656 return -EINVAL; 1657 1658 mutex_lock(&msm_host->cmd_mutex); 1659 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1660 mutex_unlock(&msm_host->cmd_mutex); 1661 1662 return ret; 1663 } 1664 1665 static const struct mipi_dsi_host_ops dsi_host_ops = { 1666 .attach = dsi_host_attach, 1667 .detach = dsi_host_detach, 1668 .transfer = dsi_host_transfer, 1669 }; 1670 1671 /* 1672 * List of supported physical to logical lane mappings. 1673 * For example, the 2nd entry represents the following mapping: 1674 * 1675 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1676 */ 1677 static const int supported_data_lane_swaps[][4] = { 1678 { 0, 1, 2, 3 }, 1679 { 3, 0, 1, 2 }, 1680 { 2, 3, 0, 1 }, 1681 { 1, 2, 3, 0 }, 1682 { 0, 3, 2, 1 }, 1683 { 1, 0, 3, 2 }, 1684 { 2, 1, 0, 3 }, 1685 { 3, 2, 1, 0 }, 1686 }; 1687 1688 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1689 struct device_node *ep) 1690 { 1691 struct device *dev = &msm_host->pdev->dev; 1692 struct property *prop; 1693 u32 lane_map[4]; 1694 int ret, i, len, num_lanes; 1695 1696 prop = of_find_property(ep, "data-lanes", &len); 1697 if (!prop) { 1698 DRM_DEV_DEBUG(dev, 1699 "failed to find data lane mapping, using default\n"); 1700 /* Set the number of date lanes to 4 by default. */ 1701 msm_host->num_data_lanes = 4; 1702 return 0; 1703 } 1704 1705 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1706 if (num_lanes < 0) { 1707 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1708 return num_lanes; 1709 } 1710 1711 msm_host->num_data_lanes = num_lanes; 1712 1713 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1714 num_lanes); 1715 if (ret) { 1716 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1717 return ret; 1718 } 1719 1720 /* 1721 * compare DT specified physical-logical lane mappings with the ones 1722 * supported by hardware 1723 */ 1724 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1725 const int *swap = supported_data_lane_swaps[i]; 1726 int j; 1727 1728 /* 1729 * the data-lanes array we get from DT has a logical->physical 1730 * mapping. The "data lane swap" register field represents 1731 * supported configurations in a physical->logical mapping. 1732 * Translate the DT mapping to what we understand and find a 1733 * configuration that works. 1734 */ 1735 for (j = 0; j < num_lanes; j++) { 1736 if (lane_map[j] < 0 || lane_map[j] > 3) 1737 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1738 lane_map[j]); 1739 1740 if (swap[lane_map[j]] != j) 1741 break; 1742 } 1743 1744 if (j == num_lanes) { 1745 msm_host->dlane_swap = i; 1746 return 0; 1747 } 1748 } 1749 1750 return -EINVAL; 1751 } 1752 1753 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1754 { 1755 int ret; 1756 1757 if (dsc->bits_per_pixel & 0xf) { 1758 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1759 return -EINVAL; 1760 } 1761 1762 switch (dsc->bits_per_component) { 1763 case 8: 1764 case 10: 1765 case 12: 1766 /* 1767 * Only 8, 10, and 12 bpc are supported for DSC 1.1 block. 1768 * If additional bpc values need to be supported, update 1769 * this quard with the appropriate DSC version verification. 1770 */ 1771 break; 1772 default: 1773 DRM_DEV_ERROR(&msm_host->pdev->dev, 1774 "Unsupported bits_per_component value: %d\n", 1775 dsc->bits_per_component); 1776 return -EOPNOTSUPP; 1777 } 1778 1779 dsc->simple_422 = 0; 1780 dsc->convert_rgb = 1; 1781 dsc->vbr_enable = 0; 1782 1783 drm_dsc_set_const_params(dsc); 1784 drm_dsc_set_rc_buf_thresh(dsc); 1785 1786 /* DPU supports only pre-SCR panels */ 1787 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); 1788 if (ret) { 1789 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); 1790 return ret; 1791 } 1792 1793 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); 1794 dsc->line_buf_depth = dsc->bits_per_component + 1; 1795 1796 return drm_dsc_compute_rc_parameters(dsc); 1797 } 1798 1799 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1800 { 1801 struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev); 1802 struct device *dev = &msm_host->pdev->dev; 1803 struct device_node *np = dev->of_node; 1804 struct device_node *endpoint; 1805 const char *te_source; 1806 int ret = 0; 1807 1808 /* 1809 * Get the endpoint of the output port of the DSI host. In our case, 1810 * this is mapped to port number with reg = 1. Don't return an error if 1811 * the remote endpoint isn't defined. It's possible that there is 1812 * nothing connected to the dsi output. 1813 */ 1814 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1815 if (!endpoint) { 1816 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1817 return 0; 1818 } 1819 1820 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1821 if (ret) { 1822 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1823 __func__, ret); 1824 ret = -EINVAL; 1825 goto err; 1826 } 1827 1828 ret = of_property_read_string(endpoint, "qcom,te-source", &te_source); 1829 if (ret && ret != -EINVAL) { 1830 DRM_DEV_ERROR(dev, "%s: invalid TE source configuration %d\n", 1831 __func__, ret); 1832 goto err; 1833 } 1834 if (!ret) { 1835 msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL); 1836 if (!msm_dsi->te_source) { 1837 DRM_DEV_ERROR(dev, "%s: failed to allocate te_source\n", 1838 __func__); 1839 ret = -ENOMEM; 1840 goto err; 1841 } 1842 } 1843 ret = 0; 1844 1845 if (of_property_present(np, "syscon-sfpb")) { 1846 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1847 "syscon-sfpb"); 1848 if (IS_ERR(msm_host->sfpb)) { 1849 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1850 __func__); 1851 ret = PTR_ERR(msm_host->sfpb); 1852 } 1853 } 1854 1855 err: 1856 of_node_put(endpoint); 1857 1858 return ret; 1859 } 1860 1861 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1862 { 1863 struct platform_device *pdev = msm_host->pdev; 1864 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1865 struct resource *res; 1866 int i, j; 1867 1868 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1869 if (!res) 1870 return -EINVAL; 1871 1872 for (i = 0; i < VARIANTS_MAX; i++) 1873 for (j = 0; j < DSI_MAX; j++) 1874 if (cfg->io_start[i][j] == res->start) 1875 return j; 1876 1877 return -EINVAL; 1878 } 1879 1880 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1881 { 1882 struct msm_dsi_host *msm_host = NULL; 1883 struct platform_device *pdev = msm_dsi->pdev; 1884 const struct msm_dsi_config *cfg; 1885 int ret; 1886 1887 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1888 if (!msm_host) 1889 return -ENOMEM; 1890 1891 msm_host->pdev = pdev; 1892 msm_dsi->host = &msm_host->base; 1893 1894 ret = dsi_host_parse_dt(msm_host); 1895 if (ret) 1896 return dev_err_probe(&pdev->dev, ret, "%s: failed to parse dt\n", 1897 __func__); 1898 1899 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 1900 if (IS_ERR(msm_host->ctrl_base)) 1901 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->ctrl_base), 1902 "%s: unable to map Dsi ctrl base\n", __func__); 1903 1904 pm_runtime_enable(&pdev->dev); 1905 1906 msm_host->cfg_hnd = dsi_get_config(msm_host); 1907 if (!msm_host->cfg_hnd) 1908 return dev_err_probe(&pdev->dev, -EINVAL, 1909 "%s: get config failed\n", __func__); 1910 cfg = msm_host->cfg_hnd->cfg; 1911 1912 msm_host->id = dsi_host_get_id(msm_host); 1913 if (msm_host->id < 0) 1914 return dev_err_probe(&pdev->dev, msm_host->id, 1915 "%s: unable to identify DSI host index\n", 1916 __func__); 1917 1918 /* fixup base address by io offset */ 1919 msm_host->ctrl_base += cfg->io_offset; 1920 1921 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 1922 cfg->regulator_data, 1923 &msm_host->supplies); 1924 if (ret) 1925 return ret; 1926 1927 ret = dsi_clk_init(msm_host); 1928 if (ret) 1929 return dev_err_probe(&pdev->dev, ret, "%s: unable to initialize dsi clks\n", __func__); 1930 1931 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1932 if (!msm_host->rx_buf) 1933 return -ENOMEM; 1934 1935 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 1936 if (ret) 1937 return ret; 1938 /* OPP table is optional */ 1939 ret = devm_pm_opp_of_add_table(&pdev->dev); 1940 if (ret && ret != -ENODEV) 1941 return dev_err_probe(&pdev->dev, ret, "invalid OPP table in device tree\n"); 1942 1943 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1944 if (!msm_host->irq) 1945 return dev_err_probe(&pdev->dev, -EINVAL, "failed to get irq\n"); 1946 1947 /* do not autoenable, will be enabled later */ 1948 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 1949 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 1950 "dsi_isr", msm_host); 1951 if (ret < 0) 1952 return dev_err_probe(&pdev->dev, ret, "failed to request IRQ%u\n", 1953 msm_host->irq); 1954 1955 init_completion(&msm_host->dma_comp); 1956 init_completion(&msm_host->video_comp); 1957 mutex_init(&msm_host->dev_mutex); 1958 mutex_init(&msm_host->cmd_mutex); 1959 spin_lock_init(&msm_host->intr_lock); 1960 1961 /* setup workqueue */ 1962 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1963 if (!msm_host->workqueue) 1964 return -ENOMEM; 1965 1966 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1967 1968 msm_dsi->id = msm_host->id; 1969 1970 DBG("Dsi Host %d initialized", msm_host->id); 1971 return 0; 1972 } 1973 1974 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1975 { 1976 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1977 1978 DBG(""); 1979 if (msm_host->workqueue) { 1980 destroy_workqueue(msm_host->workqueue); 1981 msm_host->workqueue = NULL; 1982 } 1983 1984 mutex_destroy(&msm_host->cmd_mutex); 1985 mutex_destroy(&msm_host->dev_mutex); 1986 1987 pm_runtime_disable(&msm_host->pdev->dev); 1988 } 1989 1990 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1991 struct drm_device *dev) 1992 { 1993 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1994 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1995 int ret; 1996 1997 msm_host->dev = dev; 1998 1999 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2000 if (ret) { 2001 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2002 return ret; 2003 } 2004 2005 return 0; 2006 } 2007 2008 int msm_dsi_host_register(struct mipi_dsi_host *host) 2009 { 2010 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2011 int ret; 2012 2013 /* Register mipi dsi host */ 2014 if (!msm_host->registered) { 2015 host->dev = &msm_host->pdev->dev; 2016 host->ops = &dsi_host_ops; 2017 ret = mipi_dsi_host_register(host); 2018 if (ret) 2019 return ret; 2020 2021 msm_host->registered = true; 2022 } 2023 2024 return 0; 2025 } 2026 2027 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2028 { 2029 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2030 2031 if (msm_host->registered) { 2032 mipi_dsi_host_unregister(host); 2033 host->dev = NULL; 2034 host->ops = NULL; 2035 msm_host->registered = false; 2036 } 2037 } 2038 2039 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2040 const struct mipi_dsi_msg *msg) 2041 { 2042 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2043 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2044 2045 /* TODO: make sure dsi_cmd_mdp is idle. 2046 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2047 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2048 * How to handle the old versions? Wait for mdp cmd done? 2049 */ 2050 2051 /* 2052 * mdss interrupt is generated in mdp core clock domain 2053 * mdp clock need to be enabled to receive dsi interrupt 2054 */ 2055 pm_runtime_get_sync(&msm_host->pdev->dev); 2056 cfg_hnd->ops->link_clk_set_rate(msm_host); 2057 cfg_hnd->ops->link_clk_enable(msm_host); 2058 2059 /* TODO: vote for bus bandwidth */ 2060 2061 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2062 dsi_set_tx_power_mode(0, msm_host); 2063 2064 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2065 dsi_write(msm_host, REG_DSI_CTRL, 2066 msm_host->dma_cmd_ctrl_restore | 2067 DSI_CTRL_CMD_MODE_EN | 2068 DSI_CTRL_ENABLE); 2069 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2070 2071 return 0; 2072 } 2073 2074 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2075 const struct mipi_dsi_msg *msg) 2076 { 2077 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2078 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2079 2080 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2081 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2082 2083 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2084 dsi_set_tx_power_mode(1, msm_host); 2085 2086 /* TODO: unvote for bus bandwidth */ 2087 2088 cfg_hnd->ops->link_clk_disable(msm_host); 2089 pm_runtime_put(&msm_host->pdev->dev); 2090 } 2091 2092 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2093 const struct mipi_dsi_msg *msg) 2094 { 2095 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2096 2097 return dsi_cmds2buf_tx(msm_host, msg); 2098 } 2099 2100 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2101 const struct mipi_dsi_msg *msg) 2102 { 2103 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2104 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2105 int data_byte, rx_byte, dlen, end; 2106 int short_response, diff, pkt_size, ret = 0; 2107 char cmd; 2108 int rlen = msg->rx_len; 2109 u8 *buf; 2110 2111 if (rlen <= 2) { 2112 short_response = 1; 2113 pkt_size = rlen; 2114 rx_byte = 4; 2115 } else { 2116 short_response = 0; 2117 data_byte = 10; /* first read */ 2118 if (rlen < data_byte) 2119 pkt_size = rlen; 2120 else 2121 pkt_size = data_byte; 2122 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2123 } 2124 2125 buf = msm_host->rx_buf; 2126 end = 0; 2127 while (!end) { 2128 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2129 struct mipi_dsi_msg max_pkt_size_msg = { 2130 .channel = msg->channel, 2131 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2132 .tx_len = 2, 2133 .tx_buf = tx, 2134 }; 2135 2136 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2137 rlen, pkt_size, rx_byte); 2138 2139 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2140 if (ret < 2) { 2141 pr_err("%s: Set max pkt size failed, %d\n", 2142 __func__, ret); 2143 return -EINVAL; 2144 } 2145 2146 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2147 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2148 /* Clear the RDBK_DATA registers */ 2149 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2150 DSI_RDBK_DATA_CTRL_CLR); 2151 wmb(); /* make sure the RDBK registers are cleared */ 2152 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2153 wmb(); /* release cleared status before transfer */ 2154 } 2155 2156 ret = dsi_cmds2buf_tx(msm_host, msg); 2157 if (ret < 0) { 2158 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2159 return ret; 2160 } else if (ret < msg->tx_len) { 2161 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2162 return -ECOMM; 2163 } 2164 2165 /* 2166 * once cmd_dma_done interrupt received, 2167 * return data from client is ready and stored 2168 * at RDBK_DATA register already 2169 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2170 * after that dcs header lost during shift into registers 2171 */ 2172 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2173 2174 if (dlen <= 0) 2175 return 0; 2176 2177 if (short_response) 2178 break; 2179 2180 if (rlen <= data_byte) { 2181 diff = data_byte - rlen; 2182 end = 1; 2183 } else { 2184 diff = 0; 2185 rlen -= data_byte; 2186 } 2187 2188 if (!end) { 2189 dlen -= 2; /* 2 crc */ 2190 dlen -= diff; 2191 buf += dlen; /* next start position */ 2192 data_byte = 14; /* NOT first read */ 2193 if (rlen < data_byte) 2194 pkt_size += rlen; 2195 else 2196 pkt_size += data_byte; 2197 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2198 } 2199 } 2200 2201 /* 2202 * For single Long read, if the requested rlen < 10, 2203 * we need to shift the start position of rx 2204 * data buffer to skip the bytes which are not 2205 * updated. 2206 */ 2207 if (pkt_size < 10 && !short_response) 2208 buf = msm_host->rx_buf + (10 - rlen); 2209 else 2210 buf = msm_host->rx_buf; 2211 2212 cmd = buf[0]; 2213 switch (cmd) { 2214 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2215 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2216 ret = 0; 2217 break; 2218 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2219 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2220 ret = dsi_short_read1_resp(buf, msg); 2221 break; 2222 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2223 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2224 ret = dsi_short_read2_resp(buf, msg); 2225 break; 2226 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2227 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2228 ret = dsi_long_read_resp(buf, msg); 2229 break; 2230 default: 2231 pr_warn("%s:Invalid response cmd\n", __func__); 2232 ret = 0; 2233 } 2234 2235 return ret; 2236 } 2237 2238 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2239 u32 len) 2240 { 2241 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2242 2243 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2244 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2245 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2246 2247 /* Make sure trigger happens */ 2248 wmb(); 2249 } 2250 2251 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2252 struct msm_dsi_phy *src_phy) 2253 { 2254 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2255 2256 msm_host->cphy_mode = src_phy->cphy_mode; 2257 } 2258 2259 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2260 { 2261 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2262 2263 DBG(""); 2264 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2265 /* Make sure fully reset */ 2266 wmb(); 2267 udelay(1000); 2268 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2269 udelay(100); 2270 } 2271 2272 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2273 struct msm_dsi_phy_clk_request *clk_req, 2274 bool is_bonded_dsi) 2275 { 2276 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2277 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2278 int ret; 2279 2280 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2281 if (ret) { 2282 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2283 return; 2284 } 2285 2286 /* CPHY transmits 16 bits over 7 clock cycles 2287 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2288 * so multiply by 7 to get the "bitclk rate" 2289 */ 2290 if (msm_host->cphy_mode) 2291 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2292 else 2293 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2294 clk_req->escclk_rate = msm_host->esc_clk_rate; 2295 } 2296 2297 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2298 { 2299 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2300 2301 enable_irq(msm_host->irq); 2302 } 2303 2304 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2305 { 2306 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2307 2308 disable_irq(msm_host->irq); 2309 } 2310 2311 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2312 { 2313 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2314 2315 dsi_op_mode_config(msm_host, 2316 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2317 2318 /* TODO: clock should be turned off for command mode, 2319 * and only turned on before MDP START. 2320 * This part of code should be enabled once mdp driver support it. 2321 */ 2322 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2323 * dsi_link_clk_disable(msm_host); 2324 * pm_runtime_put(&msm_host->pdev->dev); 2325 * } 2326 */ 2327 msm_host->enabled = true; 2328 return 0; 2329 } 2330 2331 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2332 { 2333 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2334 2335 msm_host->enabled = false; 2336 dsi_op_mode_config(msm_host, 2337 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2338 2339 /* Since we have disabled INTF, the video engine won't stop so that 2340 * the cmd engine will be blocked. 2341 * Reset to disable video engine so that we can send off cmd. 2342 */ 2343 dsi_sw_reset(msm_host); 2344 2345 return 0; 2346 } 2347 2348 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2349 { 2350 enum sfpb_ahb_arb_master_port_en en; 2351 2352 if (!msm_host->sfpb) 2353 return; 2354 2355 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2356 2357 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2358 SFPB_GPREG_MASTER_PORT_EN__MASK, 2359 SFPB_GPREG_MASTER_PORT_EN(en)); 2360 } 2361 2362 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2363 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2364 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2365 { 2366 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2367 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2368 int ret = 0; 2369 2370 mutex_lock(&msm_host->dev_mutex); 2371 if (msm_host->power_on) { 2372 DBG("dsi host already on"); 2373 goto unlock_ret; 2374 } 2375 2376 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; 2377 if (phy_shared_timings->byte_intf_clk_div_2) 2378 msm_host->byte_intf_clk_rate /= 2; 2379 2380 msm_dsi_sfpb_config(msm_host, true); 2381 2382 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2383 msm_host->supplies); 2384 if (ret) { 2385 pr_err("%s:Failed to enable vregs.ret=%d\n", 2386 __func__, ret); 2387 goto unlock_ret; 2388 } 2389 2390 pm_runtime_get_sync(&msm_host->pdev->dev); 2391 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2392 if (!ret) 2393 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2394 if (ret) { 2395 pr_err("%s: failed to enable link clocks. ret=%d\n", 2396 __func__, ret); 2397 goto fail_disable_reg; 2398 } 2399 2400 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2401 if (ret) { 2402 pr_err("%s: failed to set pinctrl default state, %d\n", 2403 __func__, ret); 2404 goto fail_disable_clk; 2405 } 2406 2407 dsi_timing_setup(msm_host, is_bonded_dsi); 2408 dsi_sw_reset(msm_host); 2409 dsi_ctrl_enable(msm_host, phy_shared_timings, phy); 2410 2411 msm_host->power_on = true; 2412 mutex_unlock(&msm_host->dev_mutex); 2413 2414 return 0; 2415 2416 fail_disable_clk: 2417 cfg_hnd->ops->link_clk_disable(msm_host); 2418 pm_runtime_put(&msm_host->pdev->dev); 2419 fail_disable_reg: 2420 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2421 msm_host->supplies); 2422 unlock_ret: 2423 mutex_unlock(&msm_host->dev_mutex); 2424 return ret; 2425 } 2426 2427 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2428 { 2429 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2430 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2431 2432 mutex_lock(&msm_host->dev_mutex); 2433 if (!msm_host->power_on) { 2434 DBG("dsi host already off"); 2435 goto unlock_ret; 2436 } 2437 2438 dsi_ctrl_disable(msm_host); 2439 2440 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2441 2442 cfg_hnd->ops->link_clk_disable(msm_host); 2443 pm_runtime_put(&msm_host->pdev->dev); 2444 2445 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2446 msm_host->supplies); 2447 2448 msm_dsi_sfpb_config(msm_host, false); 2449 2450 DBG("-"); 2451 2452 msm_host->power_on = false; 2453 2454 unlock_ret: 2455 mutex_unlock(&msm_host->dev_mutex); 2456 return 0; 2457 } 2458 2459 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2460 const struct drm_display_mode *mode) 2461 { 2462 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2463 2464 if (msm_host->mode) { 2465 drm_mode_destroy(msm_host->dev, msm_host->mode); 2466 msm_host->mode = NULL; 2467 } 2468 2469 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2470 if (!msm_host->mode) { 2471 pr_err("%s: cannot duplicate mode\n", __func__); 2472 return -ENOMEM; 2473 } 2474 2475 return 0; 2476 } 2477 2478 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2479 const struct drm_display_mode *mode) 2480 { 2481 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2482 struct drm_dsc_config *dsc = msm_host->dsc; 2483 int pic_width = mode->hdisplay; 2484 int pic_height = mode->vdisplay; 2485 2486 if (!msm_host->dsc) 2487 return MODE_OK; 2488 2489 if (pic_width % dsc->slice_width) { 2490 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2491 pic_width, dsc->slice_width); 2492 return MODE_H_ILLEGAL; 2493 } 2494 2495 if (pic_height % dsc->slice_height) { 2496 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2497 pic_height, dsc->slice_height); 2498 return MODE_V_ILLEGAL; 2499 } 2500 2501 return MODE_OK; 2502 } 2503 2504 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2505 { 2506 return to_msm_dsi_host(host)->mode_flags; 2507 } 2508 2509 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2510 { 2511 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2512 2513 pm_runtime_get_sync(&msm_host->pdev->dev); 2514 2515 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2516 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2517 2518 pm_runtime_put_sync(&msm_host->pdev->dev); 2519 } 2520 2521 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2522 { 2523 u32 reg; 2524 2525 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2526 2527 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2528 /* draw checkered rectangle pattern */ 2529 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2530 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2531 /* use 24-bit RGB test pttern */ 2532 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2533 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2534 DSI_TPG_VIDEO_CONFIG_RGB); 2535 2536 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2537 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2538 2539 DBG("Video test pattern setup done\n"); 2540 } 2541 2542 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2543 { 2544 u32 reg; 2545 2546 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2547 2548 /* initial value for test pattern */ 2549 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2550 2551 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2552 2553 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2554 /* draw checkered rectangle pattern */ 2555 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2556 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2557 2558 DBG("Cmd test pattern setup done\n"); 2559 } 2560 2561 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2562 { 2563 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2564 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2565 u32 reg; 2566 2567 if (is_video_mode) 2568 msm_dsi_host_video_test_pattern_setup(msm_host); 2569 else 2570 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2571 2572 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2573 /* enable the test pattern generator */ 2574 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2575 2576 /* for command mode need to trigger one frame from tpg */ 2577 if (!is_video_mode) 2578 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2579 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2580 } 2581 2582 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2583 { 2584 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2585 2586 return msm_host->dsc; 2587 } 2588