1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/interrupt.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of.h> 14 #include <linux/of_graph.h> 15 #include <linux/of_irq.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_opp.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spinlock.h> 21 22 #include <video/mipi_display.h> 23 24 #include <drm/display/drm_dsc_helper.h> 25 #include <drm/drm_of.h> 26 27 #include "dsi.h" 28 #include "dsi.xml.h" 29 #include "sfpb.xml.h" 30 #include "dsi_cfg.h" 31 #include "msm_dsc_helper.h" 32 #include "msm_kms.h" 33 #include "msm_gem.h" 34 #include "phy/dsi_phy.h" 35 36 #define DSI_RESET_TOGGLE_DELAY_MS 20 37 38 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 39 40 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 41 { 42 u32 ver; 43 44 if (!major || !minor) 45 return -EINVAL; 46 47 /* 48 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 49 * makes all other registers 4-byte shifted down. 50 * 51 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 52 * older, we read the DSI_VERSION register without any shift(offset 53 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 54 * the case of DSI6G, this has to be zero (the offset points to a 55 * scratch register which we never touch) 56 */ 57 58 ver = readl(base + REG_DSI_VERSION); 59 if (ver) { 60 /* older dsi host, there is no register shift */ 61 ver = FIELD(ver, DSI_VERSION_MAJOR); 62 if (ver <= MSM_DSI_VER_MAJOR_V2) { 63 /* old versions */ 64 *major = ver; 65 *minor = 0; 66 return 0; 67 } else { 68 return -EINVAL; 69 } 70 } else { 71 /* 72 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 73 * registers are shifted down, read DSI_VERSION again with 74 * the shifted offset 75 */ 76 ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 77 ver = FIELD(ver, DSI_VERSION_MAJOR); 78 if (ver == MSM_DSI_VER_MAJOR_6G) { 79 /* 6G version */ 80 *major = ver; 81 *minor = readl(base + REG_DSI_6G_HW_VERSION); 82 return 0; 83 } else { 84 return -EINVAL; 85 } 86 } 87 } 88 89 #define DSI_ERR_STATE_ACK 0x0000 90 #define DSI_ERR_STATE_TIMEOUT 0x0001 91 #define DSI_ERR_STATE_DLN0_PHY 0x0002 92 #define DSI_ERR_STATE_FIFO 0x0004 93 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 94 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 95 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 96 97 #define DSI_CLK_CTRL_ENABLE_CLKS \ 98 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 99 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 100 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 101 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 102 103 struct msm_dsi_host { 104 struct mipi_dsi_host base; 105 106 struct platform_device *pdev; 107 struct drm_device *dev; 108 109 int id; 110 111 void __iomem *ctrl_base; 112 phys_addr_t ctrl_size; 113 struct regulator_bulk_data *supplies; 114 115 int num_bus_clks; 116 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 117 118 struct clk *byte_clk; 119 struct clk *esc_clk; 120 struct clk *pixel_clk; 121 struct clk *byte_intf_clk; 122 123 unsigned long byte_clk_rate; 124 unsigned long byte_intf_clk_rate; 125 unsigned long pixel_clk_rate; 126 unsigned long esc_clk_rate; 127 128 /* DSI v2 specific clocks */ 129 struct clk *src_clk; 130 131 unsigned long src_clk_rate; 132 133 struct gpio_desc *disp_en_gpio; 134 struct gpio_desc *te_gpio; 135 136 const struct msm_dsi_cfg_handler *cfg_hnd; 137 138 struct completion dma_comp; 139 struct completion video_comp; 140 struct mutex dev_mutex; 141 struct mutex cmd_mutex; 142 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 143 144 u32 err_work_state; 145 struct work_struct err_work; 146 struct workqueue_struct *workqueue; 147 148 /* DSI 6G TX buffer*/ 149 struct drm_gem_object *tx_gem_obj; 150 struct msm_gem_address_space *aspace; 151 152 /* DSI v2 TX buffer */ 153 void *tx_buf; 154 dma_addr_t tx_buf_paddr; 155 156 int tx_size; 157 158 u8 *rx_buf; 159 160 struct regmap *sfpb; 161 162 struct drm_display_mode *mode; 163 struct drm_dsc_config *dsc; 164 165 /* connected device info */ 166 unsigned int channel; 167 unsigned int lanes; 168 enum mipi_dsi_pixel_format format; 169 unsigned long mode_flags; 170 171 /* lane data parsed via DT */ 172 int dlane_swap; 173 int num_data_lanes; 174 175 /* from phy DT */ 176 bool cphy_mode; 177 178 u32 dma_cmd_ctrl_restore; 179 180 bool registered; 181 bool power_on; 182 bool enabled; 183 int irq; 184 }; 185 186 187 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 188 { 189 return readl(msm_host->ctrl_base + reg); 190 } 191 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 192 { 193 writel(data, msm_host->ctrl_base + reg); 194 } 195 196 static const struct msm_dsi_cfg_handler *dsi_get_config( 197 struct msm_dsi_host *msm_host) 198 { 199 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 200 struct device *dev = &msm_host->pdev->dev; 201 struct clk *ahb_clk; 202 int ret; 203 u32 major = 0, minor = 0; 204 205 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 206 if (IS_ERR(ahb_clk)) { 207 pr_err("%s: cannot get interface clock\n", __func__); 208 goto exit; 209 } 210 211 pm_runtime_get_sync(dev); 212 213 ret = clk_prepare_enable(ahb_clk); 214 if (ret) { 215 pr_err("%s: unable to enable ahb_clk\n", __func__); 216 goto runtime_put; 217 } 218 219 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 220 if (ret) { 221 pr_err("%s: Invalid version\n", __func__); 222 goto disable_clks; 223 } 224 225 cfg_hnd = msm_dsi_cfg_get(major, minor); 226 227 DBG("%s: Version %x:%x\n", __func__, major, minor); 228 229 disable_clks: 230 clk_disable_unprepare(ahb_clk); 231 runtime_put: 232 pm_runtime_put_sync(dev); 233 exit: 234 return cfg_hnd; 235 } 236 237 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 238 { 239 return container_of(host, struct msm_dsi_host, base); 240 } 241 242 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 243 { 244 struct platform_device *pdev = msm_host->pdev; 245 int ret = 0; 246 247 msm_host->src_clk = msm_clk_get(pdev, "src"); 248 249 if (IS_ERR(msm_host->src_clk)) { 250 ret = PTR_ERR(msm_host->src_clk); 251 pr_err("%s: can't find src clock. ret=%d\n", 252 __func__, ret); 253 msm_host->src_clk = NULL; 254 return ret; 255 } 256 257 return ret; 258 } 259 260 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 261 { 262 struct platform_device *pdev = msm_host->pdev; 263 int ret = 0; 264 265 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 266 if (IS_ERR(msm_host->byte_intf_clk)) { 267 ret = PTR_ERR(msm_host->byte_intf_clk); 268 pr_err("%s: can't find byte_intf clock. ret=%d\n", 269 __func__, ret); 270 } 271 272 return ret; 273 } 274 275 static int dsi_clk_init(struct msm_dsi_host *msm_host) 276 { 277 struct platform_device *pdev = msm_host->pdev; 278 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 279 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 280 int i, ret = 0; 281 282 /* get bus clocks */ 283 for (i = 0; i < cfg->num_bus_clks; i++) 284 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 285 msm_host->num_bus_clks = cfg->num_bus_clks; 286 287 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 288 if (ret < 0) { 289 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret); 290 goto exit; 291 } 292 293 /* get link and source clocks */ 294 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 295 if (IS_ERR(msm_host->byte_clk)) { 296 ret = PTR_ERR(msm_host->byte_clk); 297 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 298 __func__, ret); 299 msm_host->byte_clk = NULL; 300 goto exit; 301 } 302 303 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 304 if (IS_ERR(msm_host->pixel_clk)) { 305 ret = PTR_ERR(msm_host->pixel_clk); 306 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 307 __func__, ret); 308 msm_host->pixel_clk = NULL; 309 goto exit; 310 } 311 312 msm_host->esc_clk = msm_clk_get(pdev, "core"); 313 if (IS_ERR(msm_host->esc_clk)) { 314 ret = PTR_ERR(msm_host->esc_clk); 315 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 316 __func__, ret); 317 msm_host->esc_clk = NULL; 318 goto exit; 319 } 320 321 if (cfg_hnd->ops->clk_init_ver) 322 ret = cfg_hnd->ops->clk_init_ver(msm_host); 323 exit: 324 return ret; 325 } 326 327 int msm_dsi_runtime_suspend(struct device *dev) 328 { 329 struct platform_device *pdev = to_platform_device(dev); 330 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 331 struct mipi_dsi_host *host = msm_dsi->host; 332 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 333 334 if (!msm_host->cfg_hnd) 335 return 0; 336 337 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 338 339 return 0; 340 } 341 342 int msm_dsi_runtime_resume(struct device *dev) 343 { 344 struct platform_device *pdev = to_platform_device(dev); 345 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 346 struct mipi_dsi_host *host = msm_dsi->host; 347 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 348 349 if (!msm_host->cfg_hnd) 350 return 0; 351 352 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 353 } 354 355 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 356 { 357 int ret; 358 359 DBG("Set clk rates: pclk=%lu, byteclk=%lu", 360 msm_host->pixel_clk_rate, msm_host->byte_clk_rate); 361 362 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 363 msm_host->byte_clk_rate); 364 if (ret) { 365 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 366 return ret; 367 } 368 369 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 370 if (ret) { 371 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 372 return ret; 373 } 374 375 if (msm_host->byte_intf_clk) { 376 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); 377 if (ret) { 378 pr_err("%s: Failed to set rate byte intf clk, %d\n", 379 __func__, ret); 380 return ret; 381 } 382 } 383 384 return 0; 385 } 386 387 388 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 389 { 390 int ret; 391 392 ret = clk_prepare_enable(msm_host->esc_clk); 393 if (ret) { 394 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 395 goto error; 396 } 397 398 ret = clk_prepare_enable(msm_host->byte_clk); 399 if (ret) { 400 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 401 goto byte_clk_err; 402 } 403 404 ret = clk_prepare_enable(msm_host->pixel_clk); 405 if (ret) { 406 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 407 goto pixel_clk_err; 408 } 409 410 ret = clk_prepare_enable(msm_host->byte_intf_clk); 411 if (ret) { 412 pr_err("%s: Failed to enable byte intf clk\n", 413 __func__); 414 goto byte_intf_clk_err; 415 } 416 417 return 0; 418 419 byte_intf_clk_err: 420 clk_disable_unprepare(msm_host->pixel_clk); 421 pixel_clk_err: 422 clk_disable_unprepare(msm_host->byte_clk); 423 byte_clk_err: 424 clk_disable_unprepare(msm_host->esc_clk); 425 error: 426 return ret; 427 } 428 429 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 430 { 431 int ret; 432 433 DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 434 msm_host->pixel_clk_rate, msm_host->byte_clk_rate, 435 msm_host->esc_clk_rate, msm_host->src_clk_rate); 436 437 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 438 if (ret) { 439 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 440 return ret; 441 } 442 443 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 444 if (ret) { 445 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 446 return ret; 447 } 448 449 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 450 if (ret) { 451 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 452 return ret; 453 } 454 455 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 456 if (ret) { 457 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 458 return ret; 459 } 460 461 return 0; 462 } 463 464 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 465 { 466 int ret; 467 468 ret = clk_prepare_enable(msm_host->byte_clk); 469 if (ret) { 470 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 471 goto error; 472 } 473 474 ret = clk_prepare_enable(msm_host->esc_clk); 475 if (ret) { 476 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 477 goto esc_clk_err; 478 } 479 480 ret = clk_prepare_enable(msm_host->src_clk); 481 if (ret) { 482 pr_err("%s: Failed to enable dsi src clk\n", __func__); 483 goto src_clk_err; 484 } 485 486 ret = clk_prepare_enable(msm_host->pixel_clk); 487 if (ret) { 488 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 489 goto pixel_clk_err; 490 } 491 492 return 0; 493 494 pixel_clk_err: 495 clk_disable_unprepare(msm_host->src_clk); 496 src_clk_err: 497 clk_disable_unprepare(msm_host->esc_clk); 498 esc_clk_err: 499 clk_disable_unprepare(msm_host->byte_clk); 500 error: 501 return ret; 502 } 503 504 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 505 { 506 /* Drop the performance state vote */ 507 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 508 clk_disable_unprepare(msm_host->esc_clk); 509 clk_disable_unprepare(msm_host->pixel_clk); 510 clk_disable_unprepare(msm_host->byte_intf_clk); 511 clk_disable_unprepare(msm_host->byte_clk); 512 } 513 514 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 515 { 516 clk_disable_unprepare(msm_host->pixel_clk); 517 clk_disable_unprepare(msm_host->src_clk); 518 clk_disable_unprepare(msm_host->esc_clk); 519 clk_disable_unprepare(msm_host->byte_clk); 520 } 521 522 /** 523 * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case 524 * @mode: The selected mode for the DSI output 525 * @dsc: DRM DSC configuration for this DSI output 526 * 527 * Adjust the pclk rate by calculating a new hdisplay proportional to 528 * the compression ratio such that: 529 * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp 530 * 531 * Porches do not need to be adjusted: 532 * - For VIDEO mode they are not compressed by DSC and are passed as is. 533 * - For CMD mode there are no actual porches. Instead these fields 534 * currently represent the overhead to the image data transfer. As such, they 535 * are calculated for the final mode parameters (after the compression) and 536 * are not to be adjusted too. 537 * 538 * FIXME: Reconsider this if/when CMD mode handling is rewritten to use 539 * transfer time and data overhead as a starting point of the calculations. 540 */ 541 static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, 542 const struct drm_dsc_config *dsc) 543 { 544 int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc), 545 dsc->bits_per_component * 3); 546 547 int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; 548 549 return new_htotal * mode->vtotal * drm_mode_vrefresh(mode); 550 } 551 552 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, 553 const struct drm_dsc_config *dsc, bool is_bonded_dsi) 554 { 555 unsigned long pclk_rate; 556 557 pclk_rate = mode->clock * 1000; 558 559 if (dsc) 560 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc); 561 562 /* 563 * For bonded DSI mode, the current DRM mode has the complete width of the 564 * panel. Since, the complete panel is driven by two DSI controllers, 565 * the clock rates have to be split between the two dsi controllers. 566 * Adjust the byte and pixel clock rates for each dsi host accordingly. 567 */ 568 if (is_bonded_dsi) 569 pclk_rate /= 2; 570 571 return pclk_rate; 572 } 573 574 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 575 const struct drm_display_mode *mode) 576 { 577 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 578 u8 lanes = msm_host->lanes; 579 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 580 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); 581 unsigned long pclk_bpp; 582 583 if (lanes == 0) { 584 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 585 lanes = 1; 586 } 587 588 /* CPHY "byte_clk" is in units of 16 bits */ 589 if (msm_host->cphy_mode) 590 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); 591 else 592 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); 593 594 return pclk_bpp; 595 } 596 597 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 598 { 599 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); 600 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 601 msm_host->mode); 602 603 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 604 msm_host->byte_clk_rate); 605 606 } 607 608 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 609 { 610 if (!msm_host->mode) { 611 pr_err("%s: mode not set\n", __func__); 612 return -EINVAL; 613 } 614 615 dsi_calc_pclk(msm_host, is_bonded_dsi); 616 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 617 return 0; 618 } 619 620 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 621 { 622 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 623 unsigned int esc_mhz, esc_div; 624 unsigned long byte_mhz; 625 626 dsi_calc_pclk(msm_host, is_bonded_dsi); 627 628 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); 629 630 /* 631 * esc clock is byte clock followed by a 4 bit divider, 632 * we need to find an escape clock frequency within the 633 * mipi DSI spec range within the maximum divider limit 634 * We iterate here between an escape clock frequencey 635 * between 20 Mhz to 5 Mhz and pick up the first one 636 * that can be supported by our divider 637 */ 638 639 byte_mhz = msm_host->byte_clk_rate / 1000000; 640 641 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 642 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 643 644 /* 645 * TODO: Ideally, we shouldn't know what sort of divider 646 * is available in mmss_cc, we're just assuming that 647 * it'll always be a 4 bit divider. Need to come up with 648 * a better way here. 649 */ 650 if (esc_div >= 1 && esc_div <= 16) 651 break; 652 } 653 654 if (esc_mhz < 5) 655 return -EINVAL; 656 657 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 658 659 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 660 msm_host->src_clk_rate); 661 662 return 0; 663 } 664 665 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 666 { 667 u32 intr; 668 unsigned long flags; 669 670 spin_lock_irqsave(&msm_host->intr_lock, flags); 671 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 672 673 if (enable) 674 intr |= mask; 675 else 676 intr &= ~mask; 677 678 DBG("intr=%x enable=%d", intr, enable); 679 680 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 681 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 682 } 683 684 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 685 { 686 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 687 return BURST_MODE; 688 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 689 return NON_BURST_SYNCH_PULSE; 690 691 return NON_BURST_SYNCH_EVENT; 692 } 693 694 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 695 const enum mipi_dsi_pixel_format mipi_fmt) 696 { 697 switch (mipi_fmt) { 698 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 699 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 700 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 701 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 702 default: return VID_DST_FORMAT_RGB888; 703 } 704 } 705 706 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 707 const enum mipi_dsi_pixel_format mipi_fmt) 708 { 709 switch (mipi_fmt) { 710 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 711 case MIPI_DSI_FMT_RGB666_PACKED: 712 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 713 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 714 default: return CMD_DST_FORMAT_RGB888; 715 } 716 } 717 718 static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) 719 { 720 dsi_write(msm_host, REG_DSI_CTRL, 0); 721 } 722 723 bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host) 724 { 725 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 726 727 return msm_host->dsc && 728 (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && 729 msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0); 730 } 731 732 static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, 733 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 734 { 735 u32 flags = msm_host->mode_flags; 736 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 737 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 738 u32 data = 0, lane_ctrl = 0; 739 740 if (flags & MIPI_DSI_MODE_VIDEO) { 741 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 742 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 743 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 744 data |= DSI_VID_CFG0_HFP_POWER_STOP; 745 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 746 data |= DSI_VID_CFG0_HBP_POWER_STOP; 747 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 748 data |= DSI_VID_CFG0_HSA_POWER_STOP; 749 /* Always set low power stop mode for BLLP 750 * to let command engine send packets 751 */ 752 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 753 DSI_VID_CFG0_BLLP_POWER_STOP; 754 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 755 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 756 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 757 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 758 data |= DSI_VID_CFG0_DATABUS_WIDEN; 759 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 760 761 /* Do not swap RGB colors */ 762 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 763 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 764 } else { 765 /* Do not swap RGB colors */ 766 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 767 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 768 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 769 770 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 771 DSI_CMD_CFG1_WR_MEM_CONTINUE( 772 MIPI_DCS_WRITE_MEMORY_CONTINUE); 773 /* Always insert DCS command */ 774 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 775 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 776 777 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 778 data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); 779 780 if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) 781 data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; 782 783 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 784 data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; 785 786 dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); 787 } 788 } 789 790 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 791 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 792 DSI_CMD_DMA_CTRL_LOW_POWER); 793 794 data = 0; 795 /* Always assume dedicated TE pin */ 796 data |= DSI_TRIG_CTRL_TE; 797 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 798 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 799 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 800 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 801 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 802 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 803 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 804 805 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 806 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 807 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 808 809 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 810 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 811 phy_shared_timings->clk_pre_inc_by_2) 812 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 813 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 814 815 data = 0; 816 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 817 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 818 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 819 820 /* allow only ack-err-status to generate interrupt */ 821 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 822 823 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 824 825 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 826 827 data = DSI_CTRL_CLK_EN; 828 829 DBG("lane number=%d", msm_host->lanes); 830 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 831 832 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 833 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 834 835 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 836 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 837 838 if (msm_dsi_phy_set_continuous_clock(phy, true)) 839 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 840 841 dsi_write(msm_host, REG_DSI_LANE_CTRL, 842 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 843 } 844 845 data |= DSI_CTRL_ENABLE; 846 847 dsi_write(msm_host, REG_DSI_CTRL, data); 848 849 if (msm_host->cphy_mode) 850 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 851 } 852 853 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) 854 { 855 struct drm_dsc_config *dsc = msm_host->dsc; 856 u32 reg, reg_ctrl, reg_ctrl2; 857 u32 slice_per_intf, total_bytes_per_intf; 858 u32 pkt_per_line; 859 u32 eol_byte_num; 860 u32 bytes_per_pkt; 861 862 /* first calculate dsc parameters and then program 863 * compress mode registers 864 */ 865 slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); 866 867 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 868 bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ 869 870 eol_byte_num = total_bytes_per_intf % 3; 871 872 /* 873 * Typically, pkt_per_line = slice_per_intf * slice_per_pkt. 874 * 875 * Since the current driver only supports slice_per_pkt = 1, 876 * pkt_per_line will be equal to slice per intf for now. 877 */ 878 pkt_per_line = slice_per_intf; 879 880 if (is_cmd_mode) /* packet data type */ 881 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 882 else 883 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 884 885 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 886 * registers have similar offsets, so for below common code use 887 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 888 * 889 * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) 890 */ 891 if (pkt_per_line > 4) 892 drm_warn_once(msm_host->dev, "pkt_per_line too big"); 893 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 894 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 895 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 896 897 if (is_cmd_mode) { 898 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 899 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 900 901 reg_ctrl &= ~0xffff; 902 reg_ctrl |= reg; 903 904 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 905 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 906 907 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 908 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 909 } else { 910 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); 911 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 912 } 913 } 914 915 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 916 { 917 struct drm_display_mode *mode = msm_host->mode; 918 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 919 u32 h_total = mode->htotal; 920 u32 v_total = mode->vtotal; 921 u32 hs_end = mode->hsync_end - mode->hsync_start; 922 u32 vs_end = mode->vsync_end - mode->vsync_start; 923 u32 ha_start = h_total - mode->hsync_start; 924 u32 ha_end = ha_start + mode->hdisplay; 925 u32 va_start = v_total - mode->vsync_start; 926 u32 va_end = va_start + mode->vdisplay; 927 u32 hdisplay = mode->hdisplay; 928 u32 wc; 929 int ret; 930 bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base); 931 932 DBG(""); 933 934 /* 935 * For bonded DSI mode, the current DRM mode has 936 * the complete width of the panel. Since, the complete 937 * panel is driven by two DSI controllers, the horizontal 938 * timings have to be split between the two dsi controllers. 939 * Adjust the DSI host timing values accordingly. 940 */ 941 if (is_bonded_dsi) { 942 h_total /= 2; 943 hs_end /= 2; 944 ha_start /= 2; 945 ha_end /= 2; 946 hdisplay /= 2; 947 } 948 949 if (msm_host->dsc) { 950 struct drm_dsc_config *dsc = msm_host->dsc; 951 u32 bytes_per_pclk; 952 953 /* update dsc params with timing params */ 954 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 955 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 956 mode->hdisplay, mode->vdisplay); 957 return; 958 } 959 960 dsc->pic_width = mode->hdisplay; 961 dsc->pic_height = mode->vdisplay; 962 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 963 964 /* we do the calculations for dsc parameters here so that 965 * panel can use these parameters 966 */ 967 ret = dsi_populate_dsc_params(msm_host, dsc); 968 if (ret) 969 return; 970 971 /* 972 * DPU sends 3 bytes per pclk cycle to DSI. If widebus is 973 * enabled, bus width is extended to 6 bytes. 974 * 975 * Calculate the number of pclks needed to transmit one line of 976 * the compressed data. 977 978 * The back/font porch and pulse width are kept intact. For 979 * VIDEO mode they represent timing parameters rather than 980 * actual data transfer, see the documentation for 981 * dsi_adjust_pclk_for_compression(). For CMD mode they are 982 * unused anyway. 983 */ 984 h_total -= hdisplay; 985 if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 986 bytes_per_pclk = 6; 987 else 988 bytes_per_pclk = 3; 989 990 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk); 991 992 h_total += hdisplay; 993 ha_end = ha_start + hdisplay; 994 } 995 996 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 997 if (msm_host->dsc) 998 dsi_update_dsc_timing(msm_host, false, mode->hdisplay); 999 1000 dsi_write(msm_host, REG_DSI_ACTIVE_H, 1001 DSI_ACTIVE_H_START(ha_start) | 1002 DSI_ACTIVE_H_END(ha_end)); 1003 dsi_write(msm_host, REG_DSI_ACTIVE_V, 1004 DSI_ACTIVE_V_START(va_start) | 1005 DSI_ACTIVE_V_END(va_end)); 1006 dsi_write(msm_host, REG_DSI_TOTAL, 1007 DSI_TOTAL_H_TOTAL(h_total - 1) | 1008 DSI_TOTAL_V_TOTAL(v_total - 1)); 1009 1010 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 1011 DSI_ACTIVE_HSYNC_START(hs_start) | 1012 DSI_ACTIVE_HSYNC_END(hs_end)); 1013 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 1014 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 1015 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1016 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1017 } else { /* command mode */ 1018 if (msm_host->dsc) 1019 dsi_update_dsc_timing(msm_host, true, mode->hdisplay); 1020 1021 /* image data and 1 byte write_memory_start cmd */ 1022 if (!msm_host->dsc) 1023 wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; 1024 else 1025 /* 1026 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. 1027 * Currently, the driver only supports default value of slice_per_pkt = 1 1028 * 1029 * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info 1030 * and adjust DSC math to account for slice_per_pkt. 1031 */ 1032 wc = msm_host->dsc->slice_chunk_size + 1; 1033 1034 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1035 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1036 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1037 msm_host->channel) | 1038 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1039 MIPI_DSI_DCS_LONG_WRITE)); 1040 1041 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1042 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1043 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1044 } 1045 } 1046 1047 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1048 { 1049 u32 ctrl; 1050 1051 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1052 1053 if (ctrl & DSI_CTRL_ENABLE) { 1054 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1055 /* 1056 * dsi controller need to be disabled before 1057 * clocks turned on 1058 */ 1059 wmb(); 1060 } 1061 1062 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1063 wmb(); /* clocks need to be enabled before reset */ 1064 1065 /* dsi controller can only be reset while clocks are running */ 1066 dsi_write(msm_host, REG_DSI_RESET, 1); 1067 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1068 dsi_write(msm_host, REG_DSI_RESET, 0); 1069 wmb(); /* controller out of reset */ 1070 1071 if (ctrl & DSI_CTRL_ENABLE) { 1072 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1073 wmb(); /* make sure dsi controller enabled again */ 1074 } 1075 } 1076 1077 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1078 bool video_mode, bool enable) 1079 { 1080 u32 dsi_ctrl; 1081 1082 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1083 1084 if (!enable) { 1085 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1086 DSI_CTRL_CMD_MODE_EN); 1087 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1088 DSI_IRQ_MASK_VIDEO_DONE, 0); 1089 } else { 1090 if (video_mode) { 1091 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1092 } else { /* command mode */ 1093 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1094 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1095 } 1096 dsi_ctrl |= DSI_CTRL_ENABLE; 1097 } 1098 1099 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1100 } 1101 1102 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1103 { 1104 u32 data; 1105 1106 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1107 1108 if (mode == 0) 1109 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1110 else 1111 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1112 1113 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1114 } 1115 1116 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1117 { 1118 u32 ret = 0; 1119 struct device *dev = &msm_host->pdev->dev; 1120 1121 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1122 1123 reinit_completion(&msm_host->video_comp); 1124 1125 ret = wait_for_completion_timeout(&msm_host->video_comp, 1126 msecs_to_jiffies(70)); 1127 1128 if (ret == 0) 1129 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1130 1131 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1132 } 1133 1134 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1135 { 1136 u32 data; 1137 1138 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1139 return; 1140 1141 data = dsi_read(msm_host, REG_DSI_STATUS0); 1142 1143 /* if video mode engine is not busy, its because 1144 * either timing engine was not turned on or the 1145 * DSI controller has finished transmitting the video 1146 * data already, so no need to wait in those cases 1147 */ 1148 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1149 return; 1150 1151 if (msm_host->power_on && msm_host->enabled) { 1152 dsi_wait4video_done(msm_host); 1153 /* delay 4 ms to skip BLLP */ 1154 usleep_range(2000, 4000); 1155 } 1156 } 1157 1158 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1159 { 1160 struct drm_device *dev = msm_host->dev; 1161 struct msm_drm_private *priv = dev->dev_private; 1162 uint64_t iova; 1163 u8 *data; 1164 1165 msm_host->aspace = msm_gem_address_space_get(priv->kms->aspace); 1166 1167 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1168 msm_host->aspace, 1169 &msm_host->tx_gem_obj, &iova); 1170 1171 if (IS_ERR(data)) { 1172 msm_host->tx_gem_obj = NULL; 1173 return PTR_ERR(data); 1174 } 1175 1176 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1177 1178 msm_host->tx_size = msm_host->tx_gem_obj->size; 1179 1180 return 0; 1181 } 1182 1183 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1184 { 1185 struct drm_device *dev = msm_host->dev; 1186 1187 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1188 &msm_host->tx_buf_paddr, GFP_KERNEL); 1189 if (!msm_host->tx_buf) 1190 return -ENOMEM; 1191 1192 msm_host->tx_size = size; 1193 1194 return 0; 1195 } 1196 1197 void msm_dsi_tx_buf_free(struct mipi_dsi_host *host) 1198 { 1199 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1200 struct drm_device *dev = msm_host->dev; 1201 1202 /* 1203 * This is possible if we're tearing down before we've had a chance to 1204 * fully initialize. A very real possibility if our probe is deferred, 1205 * in which case we'll hit msm_dsi_host_destroy() without having run 1206 * through the dsi_tx_buf_alloc(). 1207 */ 1208 if (!dev) 1209 return; 1210 1211 if (msm_host->tx_gem_obj) { 1212 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->aspace); 1213 msm_gem_address_space_put(msm_host->aspace); 1214 msm_host->tx_gem_obj = NULL; 1215 msm_host->aspace = NULL; 1216 } 1217 1218 if (msm_host->tx_buf) 1219 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1220 msm_host->tx_buf_paddr); 1221 } 1222 1223 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1224 { 1225 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1226 } 1227 1228 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1229 { 1230 return msm_host->tx_buf; 1231 } 1232 1233 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1234 { 1235 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1236 } 1237 1238 /* 1239 * prepare cmd buffer to be txed 1240 */ 1241 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1242 const struct mipi_dsi_msg *msg) 1243 { 1244 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1245 struct mipi_dsi_packet packet; 1246 int len; 1247 int ret; 1248 u8 *data; 1249 1250 ret = mipi_dsi_create_packet(&packet, msg); 1251 if (ret) { 1252 pr_err("%s: create packet failed, %d\n", __func__, ret); 1253 return ret; 1254 } 1255 len = (packet.size + 3) & (~0x3); 1256 1257 if (len > msm_host->tx_size) { 1258 pr_err("%s: packet size is too big\n", __func__); 1259 return -EINVAL; 1260 } 1261 1262 data = cfg_hnd->ops->tx_buf_get(msm_host); 1263 if (IS_ERR(data)) { 1264 ret = PTR_ERR(data); 1265 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1266 return ret; 1267 } 1268 1269 /* MSM specific command format in memory */ 1270 data[0] = packet.header[1]; 1271 data[1] = packet.header[2]; 1272 data[2] = packet.header[0]; 1273 data[3] = BIT(7); /* Last packet */ 1274 if (mipi_dsi_packet_format_is_long(msg->type)) 1275 data[3] |= BIT(6); 1276 if (msg->rx_buf && msg->rx_len) 1277 data[3] |= BIT(5); 1278 1279 /* Long packet */ 1280 if (packet.payload && packet.payload_length) 1281 memcpy(data + 4, packet.payload, packet.payload_length); 1282 1283 /* Append 0xff to the end */ 1284 if (packet.size < len) 1285 memset(data + packet.size, 0xff, len - packet.size); 1286 1287 if (cfg_hnd->ops->tx_buf_put) 1288 cfg_hnd->ops->tx_buf_put(msm_host); 1289 1290 return len; 1291 } 1292 1293 /* 1294 * dsi_short_read1_resp: 1 parameter 1295 */ 1296 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1297 { 1298 u8 *data = msg->rx_buf; 1299 if (data && (msg->rx_len >= 1)) { 1300 *data = buf[1]; /* strip out dcs type */ 1301 return 1; 1302 } else { 1303 pr_err("%s: read data does not match with rx_buf len %zu\n", 1304 __func__, msg->rx_len); 1305 return -EINVAL; 1306 } 1307 } 1308 1309 /* 1310 * dsi_short_read2_resp: 2 parameter 1311 */ 1312 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1313 { 1314 u8 *data = msg->rx_buf; 1315 if (data && (msg->rx_len >= 2)) { 1316 data[0] = buf[1]; /* strip out dcs type */ 1317 data[1] = buf[2]; 1318 return 2; 1319 } else { 1320 pr_err("%s: read data does not match with rx_buf len %zu\n", 1321 __func__, msg->rx_len); 1322 return -EINVAL; 1323 } 1324 } 1325 1326 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1327 { 1328 /* strip out 4 byte dcs header */ 1329 if (msg->rx_buf && msg->rx_len) 1330 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1331 1332 return msg->rx_len; 1333 } 1334 1335 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1336 { 1337 struct drm_device *dev = msm_host->dev; 1338 struct msm_drm_private *priv = dev->dev_private; 1339 1340 if (!dma_base) 1341 return -EINVAL; 1342 1343 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1344 priv->kms->aspace, dma_base); 1345 } 1346 1347 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1348 { 1349 if (!dma_base) 1350 return -EINVAL; 1351 1352 *dma_base = msm_host->tx_buf_paddr; 1353 return 0; 1354 } 1355 1356 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1357 { 1358 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1359 int ret; 1360 uint64_t dma_base; 1361 bool triggered; 1362 1363 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1364 if (ret) { 1365 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1366 return ret; 1367 } 1368 1369 reinit_completion(&msm_host->dma_comp); 1370 1371 dsi_wait4video_eng_busy(msm_host); 1372 1373 triggered = msm_dsi_manager_cmd_xfer_trigger( 1374 msm_host->id, dma_base, len); 1375 if (triggered) { 1376 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1377 msecs_to_jiffies(200)); 1378 DBG("ret=%d", ret); 1379 if (ret == 0) 1380 ret = -ETIMEDOUT; 1381 else 1382 ret = len; 1383 } else 1384 ret = len; 1385 1386 return ret; 1387 } 1388 1389 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1390 u8 *buf, int rx_byte, int pkt_size) 1391 { 1392 u32 *temp, data; 1393 int i, j = 0, cnt; 1394 u32 read_cnt; 1395 u8 reg[16]; 1396 int repeated_bytes = 0; 1397 int buf_offset = buf - msm_host->rx_buf; 1398 1399 temp = (u32 *)reg; 1400 cnt = (rx_byte + 3) >> 2; 1401 if (cnt > 4) 1402 cnt = 4; /* 4 x 32 bits registers only */ 1403 1404 if (rx_byte == 4) 1405 read_cnt = 4; 1406 else 1407 read_cnt = pkt_size + 6; 1408 1409 /* 1410 * In case of multiple reads from the panel, after the first read, there 1411 * is possibility that there are some bytes in the payload repeating in 1412 * the RDBK_DATA registers. Since we read all the parameters from the 1413 * panel right from the first byte for every pass. We need to skip the 1414 * repeating bytes and then append the new parameters to the rx buffer. 1415 */ 1416 if (read_cnt > 16) { 1417 int bytes_shifted; 1418 /* Any data more than 16 bytes will be shifted out. 1419 * The temp read buffer should already contain these bytes. 1420 * The remaining bytes in read buffer are the repeated bytes. 1421 */ 1422 bytes_shifted = read_cnt - 16; 1423 repeated_bytes = buf_offset - bytes_shifted; 1424 } 1425 1426 for (i = cnt - 1; i >= 0; i--) { 1427 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1428 *temp++ = ntohl(data); /* to host byte order */ 1429 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1430 } 1431 1432 for (i = repeated_bytes; i < 16; i++) 1433 buf[j++] = reg[i]; 1434 1435 return j; 1436 } 1437 1438 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1439 const struct mipi_dsi_msg *msg) 1440 { 1441 int len, ret; 1442 int bllp_len = msm_host->mode->hdisplay * 1443 mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; 1444 1445 len = dsi_cmd_dma_add(msm_host, msg); 1446 if (len < 0) { 1447 pr_err("%s: failed to add cmd type = 0x%x\n", 1448 __func__, msg->type); 1449 return len; 1450 } 1451 1452 /* for video mode, do not send cmds more than 1453 * one pixel line, since it only transmit it 1454 * during BLLP. 1455 */ 1456 /* TODO: if the command is sent in LP mode, the bit rate is only 1457 * half of esc clk rate. In this case, if the video is already 1458 * actively streaming, we need to check more carefully if the 1459 * command can be fit into one BLLP. 1460 */ 1461 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1462 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1463 __func__, len); 1464 return -EINVAL; 1465 } 1466 1467 ret = dsi_cmd_dma_tx(msm_host, len); 1468 if (ret < 0) { 1469 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1470 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1471 return ret; 1472 } else if (ret < len) { 1473 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1474 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1475 return -EIO; 1476 } 1477 1478 return len; 1479 } 1480 1481 static void dsi_err_worker(struct work_struct *work) 1482 { 1483 struct msm_dsi_host *msm_host = 1484 container_of(work, struct msm_dsi_host, err_work); 1485 u32 status = msm_host->err_work_state; 1486 1487 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1488 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1489 dsi_sw_reset(msm_host); 1490 1491 /* It is safe to clear here because error irq is disabled. */ 1492 msm_host->err_work_state = 0; 1493 1494 /* enable dsi error interrupt */ 1495 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1496 } 1497 1498 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1499 { 1500 u32 status; 1501 1502 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1503 1504 if (status) { 1505 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1506 /* Writing of an extra 0 needed to clear error bits */ 1507 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1508 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1509 } 1510 } 1511 1512 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1513 { 1514 u32 status; 1515 1516 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1517 1518 if (status) { 1519 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1520 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1521 } 1522 } 1523 1524 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1525 { 1526 u32 status; 1527 1528 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1529 1530 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1531 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1532 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1533 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1534 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1535 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1536 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1537 } 1538 } 1539 1540 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1541 { 1542 u32 status; 1543 1544 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1545 1546 /* fifo underflow, overflow */ 1547 if (status) { 1548 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1549 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1550 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1551 msm_host->err_work_state |= 1552 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1553 } 1554 } 1555 1556 static void dsi_status(struct msm_dsi_host *msm_host) 1557 { 1558 u32 status; 1559 1560 status = dsi_read(msm_host, REG_DSI_STATUS0); 1561 1562 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1563 dsi_write(msm_host, REG_DSI_STATUS0, status); 1564 msm_host->err_work_state |= 1565 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1566 } 1567 } 1568 1569 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1570 { 1571 u32 status; 1572 1573 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1574 1575 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1576 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1577 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1578 } 1579 } 1580 1581 static void dsi_error(struct msm_dsi_host *msm_host) 1582 { 1583 /* disable dsi error interrupt */ 1584 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1585 1586 dsi_clk_status(msm_host); 1587 dsi_fifo_status(msm_host); 1588 dsi_ack_err_status(msm_host); 1589 dsi_timeout_status(msm_host); 1590 dsi_status(msm_host); 1591 dsi_dln0_phy_err(msm_host); 1592 1593 queue_work(msm_host->workqueue, &msm_host->err_work); 1594 } 1595 1596 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1597 { 1598 struct msm_dsi_host *msm_host = ptr; 1599 u32 isr; 1600 unsigned long flags; 1601 1602 if (!msm_host->ctrl_base) 1603 return IRQ_HANDLED; 1604 1605 spin_lock_irqsave(&msm_host->intr_lock, flags); 1606 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1607 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1608 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1609 1610 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1611 1612 if (isr & DSI_IRQ_ERROR) 1613 dsi_error(msm_host); 1614 1615 if (isr & DSI_IRQ_VIDEO_DONE) 1616 complete(&msm_host->video_comp); 1617 1618 if (isr & DSI_IRQ_CMD_DMA_DONE) 1619 complete(&msm_host->dma_comp); 1620 1621 return IRQ_HANDLED; 1622 } 1623 1624 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1625 struct device *panel_device) 1626 { 1627 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1628 "disp-enable", 1629 GPIOD_OUT_LOW); 1630 if (IS_ERR(msm_host->disp_en_gpio)) { 1631 DBG("cannot get disp-enable-gpios %ld", 1632 PTR_ERR(msm_host->disp_en_gpio)); 1633 return PTR_ERR(msm_host->disp_en_gpio); 1634 } 1635 1636 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1637 GPIOD_IN); 1638 if (IS_ERR(msm_host->te_gpio)) { 1639 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1640 return PTR_ERR(msm_host->te_gpio); 1641 } 1642 1643 return 0; 1644 } 1645 1646 static int dsi_host_attach(struct mipi_dsi_host *host, 1647 struct mipi_dsi_device *dsi) 1648 { 1649 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1650 int ret; 1651 1652 if (dsi->lanes > msm_host->num_data_lanes) 1653 return -EINVAL; 1654 1655 msm_host->channel = dsi->channel; 1656 msm_host->lanes = dsi->lanes; 1657 msm_host->format = dsi->format; 1658 msm_host->mode_flags = dsi->mode_flags; 1659 if (dsi->dsc) 1660 msm_host->dsc = dsi->dsc; 1661 1662 /* Some gpios defined in panel DT need to be controlled by host */ 1663 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1664 if (ret) 1665 return ret; 1666 1667 ret = dsi_dev_attach(msm_host->pdev); 1668 if (ret) 1669 return ret; 1670 1671 DBG("id=%d", msm_host->id); 1672 1673 return 0; 1674 } 1675 1676 static int dsi_host_detach(struct mipi_dsi_host *host, 1677 struct mipi_dsi_device *dsi) 1678 { 1679 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1680 1681 dsi_dev_detach(msm_host->pdev); 1682 1683 DBG("id=%d", msm_host->id); 1684 1685 return 0; 1686 } 1687 1688 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1689 const struct mipi_dsi_msg *msg) 1690 { 1691 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1692 int ret; 1693 1694 if (!msg || !msm_host->power_on) 1695 return -EINVAL; 1696 1697 mutex_lock(&msm_host->cmd_mutex); 1698 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1699 mutex_unlock(&msm_host->cmd_mutex); 1700 1701 return ret; 1702 } 1703 1704 static const struct mipi_dsi_host_ops dsi_host_ops = { 1705 .attach = dsi_host_attach, 1706 .detach = dsi_host_detach, 1707 .transfer = dsi_host_transfer, 1708 }; 1709 1710 /* 1711 * List of supported physical to logical lane mappings. 1712 * For example, the 2nd entry represents the following mapping: 1713 * 1714 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1715 */ 1716 static const int supported_data_lane_swaps[][4] = { 1717 { 0, 1, 2, 3 }, 1718 { 3, 0, 1, 2 }, 1719 { 2, 3, 0, 1 }, 1720 { 1, 2, 3, 0 }, 1721 { 0, 3, 2, 1 }, 1722 { 1, 0, 3, 2 }, 1723 { 2, 1, 0, 3 }, 1724 { 3, 2, 1, 0 }, 1725 }; 1726 1727 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1728 struct device_node *ep) 1729 { 1730 struct device *dev = &msm_host->pdev->dev; 1731 struct property *prop; 1732 u32 lane_map[4]; 1733 int ret, i, len, num_lanes; 1734 1735 prop = of_find_property(ep, "data-lanes", &len); 1736 if (!prop) { 1737 DRM_DEV_DEBUG(dev, 1738 "failed to find data lane mapping, using default\n"); 1739 /* Set the number of date lanes to 4 by default. */ 1740 msm_host->num_data_lanes = 4; 1741 return 0; 1742 } 1743 1744 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1745 if (num_lanes < 0) { 1746 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1747 return num_lanes; 1748 } 1749 1750 msm_host->num_data_lanes = num_lanes; 1751 1752 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1753 num_lanes); 1754 if (ret) { 1755 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1756 return ret; 1757 } 1758 1759 /* 1760 * compare DT specified physical-logical lane mappings with the ones 1761 * supported by hardware 1762 */ 1763 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1764 const int *swap = supported_data_lane_swaps[i]; 1765 int j; 1766 1767 /* 1768 * the data-lanes array we get from DT has a logical->physical 1769 * mapping. The "data lane swap" register field represents 1770 * supported configurations in a physical->logical mapping. 1771 * Translate the DT mapping to what we understand and find a 1772 * configuration that works. 1773 */ 1774 for (j = 0; j < num_lanes; j++) { 1775 if (lane_map[j] < 0 || lane_map[j] > 3) 1776 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1777 lane_map[j]); 1778 1779 if (swap[lane_map[j]] != j) 1780 break; 1781 } 1782 1783 if (j == num_lanes) { 1784 msm_host->dlane_swap = i; 1785 return 0; 1786 } 1787 } 1788 1789 return -EINVAL; 1790 } 1791 1792 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1793 { 1794 int ret; 1795 1796 if (dsc->bits_per_pixel & 0xf) { 1797 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1798 return -EINVAL; 1799 } 1800 1801 if (dsc->bits_per_component != 8) { 1802 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n"); 1803 return -EOPNOTSUPP; 1804 } 1805 1806 dsc->simple_422 = 0; 1807 dsc->convert_rgb = 1; 1808 dsc->vbr_enable = 0; 1809 1810 drm_dsc_set_const_params(dsc); 1811 drm_dsc_set_rc_buf_thresh(dsc); 1812 1813 /* handle only bpp = bpc = 8, pre-SCR panels */ 1814 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); 1815 if (ret) { 1816 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); 1817 return ret; 1818 } 1819 1820 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); 1821 dsc->line_buf_depth = dsc->bits_per_component + 1; 1822 1823 return drm_dsc_compute_rc_parameters(dsc); 1824 } 1825 1826 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1827 { 1828 struct device *dev = &msm_host->pdev->dev; 1829 struct device_node *np = dev->of_node; 1830 struct device_node *endpoint; 1831 int ret = 0; 1832 1833 /* 1834 * Get the endpoint of the output port of the DSI host. In our case, 1835 * this is mapped to port number with reg = 1. Don't return an error if 1836 * the remote endpoint isn't defined. It's possible that there is 1837 * nothing connected to the dsi output. 1838 */ 1839 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1840 if (!endpoint) { 1841 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1842 return 0; 1843 } 1844 1845 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1846 if (ret) { 1847 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1848 __func__, ret); 1849 ret = -EINVAL; 1850 goto err; 1851 } 1852 1853 if (of_property_read_bool(np, "syscon-sfpb")) { 1854 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1855 "syscon-sfpb"); 1856 if (IS_ERR(msm_host->sfpb)) { 1857 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1858 __func__); 1859 ret = PTR_ERR(msm_host->sfpb); 1860 } 1861 } 1862 1863 err: 1864 of_node_put(endpoint); 1865 1866 return ret; 1867 } 1868 1869 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1870 { 1871 struct platform_device *pdev = msm_host->pdev; 1872 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1873 struct resource *res; 1874 int i, j; 1875 1876 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1877 if (!res) 1878 return -EINVAL; 1879 1880 for (i = 0; i < VARIANTS_MAX; i++) 1881 for (j = 0; j < DSI_MAX; j++) 1882 if (cfg->io_start[i][j] == res->start) 1883 return j; 1884 1885 return -EINVAL; 1886 } 1887 1888 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1889 { 1890 struct msm_dsi_host *msm_host = NULL; 1891 struct platform_device *pdev = msm_dsi->pdev; 1892 const struct msm_dsi_config *cfg; 1893 int ret; 1894 1895 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1896 if (!msm_host) { 1897 return -ENOMEM; 1898 } 1899 1900 msm_host->pdev = pdev; 1901 msm_dsi->host = &msm_host->base; 1902 1903 ret = dsi_host_parse_dt(msm_host); 1904 if (ret) { 1905 pr_err("%s: failed to parse dt\n", __func__); 1906 return ret; 1907 } 1908 1909 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 1910 if (IS_ERR(msm_host->ctrl_base)) { 1911 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1912 return PTR_ERR(msm_host->ctrl_base); 1913 } 1914 1915 pm_runtime_enable(&pdev->dev); 1916 1917 msm_host->cfg_hnd = dsi_get_config(msm_host); 1918 if (!msm_host->cfg_hnd) { 1919 pr_err("%s: get config failed\n", __func__); 1920 return -EINVAL; 1921 } 1922 cfg = msm_host->cfg_hnd->cfg; 1923 1924 msm_host->id = dsi_host_get_id(msm_host); 1925 if (msm_host->id < 0) { 1926 pr_err("%s: unable to identify DSI host index\n", __func__); 1927 return msm_host->id; 1928 } 1929 1930 /* fixup base address by io offset */ 1931 msm_host->ctrl_base += cfg->io_offset; 1932 1933 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 1934 cfg->regulator_data, 1935 &msm_host->supplies); 1936 if (ret) 1937 return ret; 1938 1939 ret = dsi_clk_init(msm_host); 1940 if (ret) { 1941 pr_err("%s: unable to initialize dsi clks\n", __func__); 1942 return ret; 1943 } 1944 1945 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1946 if (!msm_host->rx_buf) { 1947 pr_err("%s: alloc rx temp buf failed\n", __func__); 1948 return -ENOMEM; 1949 } 1950 1951 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 1952 if (ret) 1953 return ret; 1954 /* OPP table is optional */ 1955 ret = devm_pm_opp_of_add_table(&pdev->dev); 1956 if (ret && ret != -ENODEV) { 1957 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1958 return ret; 1959 } 1960 1961 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1962 if (!msm_host->irq) { 1963 dev_err(&pdev->dev, "failed to get irq\n"); 1964 return -EINVAL; 1965 } 1966 1967 /* do not autoenable, will be enabled later */ 1968 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 1969 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 1970 "dsi_isr", msm_host); 1971 if (ret < 0) { 1972 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1973 msm_host->irq, ret); 1974 return ret; 1975 } 1976 1977 init_completion(&msm_host->dma_comp); 1978 init_completion(&msm_host->video_comp); 1979 mutex_init(&msm_host->dev_mutex); 1980 mutex_init(&msm_host->cmd_mutex); 1981 spin_lock_init(&msm_host->intr_lock); 1982 1983 /* setup workqueue */ 1984 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1985 if (!msm_host->workqueue) 1986 return -ENOMEM; 1987 1988 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1989 1990 msm_dsi->id = msm_host->id; 1991 1992 DBG("Dsi Host %d initialized", msm_host->id); 1993 return 0; 1994 } 1995 1996 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1997 { 1998 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1999 2000 DBG(""); 2001 if (msm_host->workqueue) { 2002 destroy_workqueue(msm_host->workqueue); 2003 msm_host->workqueue = NULL; 2004 } 2005 2006 mutex_destroy(&msm_host->cmd_mutex); 2007 mutex_destroy(&msm_host->dev_mutex); 2008 2009 pm_runtime_disable(&msm_host->pdev->dev); 2010 } 2011 2012 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 2013 struct drm_device *dev) 2014 { 2015 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2016 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2017 int ret; 2018 2019 msm_host->dev = dev; 2020 2021 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2022 if (ret) { 2023 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2024 return ret; 2025 } 2026 2027 return 0; 2028 } 2029 2030 int msm_dsi_host_register(struct mipi_dsi_host *host) 2031 { 2032 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2033 int ret; 2034 2035 /* Register mipi dsi host */ 2036 if (!msm_host->registered) { 2037 host->dev = &msm_host->pdev->dev; 2038 host->ops = &dsi_host_ops; 2039 ret = mipi_dsi_host_register(host); 2040 if (ret) 2041 return ret; 2042 2043 msm_host->registered = true; 2044 } 2045 2046 return 0; 2047 } 2048 2049 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2050 { 2051 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2052 2053 if (msm_host->registered) { 2054 mipi_dsi_host_unregister(host); 2055 host->dev = NULL; 2056 host->ops = NULL; 2057 msm_host->registered = false; 2058 } 2059 } 2060 2061 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2062 const struct mipi_dsi_msg *msg) 2063 { 2064 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2065 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2066 2067 /* TODO: make sure dsi_cmd_mdp is idle. 2068 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2069 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2070 * How to handle the old versions? Wait for mdp cmd done? 2071 */ 2072 2073 /* 2074 * mdss interrupt is generated in mdp core clock domain 2075 * mdp clock need to be enabled to receive dsi interrupt 2076 */ 2077 pm_runtime_get_sync(&msm_host->pdev->dev); 2078 cfg_hnd->ops->link_clk_set_rate(msm_host); 2079 cfg_hnd->ops->link_clk_enable(msm_host); 2080 2081 /* TODO: vote for bus bandwidth */ 2082 2083 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2084 dsi_set_tx_power_mode(0, msm_host); 2085 2086 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2087 dsi_write(msm_host, REG_DSI_CTRL, 2088 msm_host->dma_cmd_ctrl_restore | 2089 DSI_CTRL_CMD_MODE_EN | 2090 DSI_CTRL_ENABLE); 2091 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2092 2093 return 0; 2094 } 2095 2096 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2097 const struct mipi_dsi_msg *msg) 2098 { 2099 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2100 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2101 2102 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2103 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2104 2105 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2106 dsi_set_tx_power_mode(1, msm_host); 2107 2108 /* TODO: unvote for bus bandwidth */ 2109 2110 cfg_hnd->ops->link_clk_disable(msm_host); 2111 pm_runtime_put(&msm_host->pdev->dev); 2112 } 2113 2114 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2115 const struct mipi_dsi_msg *msg) 2116 { 2117 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2118 2119 return dsi_cmds2buf_tx(msm_host, msg); 2120 } 2121 2122 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2123 const struct mipi_dsi_msg *msg) 2124 { 2125 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2126 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2127 int data_byte, rx_byte, dlen, end; 2128 int short_response, diff, pkt_size, ret = 0; 2129 char cmd; 2130 int rlen = msg->rx_len; 2131 u8 *buf; 2132 2133 if (rlen <= 2) { 2134 short_response = 1; 2135 pkt_size = rlen; 2136 rx_byte = 4; 2137 } else { 2138 short_response = 0; 2139 data_byte = 10; /* first read */ 2140 if (rlen < data_byte) 2141 pkt_size = rlen; 2142 else 2143 pkt_size = data_byte; 2144 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2145 } 2146 2147 buf = msm_host->rx_buf; 2148 end = 0; 2149 while (!end) { 2150 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2151 struct mipi_dsi_msg max_pkt_size_msg = { 2152 .channel = msg->channel, 2153 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2154 .tx_len = 2, 2155 .tx_buf = tx, 2156 }; 2157 2158 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2159 rlen, pkt_size, rx_byte); 2160 2161 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2162 if (ret < 2) { 2163 pr_err("%s: Set max pkt size failed, %d\n", 2164 __func__, ret); 2165 return -EINVAL; 2166 } 2167 2168 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2169 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2170 /* Clear the RDBK_DATA registers */ 2171 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2172 DSI_RDBK_DATA_CTRL_CLR); 2173 wmb(); /* make sure the RDBK registers are cleared */ 2174 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2175 wmb(); /* release cleared status before transfer */ 2176 } 2177 2178 ret = dsi_cmds2buf_tx(msm_host, msg); 2179 if (ret < 0) { 2180 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2181 return ret; 2182 } else if (ret < msg->tx_len) { 2183 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2184 return -ECOMM; 2185 } 2186 2187 /* 2188 * once cmd_dma_done interrupt received, 2189 * return data from client is ready and stored 2190 * at RDBK_DATA register already 2191 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2192 * after that dcs header lost during shift into registers 2193 */ 2194 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2195 2196 if (dlen <= 0) 2197 return 0; 2198 2199 if (short_response) 2200 break; 2201 2202 if (rlen <= data_byte) { 2203 diff = data_byte - rlen; 2204 end = 1; 2205 } else { 2206 diff = 0; 2207 rlen -= data_byte; 2208 } 2209 2210 if (!end) { 2211 dlen -= 2; /* 2 crc */ 2212 dlen -= diff; 2213 buf += dlen; /* next start position */ 2214 data_byte = 14; /* NOT first read */ 2215 if (rlen < data_byte) 2216 pkt_size += rlen; 2217 else 2218 pkt_size += data_byte; 2219 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2220 } 2221 } 2222 2223 /* 2224 * For single Long read, if the requested rlen < 10, 2225 * we need to shift the start position of rx 2226 * data buffer to skip the bytes which are not 2227 * updated. 2228 */ 2229 if (pkt_size < 10 && !short_response) 2230 buf = msm_host->rx_buf + (10 - rlen); 2231 else 2232 buf = msm_host->rx_buf; 2233 2234 cmd = buf[0]; 2235 switch (cmd) { 2236 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2237 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2238 ret = 0; 2239 break; 2240 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2241 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2242 ret = dsi_short_read1_resp(buf, msg); 2243 break; 2244 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2245 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2246 ret = dsi_short_read2_resp(buf, msg); 2247 break; 2248 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2249 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2250 ret = dsi_long_read_resp(buf, msg); 2251 break; 2252 default: 2253 pr_warn("%s:Invalid response cmd\n", __func__); 2254 ret = 0; 2255 } 2256 2257 return ret; 2258 } 2259 2260 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2261 u32 len) 2262 { 2263 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2264 2265 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2266 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2267 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2268 2269 /* Make sure trigger happens */ 2270 wmb(); 2271 } 2272 2273 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2274 struct msm_dsi_phy *src_phy) 2275 { 2276 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2277 2278 msm_host->cphy_mode = src_phy->cphy_mode; 2279 } 2280 2281 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2282 { 2283 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2284 2285 DBG(""); 2286 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2287 /* Make sure fully reset */ 2288 wmb(); 2289 udelay(1000); 2290 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2291 udelay(100); 2292 } 2293 2294 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2295 struct msm_dsi_phy_clk_request *clk_req, 2296 bool is_bonded_dsi) 2297 { 2298 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2299 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2300 int ret; 2301 2302 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2303 if (ret) { 2304 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2305 return; 2306 } 2307 2308 /* CPHY transmits 16 bits over 7 clock cycles 2309 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2310 * so multiply by 7 to get the "bitclk rate" 2311 */ 2312 if (msm_host->cphy_mode) 2313 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2314 else 2315 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2316 clk_req->escclk_rate = msm_host->esc_clk_rate; 2317 } 2318 2319 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2320 { 2321 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2322 2323 enable_irq(msm_host->irq); 2324 } 2325 2326 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2327 { 2328 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2329 2330 disable_irq(msm_host->irq); 2331 } 2332 2333 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2334 { 2335 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2336 2337 dsi_op_mode_config(msm_host, 2338 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2339 2340 /* TODO: clock should be turned off for command mode, 2341 * and only turned on before MDP START. 2342 * This part of code should be enabled once mdp driver support it. 2343 */ 2344 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2345 * dsi_link_clk_disable(msm_host); 2346 * pm_runtime_put(&msm_host->pdev->dev); 2347 * } 2348 */ 2349 msm_host->enabled = true; 2350 return 0; 2351 } 2352 2353 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2354 { 2355 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2356 2357 msm_host->enabled = false; 2358 dsi_op_mode_config(msm_host, 2359 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2360 2361 /* Since we have disabled INTF, the video engine won't stop so that 2362 * the cmd engine will be blocked. 2363 * Reset to disable video engine so that we can send off cmd. 2364 */ 2365 dsi_sw_reset(msm_host); 2366 2367 return 0; 2368 } 2369 2370 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2371 { 2372 enum sfpb_ahb_arb_master_port_en en; 2373 2374 if (!msm_host->sfpb) 2375 return; 2376 2377 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2378 2379 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2380 SFPB_GPREG_MASTER_PORT_EN__MASK, 2381 SFPB_GPREG_MASTER_PORT_EN(en)); 2382 } 2383 2384 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2385 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2386 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2387 { 2388 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2389 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2390 int ret = 0; 2391 2392 mutex_lock(&msm_host->dev_mutex); 2393 if (msm_host->power_on) { 2394 DBG("dsi host already on"); 2395 goto unlock_ret; 2396 } 2397 2398 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; 2399 if (phy_shared_timings->byte_intf_clk_div_2) 2400 msm_host->byte_intf_clk_rate /= 2; 2401 2402 msm_dsi_sfpb_config(msm_host, true); 2403 2404 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2405 msm_host->supplies); 2406 if (ret) { 2407 pr_err("%s:Failed to enable vregs.ret=%d\n", 2408 __func__, ret); 2409 goto unlock_ret; 2410 } 2411 2412 pm_runtime_get_sync(&msm_host->pdev->dev); 2413 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2414 if (!ret) 2415 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2416 if (ret) { 2417 pr_err("%s: failed to enable link clocks. ret=%d\n", 2418 __func__, ret); 2419 goto fail_disable_reg; 2420 } 2421 2422 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2423 if (ret) { 2424 pr_err("%s: failed to set pinctrl default state, %d\n", 2425 __func__, ret); 2426 goto fail_disable_clk; 2427 } 2428 2429 dsi_timing_setup(msm_host, is_bonded_dsi); 2430 dsi_sw_reset(msm_host); 2431 dsi_ctrl_enable(msm_host, phy_shared_timings, phy); 2432 2433 if (msm_host->disp_en_gpio) 2434 gpiod_set_value(msm_host->disp_en_gpio, 1); 2435 2436 msm_host->power_on = true; 2437 mutex_unlock(&msm_host->dev_mutex); 2438 2439 return 0; 2440 2441 fail_disable_clk: 2442 cfg_hnd->ops->link_clk_disable(msm_host); 2443 pm_runtime_put(&msm_host->pdev->dev); 2444 fail_disable_reg: 2445 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2446 msm_host->supplies); 2447 unlock_ret: 2448 mutex_unlock(&msm_host->dev_mutex); 2449 return ret; 2450 } 2451 2452 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2453 { 2454 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2455 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2456 2457 mutex_lock(&msm_host->dev_mutex); 2458 if (!msm_host->power_on) { 2459 DBG("dsi host already off"); 2460 goto unlock_ret; 2461 } 2462 2463 dsi_ctrl_disable(msm_host); 2464 2465 if (msm_host->disp_en_gpio) 2466 gpiod_set_value(msm_host->disp_en_gpio, 0); 2467 2468 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2469 2470 cfg_hnd->ops->link_clk_disable(msm_host); 2471 pm_runtime_put(&msm_host->pdev->dev); 2472 2473 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2474 msm_host->supplies); 2475 2476 msm_dsi_sfpb_config(msm_host, false); 2477 2478 DBG("-"); 2479 2480 msm_host->power_on = false; 2481 2482 unlock_ret: 2483 mutex_unlock(&msm_host->dev_mutex); 2484 return 0; 2485 } 2486 2487 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2488 const struct drm_display_mode *mode) 2489 { 2490 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2491 2492 if (msm_host->mode) { 2493 drm_mode_destroy(msm_host->dev, msm_host->mode); 2494 msm_host->mode = NULL; 2495 } 2496 2497 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2498 if (!msm_host->mode) { 2499 pr_err("%s: cannot duplicate mode\n", __func__); 2500 return -ENOMEM; 2501 } 2502 2503 return 0; 2504 } 2505 2506 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2507 const struct drm_display_mode *mode) 2508 { 2509 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2510 struct drm_dsc_config *dsc = msm_host->dsc; 2511 int pic_width = mode->hdisplay; 2512 int pic_height = mode->vdisplay; 2513 2514 if (!msm_host->dsc) 2515 return MODE_OK; 2516 2517 if (pic_width % dsc->slice_width) { 2518 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2519 pic_width, dsc->slice_width); 2520 return MODE_H_ILLEGAL; 2521 } 2522 2523 if (pic_height % dsc->slice_height) { 2524 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2525 pic_height, dsc->slice_height); 2526 return MODE_V_ILLEGAL; 2527 } 2528 2529 return MODE_OK; 2530 } 2531 2532 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2533 { 2534 return to_msm_dsi_host(host)->mode_flags; 2535 } 2536 2537 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2538 { 2539 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2540 2541 pm_runtime_get_sync(&msm_host->pdev->dev); 2542 2543 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2544 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2545 2546 pm_runtime_put_sync(&msm_host->pdev->dev); 2547 } 2548 2549 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2550 { 2551 u32 reg; 2552 2553 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2554 2555 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2556 /* draw checkered rectangle pattern */ 2557 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2558 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2559 /* use 24-bit RGB test pttern */ 2560 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2561 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2562 DSI_TPG_VIDEO_CONFIG_RGB); 2563 2564 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2565 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2566 2567 DBG("Video test pattern setup done\n"); 2568 } 2569 2570 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2571 { 2572 u32 reg; 2573 2574 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2575 2576 /* initial value for test pattern */ 2577 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2578 2579 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2580 2581 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2582 /* draw checkered rectangle pattern */ 2583 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2584 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2585 2586 DBG("Cmd test pattern setup done\n"); 2587 } 2588 2589 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2590 { 2591 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2592 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2593 u32 reg; 2594 2595 if (is_video_mode) 2596 msm_dsi_host_video_test_pattern_setup(msm_host); 2597 else 2598 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2599 2600 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2601 /* enable the test pattern generator */ 2602 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2603 2604 /* for command mode need to trigger one frame from tpg */ 2605 if (!is_video_mode) 2606 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2607 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2608 } 2609 2610 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2611 { 2612 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2613 2614 return msm_host->dsc; 2615 } 2616