1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/interrupt.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/of_irq.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spinlock.h> 20 21 #include <video/mipi_display.h> 22 23 #include "dsi.h" 24 #include "dsi.xml.h" 25 #include "sfpb.xml.h" 26 #include "dsi_cfg.h" 27 #include "msm_kms.h" 28 29 #define DSI_RESET_TOGGLE_DELAY_MS 20 30 31 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 32 { 33 u32 ver; 34 35 if (!major || !minor) 36 return -EINVAL; 37 38 /* 39 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 40 * makes all other registers 4-byte shifted down. 41 * 42 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 43 * older, we read the DSI_VERSION register without any shift(offset 44 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 45 * the case of DSI6G, this has to be zero (the offset points to a 46 * scratch register which we never touch) 47 */ 48 49 ver = msm_readl(base + REG_DSI_VERSION); 50 if (ver) { 51 /* older dsi host, there is no register shift */ 52 ver = FIELD(ver, DSI_VERSION_MAJOR); 53 if (ver <= MSM_DSI_VER_MAJOR_V2) { 54 /* old versions */ 55 *major = ver; 56 *minor = 0; 57 return 0; 58 } else { 59 return -EINVAL; 60 } 61 } else { 62 /* 63 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 64 * registers are shifted down, read DSI_VERSION again with 65 * the shifted offset 66 */ 67 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 68 ver = FIELD(ver, DSI_VERSION_MAJOR); 69 if (ver == MSM_DSI_VER_MAJOR_6G) { 70 /* 6G version */ 71 *major = ver; 72 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 73 return 0; 74 } else { 75 return -EINVAL; 76 } 77 } 78 } 79 80 #define DSI_ERR_STATE_ACK 0x0000 81 #define DSI_ERR_STATE_TIMEOUT 0x0001 82 #define DSI_ERR_STATE_DLN0_PHY 0x0002 83 #define DSI_ERR_STATE_FIFO 0x0004 84 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 85 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 86 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 87 88 #define DSI_CLK_CTRL_ENABLE_CLKS \ 89 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 90 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 91 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 92 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 93 94 struct msm_dsi_host { 95 struct mipi_dsi_host base; 96 97 struct platform_device *pdev; 98 struct drm_device *dev; 99 100 int id; 101 102 void __iomem *ctrl_base; 103 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 104 105 struct clk *bus_clks[DSI_BUS_CLK_MAX]; 106 107 struct clk *byte_clk; 108 struct clk *esc_clk; 109 struct clk *pixel_clk; 110 struct clk *byte_clk_src; 111 struct clk *pixel_clk_src; 112 struct clk *byte_intf_clk; 113 114 u32 byte_clk_rate; 115 u32 pixel_clk_rate; 116 u32 esc_clk_rate; 117 118 /* DSI v2 specific clocks */ 119 struct clk *src_clk; 120 struct clk *esc_clk_src; 121 struct clk *dsi_clk_src; 122 123 u32 src_clk_rate; 124 125 struct gpio_desc *disp_en_gpio; 126 struct gpio_desc *te_gpio; 127 128 const struct msm_dsi_cfg_handler *cfg_hnd; 129 130 struct completion dma_comp; 131 struct completion video_comp; 132 struct mutex dev_mutex; 133 struct mutex cmd_mutex; 134 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 135 136 u32 err_work_state; 137 struct work_struct err_work; 138 struct work_struct hpd_work; 139 struct workqueue_struct *workqueue; 140 141 /* DSI 6G TX buffer*/ 142 struct drm_gem_object *tx_gem_obj; 143 144 /* DSI v2 TX buffer */ 145 void *tx_buf; 146 dma_addr_t tx_buf_paddr; 147 148 int tx_size; 149 150 u8 *rx_buf; 151 152 struct regmap *sfpb; 153 154 struct drm_display_mode *mode; 155 156 /* connected device info */ 157 struct device_node *device_node; 158 unsigned int channel; 159 unsigned int lanes; 160 enum mipi_dsi_pixel_format format; 161 unsigned long mode_flags; 162 163 /* lane data parsed via DT */ 164 int dlane_swap; 165 int num_data_lanes; 166 167 u32 dma_cmd_ctrl_restore; 168 169 bool registered; 170 bool power_on; 171 bool enabled; 172 int irq; 173 }; 174 175 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 176 { 177 switch (fmt) { 178 case MIPI_DSI_FMT_RGB565: return 16; 179 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 180 case MIPI_DSI_FMT_RGB666: 181 case MIPI_DSI_FMT_RGB888: 182 default: return 24; 183 } 184 } 185 186 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 187 { 188 return msm_readl(msm_host->ctrl_base + reg); 189 } 190 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 191 { 192 msm_writel(data, msm_host->ctrl_base + reg); 193 } 194 195 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 196 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 197 198 static const struct msm_dsi_cfg_handler *dsi_get_config( 199 struct msm_dsi_host *msm_host) 200 { 201 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 202 struct device *dev = &msm_host->pdev->dev; 203 struct regulator *gdsc_reg; 204 struct clk *ahb_clk; 205 int ret; 206 u32 major = 0, minor = 0; 207 208 gdsc_reg = regulator_get(dev, "gdsc"); 209 if (IS_ERR(gdsc_reg)) { 210 pr_err("%s: cannot get gdsc\n", __func__); 211 goto exit; 212 } 213 214 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 215 if (IS_ERR(ahb_clk)) { 216 pr_err("%s: cannot get interface clock\n", __func__); 217 goto put_gdsc; 218 } 219 220 pm_runtime_get_sync(dev); 221 222 ret = regulator_enable(gdsc_reg); 223 if (ret) { 224 pr_err("%s: unable to enable gdsc\n", __func__); 225 goto put_gdsc; 226 } 227 228 ret = clk_prepare_enable(ahb_clk); 229 if (ret) { 230 pr_err("%s: unable to enable ahb_clk\n", __func__); 231 goto disable_gdsc; 232 } 233 234 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 235 if (ret) { 236 pr_err("%s: Invalid version\n", __func__); 237 goto disable_clks; 238 } 239 240 cfg_hnd = msm_dsi_cfg_get(major, minor); 241 242 DBG("%s: Version %x:%x\n", __func__, major, minor); 243 244 disable_clks: 245 clk_disable_unprepare(ahb_clk); 246 disable_gdsc: 247 regulator_disable(gdsc_reg); 248 pm_runtime_put_sync(dev); 249 put_gdsc: 250 regulator_put(gdsc_reg); 251 exit: 252 return cfg_hnd; 253 } 254 255 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 256 { 257 return container_of(host, struct msm_dsi_host, base); 258 } 259 260 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 261 { 262 struct regulator_bulk_data *s = msm_host->supplies; 263 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 264 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 265 int i; 266 267 DBG(""); 268 for (i = num - 1; i >= 0; i--) 269 if (regs[i].disable_load >= 0) 270 regulator_set_load(s[i].consumer, 271 regs[i].disable_load); 272 273 regulator_bulk_disable(num, s); 274 } 275 276 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 277 { 278 struct regulator_bulk_data *s = msm_host->supplies; 279 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 280 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 281 int ret, i; 282 283 DBG(""); 284 for (i = 0; i < num; i++) { 285 if (regs[i].enable_load >= 0) { 286 ret = regulator_set_load(s[i].consumer, 287 regs[i].enable_load); 288 if (ret < 0) { 289 pr_err("regulator %d set op mode failed, %d\n", 290 i, ret); 291 goto fail; 292 } 293 } 294 } 295 296 ret = regulator_bulk_enable(num, s); 297 if (ret < 0) { 298 pr_err("regulator enable failed, %d\n", ret); 299 goto fail; 300 } 301 302 return 0; 303 304 fail: 305 for (i--; i >= 0; i--) 306 regulator_set_load(s[i].consumer, regs[i].disable_load); 307 return ret; 308 } 309 310 static int dsi_regulator_init(struct msm_dsi_host *msm_host) 311 { 312 struct regulator_bulk_data *s = msm_host->supplies; 313 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 314 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 315 int i, ret; 316 317 for (i = 0; i < num; i++) 318 s[i].supply = regs[i].name; 319 320 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 321 if (ret < 0) { 322 pr_err("%s: failed to init regulator, ret=%d\n", 323 __func__, ret); 324 return ret; 325 } 326 327 return 0; 328 } 329 330 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 331 { 332 struct platform_device *pdev = msm_host->pdev; 333 int ret = 0; 334 335 msm_host->src_clk = msm_clk_get(pdev, "src"); 336 337 if (IS_ERR(msm_host->src_clk)) { 338 ret = PTR_ERR(msm_host->src_clk); 339 pr_err("%s: can't find src clock. ret=%d\n", 340 __func__, ret); 341 msm_host->src_clk = NULL; 342 return ret; 343 } 344 345 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 346 if (!msm_host->esc_clk_src) { 347 ret = -ENODEV; 348 pr_err("%s: can't get esc clock parent. ret=%d\n", 349 __func__, ret); 350 return ret; 351 } 352 353 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 354 if (!msm_host->dsi_clk_src) { 355 ret = -ENODEV; 356 pr_err("%s: can't get src clock parent. ret=%d\n", 357 __func__, ret); 358 } 359 360 return ret; 361 } 362 363 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 364 { 365 struct platform_device *pdev = msm_host->pdev; 366 int ret = 0; 367 368 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 369 if (IS_ERR(msm_host->byte_intf_clk)) { 370 ret = PTR_ERR(msm_host->byte_intf_clk); 371 pr_err("%s: can't find byte_intf clock. ret=%d\n", 372 __func__, ret); 373 } 374 375 return ret; 376 } 377 378 static int dsi_clk_init(struct msm_dsi_host *msm_host) 379 { 380 struct platform_device *pdev = msm_host->pdev; 381 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 382 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 383 int i, ret = 0; 384 385 /* get bus clocks */ 386 for (i = 0; i < cfg->num_bus_clks; i++) { 387 msm_host->bus_clks[i] = msm_clk_get(pdev, 388 cfg->bus_clk_names[i]); 389 if (IS_ERR(msm_host->bus_clks[i])) { 390 ret = PTR_ERR(msm_host->bus_clks[i]); 391 pr_err("%s: Unable to get %s clock, ret = %d\n", 392 __func__, cfg->bus_clk_names[i], ret); 393 goto exit; 394 } 395 } 396 397 /* get link and source clocks */ 398 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 399 if (IS_ERR(msm_host->byte_clk)) { 400 ret = PTR_ERR(msm_host->byte_clk); 401 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 402 __func__, ret); 403 msm_host->byte_clk = NULL; 404 goto exit; 405 } 406 407 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 408 if (IS_ERR(msm_host->pixel_clk)) { 409 ret = PTR_ERR(msm_host->pixel_clk); 410 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 411 __func__, ret); 412 msm_host->pixel_clk = NULL; 413 goto exit; 414 } 415 416 msm_host->esc_clk = msm_clk_get(pdev, "core"); 417 if (IS_ERR(msm_host->esc_clk)) { 418 ret = PTR_ERR(msm_host->esc_clk); 419 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 420 __func__, ret); 421 msm_host->esc_clk = NULL; 422 goto exit; 423 } 424 425 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 426 if (IS_ERR(msm_host->byte_clk_src)) { 427 ret = PTR_ERR(msm_host->byte_clk_src); 428 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); 429 goto exit; 430 } 431 432 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 433 if (IS_ERR(msm_host->pixel_clk_src)) { 434 ret = PTR_ERR(msm_host->pixel_clk_src); 435 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); 436 goto exit; 437 } 438 439 if (cfg_hnd->ops->clk_init_ver) 440 ret = cfg_hnd->ops->clk_init_ver(msm_host); 441 exit: 442 return ret; 443 } 444 445 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) 446 { 447 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 448 int i, ret; 449 450 DBG("id=%d", msm_host->id); 451 452 for (i = 0; i < cfg->num_bus_clks; i++) { 453 ret = clk_prepare_enable(msm_host->bus_clks[i]); 454 if (ret) { 455 pr_err("%s: failed to enable bus clock %d ret %d\n", 456 __func__, i, ret); 457 goto err; 458 } 459 } 460 461 return 0; 462 err: 463 for (; i > 0; i--) 464 clk_disable_unprepare(msm_host->bus_clks[i]); 465 466 return ret; 467 } 468 469 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) 470 { 471 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 472 int i; 473 474 DBG(""); 475 476 for (i = cfg->num_bus_clks - 1; i >= 0; i--) 477 clk_disable_unprepare(msm_host->bus_clks[i]); 478 } 479 480 int msm_dsi_runtime_suspend(struct device *dev) 481 { 482 struct platform_device *pdev = to_platform_device(dev); 483 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 484 struct mipi_dsi_host *host = msm_dsi->host; 485 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 486 487 if (!msm_host->cfg_hnd) 488 return 0; 489 490 dsi_bus_clk_disable(msm_host); 491 492 return 0; 493 } 494 495 int msm_dsi_runtime_resume(struct device *dev) 496 { 497 struct platform_device *pdev = to_platform_device(dev); 498 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 499 struct mipi_dsi_host *host = msm_dsi->host; 500 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 501 502 if (!msm_host->cfg_hnd) 503 return 0; 504 505 return dsi_bus_clk_enable(msm_host); 506 } 507 508 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 509 { 510 int ret; 511 512 DBG("Set clk rates: pclk=%d, byteclk=%d", 513 msm_host->mode->clock, msm_host->byte_clk_rate); 514 515 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 516 if (ret) { 517 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 518 goto error; 519 } 520 521 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 522 if (ret) { 523 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 524 goto error; 525 } 526 527 if (msm_host->byte_intf_clk) { 528 ret = clk_set_rate(msm_host->byte_intf_clk, 529 msm_host->byte_clk_rate / 2); 530 if (ret) { 531 pr_err("%s: Failed to set rate byte intf clk, %d\n", 532 __func__, ret); 533 goto error; 534 } 535 } 536 537 ret = clk_prepare_enable(msm_host->esc_clk); 538 if (ret) { 539 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 540 goto error; 541 } 542 543 ret = clk_prepare_enable(msm_host->byte_clk); 544 if (ret) { 545 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 546 goto byte_clk_err; 547 } 548 549 ret = clk_prepare_enable(msm_host->pixel_clk); 550 if (ret) { 551 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 552 goto pixel_clk_err; 553 } 554 555 if (msm_host->byte_intf_clk) { 556 ret = clk_prepare_enable(msm_host->byte_intf_clk); 557 if (ret) { 558 pr_err("%s: Failed to enable byte intf clk\n", 559 __func__); 560 goto byte_intf_clk_err; 561 } 562 } 563 564 return 0; 565 566 byte_intf_clk_err: 567 clk_disable_unprepare(msm_host->pixel_clk); 568 pixel_clk_err: 569 clk_disable_unprepare(msm_host->byte_clk); 570 byte_clk_err: 571 clk_disable_unprepare(msm_host->esc_clk); 572 error: 573 return ret; 574 } 575 576 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 577 { 578 int ret; 579 580 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d", 581 msm_host->mode->clock, msm_host->byte_clk_rate, 582 msm_host->esc_clk_rate, msm_host->src_clk_rate); 583 584 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 585 if (ret) { 586 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 587 goto error; 588 } 589 590 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 591 if (ret) { 592 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 593 goto error; 594 } 595 596 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 597 if (ret) { 598 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 599 goto error; 600 } 601 602 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 603 if (ret) { 604 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 605 goto error; 606 } 607 608 ret = clk_prepare_enable(msm_host->byte_clk); 609 if (ret) { 610 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 611 goto error; 612 } 613 614 ret = clk_prepare_enable(msm_host->esc_clk); 615 if (ret) { 616 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 617 goto esc_clk_err; 618 } 619 620 ret = clk_prepare_enable(msm_host->src_clk); 621 if (ret) { 622 pr_err("%s: Failed to enable dsi src clk\n", __func__); 623 goto src_clk_err; 624 } 625 626 ret = clk_prepare_enable(msm_host->pixel_clk); 627 if (ret) { 628 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 629 goto pixel_clk_err; 630 } 631 632 return 0; 633 634 pixel_clk_err: 635 clk_disable_unprepare(msm_host->src_clk); 636 src_clk_err: 637 clk_disable_unprepare(msm_host->esc_clk); 638 esc_clk_err: 639 clk_disable_unprepare(msm_host->byte_clk); 640 error: 641 return ret; 642 } 643 644 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 645 { 646 clk_disable_unprepare(msm_host->esc_clk); 647 clk_disable_unprepare(msm_host->pixel_clk); 648 if (msm_host->byte_intf_clk) 649 clk_disable_unprepare(msm_host->byte_intf_clk); 650 clk_disable_unprepare(msm_host->byte_clk); 651 } 652 653 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 654 { 655 clk_disable_unprepare(msm_host->pixel_clk); 656 clk_disable_unprepare(msm_host->src_clk); 657 clk_disable_unprepare(msm_host->esc_clk); 658 clk_disable_unprepare(msm_host->byte_clk); 659 } 660 661 static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) 662 { 663 struct drm_display_mode *mode = msm_host->mode; 664 u32 pclk_rate; 665 666 pclk_rate = mode->clock * 1000; 667 668 /* 669 * For dual DSI mode, the current DRM mode has the complete width of the 670 * panel. Since, the complete panel is driven by two DSI controllers, 671 * the clock rates have to be split between the two dsi controllers. 672 * Adjust the byte and pixel clock rates for each dsi host accordingly. 673 */ 674 if (is_dual_dsi) 675 pclk_rate /= 2; 676 677 return pclk_rate; 678 } 679 680 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi) 681 { 682 u8 lanes = msm_host->lanes; 683 u32 bpp = dsi_get_bpp(msm_host->format); 684 u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi); 685 u64 pclk_bpp = (u64)pclk_rate * bpp; 686 687 if (lanes == 0) { 688 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 689 lanes = 1; 690 } 691 692 do_div(pclk_bpp, (8 * lanes)); 693 694 msm_host->pixel_clk_rate = pclk_rate; 695 msm_host->byte_clk_rate = pclk_bpp; 696 697 DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, 698 msm_host->byte_clk_rate); 699 700 } 701 702 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) 703 { 704 if (!msm_host->mode) { 705 pr_err("%s: mode not set\n", __func__); 706 return -EINVAL; 707 } 708 709 dsi_calc_pclk(msm_host, is_dual_dsi); 710 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 711 return 0; 712 } 713 714 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) 715 { 716 u32 bpp = dsi_get_bpp(msm_host->format); 717 u64 pclk_bpp; 718 unsigned int esc_mhz, esc_div; 719 unsigned long byte_mhz; 720 721 dsi_calc_pclk(msm_host, is_dual_dsi); 722 723 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp; 724 do_div(pclk_bpp, 8); 725 msm_host->src_clk_rate = pclk_bpp; 726 727 /* 728 * esc clock is byte clock followed by a 4 bit divider, 729 * we need to find an escape clock frequency within the 730 * mipi DSI spec range within the maximum divider limit 731 * We iterate here between an escape clock frequencey 732 * between 20 Mhz to 5 Mhz and pick up the first one 733 * that can be supported by our divider 734 */ 735 736 byte_mhz = msm_host->byte_clk_rate / 1000000; 737 738 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 739 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 740 741 /* 742 * TODO: Ideally, we shouldn't know what sort of divider 743 * is available in mmss_cc, we're just assuming that 744 * it'll always be a 4 bit divider. Need to come up with 745 * a better way here. 746 */ 747 if (esc_div >= 1 && esc_div <= 16) 748 break; 749 } 750 751 if (esc_mhz < 5) 752 return -EINVAL; 753 754 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 755 756 DBG("esc=%d, src=%d", msm_host->esc_clk_rate, 757 msm_host->src_clk_rate); 758 759 return 0; 760 } 761 762 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 763 { 764 u32 intr; 765 unsigned long flags; 766 767 spin_lock_irqsave(&msm_host->intr_lock, flags); 768 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 769 770 if (enable) 771 intr |= mask; 772 else 773 intr &= ~mask; 774 775 DBG("intr=%x enable=%d", intr, enable); 776 777 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 778 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 779 } 780 781 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 782 { 783 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 784 return BURST_MODE; 785 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 786 return NON_BURST_SYNCH_PULSE; 787 788 return NON_BURST_SYNCH_EVENT; 789 } 790 791 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 792 const enum mipi_dsi_pixel_format mipi_fmt) 793 { 794 switch (mipi_fmt) { 795 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 796 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 797 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 798 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 799 default: return VID_DST_FORMAT_RGB888; 800 } 801 } 802 803 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 804 const enum mipi_dsi_pixel_format mipi_fmt) 805 { 806 switch (mipi_fmt) { 807 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 808 case MIPI_DSI_FMT_RGB666_PACKED: 809 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 810 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 811 default: return CMD_DST_FORMAT_RGB888; 812 } 813 } 814 815 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 816 struct msm_dsi_phy_shared_timings *phy_shared_timings) 817 { 818 u32 flags = msm_host->mode_flags; 819 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 820 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 821 u32 data = 0; 822 823 if (!enable) { 824 dsi_write(msm_host, REG_DSI_CTRL, 0); 825 return; 826 } 827 828 if (flags & MIPI_DSI_MODE_VIDEO) { 829 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 830 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 831 if (flags & MIPI_DSI_MODE_VIDEO_HFP) 832 data |= DSI_VID_CFG0_HFP_POWER_STOP; 833 if (flags & MIPI_DSI_MODE_VIDEO_HBP) 834 data |= DSI_VID_CFG0_HBP_POWER_STOP; 835 if (flags & MIPI_DSI_MODE_VIDEO_HSA) 836 data |= DSI_VID_CFG0_HSA_POWER_STOP; 837 /* Always set low power stop mode for BLLP 838 * to let command engine send packets 839 */ 840 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 841 DSI_VID_CFG0_BLLP_POWER_STOP; 842 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 843 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 844 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 845 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 846 847 /* Do not swap RGB colors */ 848 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 849 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 850 } else { 851 /* Do not swap RGB colors */ 852 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 853 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 854 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 855 856 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 857 DSI_CMD_CFG1_WR_MEM_CONTINUE( 858 MIPI_DCS_WRITE_MEMORY_CONTINUE); 859 /* Always insert DCS command */ 860 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 861 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 862 } 863 864 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 865 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 866 DSI_CMD_DMA_CTRL_LOW_POWER); 867 868 data = 0; 869 /* Always assume dedicated TE pin */ 870 data |= DSI_TRIG_CTRL_TE; 871 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 872 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 873 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 874 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 875 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 876 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 877 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 878 879 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 880 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 881 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 882 883 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 884 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 885 phy_shared_timings->clk_pre_inc_by_2) 886 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 887 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 888 889 data = 0; 890 if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) 891 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 892 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 893 894 /* allow only ack-err-status to generate interrupt */ 895 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 896 897 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 898 899 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 900 901 data = DSI_CTRL_CLK_EN; 902 903 DBG("lane number=%d", msm_host->lanes); 904 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 905 906 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 907 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 908 909 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 910 dsi_write(msm_host, REG_DSI_LANE_CTRL, 911 DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 912 913 data |= DSI_CTRL_ENABLE; 914 915 dsi_write(msm_host, REG_DSI_CTRL, data); 916 } 917 918 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) 919 { 920 struct drm_display_mode *mode = msm_host->mode; 921 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 922 u32 h_total = mode->htotal; 923 u32 v_total = mode->vtotal; 924 u32 hs_end = mode->hsync_end - mode->hsync_start; 925 u32 vs_end = mode->vsync_end - mode->vsync_start; 926 u32 ha_start = h_total - mode->hsync_start; 927 u32 ha_end = ha_start + mode->hdisplay; 928 u32 va_start = v_total - mode->vsync_start; 929 u32 va_end = va_start + mode->vdisplay; 930 u32 hdisplay = mode->hdisplay; 931 u32 wc; 932 933 DBG(""); 934 935 /* 936 * For dual DSI mode, the current DRM mode has 937 * the complete width of the panel. Since, the complete 938 * panel is driven by two DSI controllers, the horizontal 939 * timings have to be split between the two dsi controllers. 940 * Adjust the DSI host timing values accordingly. 941 */ 942 if (is_dual_dsi) { 943 h_total /= 2; 944 hs_end /= 2; 945 ha_start /= 2; 946 ha_end /= 2; 947 hdisplay /= 2; 948 } 949 950 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 951 dsi_write(msm_host, REG_DSI_ACTIVE_H, 952 DSI_ACTIVE_H_START(ha_start) | 953 DSI_ACTIVE_H_END(ha_end)); 954 dsi_write(msm_host, REG_DSI_ACTIVE_V, 955 DSI_ACTIVE_V_START(va_start) | 956 DSI_ACTIVE_V_END(va_end)); 957 dsi_write(msm_host, REG_DSI_TOTAL, 958 DSI_TOTAL_H_TOTAL(h_total - 1) | 959 DSI_TOTAL_V_TOTAL(v_total - 1)); 960 961 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 962 DSI_ACTIVE_HSYNC_START(hs_start) | 963 DSI_ACTIVE_HSYNC_END(hs_end)); 964 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 965 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 966 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 967 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 968 } else { /* command mode */ 969 /* image data and 1 byte write_memory_start cmd */ 970 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 971 972 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL, 973 DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) | 974 DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL( 975 msm_host->channel) | 976 DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE( 977 MIPI_DSI_DCS_LONG_WRITE)); 978 979 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL, 980 DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) | 981 DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay)); 982 } 983 } 984 985 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 986 { 987 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 988 wmb(); /* clocks need to be enabled before reset */ 989 990 dsi_write(msm_host, REG_DSI_RESET, 1); 991 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 992 dsi_write(msm_host, REG_DSI_RESET, 0); 993 } 994 995 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 996 bool video_mode, bool enable) 997 { 998 u32 dsi_ctrl; 999 1000 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1001 1002 if (!enable) { 1003 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1004 DSI_CTRL_CMD_MODE_EN); 1005 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1006 DSI_IRQ_MASK_VIDEO_DONE, 0); 1007 } else { 1008 if (video_mode) { 1009 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1010 } else { /* command mode */ 1011 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1012 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1013 } 1014 dsi_ctrl |= DSI_CTRL_ENABLE; 1015 } 1016 1017 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1018 } 1019 1020 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1021 { 1022 u32 data; 1023 1024 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1025 1026 if (mode == 0) 1027 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1028 else 1029 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1030 1031 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1032 } 1033 1034 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1035 { 1036 u32 ret = 0; 1037 struct device *dev = &msm_host->pdev->dev; 1038 1039 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1040 1041 reinit_completion(&msm_host->video_comp); 1042 1043 ret = wait_for_completion_timeout(&msm_host->video_comp, 1044 msecs_to_jiffies(70)); 1045 1046 if (ret == 0) 1047 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1048 1049 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1050 } 1051 1052 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1053 { 1054 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1055 return; 1056 1057 if (msm_host->power_on && msm_host->enabled) { 1058 dsi_wait4video_done(msm_host); 1059 /* delay 4 ms to skip BLLP */ 1060 usleep_range(2000, 4000); 1061 } 1062 } 1063 1064 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1065 { 1066 struct drm_device *dev = msm_host->dev; 1067 struct msm_drm_private *priv = dev->dev_private; 1068 uint64_t iova; 1069 u8 *data; 1070 1071 data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED, 1072 priv->kms->aspace, 1073 &msm_host->tx_gem_obj, &iova); 1074 1075 if (IS_ERR(data)) { 1076 msm_host->tx_gem_obj = NULL; 1077 return PTR_ERR(data); 1078 } 1079 1080 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1081 1082 msm_host->tx_size = msm_host->tx_gem_obj->size; 1083 1084 return 0; 1085 } 1086 1087 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1088 { 1089 struct drm_device *dev = msm_host->dev; 1090 1091 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1092 &msm_host->tx_buf_paddr, GFP_KERNEL); 1093 if (!msm_host->tx_buf) 1094 return -ENOMEM; 1095 1096 msm_host->tx_size = size; 1097 1098 return 0; 1099 } 1100 1101 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1102 { 1103 struct drm_device *dev = msm_host->dev; 1104 struct msm_drm_private *priv; 1105 1106 /* 1107 * This is possible if we're tearing down before we've had a chance to 1108 * fully initialize. A very real possibility if our probe is deferred, 1109 * in which case we'll hit msm_dsi_host_destroy() without having run 1110 * through the dsi_tx_buf_alloc(). 1111 */ 1112 if (!dev) 1113 return; 1114 1115 priv = dev->dev_private; 1116 if (msm_host->tx_gem_obj) { 1117 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); 1118 drm_gem_object_put_unlocked(msm_host->tx_gem_obj); 1119 msm_host->tx_gem_obj = NULL; 1120 } 1121 1122 if (msm_host->tx_buf) 1123 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1124 msm_host->tx_buf_paddr); 1125 } 1126 1127 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1128 { 1129 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1130 } 1131 1132 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1133 { 1134 return msm_host->tx_buf; 1135 } 1136 1137 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1138 { 1139 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1140 } 1141 1142 /* 1143 * prepare cmd buffer to be txed 1144 */ 1145 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1146 const struct mipi_dsi_msg *msg) 1147 { 1148 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1149 struct mipi_dsi_packet packet; 1150 int len; 1151 int ret; 1152 u8 *data; 1153 1154 ret = mipi_dsi_create_packet(&packet, msg); 1155 if (ret) { 1156 pr_err("%s: create packet failed, %d\n", __func__, ret); 1157 return ret; 1158 } 1159 len = (packet.size + 3) & (~0x3); 1160 1161 if (len > msm_host->tx_size) { 1162 pr_err("%s: packet size is too big\n", __func__); 1163 return -EINVAL; 1164 } 1165 1166 data = cfg_hnd->ops->tx_buf_get(msm_host); 1167 if (IS_ERR(data)) { 1168 ret = PTR_ERR(data); 1169 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1170 return ret; 1171 } 1172 1173 /* MSM specific command format in memory */ 1174 data[0] = packet.header[1]; 1175 data[1] = packet.header[2]; 1176 data[2] = packet.header[0]; 1177 data[3] = BIT(7); /* Last packet */ 1178 if (mipi_dsi_packet_format_is_long(msg->type)) 1179 data[3] |= BIT(6); 1180 if (msg->rx_buf && msg->rx_len) 1181 data[3] |= BIT(5); 1182 1183 /* Long packet */ 1184 if (packet.payload && packet.payload_length) 1185 memcpy(data + 4, packet.payload, packet.payload_length); 1186 1187 /* Append 0xff to the end */ 1188 if (packet.size < len) 1189 memset(data + packet.size, 0xff, len - packet.size); 1190 1191 if (cfg_hnd->ops->tx_buf_put) 1192 cfg_hnd->ops->tx_buf_put(msm_host); 1193 1194 return len; 1195 } 1196 1197 /* 1198 * dsi_short_read1_resp: 1 parameter 1199 */ 1200 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1201 { 1202 u8 *data = msg->rx_buf; 1203 if (data && (msg->rx_len >= 1)) { 1204 *data = buf[1]; /* strip out dcs type */ 1205 return 1; 1206 } else { 1207 pr_err("%s: read data does not match with rx_buf len %zu\n", 1208 __func__, msg->rx_len); 1209 return -EINVAL; 1210 } 1211 } 1212 1213 /* 1214 * dsi_short_read2_resp: 2 parameter 1215 */ 1216 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1217 { 1218 u8 *data = msg->rx_buf; 1219 if (data && (msg->rx_len >= 2)) { 1220 data[0] = buf[1]; /* strip out dcs type */ 1221 data[1] = buf[2]; 1222 return 2; 1223 } else { 1224 pr_err("%s: read data does not match with rx_buf len %zu\n", 1225 __func__, msg->rx_len); 1226 return -EINVAL; 1227 } 1228 } 1229 1230 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1231 { 1232 /* strip out 4 byte dcs header */ 1233 if (msg->rx_buf && msg->rx_len) 1234 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1235 1236 return msg->rx_len; 1237 } 1238 1239 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1240 { 1241 struct drm_device *dev = msm_host->dev; 1242 struct msm_drm_private *priv = dev->dev_private; 1243 1244 if (!dma_base) 1245 return -EINVAL; 1246 1247 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1248 priv->kms->aspace, dma_base); 1249 } 1250 1251 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1252 { 1253 if (!dma_base) 1254 return -EINVAL; 1255 1256 *dma_base = msm_host->tx_buf_paddr; 1257 return 0; 1258 } 1259 1260 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1261 { 1262 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1263 int ret; 1264 uint64_t dma_base; 1265 bool triggered; 1266 1267 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1268 if (ret) { 1269 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1270 return ret; 1271 } 1272 1273 reinit_completion(&msm_host->dma_comp); 1274 1275 dsi_wait4video_eng_busy(msm_host); 1276 1277 triggered = msm_dsi_manager_cmd_xfer_trigger( 1278 msm_host->id, dma_base, len); 1279 if (triggered) { 1280 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1281 msecs_to_jiffies(200)); 1282 DBG("ret=%d", ret); 1283 if (ret == 0) 1284 ret = -ETIMEDOUT; 1285 else 1286 ret = len; 1287 } else 1288 ret = len; 1289 1290 return ret; 1291 } 1292 1293 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1294 u8 *buf, int rx_byte, int pkt_size) 1295 { 1296 u32 *temp, data; 1297 int i, j = 0, cnt; 1298 u32 read_cnt; 1299 u8 reg[16]; 1300 int repeated_bytes = 0; 1301 int buf_offset = buf - msm_host->rx_buf; 1302 1303 temp = (u32 *)reg; 1304 cnt = (rx_byte + 3) >> 2; 1305 if (cnt > 4) 1306 cnt = 4; /* 4 x 32 bits registers only */ 1307 1308 if (rx_byte == 4) 1309 read_cnt = 4; 1310 else 1311 read_cnt = pkt_size + 6; 1312 1313 /* 1314 * In case of multiple reads from the panel, after the first read, there 1315 * is possibility that there are some bytes in the payload repeating in 1316 * the RDBK_DATA registers. Since we read all the parameters from the 1317 * panel right from the first byte for every pass. We need to skip the 1318 * repeating bytes and then append the new parameters to the rx buffer. 1319 */ 1320 if (read_cnt > 16) { 1321 int bytes_shifted; 1322 /* Any data more than 16 bytes will be shifted out. 1323 * The temp read buffer should already contain these bytes. 1324 * The remaining bytes in read buffer are the repeated bytes. 1325 */ 1326 bytes_shifted = read_cnt - 16; 1327 repeated_bytes = buf_offset - bytes_shifted; 1328 } 1329 1330 for (i = cnt - 1; i >= 0; i--) { 1331 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1332 *temp++ = ntohl(data); /* to host byte order */ 1333 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1334 } 1335 1336 for (i = repeated_bytes; i < 16; i++) 1337 buf[j++] = reg[i]; 1338 1339 return j; 1340 } 1341 1342 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1343 const struct mipi_dsi_msg *msg) 1344 { 1345 int len, ret; 1346 int bllp_len = msm_host->mode->hdisplay * 1347 dsi_get_bpp(msm_host->format) / 8; 1348 1349 len = dsi_cmd_dma_add(msm_host, msg); 1350 if (!len) { 1351 pr_err("%s: failed to add cmd type = 0x%x\n", 1352 __func__, msg->type); 1353 return -EINVAL; 1354 } 1355 1356 /* for video mode, do not send cmds more than 1357 * one pixel line, since it only transmit it 1358 * during BLLP. 1359 */ 1360 /* TODO: if the command is sent in LP mode, the bit rate is only 1361 * half of esc clk rate. In this case, if the video is already 1362 * actively streaming, we need to check more carefully if the 1363 * command can be fit into one BLLP. 1364 */ 1365 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1366 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1367 __func__, len); 1368 return -EINVAL; 1369 } 1370 1371 ret = dsi_cmd_dma_tx(msm_host, len); 1372 if (ret < len) { 1373 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", 1374 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); 1375 return -ECOMM; 1376 } 1377 1378 return len; 1379 } 1380 1381 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1382 { 1383 u32 data0, data1; 1384 1385 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1386 data1 = data0; 1387 data1 &= ~DSI_CTRL_ENABLE; 1388 dsi_write(msm_host, REG_DSI_CTRL, data1); 1389 /* 1390 * dsi controller need to be disabled before 1391 * clocks turned on 1392 */ 1393 wmb(); 1394 1395 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1396 wmb(); /* make sure clocks enabled */ 1397 1398 /* dsi controller can only be reset while clocks are running */ 1399 dsi_write(msm_host, REG_DSI_RESET, 1); 1400 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1401 dsi_write(msm_host, REG_DSI_RESET, 0); 1402 wmb(); /* controller out of reset */ 1403 dsi_write(msm_host, REG_DSI_CTRL, data0); 1404 wmb(); /* make sure dsi controller enabled again */ 1405 } 1406 1407 static void dsi_hpd_worker(struct work_struct *work) 1408 { 1409 struct msm_dsi_host *msm_host = 1410 container_of(work, struct msm_dsi_host, hpd_work); 1411 1412 drm_helper_hpd_irq_event(msm_host->dev); 1413 } 1414 1415 static void dsi_err_worker(struct work_struct *work) 1416 { 1417 struct msm_dsi_host *msm_host = 1418 container_of(work, struct msm_dsi_host, err_work); 1419 u32 status = msm_host->err_work_state; 1420 1421 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1422 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1423 dsi_sw_reset_restore(msm_host); 1424 1425 /* It is safe to clear here because error irq is disabled. */ 1426 msm_host->err_work_state = 0; 1427 1428 /* enable dsi error interrupt */ 1429 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1430 } 1431 1432 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1433 { 1434 u32 status; 1435 1436 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1437 1438 if (status) { 1439 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1440 /* Writing of an extra 0 needed to clear error bits */ 1441 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1442 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1443 } 1444 } 1445 1446 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1447 { 1448 u32 status; 1449 1450 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1451 1452 if (status) { 1453 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1454 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1455 } 1456 } 1457 1458 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1459 { 1460 u32 status; 1461 1462 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1463 1464 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1465 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1466 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1467 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1468 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1469 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1470 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1471 } 1472 } 1473 1474 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1475 { 1476 u32 status; 1477 1478 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1479 1480 /* fifo underflow, overflow */ 1481 if (status) { 1482 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1483 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1484 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1485 msm_host->err_work_state |= 1486 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1487 } 1488 } 1489 1490 static void dsi_status(struct msm_dsi_host *msm_host) 1491 { 1492 u32 status; 1493 1494 status = dsi_read(msm_host, REG_DSI_STATUS0); 1495 1496 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1497 dsi_write(msm_host, REG_DSI_STATUS0, status); 1498 msm_host->err_work_state |= 1499 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1500 } 1501 } 1502 1503 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1504 { 1505 u32 status; 1506 1507 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1508 1509 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1510 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1511 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1512 } 1513 } 1514 1515 static void dsi_error(struct msm_dsi_host *msm_host) 1516 { 1517 /* disable dsi error interrupt */ 1518 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1519 1520 dsi_clk_status(msm_host); 1521 dsi_fifo_status(msm_host); 1522 dsi_ack_err_status(msm_host); 1523 dsi_timeout_status(msm_host); 1524 dsi_status(msm_host); 1525 dsi_dln0_phy_err(msm_host); 1526 1527 queue_work(msm_host->workqueue, &msm_host->err_work); 1528 } 1529 1530 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1531 { 1532 struct msm_dsi_host *msm_host = ptr; 1533 u32 isr; 1534 unsigned long flags; 1535 1536 if (!msm_host->ctrl_base) 1537 return IRQ_HANDLED; 1538 1539 spin_lock_irqsave(&msm_host->intr_lock, flags); 1540 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1541 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1542 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1543 1544 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1545 1546 if (isr & DSI_IRQ_ERROR) 1547 dsi_error(msm_host); 1548 1549 if (isr & DSI_IRQ_VIDEO_DONE) 1550 complete(&msm_host->video_comp); 1551 1552 if (isr & DSI_IRQ_CMD_DMA_DONE) 1553 complete(&msm_host->dma_comp); 1554 1555 return IRQ_HANDLED; 1556 } 1557 1558 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1559 struct device *panel_device) 1560 { 1561 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1562 "disp-enable", 1563 GPIOD_OUT_LOW); 1564 if (IS_ERR(msm_host->disp_en_gpio)) { 1565 DBG("cannot get disp-enable-gpios %ld", 1566 PTR_ERR(msm_host->disp_en_gpio)); 1567 return PTR_ERR(msm_host->disp_en_gpio); 1568 } 1569 1570 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1571 GPIOD_IN); 1572 if (IS_ERR(msm_host->te_gpio)) { 1573 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1574 return PTR_ERR(msm_host->te_gpio); 1575 } 1576 1577 return 0; 1578 } 1579 1580 static int dsi_host_attach(struct mipi_dsi_host *host, 1581 struct mipi_dsi_device *dsi) 1582 { 1583 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1584 int ret; 1585 1586 if (dsi->lanes > msm_host->num_data_lanes) 1587 return -EINVAL; 1588 1589 msm_host->channel = dsi->channel; 1590 msm_host->lanes = dsi->lanes; 1591 msm_host->format = dsi->format; 1592 msm_host->mode_flags = dsi->mode_flags; 1593 1594 /* Some gpios defined in panel DT need to be controlled by host */ 1595 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1596 if (ret) 1597 return ret; 1598 1599 DBG("id=%d", msm_host->id); 1600 if (msm_host->dev) 1601 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1602 1603 return 0; 1604 } 1605 1606 static int dsi_host_detach(struct mipi_dsi_host *host, 1607 struct mipi_dsi_device *dsi) 1608 { 1609 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1610 1611 msm_host->device_node = NULL; 1612 1613 DBG("id=%d", msm_host->id); 1614 if (msm_host->dev) 1615 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1616 1617 return 0; 1618 } 1619 1620 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1621 const struct mipi_dsi_msg *msg) 1622 { 1623 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1624 int ret; 1625 1626 if (!msg || !msm_host->power_on) 1627 return -EINVAL; 1628 1629 mutex_lock(&msm_host->cmd_mutex); 1630 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1631 mutex_unlock(&msm_host->cmd_mutex); 1632 1633 return ret; 1634 } 1635 1636 static struct mipi_dsi_host_ops dsi_host_ops = { 1637 .attach = dsi_host_attach, 1638 .detach = dsi_host_detach, 1639 .transfer = dsi_host_transfer, 1640 }; 1641 1642 /* 1643 * List of supported physical to logical lane mappings. 1644 * For example, the 2nd entry represents the following mapping: 1645 * 1646 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1647 */ 1648 static const int supported_data_lane_swaps[][4] = { 1649 { 0, 1, 2, 3 }, 1650 { 3, 0, 1, 2 }, 1651 { 2, 3, 0, 1 }, 1652 { 1, 2, 3, 0 }, 1653 { 0, 3, 2, 1 }, 1654 { 1, 0, 3, 2 }, 1655 { 2, 1, 0, 3 }, 1656 { 3, 2, 1, 0 }, 1657 }; 1658 1659 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1660 struct device_node *ep) 1661 { 1662 struct device *dev = &msm_host->pdev->dev; 1663 struct property *prop; 1664 u32 lane_map[4]; 1665 int ret, i, len, num_lanes; 1666 1667 prop = of_find_property(ep, "data-lanes", &len); 1668 if (!prop) { 1669 DRM_DEV_DEBUG(dev, 1670 "failed to find data lane mapping, using default\n"); 1671 return 0; 1672 } 1673 1674 num_lanes = len / sizeof(u32); 1675 1676 if (num_lanes < 1 || num_lanes > 4) { 1677 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1678 return -EINVAL; 1679 } 1680 1681 msm_host->num_data_lanes = num_lanes; 1682 1683 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1684 num_lanes); 1685 if (ret) { 1686 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1687 return ret; 1688 } 1689 1690 /* 1691 * compare DT specified physical-logical lane mappings with the ones 1692 * supported by hardware 1693 */ 1694 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1695 const int *swap = supported_data_lane_swaps[i]; 1696 int j; 1697 1698 /* 1699 * the data-lanes array we get from DT has a logical->physical 1700 * mapping. The "data lane swap" register field represents 1701 * supported configurations in a physical->logical mapping. 1702 * Translate the DT mapping to what we understand and find a 1703 * configuration that works. 1704 */ 1705 for (j = 0; j < num_lanes; j++) { 1706 if (lane_map[j] < 0 || lane_map[j] > 3) 1707 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1708 lane_map[j]); 1709 1710 if (swap[lane_map[j]] != j) 1711 break; 1712 } 1713 1714 if (j == num_lanes) { 1715 msm_host->dlane_swap = i; 1716 return 0; 1717 } 1718 } 1719 1720 return -EINVAL; 1721 } 1722 1723 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1724 { 1725 struct device *dev = &msm_host->pdev->dev; 1726 struct device_node *np = dev->of_node; 1727 struct device_node *endpoint, *device_node; 1728 int ret = 0; 1729 1730 /* 1731 * Get the endpoint of the output port of the DSI host. In our case, 1732 * this is mapped to port number with reg = 1. Don't return an error if 1733 * the remote endpoint isn't defined. It's possible that there is 1734 * nothing connected to the dsi output. 1735 */ 1736 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1737 if (!endpoint) { 1738 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1739 return 0; 1740 } 1741 1742 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1743 if (ret) { 1744 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1745 __func__, ret); 1746 ret = -EINVAL; 1747 goto err; 1748 } 1749 1750 /* Get panel node from the output port's endpoint data */ 1751 device_node = of_graph_get_remote_node(np, 1, 0); 1752 if (!device_node) { 1753 DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__); 1754 ret = -ENODEV; 1755 goto err; 1756 } 1757 1758 msm_host->device_node = device_node; 1759 1760 if (of_property_read_bool(np, "syscon-sfpb")) { 1761 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1762 "syscon-sfpb"); 1763 if (IS_ERR(msm_host->sfpb)) { 1764 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1765 __func__); 1766 ret = PTR_ERR(msm_host->sfpb); 1767 } 1768 } 1769 1770 of_node_put(device_node); 1771 1772 err: 1773 of_node_put(endpoint); 1774 1775 return ret; 1776 } 1777 1778 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1779 { 1780 struct platform_device *pdev = msm_host->pdev; 1781 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1782 struct resource *res; 1783 int i; 1784 1785 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1786 if (!res) 1787 return -EINVAL; 1788 1789 for (i = 0; i < cfg->num_dsi; i++) { 1790 if (cfg->io_start[i] == res->start) 1791 return i; 1792 } 1793 1794 return -EINVAL; 1795 } 1796 1797 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1798 { 1799 struct msm_dsi_host *msm_host = NULL; 1800 struct platform_device *pdev = msm_dsi->pdev; 1801 int ret; 1802 1803 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1804 if (!msm_host) { 1805 pr_err("%s: FAILED: cannot alloc dsi host\n", 1806 __func__); 1807 ret = -ENOMEM; 1808 goto fail; 1809 } 1810 1811 msm_host->pdev = pdev; 1812 msm_dsi->host = &msm_host->base; 1813 1814 ret = dsi_host_parse_dt(msm_host); 1815 if (ret) { 1816 pr_err("%s: failed to parse dt\n", __func__); 1817 goto fail; 1818 } 1819 1820 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); 1821 if (IS_ERR(msm_host->ctrl_base)) { 1822 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1823 ret = PTR_ERR(msm_host->ctrl_base); 1824 goto fail; 1825 } 1826 1827 pm_runtime_enable(&pdev->dev); 1828 1829 msm_host->cfg_hnd = dsi_get_config(msm_host); 1830 if (!msm_host->cfg_hnd) { 1831 ret = -EINVAL; 1832 pr_err("%s: get config failed\n", __func__); 1833 goto fail; 1834 } 1835 1836 msm_host->id = dsi_host_get_id(msm_host); 1837 if (msm_host->id < 0) { 1838 ret = msm_host->id; 1839 pr_err("%s: unable to identify DSI host index\n", __func__); 1840 goto fail; 1841 } 1842 1843 /* fixup base address by io offset */ 1844 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; 1845 1846 ret = dsi_regulator_init(msm_host); 1847 if (ret) { 1848 pr_err("%s: regulator init failed\n", __func__); 1849 goto fail; 1850 } 1851 1852 ret = dsi_clk_init(msm_host); 1853 if (ret) { 1854 pr_err("%s: unable to initialize dsi clks\n", __func__); 1855 goto fail; 1856 } 1857 1858 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1859 if (!msm_host->rx_buf) { 1860 ret = -ENOMEM; 1861 pr_err("%s: alloc rx temp buf failed\n", __func__); 1862 goto fail; 1863 } 1864 1865 init_completion(&msm_host->dma_comp); 1866 init_completion(&msm_host->video_comp); 1867 mutex_init(&msm_host->dev_mutex); 1868 mutex_init(&msm_host->cmd_mutex); 1869 spin_lock_init(&msm_host->intr_lock); 1870 1871 /* setup workqueue */ 1872 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1873 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1874 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); 1875 1876 msm_dsi->id = msm_host->id; 1877 1878 DBG("Dsi Host %d initialized", msm_host->id); 1879 return 0; 1880 1881 fail: 1882 return ret; 1883 } 1884 1885 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1886 { 1887 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1888 1889 DBG(""); 1890 dsi_tx_buf_free(msm_host); 1891 if (msm_host->workqueue) { 1892 flush_workqueue(msm_host->workqueue); 1893 destroy_workqueue(msm_host->workqueue); 1894 msm_host->workqueue = NULL; 1895 } 1896 1897 mutex_destroy(&msm_host->cmd_mutex); 1898 mutex_destroy(&msm_host->dev_mutex); 1899 1900 pm_runtime_disable(&msm_host->pdev->dev); 1901 } 1902 1903 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1904 struct drm_device *dev) 1905 { 1906 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1907 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1908 struct platform_device *pdev = msm_host->pdev; 1909 int ret; 1910 1911 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1912 if (msm_host->irq < 0) { 1913 ret = msm_host->irq; 1914 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); 1915 return ret; 1916 } 1917 1918 ret = devm_request_irq(&pdev->dev, msm_host->irq, 1919 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1920 "dsi_isr", msm_host); 1921 if (ret < 0) { 1922 DRM_DEV_ERROR(&pdev->dev, "failed to request IRQ%u: %d\n", 1923 msm_host->irq, ret); 1924 return ret; 1925 } 1926 1927 msm_host->dev = dev; 1928 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 1929 if (ret) { 1930 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1931 return ret; 1932 } 1933 1934 return 0; 1935 } 1936 1937 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) 1938 { 1939 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1940 int ret; 1941 1942 /* Register mipi dsi host */ 1943 if (!msm_host->registered) { 1944 host->dev = &msm_host->pdev->dev; 1945 host->ops = &dsi_host_ops; 1946 ret = mipi_dsi_host_register(host); 1947 if (ret) 1948 return ret; 1949 1950 msm_host->registered = true; 1951 1952 /* If the panel driver has not been probed after host register, 1953 * we should defer the host's probe. 1954 * It makes sure panel is connected when fbcon detects 1955 * connector status and gets the proper display mode to 1956 * create framebuffer. 1957 * Don't try to defer if there is nothing connected to the dsi 1958 * output 1959 */ 1960 if (check_defer && msm_host->device_node) { 1961 if (IS_ERR(of_drm_find_panel(msm_host->device_node))) 1962 if (!of_drm_find_bridge(msm_host->device_node)) 1963 return -EPROBE_DEFER; 1964 } 1965 } 1966 1967 return 0; 1968 } 1969 1970 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 1971 { 1972 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1973 1974 if (msm_host->registered) { 1975 mipi_dsi_host_unregister(host); 1976 host->dev = NULL; 1977 host->ops = NULL; 1978 msm_host->registered = false; 1979 } 1980 } 1981 1982 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 1983 const struct mipi_dsi_msg *msg) 1984 { 1985 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1986 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1987 1988 /* TODO: make sure dsi_cmd_mdp is idle. 1989 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 1990 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 1991 * How to handle the old versions? Wait for mdp cmd done? 1992 */ 1993 1994 /* 1995 * mdss interrupt is generated in mdp core clock domain 1996 * mdp clock need to be enabled to receive dsi interrupt 1997 */ 1998 pm_runtime_get_sync(&msm_host->pdev->dev); 1999 cfg_hnd->ops->link_clk_enable(msm_host); 2000 2001 /* TODO: vote for bus bandwidth */ 2002 2003 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2004 dsi_set_tx_power_mode(0, msm_host); 2005 2006 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2007 dsi_write(msm_host, REG_DSI_CTRL, 2008 msm_host->dma_cmd_ctrl_restore | 2009 DSI_CTRL_CMD_MODE_EN | 2010 DSI_CTRL_ENABLE); 2011 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2012 2013 return 0; 2014 } 2015 2016 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2017 const struct mipi_dsi_msg *msg) 2018 { 2019 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2020 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2021 2022 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2023 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2024 2025 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2026 dsi_set_tx_power_mode(1, msm_host); 2027 2028 /* TODO: unvote for bus bandwidth */ 2029 2030 cfg_hnd->ops->link_clk_disable(msm_host); 2031 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2032 } 2033 2034 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2035 const struct mipi_dsi_msg *msg) 2036 { 2037 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2038 2039 return dsi_cmds2buf_tx(msm_host, msg); 2040 } 2041 2042 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2043 const struct mipi_dsi_msg *msg) 2044 { 2045 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2046 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2047 int data_byte, rx_byte, dlen, end; 2048 int short_response, diff, pkt_size, ret = 0; 2049 char cmd; 2050 int rlen = msg->rx_len; 2051 u8 *buf; 2052 2053 if (rlen <= 2) { 2054 short_response = 1; 2055 pkt_size = rlen; 2056 rx_byte = 4; 2057 } else { 2058 short_response = 0; 2059 data_byte = 10; /* first read */ 2060 if (rlen < data_byte) 2061 pkt_size = rlen; 2062 else 2063 pkt_size = data_byte; 2064 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2065 } 2066 2067 buf = msm_host->rx_buf; 2068 end = 0; 2069 while (!end) { 2070 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2071 struct mipi_dsi_msg max_pkt_size_msg = { 2072 .channel = msg->channel, 2073 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2074 .tx_len = 2, 2075 .tx_buf = tx, 2076 }; 2077 2078 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2079 rlen, pkt_size, rx_byte); 2080 2081 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2082 if (ret < 2) { 2083 pr_err("%s: Set max pkt size failed, %d\n", 2084 __func__, ret); 2085 return -EINVAL; 2086 } 2087 2088 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2089 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2090 /* Clear the RDBK_DATA registers */ 2091 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2092 DSI_RDBK_DATA_CTRL_CLR); 2093 wmb(); /* make sure the RDBK registers are cleared */ 2094 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2095 wmb(); /* release cleared status before transfer */ 2096 } 2097 2098 ret = dsi_cmds2buf_tx(msm_host, msg); 2099 if (ret < msg->tx_len) { 2100 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2101 return ret; 2102 } 2103 2104 /* 2105 * once cmd_dma_done interrupt received, 2106 * return data from client is ready and stored 2107 * at RDBK_DATA register already 2108 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2109 * after that dcs header lost during shift into registers 2110 */ 2111 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2112 2113 if (dlen <= 0) 2114 return 0; 2115 2116 if (short_response) 2117 break; 2118 2119 if (rlen <= data_byte) { 2120 diff = data_byte - rlen; 2121 end = 1; 2122 } else { 2123 diff = 0; 2124 rlen -= data_byte; 2125 } 2126 2127 if (!end) { 2128 dlen -= 2; /* 2 crc */ 2129 dlen -= diff; 2130 buf += dlen; /* next start position */ 2131 data_byte = 14; /* NOT first read */ 2132 if (rlen < data_byte) 2133 pkt_size += rlen; 2134 else 2135 pkt_size += data_byte; 2136 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2137 } 2138 } 2139 2140 /* 2141 * For single Long read, if the requested rlen < 10, 2142 * we need to shift the start position of rx 2143 * data buffer to skip the bytes which are not 2144 * updated. 2145 */ 2146 if (pkt_size < 10 && !short_response) 2147 buf = msm_host->rx_buf + (10 - rlen); 2148 else 2149 buf = msm_host->rx_buf; 2150 2151 cmd = buf[0]; 2152 switch (cmd) { 2153 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2154 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2155 ret = 0; 2156 break; 2157 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2158 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2159 ret = dsi_short_read1_resp(buf, msg); 2160 break; 2161 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2162 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2163 ret = dsi_short_read2_resp(buf, msg); 2164 break; 2165 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2166 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2167 ret = dsi_long_read_resp(buf, msg); 2168 break; 2169 default: 2170 pr_warn("%s:Invalid response cmd\n", __func__); 2171 ret = 0; 2172 } 2173 2174 return ret; 2175 } 2176 2177 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2178 u32 len) 2179 { 2180 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2181 2182 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2183 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2184 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2185 2186 /* Make sure trigger happens */ 2187 wmb(); 2188 } 2189 2190 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, 2191 struct msm_dsi_pll *src_pll) 2192 { 2193 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2194 struct clk *byte_clk_provider, *pixel_clk_provider; 2195 int ret; 2196 2197 ret = msm_dsi_pll_get_clk_provider(src_pll, 2198 &byte_clk_provider, &pixel_clk_provider); 2199 if (ret) { 2200 pr_info("%s: can't get provider from pll, don't set parent\n", 2201 __func__); 2202 return 0; 2203 } 2204 2205 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); 2206 if (ret) { 2207 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", 2208 __func__, ret); 2209 goto exit; 2210 } 2211 2212 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); 2213 if (ret) { 2214 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", 2215 __func__, ret); 2216 goto exit; 2217 } 2218 2219 if (msm_host->dsi_clk_src) { 2220 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); 2221 if (ret) { 2222 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", 2223 __func__, ret); 2224 goto exit; 2225 } 2226 } 2227 2228 if (msm_host->esc_clk_src) { 2229 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); 2230 if (ret) { 2231 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", 2232 __func__, ret); 2233 goto exit; 2234 } 2235 } 2236 2237 exit: 2238 return ret; 2239 } 2240 2241 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2242 { 2243 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2244 2245 DBG(""); 2246 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2247 /* Make sure fully reset */ 2248 wmb(); 2249 udelay(1000); 2250 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2251 udelay(100); 2252 } 2253 2254 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2255 struct msm_dsi_phy_clk_request *clk_req, 2256 bool is_dual_dsi) 2257 { 2258 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2259 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2260 int ret; 2261 2262 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi); 2263 if (ret) { 2264 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2265 return; 2266 } 2267 2268 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2269 clk_req->escclk_rate = msm_host->esc_clk_rate; 2270 } 2271 2272 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2273 { 2274 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2275 2276 dsi_op_mode_config(msm_host, 2277 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2278 2279 /* TODO: clock should be turned off for command mode, 2280 * and only turned on before MDP START. 2281 * This part of code should be enabled once mdp driver support it. 2282 */ 2283 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2284 * dsi_link_clk_disable(msm_host); 2285 * pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2286 * } 2287 */ 2288 msm_host->enabled = true; 2289 return 0; 2290 } 2291 2292 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2293 { 2294 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2295 2296 msm_host->enabled = false; 2297 dsi_op_mode_config(msm_host, 2298 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2299 2300 /* Since we have disabled INTF, the video engine won't stop so that 2301 * the cmd engine will be blocked. 2302 * Reset to disable video engine so that we can send off cmd. 2303 */ 2304 dsi_sw_reset(msm_host); 2305 2306 return 0; 2307 } 2308 2309 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2310 { 2311 enum sfpb_ahb_arb_master_port_en en; 2312 2313 if (!msm_host->sfpb) 2314 return; 2315 2316 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2317 2318 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2319 SFPB_GPREG_MASTER_PORT_EN__MASK, 2320 SFPB_GPREG_MASTER_PORT_EN(en)); 2321 } 2322 2323 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2324 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2325 bool is_dual_dsi) 2326 { 2327 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2328 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2329 int ret = 0; 2330 2331 mutex_lock(&msm_host->dev_mutex); 2332 if (msm_host->power_on) { 2333 DBG("dsi host already on"); 2334 goto unlock_ret; 2335 } 2336 2337 msm_dsi_sfpb_config(msm_host, true); 2338 2339 ret = dsi_host_regulator_enable(msm_host); 2340 if (ret) { 2341 pr_err("%s:Failed to enable vregs.ret=%d\n", 2342 __func__, ret); 2343 goto unlock_ret; 2344 } 2345 2346 pm_runtime_get_sync(&msm_host->pdev->dev); 2347 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2348 if (ret) { 2349 pr_err("%s: failed to enable link clocks. ret=%d\n", 2350 __func__, ret); 2351 goto fail_disable_reg; 2352 } 2353 2354 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2355 if (ret) { 2356 pr_err("%s: failed to set pinctrl default state, %d\n", 2357 __func__, ret); 2358 goto fail_disable_clk; 2359 } 2360 2361 dsi_timing_setup(msm_host, is_dual_dsi); 2362 dsi_sw_reset(msm_host); 2363 dsi_ctrl_config(msm_host, true, phy_shared_timings); 2364 2365 if (msm_host->disp_en_gpio) 2366 gpiod_set_value(msm_host->disp_en_gpio, 1); 2367 2368 msm_host->power_on = true; 2369 mutex_unlock(&msm_host->dev_mutex); 2370 2371 return 0; 2372 2373 fail_disable_clk: 2374 cfg_hnd->ops->link_clk_disable(msm_host); 2375 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2376 fail_disable_reg: 2377 dsi_host_regulator_disable(msm_host); 2378 unlock_ret: 2379 mutex_unlock(&msm_host->dev_mutex); 2380 return ret; 2381 } 2382 2383 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2384 { 2385 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2386 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2387 2388 mutex_lock(&msm_host->dev_mutex); 2389 if (!msm_host->power_on) { 2390 DBG("dsi host already off"); 2391 goto unlock_ret; 2392 } 2393 2394 dsi_ctrl_config(msm_host, false, NULL); 2395 2396 if (msm_host->disp_en_gpio) 2397 gpiod_set_value(msm_host->disp_en_gpio, 0); 2398 2399 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2400 2401 cfg_hnd->ops->link_clk_disable(msm_host); 2402 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2403 2404 dsi_host_regulator_disable(msm_host); 2405 2406 msm_dsi_sfpb_config(msm_host, false); 2407 2408 DBG("-"); 2409 2410 msm_host->power_on = false; 2411 2412 unlock_ret: 2413 mutex_unlock(&msm_host->dev_mutex); 2414 return 0; 2415 } 2416 2417 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2418 const struct drm_display_mode *mode) 2419 { 2420 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2421 2422 if (msm_host->mode) { 2423 drm_mode_destroy(msm_host->dev, msm_host->mode); 2424 msm_host->mode = NULL; 2425 } 2426 2427 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2428 if (!msm_host->mode) { 2429 pr_err("%s: cannot duplicate mode\n", __func__); 2430 return -ENOMEM; 2431 } 2432 2433 return 0; 2434 } 2435 2436 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host) 2437 { 2438 return of_drm_find_panel(to_msm_dsi_host(host)->device_node); 2439 } 2440 2441 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2442 { 2443 return to_msm_dsi_host(host)->mode_flags; 2444 } 2445 2446 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) 2447 { 2448 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2449 2450 return of_drm_find_bridge(msm_host->device_node); 2451 } 2452