1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of.h> 13 #include <linux/of_graph.h> 14 #include <linux/of_irq.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/pm_opp.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spinlock.h> 20 21 #include <video/mipi_display.h> 22 23 #include <drm/display/drm_dsc_helper.h> 24 #include <drm/drm_of.h> 25 26 #include "dsi.h" 27 #include "dsi.xml.h" 28 #include "sfpb.xml.h" 29 #include "dsi_cfg.h" 30 #include "msm_dsc_helper.h" 31 #include "msm_kms.h" 32 #include "msm_gem.h" 33 #include "phy/dsi_phy.h" 34 35 #define DSI_RESET_TOGGLE_DELAY_MS 20 36 37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 38 39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 40 { 41 u32 ver; 42 43 if (!major || !minor) 44 return -EINVAL; 45 46 /* 47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 48 * makes all other registers 4-byte shifted down. 49 * 50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 51 * older, we read the DSI_VERSION register without any shift(offset 52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 53 * the case of DSI6G, this has to be zero (the offset points to a 54 * scratch register which we never touch) 55 */ 56 57 ver = readl(base + REG_DSI_VERSION); 58 if (ver) { 59 /* older dsi host, there is no register shift */ 60 ver = FIELD(ver, DSI_VERSION_MAJOR); 61 if (ver <= MSM_DSI_VER_MAJOR_V2) { 62 /* old versions */ 63 *major = ver; 64 *minor = 0; 65 return 0; 66 } else { 67 return -EINVAL; 68 } 69 } else { 70 /* 71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 72 * registers are shifted down, read DSI_VERSION again with 73 * the shifted offset 74 */ 75 ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 76 ver = FIELD(ver, DSI_VERSION_MAJOR); 77 if (ver == MSM_DSI_VER_MAJOR_6G) { 78 /* 6G version */ 79 *major = ver; 80 *minor = readl(base + REG_DSI_6G_HW_VERSION); 81 return 0; 82 } else { 83 return -EINVAL; 84 } 85 } 86 } 87 88 #define DSI_ERR_STATE_ACK 0x0000 89 #define DSI_ERR_STATE_TIMEOUT 0x0001 90 #define DSI_ERR_STATE_DLN0_PHY 0x0002 91 #define DSI_ERR_STATE_FIFO 0x0004 92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 95 96 #define DSI_CLK_CTRL_ENABLE_CLKS \ 97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 101 102 struct msm_dsi_host { 103 struct mipi_dsi_host base; 104 105 struct platform_device *pdev; 106 struct drm_device *dev; 107 108 int id; 109 110 void __iomem *ctrl_base; 111 phys_addr_t ctrl_size; 112 struct regulator_bulk_data *supplies; 113 114 int num_bus_clks; 115 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 116 117 struct clk *byte_clk; 118 struct clk *esc_clk; 119 struct clk *pixel_clk; 120 struct clk *byte_intf_clk; 121 122 /* 123 * Clocks which needs to be properly parented between DISPCC and DSI PHY 124 * PLL: 125 */ 126 struct clk *byte_src_clk; 127 struct clk *pixel_src_clk; 128 struct clk *dsi_pll_byte_clk; 129 struct clk *dsi_pll_pixel_clk; 130 131 unsigned long byte_clk_rate; 132 unsigned long byte_intf_clk_rate; 133 unsigned long pixel_clk_rate; 134 unsigned long esc_clk_rate; 135 136 /* DSI v2 specific clocks */ 137 struct clk *src_clk; 138 139 unsigned long src_clk_rate; 140 141 const struct msm_dsi_cfg_handler *cfg_hnd; 142 143 struct completion dma_comp; 144 struct completion video_comp; 145 struct mutex dev_mutex; 146 struct mutex cmd_mutex; 147 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 148 149 u32 err_work_state; 150 struct work_struct err_work; 151 struct workqueue_struct *workqueue; 152 153 /* DSI 6G TX buffer*/ 154 struct drm_gem_object *tx_gem_obj; 155 struct drm_gpuvm *vm; 156 157 /* DSI v2 TX buffer */ 158 void *tx_buf; 159 dma_addr_t tx_buf_paddr; 160 161 int tx_size; 162 163 u8 *rx_buf; 164 165 struct regmap *sfpb; 166 167 struct drm_display_mode *mode; 168 struct drm_dsc_config *dsc; 169 unsigned int dsc_slice_per_pkt; 170 171 /* connected device info */ 172 unsigned int channel; 173 unsigned int lanes; 174 enum mipi_dsi_pixel_format format; 175 unsigned long mode_flags; 176 177 /* lane data parsed via DT */ 178 int dlane_swap; 179 int num_data_lanes; 180 181 /* from phy DT */ 182 bool cphy_mode; 183 184 u32 dma_cmd_ctrl_restore; 185 186 bool registered; 187 bool power_on; 188 bool enabled; 189 int irq; 190 }; 191 192 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 193 { 194 return readl(msm_host->ctrl_base + reg); 195 } 196 197 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 198 { 199 writel(data, msm_host->ctrl_base + reg); 200 } 201 202 static const struct msm_dsi_cfg_handler * 203 dsi_get_config(struct msm_dsi_host *msm_host) 204 { 205 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 206 struct device *dev = &msm_host->pdev->dev; 207 struct clk *ahb_clk; 208 int ret; 209 u32 major = 0, minor = 0; 210 211 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 212 if (IS_ERR(ahb_clk)) { 213 dev_err_probe(dev, PTR_ERR(ahb_clk), "%s: cannot get interface clock\n", 214 __func__); 215 goto exit; 216 } 217 218 pm_runtime_get_sync(dev); 219 220 ret = clk_prepare_enable(ahb_clk); 221 if (ret) { 222 dev_err_probe(dev, ret, "%s: unable to enable ahb_clk\n", __func__); 223 goto runtime_put; 224 } 225 226 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 227 if (ret) { 228 dev_err_probe(dev, ret, "%s: Invalid version\n", __func__); 229 goto disable_clks; 230 } 231 232 cfg_hnd = msm_dsi_cfg_get(major, minor); 233 234 DBG("%s: Version %x:%x\n", __func__, major, minor); 235 236 disable_clks: 237 clk_disable_unprepare(ahb_clk); 238 runtime_put: 239 pm_runtime_put_sync(dev); 240 exit: 241 return cfg_hnd; 242 } 243 244 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 245 { 246 return container_of(host, struct msm_dsi_host, base); 247 } 248 249 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 250 { 251 struct platform_device *pdev = msm_host->pdev; 252 int ret = 0; 253 254 msm_host->src_clk = msm_clk_get(pdev, "src"); 255 256 if (IS_ERR(msm_host->src_clk)) { 257 ret = PTR_ERR(msm_host->src_clk); 258 pr_err("%s: can't find src clock. ret=%d\n", 259 __func__, ret); 260 msm_host->src_clk = NULL; 261 return ret; 262 } 263 264 return ret; 265 } 266 267 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 268 { 269 struct platform_device *pdev = msm_host->pdev; 270 int ret = 0; 271 272 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 273 if (IS_ERR(msm_host->byte_intf_clk)) { 274 ret = PTR_ERR(msm_host->byte_intf_clk); 275 pr_err("%s: can't find byte_intf clock. ret=%d\n", 276 __func__, ret); 277 } 278 279 return ret; 280 } 281 282 int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host) 283 { 284 struct device *dev = &msm_host->pdev->dev; 285 int ret; 286 287 ret = dsi_clk_init_6g_v2(msm_host); 288 if (ret) 289 return ret; 290 291 msm_host->byte_src_clk = devm_clk_get(dev, "byte_src"); 292 if (IS_ERR(msm_host->byte_src_clk)) 293 return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk), 294 "can't get byte_src clock\n"); 295 296 msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte"); 297 if (IS_ERR(msm_host->dsi_pll_byte_clk)) 298 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk), 299 "can't get dsi_pll_byte clock\n"); 300 301 msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src"); 302 if (IS_ERR(msm_host->pixel_src_clk)) 303 return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk), 304 "can't get pixel_src clock\n"); 305 306 msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel"); 307 if (IS_ERR(msm_host->dsi_pll_pixel_clk)) 308 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk), 309 "can't get dsi_pll_pixel clock\n"); 310 311 return 0; 312 } 313 314 static int dsi_clk_init(struct msm_dsi_host *msm_host) 315 { 316 struct platform_device *pdev = msm_host->pdev; 317 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 318 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 319 int i, ret = 0; 320 321 /* get bus clocks */ 322 for (i = 0; i < cfg->num_bus_clks; i++) 323 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 324 msm_host->num_bus_clks = cfg->num_bus_clks; 325 326 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 327 if (ret < 0) 328 return dev_err_probe(&pdev->dev, ret, "Unable to get clocks\n"); 329 330 /* get link and source clocks */ 331 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 332 if (IS_ERR(msm_host->byte_clk)) 333 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->byte_clk), 334 "%s: can't find dsi_byte clock\n", 335 __func__); 336 337 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 338 if (IS_ERR(msm_host->pixel_clk)) 339 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->pixel_clk), 340 "%s: can't find dsi_pixel clock\n", 341 __func__); 342 343 msm_host->esc_clk = msm_clk_get(pdev, "core"); 344 if (IS_ERR(msm_host->esc_clk)) 345 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->esc_clk), 346 "%s: can't find dsi_esc clock\n", 347 __func__); 348 349 if (cfg_hnd->ops->clk_init_ver) 350 ret = cfg_hnd->ops->clk_init_ver(msm_host); 351 352 return ret; 353 } 354 355 int msm_dsi_runtime_suspend(struct device *dev) 356 { 357 struct platform_device *pdev = to_platform_device(dev); 358 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 359 struct mipi_dsi_host *host = msm_dsi->host; 360 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 361 362 if (!msm_host->cfg_hnd) 363 return 0; 364 365 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 366 367 return 0; 368 } 369 370 int msm_dsi_runtime_resume(struct device *dev) 371 { 372 struct platform_device *pdev = to_platform_device(dev); 373 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 374 struct mipi_dsi_host *host = msm_dsi->host; 375 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 376 377 if (!msm_host->cfg_hnd) 378 return 0; 379 380 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 381 } 382 383 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 384 { 385 int ret; 386 387 DBG("Set clk rates: pclk=%lu, byteclk=%lu", 388 msm_host->pixel_clk_rate, msm_host->byte_clk_rate); 389 390 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 391 msm_host->byte_clk_rate); 392 if (ret) { 393 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 394 return ret; 395 } 396 397 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 398 if (ret) { 399 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 400 return ret; 401 } 402 403 if (msm_host->byte_intf_clk) { 404 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); 405 if (ret) { 406 pr_err("%s: Failed to set rate byte intf clk, %d\n", 407 __func__, ret); 408 return ret; 409 } 410 } 411 412 return 0; 413 } 414 415 int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host) 416 { 417 struct device *dev = &msm_host->pdev->dev; 418 int ret; 419 420 /* 421 * DSI PHY PLLs have to be enabled to allow reparenting to them, so 422 * cannot use assigned-clock-parents. 423 */ 424 ret = clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk); 425 if (ret) 426 dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret); 427 428 ret = clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_clk); 429 if (ret) 430 dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret); 431 432 return dsi_link_clk_set_rate_6g(msm_host); 433 } 434 435 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 436 { 437 int ret; 438 439 ret = clk_prepare_enable(msm_host->esc_clk); 440 if (ret) { 441 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 442 goto error; 443 } 444 445 ret = clk_prepare_enable(msm_host->byte_clk); 446 if (ret) { 447 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 448 goto byte_clk_err; 449 } 450 451 ret = clk_prepare_enable(msm_host->pixel_clk); 452 if (ret) { 453 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 454 goto pixel_clk_err; 455 } 456 457 ret = clk_prepare_enable(msm_host->byte_intf_clk); 458 if (ret) { 459 pr_err("%s: Failed to enable byte intf clk\n", 460 __func__); 461 goto byte_intf_clk_err; 462 } 463 464 return 0; 465 466 byte_intf_clk_err: 467 clk_disable_unprepare(msm_host->pixel_clk); 468 pixel_clk_err: 469 clk_disable_unprepare(msm_host->byte_clk); 470 byte_clk_err: 471 clk_disable_unprepare(msm_host->esc_clk); 472 error: 473 return ret; 474 } 475 476 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 477 { 478 int ret; 479 480 DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 481 msm_host->pixel_clk_rate, msm_host->byte_clk_rate, 482 msm_host->esc_clk_rate, msm_host->src_clk_rate); 483 484 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 485 if (ret) { 486 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 487 return ret; 488 } 489 490 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 491 if (ret) { 492 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 493 return ret; 494 } 495 496 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 497 if (ret) { 498 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 499 return ret; 500 } 501 502 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 503 if (ret) { 504 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 505 return ret; 506 } 507 508 return 0; 509 } 510 511 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 512 { 513 int ret; 514 515 ret = clk_prepare_enable(msm_host->byte_clk); 516 if (ret) { 517 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 518 goto error; 519 } 520 521 ret = clk_prepare_enable(msm_host->esc_clk); 522 if (ret) { 523 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 524 goto esc_clk_err; 525 } 526 527 ret = clk_prepare_enable(msm_host->src_clk); 528 if (ret) { 529 pr_err("%s: Failed to enable dsi src clk\n", __func__); 530 goto src_clk_err; 531 } 532 533 ret = clk_prepare_enable(msm_host->pixel_clk); 534 if (ret) { 535 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 536 goto pixel_clk_err; 537 } 538 539 return 0; 540 541 pixel_clk_err: 542 clk_disable_unprepare(msm_host->src_clk); 543 src_clk_err: 544 clk_disable_unprepare(msm_host->esc_clk); 545 esc_clk_err: 546 clk_disable_unprepare(msm_host->byte_clk); 547 error: 548 return ret; 549 } 550 551 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 552 { 553 /* Drop the performance state vote */ 554 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 555 clk_disable_unprepare(msm_host->esc_clk); 556 clk_disable_unprepare(msm_host->pixel_clk); 557 clk_disable_unprepare(msm_host->byte_intf_clk); 558 clk_disable_unprepare(msm_host->byte_clk); 559 } 560 561 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 562 { 563 clk_disable_unprepare(msm_host->pixel_clk); 564 clk_disable_unprepare(msm_host->src_clk); 565 clk_disable_unprepare(msm_host->esc_clk); 566 clk_disable_unprepare(msm_host->byte_clk); 567 } 568 569 /** 570 * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case 571 * @mode: The selected mode for the DSI output 572 * @dsc: DRM DSC configuration for this DSI output 573 * @is_bonded_dsi: True if two DSI controllers are bonded 574 * 575 * Adjust the pclk rate by calculating a new hdisplay proportional to 576 * the compression ratio such that: 577 * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp 578 * 579 * Porches do not need to be adjusted: 580 * - For VIDEO mode they are not compressed by DSC and are passed as is. 581 * - For CMD mode there are no actual porches. Instead these fields 582 * currently represent the overhead to the image data transfer. As such, they 583 * are calculated for the final mode parameters (after the compression) and 584 * are not to be adjusted too. 585 * 586 * FIXME: Reconsider this if/when CMD mode handling is rewritten to use 587 * transfer time and data overhead as a starting point of the calculations. 588 */ 589 static unsigned long 590 dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, 591 const struct drm_dsc_config *dsc, 592 bool is_bonded_dsi) 593 { 594 int hdisplay, new_hdisplay, new_htotal; 595 596 /* 597 * For bonded DSI, split hdisplay across two links and round up each 598 * half separately, passing the full hdisplay would only round up once. 599 * This also aligns with the hdisplay we program later in 600 * dsi_timing_setup() 601 */ 602 hdisplay = mode->hdisplay; 603 if (is_bonded_dsi) 604 hdisplay /= 2; 605 606 new_hdisplay = DIV_ROUND_UP(hdisplay * drm_dsc_get_bpp_int(dsc), 607 dsc->bits_per_component * 3); 608 609 if (is_bonded_dsi) 610 new_hdisplay *= 2; 611 612 new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; 613 614 return mult_frac(mode->clock * 1000u, new_htotal, mode->htotal); 615 } 616 617 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, 618 const struct drm_dsc_config *dsc, bool is_bonded_dsi) 619 { 620 unsigned long pclk_rate; 621 622 pclk_rate = mode->clock * 1000u; 623 624 if (dsc) 625 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc, is_bonded_dsi); 626 627 /* 628 * For bonded DSI mode, the current DRM mode has the complete width of the 629 * panel. Since, the complete panel is driven by two DSI controllers, 630 * the clock rates have to be split between the two dsi controllers. 631 * Adjust the byte and pixel clock rates for each dsi host accordingly. 632 */ 633 if (is_bonded_dsi) 634 pclk_rate /= 2; 635 636 return pclk_rate; 637 } 638 639 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 640 const struct drm_display_mode *mode) 641 { 642 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 643 u8 lanes = msm_host->lanes; 644 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 645 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); 646 unsigned long pclk_bpp; 647 648 if (lanes == 0) { 649 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 650 lanes = 1; 651 } 652 653 /* CPHY "byte_clk" is in units of 16 bits */ 654 if (msm_host->cphy_mode) 655 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); 656 else 657 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); 658 659 return pclk_bpp; 660 } 661 662 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 663 { 664 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); 665 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 666 msm_host->mode); 667 668 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 669 msm_host->byte_clk_rate); 670 } 671 672 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 673 { 674 if (!msm_host->mode) { 675 pr_err("%s: mode not set\n", __func__); 676 return -EINVAL; 677 } 678 679 dsi_calc_pclk(msm_host, is_bonded_dsi); 680 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 681 return 0; 682 } 683 684 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 685 { 686 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 687 unsigned int esc_mhz, esc_div; 688 unsigned long byte_mhz; 689 690 dsi_calc_pclk(msm_host, is_bonded_dsi); 691 692 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); 693 694 /* 695 * esc clock is byte clock followed by a 4 bit divider, 696 * we need to find an escape clock frequency within the 697 * mipi DSI spec range within the maximum divider limit 698 * We iterate here between an escape clock frequencey 699 * between 20 Mhz to 5 Mhz and pick up the first one 700 * that can be supported by our divider 701 */ 702 703 byte_mhz = msm_host->byte_clk_rate / 1000000; 704 705 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 706 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 707 708 /* 709 * TODO: Ideally, we shouldn't know what sort of divider 710 * is available in mmss_cc, we're just assuming that 711 * it'll always be a 4 bit divider. Need to come up with 712 * a better way here. 713 */ 714 if (esc_div >= 1 && esc_div <= 16) 715 break; 716 } 717 718 if (esc_mhz < 5) 719 return -EINVAL; 720 721 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 722 723 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 724 msm_host->src_clk_rate); 725 726 return 0; 727 } 728 729 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 730 { 731 u32 intr; 732 unsigned long flags; 733 734 spin_lock_irqsave(&msm_host->intr_lock, flags); 735 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 736 737 if (enable) 738 intr |= mask; 739 else 740 intr &= ~mask; 741 742 DBG("intr=%x enable=%d", intr, enable); 743 744 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 745 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 746 } 747 748 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 749 { 750 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 751 return BURST_MODE; 752 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 753 return NON_BURST_SYNCH_PULSE; 754 755 return NON_BURST_SYNCH_EVENT; 756 } 757 758 static inline enum dsi_vid_dst_format 759 dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 760 { 761 switch (mipi_fmt) { 762 case MIPI_DSI_FMT_RGB101010: return VID_DST_FORMAT_RGB101010; 763 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 764 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 765 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 766 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 767 default: return VID_DST_FORMAT_RGB888; 768 } 769 } 770 771 static inline enum dsi_cmd_dst_format 772 dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 773 { 774 switch (mipi_fmt) { 775 case MIPI_DSI_FMT_RGB101010: return CMD_DST_FORMAT_RGB101010; 776 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 777 case MIPI_DSI_FMT_RGB666_PACKED: 778 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 779 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 780 default: return CMD_DST_FORMAT_RGB888; 781 } 782 } 783 784 static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) 785 { 786 dsi_write(msm_host, REG_DSI_CTRL, 0); 787 } 788 789 static bool msm_dsi_host_version_geq(struct msm_dsi_host *msm_host, 790 u32 major, u32 minor) 791 { 792 return msm_host->cfg_hnd->major > major || 793 (msm_host->cfg_hnd->major == major && 794 msm_host->cfg_hnd->minor >= minor); 795 } 796 797 bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host) 798 { 799 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 800 801 return msm_host->dsc && 802 msm_dsi_host_version_geq(msm_host, MSM_DSI_VER_MAJOR_6G, 803 MSM_DSI_6G_VER_MINOR_V2_5_0); 804 } 805 806 static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, 807 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 808 { 809 u32 flags = msm_host->mode_flags; 810 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 811 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 812 u32 data = 0, lane_ctrl = 0; 813 814 if (flags & MIPI_DSI_MODE_VIDEO) { 815 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 816 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 817 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 818 data |= DSI_VID_CFG0_HFP_POWER_STOP; 819 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 820 data |= DSI_VID_CFG0_HBP_POWER_STOP; 821 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 822 data |= DSI_VID_CFG0_HSA_POWER_STOP; 823 /* Always set low power stop mode for BLLP 824 * to let command engine send packets 825 */ 826 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 827 DSI_VID_CFG0_BLLP_POWER_STOP; 828 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 829 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 830 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 831 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 832 data |= DSI_VID_CFG0_DATABUS_WIDEN; 833 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 834 835 /* Do not swap RGB colors */ 836 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 837 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 838 } else { 839 /* Do not swap RGB colors */ 840 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 841 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 842 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 843 844 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 845 DSI_CMD_CFG1_WR_MEM_CONTINUE( 846 MIPI_DCS_WRITE_MEMORY_CONTINUE); 847 /* Always insert DCS command */ 848 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 849 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 850 851 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 852 data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); 853 854 if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) 855 data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; 856 857 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 858 data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; 859 860 dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); 861 } 862 } 863 864 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 865 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 866 DSI_CMD_DMA_CTRL_LOW_POWER); 867 868 data = 0; 869 /* Always assume dedicated TE pin */ 870 data |= DSI_TRIG_CTRL_TE; 871 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 872 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 873 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 874 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 875 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 876 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 877 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 878 879 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 880 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 881 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 882 883 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 884 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 885 phy_shared_timings->clk_pre_inc_by_2) 886 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 887 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 888 889 data = 0; 890 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 891 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 892 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 893 894 /* allow only ack-err-status to generate interrupt */ 895 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 896 897 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 898 899 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 900 901 data = DSI_CTRL_CLK_EN; 902 903 DBG("lane number=%d", msm_host->lanes); 904 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 905 906 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 907 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 908 909 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 910 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 911 912 if (msm_dsi_phy_set_continuous_clock(phy, true)) 913 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 914 915 dsi_write(msm_host, REG_DSI_LANE_CTRL, 916 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 917 } 918 919 data |= DSI_CTRL_ENABLE; 920 921 dsi_write(msm_host, REG_DSI_CTRL, data); 922 923 if (msm_host->cphy_mode) 924 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 925 } 926 927 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode) 928 { 929 struct drm_dsc_config *dsc = msm_host->dsc; 930 u32 reg, reg_ctrl, reg_ctrl2; 931 u32 slice_per_intf, total_bytes_per_intf; 932 u32 pkt_per_line; 933 u32 eol_byte_num; 934 u32 bytes_per_pkt; 935 936 /* first calculate dsc parameters and then program 937 * compress mode registers 938 */ 939 slice_per_intf = dsc->slice_count; 940 941 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 942 bytes_per_pkt = dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt; 943 944 eol_byte_num = total_bytes_per_intf % 3; 945 pkt_per_line = slice_per_intf / msm_host->dsc_slice_per_pkt; 946 947 if (is_cmd_mode) /* packet data type */ 948 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 949 else 950 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 951 952 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 953 * registers have similar offsets, so for below common code use 954 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 955 * 956 * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) 957 */ 958 if (pkt_per_line > 4) 959 drm_warn_once(msm_host->dev, "pkt_per_line too big"); 960 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 961 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 962 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 963 964 if (is_cmd_mode) { 965 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 966 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 967 968 reg_ctrl &= ~0xffff; 969 reg_ctrl |= reg; 970 971 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 972 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 973 974 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 975 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 976 } else { 977 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); 978 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 979 } 980 } 981 982 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 983 { 984 struct drm_display_mode *mode = msm_host->mode; 985 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 986 u32 h_total = mode->htotal; 987 u32 v_total = mode->vtotal; 988 u32 hs_end = mode->hsync_end - mode->hsync_start; 989 u32 vs_end = mode->vsync_end - mode->vsync_start; 990 u32 ha_start = h_total - mode->hsync_start; 991 u32 ha_end = ha_start + mode->hdisplay; 992 u32 va_start = v_total - mode->vsync_start; 993 u32 va_end = va_start + mode->vdisplay; 994 u32 hdisplay = mode->hdisplay; 995 u32 wc; 996 int ret; 997 bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base); 998 999 DBG(""); 1000 1001 /* 1002 * For bonded DSI mode, the current DRM mode has 1003 * the complete width of the panel. Since, the complete 1004 * panel is driven by two DSI controllers, the horizontal 1005 * timings have to be split between the two dsi controllers. 1006 * Adjust the DSI host timing values accordingly. 1007 */ 1008 if (is_bonded_dsi) { 1009 h_total /= 2; 1010 hs_end /= 2; 1011 ha_start /= 2; 1012 ha_end /= 2; 1013 hdisplay /= 2; 1014 } 1015 1016 if (msm_host->dsc) { 1017 struct drm_dsc_config *dsc = msm_host->dsc; 1018 u32 bits_per_pclk; 1019 1020 /* update dsc params with timing params */ 1021 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 1022 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 1023 mode->hdisplay, mode->vdisplay); 1024 return; 1025 } 1026 1027 dsc->pic_width = mode->hdisplay; 1028 dsc->pic_height = mode->vdisplay; 1029 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 1030 1031 /* we do the calculations for dsc parameters here so that 1032 * panel can use these parameters 1033 */ 1034 ret = dsi_populate_dsc_params(msm_host, dsc); 1035 if (ret) 1036 return; 1037 1038 /* 1039 * DPU sends 3 bytes per pclk cycle to DSI. If widebus is 1040 * enabled, MDP always sends out 48-bit compressed data per 1041 * pclk and on average, for video mode, DSI consumes only an 1042 * amount of compressed data equivalent to the uncompressed 1043 * pixel depth per pclk. 1044 * 1045 * Calculate the number of pclks needed to transmit one line of 1046 * the compressed data. 1047 1048 * The back/font porch and pulse width are kept intact. For 1049 * VIDEO mode they represent timing parameters rather than 1050 * actual data transfer, see the documentation for 1051 * dsi_adjust_pclk_for_compression(). For CMD mode they are 1052 * unused anyway. 1053 */ 1054 h_total -= hdisplay; 1055 if (wide_bus_enabled) { 1056 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) 1057 bits_per_pclk = dsc->bits_per_component * 3; 1058 else 1059 bits_per_pclk = 48; 1060 } else { 1061 bits_per_pclk = 24; 1062 } 1063 1064 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc) * 8, bits_per_pclk); 1065 1066 h_total += hdisplay; 1067 ha_end = ha_start + hdisplay; 1068 } 1069 1070 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 1071 if (msm_host->dsc) 1072 dsi_update_dsc_timing(msm_host, false); 1073 1074 dsi_write(msm_host, REG_DSI_ACTIVE_H, 1075 DSI_ACTIVE_H_START(ha_start) | 1076 DSI_ACTIVE_H_END(ha_end)); 1077 dsi_write(msm_host, REG_DSI_ACTIVE_V, 1078 DSI_ACTIVE_V_START(va_start) | 1079 DSI_ACTIVE_V_END(va_end)); 1080 dsi_write(msm_host, REG_DSI_TOTAL, 1081 DSI_TOTAL_H_TOTAL(h_total - 1) | 1082 DSI_TOTAL_V_TOTAL(v_total - 1)); 1083 1084 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 1085 DSI_ACTIVE_HSYNC_START(hs_start) | 1086 DSI_ACTIVE_HSYNC_END(hs_end)); 1087 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 1088 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 1089 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1090 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1091 } else { /* command mode */ 1092 if (msm_host->dsc) 1093 dsi_update_dsc_timing(msm_host, true); 1094 1095 /* image data and 1 byte write_memory_start cmd */ 1096 if (!msm_host->dsc) 1097 wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; 1098 else 1099 /* 1100 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. 1101 */ 1102 wc = msm_host->dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt + 1; 1103 1104 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1105 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1106 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1107 msm_host->channel) | 1108 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1109 MIPI_DSI_DCS_LONG_WRITE)); 1110 1111 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1112 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1113 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1114 } 1115 } 1116 1117 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1118 { 1119 u32 ctrl; 1120 1121 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1122 1123 if (ctrl & DSI_CTRL_ENABLE) { 1124 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1125 /* 1126 * dsi controller need to be disabled before 1127 * clocks turned on 1128 */ 1129 wmb(); 1130 } 1131 1132 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1133 wmb(); /* clocks need to be enabled before reset */ 1134 1135 /* dsi controller can only be reset while clocks are running */ 1136 dsi_write(msm_host, REG_DSI_RESET, 1); 1137 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1138 dsi_write(msm_host, REG_DSI_RESET, 0); 1139 wmb(); /* controller out of reset */ 1140 1141 if (ctrl & DSI_CTRL_ENABLE) { 1142 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1143 wmb(); /* make sure dsi controller enabled again */ 1144 } 1145 } 1146 1147 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1148 bool video_mode, bool enable) 1149 { 1150 u32 dsi_ctrl; 1151 1152 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1153 1154 if (!enable) { 1155 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1156 DSI_CTRL_CMD_MODE_EN); 1157 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1158 DSI_IRQ_MASK_VIDEO_DONE, 0); 1159 } else { 1160 if (video_mode) { 1161 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1162 } else { /* command mode */ 1163 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1164 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1165 } 1166 dsi_ctrl |= DSI_CTRL_ENABLE; 1167 } 1168 1169 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1170 } 1171 1172 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1173 { 1174 u32 data; 1175 1176 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1177 1178 if (mode == 0) 1179 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1180 else 1181 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1182 1183 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1184 } 1185 1186 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1187 { 1188 u32 ret = 0; 1189 struct device *dev = &msm_host->pdev->dev; 1190 1191 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1192 1193 reinit_completion(&msm_host->video_comp); 1194 1195 ret = wait_for_completion_timeout(&msm_host->video_comp, 1196 msecs_to_jiffies(70)); 1197 1198 if (ret == 0) 1199 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1200 1201 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1202 } 1203 1204 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1205 { 1206 u32 data; 1207 1208 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1209 return; 1210 1211 data = dsi_read(msm_host, REG_DSI_STATUS0); 1212 1213 /* if video mode engine is not busy, its because 1214 * either timing engine was not turned on or the 1215 * DSI controller has finished transmitting the video 1216 * data already, so no need to wait in those cases 1217 */ 1218 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1219 return; 1220 1221 if (msm_host->power_on && msm_host->enabled) { 1222 dsi_wait4video_done(msm_host); 1223 /* delay 4 ms to skip BLLP */ 1224 usleep_range(2000, 4000); 1225 } 1226 } 1227 1228 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1229 { 1230 struct drm_device *dev = msm_host->dev; 1231 struct msm_drm_private *priv = dev->dev_private; 1232 uint64_t iova; 1233 u8 *data; 1234 1235 msm_host->vm = drm_gpuvm_get(priv->kms->vm); 1236 1237 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1238 msm_host->vm, 1239 &msm_host->tx_gem_obj, &iova); 1240 1241 if (IS_ERR(data)) { 1242 msm_host->tx_gem_obj = NULL; 1243 return PTR_ERR(data); 1244 } 1245 1246 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1247 1248 msm_host->tx_size = msm_host->tx_gem_obj->size; 1249 1250 return 0; 1251 } 1252 1253 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1254 { 1255 struct drm_device *dev = msm_host->dev; 1256 1257 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1258 &msm_host->tx_buf_paddr, GFP_KERNEL); 1259 if (!msm_host->tx_buf) 1260 return -ENOMEM; 1261 1262 msm_host->tx_size = size; 1263 1264 return 0; 1265 } 1266 1267 void msm_dsi_tx_buf_free(struct mipi_dsi_host *host) 1268 { 1269 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1270 struct drm_device *dev = msm_host->dev; 1271 1272 /* 1273 * This is possible if we're tearing down before we've had a chance to 1274 * fully initialize. A very real possibility if our probe is deferred, 1275 * in which case we'll hit msm_dsi_host_destroy() without having run 1276 * through the dsi_tx_buf_alloc(). 1277 */ 1278 if (!dev) 1279 return; 1280 1281 if (msm_host->tx_gem_obj) { 1282 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->vm); 1283 drm_gpuvm_put(msm_host->vm); 1284 msm_host->tx_gem_obj = NULL; 1285 msm_host->vm = NULL; 1286 } 1287 1288 if (msm_host->tx_buf) 1289 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1290 msm_host->tx_buf_paddr); 1291 } 1292 1293 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1294 { 1295 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1296 } 1297 1298 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1299 { 1300 return msm_host->tx_buf; 1301 } 1302 1303 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1304 { 1305 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1306 } 1307 1308 /* 1309 * prepare cmd buffer to be txed 1310 */ 1311 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1312 const struct mipi_dsi_msg *msg) 1313 { 1314 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1315 struct mipi_dsi_packet packet; 1316 int len; 1317 int ret; 1318 u8 *data; 1319 1320 ret = mipi_dsi_create_packet(&packet, msg); 1321 if (ret) { 1322 pr_err("%s: create packet failed, %d\n", __func__, ret); 1323 return ret; 1324 } 1325 len = (packet.size + 3) & (~0x3); 1326 1327 if (len > msm_host->tx_size) { 1328 pr_err("%s: packet size is too big\n", __func__); 1329 return -EINVAL; 1330 } 1331 1332 data = cfg_hnd->ops->tx_buf_get(msm_host); 1333 if (IS_ERR(data)) { 1334 ret = PTR_ERR(data); 1335 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1336 return ret; 1337 } 1338 1339 /* MSM specific command format in memory */ 1340 data[0] = packet.header[1]; 1341 data[1] = packet.header[2]; 1342 data[2] = packet.header[0]; 1343 data[3] = BIT(7); /* Last packet */ 1344 if (mipi_dsi_packet_format_is_long(msg->type)) 1345 data[3] |= BIT(6); 1346 if (msg->rx_buf && msg->rx_len) 1347 data[3] |= BIT(5); 1348 1349 /* Long packet */ 1350 if (packet.payload && packet.payload_length) 1351 memcpy(data + 4, packet.payload, packet.payload_length); 1352 1353 /* Append 0xff to the end */ 1354 if (packet.size < len) 1355 memset(data + packet.size, 0xff, len - packet.size); 1356 1357 if (cfg_hnd->ops->tx_buf_put) 1358 cfg_hnd->ops->tx_buf_put(msm_host); 1359 1360 return len; 1361 } 1362 1363 /* 1364 * dsi_short_read1_resp: 1 parameter 1365 */ 1366 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1367 { 1368 u8 *data = msg->rx_buf; 1369 1370 if (data && (msg->rx_len >= 1)) { 1371 *data = buf[1]; /* strip out dcs type */ 1372 return 1; 1373 } 1374 1375 pr_err("%s: read data does not match with rx_buf len %zu\n", 1376 __func__, msg->rx_len); 1377 return -EINVAL; 1378 } 1379 1380 /* 1381 * dsi_short_read2_resp: 2 parameter 1382 */ 1383 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1384 { 1385 u8 *data = msg->rx_buf; 1386 1387 if (data && (msg->rx_len >= 2)) { 1388 data[0] = buf[1]; /* strip out dcs type */ 1389 data[1] = buf[2]; 1390 return 2; 1391 } 1392 1393 pr_err("%s: read data does not match with rx_buf len %zu\n", 1394 __func__, msg->rx_len); 1395 return -EINVAL; 1396 } 1397 1398 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1399 { 1400 /* strip out 4 byte dcs header */ 1401 if (msg->rx_buf && msg->rx_len) 1402 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1403 1404 return msg->rx_len; 1405 } 1406 1407 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1408 { 1409 struct drm_device *dev = msm_host->dev; 1410 struct msm_drm_private *priv = dev->dev_private; 1411 1412 if (!dma_base) 1413 return -EINVAL; 1414 1415 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1416 priv->kms->vm, dma_base); 1417 } 1418 1419 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1420 { 1421 if (!dma_base) 1422 return -EINVAL; 1423 1424 *dma_base = msm_host->tx_buf_paddr; 1425 return 0; 1426 } 1427 1428 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1429 { 1430 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1431 int ret; 1432 uint64_t dma_base; 1433 bool triggered; 1434 1435 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1436 if (ret) { 1437 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1438 return ret; 1439 } 1440 1441 reinit_completion(&msm_host->dma_comp); 1442 1443 dsi_wait4video_eng_busy(msm_host); 1444 1445 triggered = msm_dsi_manager_cmd_xfer_trigger( 1446 msm_host->id, dma_base, len); 1447 if (triggered) { 1448 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1449 msecs_to_jiffies(200)); 1450 DBG("ret=%d", ret); 1451 if (ret == 0) 1452 ret = -ETIMEDOUT; 1453 else 1454 ret = len; 1455 } else { 1456 ret = len; 1457 } 1458 1459 return ret; 1460 } 1461 1462 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1463 u8 *buf, int rx_byte, int pkt_size) 1464 { 1465 u32 *temp, data; 1466 int i, j = 0, cnt; 1467 u32 read_cnt; 1468 u8 reg[16]; 1469 int repeated_bytes = 0; 1470 int buf_offset = buf - msm_host->rx_buf; 1471 1472 temp = (u32 *)reg; 1473 cnt = (rx_byte + 3) >> 2; 1474 if (cnt > 4) 1475 cnt = 4; /* 4 x 32 bits registers only */ 1476 1477 if (rx_byte == 4) 1478 read_cnt = 4; 1479 else 1480 read_cnt = pkt_size + 6; 1481 1482 /* 1483 * In case of multiple reads from the panel, after the first read, there 1484 * is possibility that there are some bytes in the payload repeating in 1485 * the RDBK_DATA registers. Since we read all the parameters from the 1486 * panel right from the first byte for every pass. We need to skip the 1487 * repeating bytes and then append the new parameters to the rx buffer. 1488 */ 1489 if (read_cnt > 16) { 1490 int bytes_shifted; 1491 /* Any data more than 16 bytes will be shifted out. 1492 * The temp read buffer should already contain these bytes. 1493 * The remaining bytes in read buffer are the repeated bytes. 1494 */ 1495 bytes_shifted = read_cnt - 16; 1496 repeated_bytes = buf_offset - bytes_shifted; 1497 } 1498 1499 for (i = cnt - 1; i >= 0; i--) { 1500 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1501 *temp++ = ntohl(data); /* to host byte order */ 1502 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1503 } 1504 1505 for (i = repeated_bytes; i < 16; i++) 1506 buf[j++] = reg[i]; 1507 1508 return j; 1509 } 1510 1511 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1512 const struct mipi_dsi_msg *msg) 1513 { 1514 int len, ret; 1515 int bllp_len = msm_host->mode->hdisplay * 1516 mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; 1517 1518 len = dsi_cmd_dma_add(msm_host, msg); 1519 if (len < 0) { 1520 pr_err("%s: failed to add cmd type = 0x%x\n", 1521 __func__, msg->type); 1522 return len; 1523 } 1524 1525 /* 1526 * for video mode, do not send cmds more than 1527 * one pixel line, since it only transmit it 1528 * during BLLP. 1529 * 1530 * TODO: if the command is sent in LP mode, the bit rate is only 1531 * half of esc clk rate. In this case, if the video is already 1532 * actively streaming, we need to check more carefully if the 1533 * command can be fit into one BLLP. 1534 */ 1535 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1536 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1537 __func__, len); 1538 return -EINVAL; 1539 } 1540 1541 ret = dsi_cmd_dma_tx(msm_host, len); 1542 if (ret < 0) { 1543 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1544 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1545 return ret; 1546 } else if (ret < len) { 1547 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1548 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1549 return -EIO; 1550 } 1551 1552 return len; 1553 } 1554 1555 static void dsi_err_worker(struct work_struct *work) 1556 { 1557 struct msm_dsi_host *msm_host = 1558 container_of(work, struct msm_dsi_host, err_work); 1559 u32 status = msm_host->err_work_state; 1560 1561 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1562 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1563 dsi_sw_reset(msm_host); 1564 1565 /* It is safe to clear here because error irq is disabled. */ 1566 msm_host->err_work_state = 0; 1567 1568 /* enable dsi error interrupt */ 1569 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1570 } 1571 1572 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1573 { 1574 u32 status; 1575 1576 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1577 1578 if (status) { 1579 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1580 /* Writing of an extra 0 needed to clear error bits */ 1581 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1582 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1583 } 1584 } 1585 1586 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1587 { 1588 u32 status; 1589 1590 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1591 1592 if (status) { 1593 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1594 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1595 } 1596 } 1597 1598 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1599 { 1600 u32 status; 1601 1602 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1603 1604 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1605 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1606 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1607 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1608 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1609 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1610 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1611 } 1612 } 1613 1614 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1615 { 1616 u32 status; 1617 1618 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1619 1620 /* fifo underflow, overflow */ 1621 if (status) { 1622 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1623 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1624 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1625 msm_host->err_work_state |= 1626 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1627 } 1628 } 1629 1630 static void dsi_status(struct msm_dsi_host *msm_host) 1631 { 1632 u32 status; 1633 1634 status = dsi_read(msm_host, REG_DSI_STATUS0); 1635 1636 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1637 dsi_write(msm_host, REG_DSI_STATUS0, status); 1638 msm_host->err_work_state |= 1639 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1640 } 1641 } 1642 1643 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1644 { 1645 u32 status; 1646 1647 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1648 1649 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1650 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1651 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1652 } 1653 } 1654 1655 static void dsi_error(struct msm_dsi_host *msm_host) 1656 { 1657 /* disable dsi error interrupt */ 1658 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1659 1660 dsi_clk_status(msm_host); 1661 dsi_fifo_status(msm_host); 1662 dsi_ack_err_status(msm_host); 1663 dsi_timeout_status(msm_host); 1664 dsi_status(msm_host); 1665 dsi_dln0_phy_err(msm_host); 1666 1667 queue_work(msm_host->workqueue, &msm_host->err_work); 1668 } 1669 1670 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1671 { 1672 struct msm_dsi_host *msm_host = ptr; 1673 u32 isr; 1674 unsigned long flags; 1675 1676 if (!msm_host->ctrl_base) 1677 return IRQ_HANDLED; 1678 1679 spin_lock_irqsave(&msm_host->intr_lock, flags); 1680 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1681 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1682 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1683 1684 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1685 1686 if (isr & DSI_IRQ_ERROR) 1687 dsi_error(msm_host); 1688 1689 if (isr & DSI_IRQ_VIDEO_DONE) 1690 complete(&msm_host->video_comp); 1691 1692 if (isr & DSI_IRQ_CMD_DMA_DONE) 1693 complete(&msm_host->dma_comp); 1694 1695 return IRQ_HANDLED; 1696 } 1697 1698 static int dsi_host_attach(struct mipi_dsi_host *host, 1699 struct mipi_dsi_device *dsi) 1700 { 1701 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1702 int ret; 1703 1704 if (dsi->lanes > msm_host->num_data_lanes) 1705 return -EINVAL; 1706 1707 msm_host->channel = dsi->channel; 1708 msm_host->lanes = dsi->lanes; 1709 msm_host->format = dsi->format; 1710 msm_host->mode_flags = dsi->mode_flags; 1711 if (dsi->dsc) { 1712 msm_host->dsc = dsi->dsc; 1713 if (dsi->mode_flags & MIPI_DSI_MODE_DSC_ALL_SLICES_IN_PKT) 1714 msm_host->dsc_slice_per_pkt = dsi->dsc->slice_count; 1715 else 1716 msm_host->dsc_slice_per_pkt = 1; 1717 } 1718 1719 if (msm_host->format == MIPI_DSI_FMT_RGB101010) { 1720 if (!msm_dsi_host_version_geq(msm_host, MSM_DSI_VER_MAJOR_6G, 1721 MSM_DSI_6G_VER_MINOR_V2_1_0)) { 1722 DRM_DEV_ERROR(&msm_host->pdev->dev, 1723 "RGB101010 not supported on this DSI controller\n"); 1724 return -EINVAL; 1725 } 1726 1727 /* 1728 * Downstream overrides RGB101010 back to RGB888 when DSC is enabled 1729 * but widebus is not. Using RGB101010 in this case may require some 1730 * extra changes. 1731 */ 1732 if (msm_host->dsc && 1733 !msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) { 1734 dev_warn(&msm_host->pdev->dev, 1735 "RGB101010 with DSC but without widebus, may need extra changes\n"); 1736 } 1737 } 1738 1739 ret = dsi_dev_attach(msm_host->pdev); 1740 if (ret) 1741 return ret; 1742 1743 DBG("id=%d", msm_host->id); 1744 1745 return 0; 1746 } 1747 1748 static int dsi_host_detach(struct mipi_dsi_host *host, 1749 struct mipi_dsi_device *dsi) 1750 { 1751 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1752 1753 dsi_dev_detach(msm_host->pdev); 1754 1755 DBG("id=%d", msm_host->id); 1756 1757 return 0; 1758 } 1759 1760 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1761 const struct mipi_dsi_msg *msg) 1762 { 1763 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1764 int ret; 1765 1766 if (!msg || !msm_host->power_on) 1767 return -EINVAL; 1768 1769 mutex_lock(&msm_host->cmd_mutex); 1770 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1771 mutex_unlock(&msm_host->cmd_mutex); 1772 1773 return ret; 1774 } 1775 1776 static const struct mipi_dsi_host_ops dsi_host_ops = { 1777 .attach = dsi_host_attach, 1778 .detach = dsi_host_detach, 1779 .transfer = dsi_host_transfer, 1780 }; 1781 1782 /* 1783 * List of supported physical to logical lane mappings. 1784 * For example, the 2nd entry represents the following mapping: 1785 * 1786 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1787 */ 1788 static const int supported_data_lane_swaps[][4] = { 1789 { 0, 1, 2, 3 }, 1790 { 3, 0, 1, 2 }, 1791 { 2, 3, 0, 1 }, 1792 { 1, 2, 3, 0 }, 1793 { 0, 3, 2, 1 }, 1794 { 1, 0, 3, 2 }, 1795 { 2, 1, 0, 3 }, 1796 { 3, 2, 1, 0 }, 1797 }; 1798 1799 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1800 struct device_node *ep) 1801 { 1802 struct device *dev = &msm_host->pdev->dev; 1803 struct property *prop; 1804 u32 lane_map[4]; 1805 int ret, i, len, num_lanes; 1806 1807 prop = of_find_property(ep, "data-lanes", &len); 1808 if (!prop) { 1809 DRM_DEV_DEBUG(dev, 1810 "failed to find data lane mapping, using default\n"); 1811 /* Set the number of date lanes to 4 by default. */ 1812 msm_host->num_data_lanes = 4; 1813 return 0; 1814 } 1815 1816 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1817 if (num_lanes < 0) { 1818 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1819 return num_lanes; 1820 } 1821 1822 msm_host->num_data_lanes = num_lanes; 1823 1824 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1825 num_lanes); 1826 if (ret) { 1827 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1828 return ret; 1829 } 1830 1831 /* 1832 * compare DT specified physical-logical lane mappings with the ones 1833 * supported by hardware 1834 */ 1835 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1836 const int *swap = supported_data_lane_swaps[i]; 1837 int j; 1838 1839 /* 1840 * the data-lanes array we get from DT has a logical->physical 1841 * mapping. The "data lane swap" register field represents 1842 * supported configurations in a physical->logical mapping. 1843 * Translate the DT mapping to what we understand and find a 1844 * configuration that works. 1845 */ 1846 for (j = 0; j < num_lanes; j++) { 1847 if (lane_map[j] < 0 || lane_map[j] > 3) 1848 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1849 lane_map[j]); 1850 1851 if (swap[lane_map[j]] != j) 1852 break; 1853 } 1854 1855 if (j == num_lanes) { 1856 msm_host->dlane_swap = i; 1857 return 0; 1858 } 1859 } 1860 1861 return -EINVAL; 1862 } 1863 1864 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1865 { 1866 int ret; 1867 1868 if (dsc->bits_per_pixel & 0xf) { 1869 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1870 return -EINVAL; 1871 } 1872 1873 switch (dsc->bits_per_component) { 1874 case 8: 1875 case 10: 1876 case 12: 1877 /* 1878 * Only 8, 10, and 12 bpc are supported for DSC 1.1 block. 1879 * If additional bpc values need to be supported, update 1880 * this quard with the appropriate DSC version verification. 1881 */ 1882 break; 1883 default: 1884 DRM_DEV_ERROR(&msm_host->pdev->dev, 1885 "Unsupported bits_per_component value: %d\n", 1886 dsc->bits_per_component); 1887 return -EOPNOTSUPP; 1888 } 1889 1890 dsc->simple_422 = 0; 1891 dsc->convert_rgb = 1; 1892 dsc->vbr_enable = 0; 1893 1894 drm_dsc_set_const_params(dsc); 1895 drm_dsc_set_rc_buf_thresh(dsc); 1896 1897 /* DPU supports only pre-SCR panels */ 1898 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); 1899 if (ret) { 1900 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); 1901 return ret; 1902 } 1903 1904 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); 1905 dsc->line_buf_depth = dsc->bits_per_component + 1; 1906 1907 return drm_dsc_compute_rc_parameters(dsc); 1908 } 1909 1910 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1911 { 1912 struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev); 1913 struct device *dev = &msm_host->pdev->dev; 1914 struct device_node *np = dev->of_node; 1915 struct device_node *endpoint; 1916 const char *te_source; 1917 int ret = 0; 1918 1919 /* 1920 * Get the endpoint of the output port of the DSI host. In our case, 1921 * this is mapped to port number with reg = 1. Don't return an error if 1922 * the remote endpoint isn't defined. It's possible that there is 1923 * nothing connected to the dsi output. 1924 */ 1925 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1926 if (!endpoint) { 1927 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1928 return 0; 1929 } 1930 1931 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1932 if (ret) { 1933 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1934 __func__, ret); 1935 ret = -EINVAL; 1936 goto err; 1937 } 1938 1939 ret = of_property_read_string(endpoint, "qcom,te-source", &te_source); 1940 if (ret && ret != -EINVAL) { 1941 DRM_DEV_ERROR(dev, "%s: invalid TE source configuration %d\n", 1942 __func__, ret); 1943 goto err; 1944 } 1945 if (!ret) { 1946 msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL); 1947 if (!msm_dsi->te_source) { 1948 DRM_DEV_ERROR(dev, "%s: failed to allocate te_source\n", 1949 __func__); 1950 ret = -ENOMEM; 1951 goto err; 1952 } 1953 } 1954 ret = 0; 1955 1956 if (of_property_present(np, "syscon-sfpb")) { 1957 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1958 "syscon-sfpb"); 1959 if (IS_ERR(msm_host->sfpb)) { 1960 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1961 __func__); 1962 ret = PTR_ERR(msm_host->sfpb); 1963 } 1964 } 1965 1966 err: 1967 of_node_put(endpoint); 1968 1969 return ret; 1970 } 1971 1972 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1973 { 1974 struct platform_device *pdev = msm_host->pdev; 1975 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1976 struct resource *res; 1977 int i, j; 1978 1979 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1980 if (!res) 1981 return -EINVAL; 1982 1983 for (i = 0; i < VARIANTS_MAX; i++) 1984 for (j = 0; j < DSI_MAX; j++) 1985 if (cfg->io_start[i][j] == res->start) 1986 return j; 1987 1988 return -EINVAL; 1989 } 1990 1991 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1992 { 1993 struct msm_dsi_host *msm_host = NULL; 1994 struct platform_device *pdev = msm_dsi->pdev; 1995 const struct msm_dsi_config *cfg; 1996 int ret; 1997 1998 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1999 if (!msm_host) 2000 return -ENOMEM; 2001 2002 msm_host->pdev = pdev; 2003 msm_dsi->host = &msm_host->base; 2004 2005 ret = dsi_host_parse_dt(msm_host); 2006 if (ret) 2007 return dev_err_probe(&pdev->dev, ret, "%s: failed to parse dt\n", 2008 __func__); 2009 2010 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 2011 if (IS_ERR(msm_host->ctrl_base)) 2012 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->ctrl_base), 2013 "%s: unable to map Dsi ctrl base\n", __func__); 2014 2015 pm_runtime_enable(&pdev->dev); 2016 2017 msm_host->cfg_hnd = dsi_get_config(msm_host); 2018 if (!msm_host->cfg_hnd) 2019 return dev_err_probe(&pdev->dev, -EINVAL, 2020 "%s: get config failed\n", __func__); 2021 cfg = msm_host->cfg_hnd->cfg; 2022 2023 msm_host->id = dsi_host_get_id(msm_host); 2024 if (msm_host->id < 0) 2025 return dev_err_probe(&pdev->dev, msm_host->id, 2026 "%s: unable to identify DSI host index\n", 2027 __func__); 2028 2029 /* fixup base address by io offset */ 2030 msm_host->ctrl_base += cfg->io_offset; 2031 msm_host->ctrl_size -= cfg->io_offset; 2032 2033 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 2034 cfg->regulator_data, 2035 &msm_host->supplies); 2036 if (ret) 2037 return ret; 2038 2039 ret = dsi_clk_init(msm_host); 2040 if (ret) 2041 return dev_err_probe(&pdev->dev, ret, "%s: unable to initialize dsi clks\n", __func__); 2042 2043 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 2044 if (!msm_host->rx_buf) 2045 return -ENOMEM; 2046 2047 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 2048 if (ret) 2049 return ret; 2050 /* OPP table is optional */ 2051 ret = devm_pm_opp_of_add_table(&pdev->dev); 2052 if (ret && ret != -ENODEV) 2053 return dev_err_probe(&pdev->dev, ret, "invalid OPP table in device tree\n"); 2054 2055 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 2056 if (!msm_host->irq) 2057 return dev_err_probe(&pdev->dev, -EINVAL, "failed to get irq\n"); 2058 2059 /* do not autoenable, will be enabled later */ 2060 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 2061 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 2062 "dsi_isr", msm_host); 2063 if (ret < 0) 2064 return dev_err_probe(&pdev->dev, ret, "failed to request IRQ%u\n", 2065 msm_host->irq); 2066 2067 init_completion(&msm_host->dma_comp); 2068 init_completion(&msm_host->video_comp); 2069 mutex_init(&msm_host->dev_mutex); 2070 mutex_init(&msm_host->cmd_mutex); 2071 spin_lock_init(&msm_host->intr_lock); 2072 2073 /* setup workqueue */ 2074 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 2075 if (!msm_host->workqueue) 2076 return -ENOMEM; 2077 2078 INIT_WORK(&msm_host->err_work, dsi_err_worker); 2079 2080 msm_dsi->id = msm_host->id; 2081 2082 DBG("Dsi Host %d initialized", msm_host->id); 2083 return 0; 2084 } 2085 2086 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 2087 { 2088 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2089 2090 DBG(""); 2091 if (msm_host->workqueue) { 2092 destroy_workqueue(msm_host->workqueue); 2093 msm_host->workqueue = NULL; 2094 } 2095 2096 mutex_destroy(&msm_host->cmd_mutex); 2097 mutex_destroy(&msm_host->dev_mutex); 2098 2099 pm_runtime_disable(&msm_host->pdev->dev); 2100 } 2101 2102 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 2103 struct drm_device *dev) 2104 { 2105 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2106 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2107 int ret; 2108 2109 msm_host->dev = dev; 2110 2111 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2112 if (ret) { 2113 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2114 return ret; 2115 } 2116 2117 return 0; 2118 } 2119 2120 int msm_dsi_host_register(struct mipi_dsi_host *host) 2121 { 2122 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2123 int ret; 2124 2125 /* Register mipi dsi host */ 2126 if (!msm_host->registered) { 2127 host->dev = &msm_host->pdev->dev; 2128 host->ops = &dsi_host_ops; 2129 ret = mipi_dsi_host_register(host); 2130 if (ret) 2131 return ret; 2132 2133 msm_host->registered = true; 2134 } 2135 2136 return 0; 2137 } 2138 2139 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2140 { 2141 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2142 2143 if (msm_host->registered) { 2144 mipi_dsi_host_unregister(host); 2145 host->dev = NULL; 2146 host->ops = NULL; 2147 msm_host->registered = false; 2148 } 2149 } 2150 2151 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2152 const struct mipi_dsi_msg *msg) 2153 { 2154 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2155 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2156 2157 /* TODO: make sure dsi_cmd_mdp is idle. 2158 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2159 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2160 * How to handle the old versions? Wait for mdp cmd done? 2161 */ 2162 2163 /* 2164 * mdss interrupt is generated in mdp core clock domain 2165 * mdp clock need to be enabled to receive dsi interrupt 2166 */ 2167 pm_runtime_get_sync(&msm_host->pdev->dev); 2168 cfg_hnd->ops->link_clk_set_rate(msm_host); 2169 cfg_hnd->ops->link_clk_enable(msm_host); 2170 2171 /* TODO: vote for bus bandwidth */ 2172 2173 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2174 dsi_set_tx_power_mode(0, msm_host); 2175 2176 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2177 dsi_write(msm_host, REG_DSI_CTRL, 2178 msm_host->dma_cmd_ctrl_restore | 2179 DSI_CTRL_CMD_MODE_EN | 2180 DSI_CTRL_ENABLE); 2181 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2182 2183 return 0; 2184 } 2185 2186 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2187 const struct mipi_dsi_msg *msg) 2188 { 2189 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2190 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2191 2192 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2193 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2194 2195 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2196 dsi_set_tx_power_mode(1, msm_host); 2197 2198 /* TODO: unvote for bus bandwidth */ 2199 2200 cfg_hnd->ops->link_clk_disable(msm_host); 2201 pm_runtime_put(&msm_host->pdev->dev); 2202 } 2203 2204 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2205 const struct mipi_dsi_msg *msg) 2206 { 2207 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2208 2209 return dsi_cmds2buf_tx(msm_host, msg); 2210 } 2211 2212 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2213 const struct mipi_dsi_msg *msg) 2214 { 2215 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2216 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2217 int data_byte, rx_byte, dlen, end; 2218 int short_response, diff, pkt_size, ret = 0; 2219 char cmd; 2220 int rlen = msg->rx_len; 2221 u8 *buf; 2222 2223 if (rlen <= 2) { 2224 short_response = 1; 2225 pkt_size = rlen; 2226 rx_byte = 4; 2227 } else { 2228 short_response = 0; 2229 data_byte = 10; /* first read */ 2230 if (rlen < data_byte) 2231 pkt_size = rlen; 2232 else 2233 pkt_size = data_byte; 2234 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2235 } 2236 2237 buf = msm_host->rx_buf; 2238 end = 0; 2239 while (!end) { 2240 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2241 struct mipi_dsi_msg max_pkt_size_msg = { 2242 .channel = msg->channel, 2243 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2244 .tx_len = 2, 2245 .tx_buf = tx, 2246 }; 2247 2248 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2249 rlen, pkt_size, rx_byte); 2250 2251 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2252 if (ret < 2) { 2253 pr_err("%s: Set max pkt size failed, %d\n", 2254 __func__, ret); 2255 return -EINVAL; 2256 } 2257 2258 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2259 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2260 /* Clear the RDBK_DATA registers */ 2261 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2262 DSI_RDBK_DATA_CTRL_CLR); 2263 wmb(); /* make sure the RDBK registers are cleared */ 2264 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2265 wmb(); /* release cleared status before transfer */ 2266 } 2267 2268 ret = dsi_cmds2buf_tx(msm_host, msg); 2269 if (ret < 0) { 2270 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2271 return ret; 2272 } else if (ret < msg->tx_len) { 2273 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2274 return -ECOMM; 2275 } 2276 2277 /* 2278 * once cmd_dma_done interrupt received, 2279 * return data from client is ready and stored 2280 * at RDBK_DATA register already 2281 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2282 * after that dcs header lost during shift into registers 2283 */ 2284 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2285 2286 if (dlen <= 0) 2287 return 0; 2288 2289 if (short_response) 2290 break; 2291 2292 if (rlen <= data_byte) { 2293 diff = data_byte - rlen; 2294 end = 1; 2295 } else { 2296 diff = 0; 2297 rlen -= data_byte; 2298 } 2299 2300 if (!end) { 2301 dlen -= 2; /* 2 crc */ 2302 dlen -= diff; 2303 buf += dlen; /* next start position */ 2304 data_byte = 14; /* NOT first read */ 2305 if (rlen < data_byte) 2306 pkt_size += rlen; 2307 else 2308 pkt_size += data_byte; 2309 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2310 } 2311 } 2312 2313 /* 2314 * For single Long read, if the requested rlen < 10, 2315 * we need to shift the start position of rx 2316 * data buffer to skip the bytes which are not 2317 * updated. 2318 */ 2319 if (pkt_size < 10 && !short_response) 2320 buf = msm_host->rx_buf + (10 - rlen); 2321 else 2322 buf = msm_host->rx_buf; 2323 2324 cmd = buf[0]; 2325 switch (cmd) { 2326 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2327 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2328 ret = 0; 2329 break; 2330 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2331 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2332 ret = dsi_short_read1_resp(buf, msg); 2333 break; 2334 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2335 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2336 ret = dsi_short_read2_resp(buf, msg); 2337 break; 2338 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2339 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2340 ret = dsi_long_read_resp(buf, msg); 2341 break; 2342 default: 2343 pr_warn("%s:Invalid response cmd\n", __func__); 2344 ret = 0; 2345 } 2346 2347 return ret; 2348 } 2349 2350 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2351 u32 len) 2352 { 2353 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2354 2355 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2356 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2357 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2358 2359 /* Make sure trigger happens */ 2360 wmb(); 2361 } 2362 2363 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2364 struct msm_dsi_phy *src_phy) 2365 { 2366 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2367 2368 msm_host->cphy_mode = src_phy->cphy_mode; 2369 } 2370 2371 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2372 { 2373 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2374 2375 DBG(""); 2376 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2377 /* Make sure fully reset */ 2378 wmb(); 2379 udelay(1000); 2380 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2381 udelay(100); 2382 } 2383 2384 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2385 struct msm_dsi_phy_clk_request *clk_req, 2386 bool is_bonded_dsi) 2387 { 2388 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2389 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2390 int ret; 2391 2392 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2393 if (ret) { 2394 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2395 return; 2396 } 2397 2398 /* CPHY transmits 16 bits over 7 clock cycles 2399 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2400 * so multiply by 7 to get the "bitclk rate" 2401 */ 2402 if (msm_host->cphy_mode) 2403 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2404 else 2405 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2406 clk_req->escclk_rate = msm_host->esc_clk_rate; 2407 } 2408 2409 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2410 { 2411 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2412 2413 enable_irq(msm_host->irq); 2414 } 2415 2416 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2417 { 2418 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2419 2420 disable_irq(msm_host->irq); 2421 } 2422 2423 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2424 { 2425 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2426 2427 dsi_op_mode_config(msm_host, 2428 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2429 2430 /* TODO: clock should be turned off for command mode, 2431 * and only turned on before MDP START. 2432 * This part of code should be enabled once mdp driver support it. 2433 */ 2434 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2435 * dsi_link_clk_disable(msm_host); 2436 * pm_runtime_put(&msm_host->pdev->dev); 2437 * } 2438 */ 2439 msm_host->enabled = true; 2440 return 0; 2441 } 2442 2443 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2444 { 2445 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2446 2447 msm_host->enabled = false; 2448 dsi_op_mode_config(msm_host, 2449 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2450 2451 /* Since we have disabled INTF, the video engine won't stop so that 2452 * the cmd engine will be blocked. 2453 * Reset to disable video engine so that we can send off cmd. 2454 */ 2455 dsi_sw_reset(msm_host); 2456 2457 return 0; 2458 } 2459 2460 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2461 { 2462 enum sfpb_ahb_arb_master_port_en en; 2463 2464 if (!msm_host->sfpb) 2465 return; 2466 2467 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2468 2469 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2470 SFPB_GPREG_MASTER_PORT_EN__MASK, 2471 SFPB_GPREG_MASTER_PORT_EN(en)); 2472 } 2473 2474 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2475 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2476 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2477 { 2478 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2479 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2480 int ret = 0; 2481 2482 mutex_lock(&msm_host->dev_mutex); 2483 if (msm_host->power_on) { 2484 DBG("dsi host already on"); 2485 goto unlock_ret; 2486 } 2487 2488 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; 2489 if (phy_shared_timings->byte_intf_clk_div_2) 2490 msm_host->byte_intf_clk_rate /= 2; 2491 2492 msm_dsi_sfpb_config(msm_host, true); 2493 2494 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2495 msm_host->supplies); 2496 if (ret) { 2497 pr_err("%s:Failed to enable vregs.ret=%d\n", 2498 __func__, ret); 2499 goto unlock_ret; 2500 } 2501 2502 pm_runtime_get_sync(&msm_host->pdev->dev); 2503 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2504 if (!ret) 2505 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2506 if (ret) { 2507 pr_err("%s: failed to enable link clocks. ret=%d\n", 2508 __func__, ret); 2509 goto fail_disable_reg; 2510 } 2511 2512 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2513 if (ret) { 2514 pr_err("%s: failed to set pinctrl default state, %d\n", 2515 __func__, ret); 2516 goto fail_disable_clk; 2517 } 2518 2519 dsi_timing_setup(msm_host, is_bonded_dsi); 2520 dsi_sw_reset(msm_host); 2521 dsi_ctrl_enable(msm_host, phy_shared_timings, phy); 2522 2523 msm_host->power_on = true; 2524 mutex_unlock(&msm_host->dev_mutex); 2525 2526 return 0; 2527 2528 fail_disable_clk: 2529 cfg_hnd->ops->link_clk_disable(msm_host); 2530 pm_runtime_put(&msm_host->pdev->dev); 2531 fail_disable_reg: 2532 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2533 msm_host->supplies); 2534 unlock_ret: 2535 mutex_unlock(&msm_host->dev_mutex); 2536 return ret; 2537 } 2538 2539 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2540 { 2541 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2542 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2543 2544 mutex_lock(&msm_host->dev_mutex); 2545 if (!msm_host->power_on) { 2546 DBG("dsi host already off"); 2547 goto unlock_ret; 2548 } 2549 2550 dsi_ctrl_disable(msm_host); 2551 2552 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2553 2554 cfg_hnd->ops->link_clk_disable(msm_host); 2555 pm_runtime_put(&msm_host->pdev->dev); 2556 2557 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2558 msm_host->supplies); 2559 2560 msm_dsi_sfpb_config(msm_host, false); 2561 2562 DBG("-"); 2563 2564 msm_host->power_on = false; 2565 2566 unlock_ret: 2567 mutex_unlock(&msm_host->dev_mutex); 2568 return 0; 2569 } 2570 2571 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2572 const struct drm_display_mode *mode) 2573 { 2574 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2575 2576 if (msm_host->mode) { 2577 drm_mode_destroy(msm_host->dev, msm_host->mode); 2578 msm_host->mode = NULL; 2579 } 2580 2581 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2582 if (!msm_host->mode) { 2583 pr_err("%s: cannot duplicate mode\n", __func__); 2584 return -ENOMEM; 2585 } 2586 2587 return 0; 2588 } 2589 2590 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2591 const struct drm_display_mode *mode) 2592 { 2593 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2594 struct drm_dsc_config *dsc = msm_host->dsc; 2595 int pic_width = mode->hdisplay; 2596 int pic_height = mode->vdisplay; 2597 2598 if (!msm_host->dsc) 2599 return MODE_OK; 2600 2601 if (pic_width % dsc->slice_width) { 2602 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2603 pic_width, dsc->slice_width); 2604 return MODE_H_ILLEGAL; 2605 } 2606 2607 if (pic_height % dsc->slice_height) { 2608 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2609 pic_height, dsc->slice_height); 2610 return MODE_V_ILLEGAL; 2611 } 2612 2613 return MODE_OK; 2614 } 2615 2616 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2617 { 2618 return to_msm_dsi_host(host)->mode_flags; 2619 } 2620 2621 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2622 { 2623 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2624 2625 pm_runtime_get_sync(&msm_host->pdev->dev); 2626 2627 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2628 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2629 2630 pm_runtime_put_sync(&msm_host->pdev->dev); 2631 } 2632 2633 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2634 { 2635 u32 reg; 2636 2637 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2638 2639 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2640 /* draw checkered rectangle pattern */ 2641 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2642 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2643 /* use 24-bit RGB test pttern */ 2644 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2645 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2646 DSI_TPG_VIDEO_CONFIG_RGB); 2647 2648 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2649 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2650 2651 DBG("Video test pattern setup done\n"); 2652 } 2653 2654 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2655 { 2656 u32 reg; 2657 2658 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2659 2660 /* initial value for test pattern */ 2661 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2662 2663 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2664 2665 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2666 /* draw checkered rectangle pattern */ 2667 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2668 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2669 2670 DBG("Cmd test pattern setup done\n"); 2671 } 2672 2673 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2674 { 2675 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2676 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2677 u32 reg; 2678 2679 if (is_video_mode) 2680 msm_dsi_host_video_test_pattern_setup(msm_host); 2681 else 2682 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2683 2684 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2685 /* enable the test pattern generator */ 2686 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2687 2688 /* for command mode need to trigger one frame from tpg */ 2689 if (!is_video_mode) 2690 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2691 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2692 } 2693 2694 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2695 { 2696 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2697 2698 return msm_host->dsc; 2699 } 2700