1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/interrupt.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/of_irq.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_opp.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spinlock.h> 21 22 #include <video/mipi_display.h> 23 24 #include "dsi.h" 25 #include "dsi.xml.h" 26 #include "sfpb.xml.h" 27 #include "dsi_cfg.h" 28 #include "msm_kms.h" 29 #include "msm_gem.h" 30 31 #define DSI_RESET_TOGGLE_DELAY_MS 20 32 33 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 34 { 35 u32 ver; 36 37 if (!major || !minor) 38 return -EINVAL; 39 40 /* 41 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 42 * makes all other registers 4-byte shifted down. 43 * 44 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 45 * older, we read the DSI_VERSION register without any shift(offset 46 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 47 * the case of DSI6G, this has to be zero (the offset points to a 48 * scratch register which we never touch) 49 */ 50 51 ver = msm_readl(base + REG_DSI_VERSION); 52 if (ver) { 53 /* older dsi host, there is no register shift */ 54 ver = FIELD(ver, DSI_VERSION_MAJOR); 55 if (ver <= MSM_DSI_VER_MAJOR_V2) { 56 /* old versions */ 57 *major = ver; 58 *minor = 0; 59 return 0; 60 } else { 61 return -EINVAL; 62 } 63 } else { 64 /* 65 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 66 * registers are shifted down, read DSI_VERSION again with 67 * the shifted offset 68 */ 69 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 70 ver = FIELD(ver, DSI_VERSION_MAJOR); 71 if (ver == MSM_DSI_VER_MAJOR_6G) { 72 /* 6G version */ 73 *major = ver; 74 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 75 return 0; 76 } else { 77 return -EINVAL; 78 } 79 } 80 } 81 82 #define DSI_ERR_STATE_ACK 0x0000 83 #define DSI_ERR_STATE_TIMEOUT 0x0001 84 #define DSI_ERR_STATE_DLN0_PHY 0x0002 85 #define DSI_ERR_STATE_FIFO 0x0004 86 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 87 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 88 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 89 90 #define DSI_CLK_CTRL_ENABLE_CLKS \ 91 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 92 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 93 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 94 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 95 96 struct msm_dsi_host { 97 struct mipi_dsi_host base; 98 99 struct platform_device *pdev; 100 struct drm_device *dev; 101 102 int id; 103 104 void __iomem *ctrl_base; 105 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 106 107 struct clk *bus_clks[DSI_BUS_CLK_MAX]; 108 109 struct clk *byte_clk; 110 struct clk *esc_clk; 111 struct clk *pixel_clk; 112 struct clk *byte_clk_src; 113 struct clk *pixel_clk_src; 114 struct clk *byte_intf_clk; 115 116 struct opp_table *opp_table; 117 118 u32 byte_clk_rate; 119 u32 pixel_clk_rate; 120 u32 esc_clk_rate; 121 122 /* DSI v2 specific clocks */ 123 struct clk *src_clk; 124 struct clk *esc_clk_src; 125 struct clk *dsi_clk_src; 126 127 u32 src_clk_rate; 128 129 struct gpio_desc *disp_en_gpio; 130 struct gpio_desc *te_gpio; 131 132 const struct msm_dsi_cfg_handler *cfg_hnd; 133 134 struct completion dma_comp; 135 struct completion video_comp; 136 struct mutex dev_mutex; 137 struct mutex cmd_mutex; 138 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 139 140 u32 err_work_state; 141 struct work_struct err_work; 142 struct work_struct hpd_work; 143 struct workqueue_struct *workqueue; 144 145 /* DSI 6G TX buffer*/ 146 struct drm_gem_object *tx_gem_obj; 147 148 /* DSI v2 TX buffer */ 149 void *tx_buf; 150 dma_addr_t tx_buf_paddr; 151 152 int tx_size; 153 154 u8 *rx_buf; 155 156 struct regmap *sfpb; 157 158 struct drm_display_mode *mode; 159 160 /* connected device info */ 161 struct device_node *device_node; 162 unsigned int channel; 163 unsigned int lanes; 164 enum mipi_dsi_pixel_format format; 165 unsigned long mode_flags; 166 167 /* lane data parsed via DT */ 168 int dlane_swap; 169 int num_data_lanes; 170 171 u32 dma_cmd_ctrl_restore; 172 173 bool registered; 174 bool power_on; 175 bool enabled; 176 int irq; 177 }; 178 179 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 180 { 181 switch (fmt) { 182 case MIPI_DSI_FMT_RGB565: return 16; 183 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 184 case MIPI_DSI_FMT_RGB666: 185 case MIPI_DSI_FMT_RGB888: 186 default: return 24; 187 } 188 } 189 190 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 191 { 192 return msm_readl(msm_host->ctrl_base + reg); 193 } 194 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 195 { 196 msm_writel(data, msm_host->ctrl_base + reg); 197 } 198 199 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 200 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 201 202 static const struct msm_dsi_cfg_handler *dsi_get_config( 203 struct msm_dsi_host *msm_host) 204 { 205 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 206 struct device *dev = &msm_host->pdev->dev; 207 struct regulator *gdsc_reg; 208 struct clk *ahb_clk; 209 int ret; 210 u32 major = 0, minor = 0; 211 212 gdsc_reg = regulator_get(dev, "gdsc"); 213 if (IS_ERR(gdsc_reg)) { 214 pr_err("%s: cannot get gdsc\n", __func__); 215 goto exit; 216 } 217 218 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 219 if (IS_ERR(ahb_clk)) { 220 pr_err("%s: cannot get interface clock\n", __func__); 221 goto put_gdsc; 222 } 223 224 pm_runtime_get_sync(dev); 225 226 ret = regulator_enable(gdsc_reg); 227 if (ret) { 228 pr_err("%s: unable to enable gdsc\n", __func__); 229 goto put_gdsc; 230 } 231 232 ret = clk_prepare_enable(ahb_clk); 233 if (ret) { 234 pr_err("%s: unable to enable ahb_clk\n", __func__); 235 goto disable_gdsc; 236 } 237 238 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 239 if (ret) { 240 pr_err("%s: Invalid version\n", __func__); 241 goto disable_clks; 242 } 243 244 cfg_hnd = msm_dsi_cfg_get(major, minor); 245 246 DBG("%s: Version %x:%x\n", __func__, major, minor); 247 248 disable_clks: 249 clk_disable_unprepare(ahb_clk); 250 disable_gdsc: 251 regulator_disable(gdsc_reg); 252 pm_runtime_put_sync(dev); 253 put_gdsc: 254 regulator_put(gdsc_reg); 255 exit: 256 return cfg_hnd; 257 } 258 259 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 260 { 261 return container_of(host, struct msm_dsi_host, base); 262 } 263 264 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 265 { 266 struct regulator_bulk_data *s = msm_host->supplies; 267 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 268 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 269 int i; 270 271 DBG(""); 272 for (i = num - 1; i >= 0; i--) 273 if (regs[i].disable_load >= 0) 274 regulator_set_load(s[i].consumer, 275 regs[i].disable_load); 276 277 regulator_bulk_disable(num, s); 278 } 279 280 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 281 { 282 struct regulator_bulk_data *s = msm_host->supplies; 283 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 284 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 285 int ret, i; 286 287 DBG(""); 288 for (i = 0; i < num; i++) { 289 if (regs[i].enable_load >= 0) { 290 ret = regulator_set_load(s[i].consumer, 291 regs[i].enable_load); 292 if (ret < 0) { 293 pr_err("regulator %d set op mode failed, %d\n", 294 i, ret); 295 goto fail; 296 } 297 } 298 } 299 300 ret = regulator_bulk_enable(num, s); 301 if (ret < 0) { 302 pr_err("regulator enable failed, %d\n", ret); 303 goto fail; 304 } 305 306 return 0; 307 308 fail: 309 for (i--; i >= 0; i--) 310 regulator_set_load(s[i].consumer, regs[i].disable_load); 311 return ret; 312 } 313 314 static int dsi_regulator_init(struct msm_dsi_host *msm_host) 315 { 316 struct regulator_bulk_data *s = msm_host->supplies; 317 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 318 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 319 int i, ret; 320 321 for (i = 0; i < num; i++) 322 s[i].supply = regs[i].name; 323 324 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 325 if (ret < 0) { 326 pr_err("%s: failed to init regulator, ret=%d\n", 327 __func__, ret); 328 return ret; 329 } 330 331 return 0; 332 } 333 334 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 335 { 336 struct platform_device *pdev = msm_host->pdev; 337 int ret = 0; 338 339 msm_host->src_clk = msm_clk_get(pdev, "src"); 340 341 if (IS_ERR(msm_host->src_clk)) { 342 ret = PTR_ERR(msm_host->src_clk); 343 pr_err("%s: can't find src clock. ret=%d\n", 344 __func__, ret); 345 msm_host->src_clk = NULL; 346 return ret; 347 } 348 349 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 350 if (!msm_host->esc_clk_src) { 351 ret = -ENODEV; 352 pr_err("%s: can't get esc clock parent. ret=%d\n", 353 __func__, ret); 354 return ret; 355 } 356 357 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 358 if (!msm_host->dsi_clk_src) { 359 ret = -ENODEV; 360 pr_err("%s: can't get src clock parent. ret=%d\n", 361 __func__, ret); 362 } 363 364 return ret; 365 } 366 367 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 368 { 369 struct platform_device *pdev = msm_host->pdev; 370 int ret = 0; 371 372 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 373 if (IS_ERR(msm_host->byte_intf_clk)) { 374 ret = PTR_ERR(msm_host->byte_intf_clk); 375 pr_err("%s: can't find byte_intf clock. ret=%d\n", 376 __func__, ret); 377 } 378 379 return ret; 380 } 381 382 static int dsi_clk_init(struct msm_dsi_host *msm_host) 383 { 384 struct platform_device *pdev = msm_host->pdev; 385 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 386 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 387 int i, ret = 0; 388 389 /* get bus clocks */ 390 for (i = 0; i < cfg->num_bus_clks; i++) { 391 msm_host->bus_clks[i] = msm_clk_get(pdev, 392 cfg->bus_clk_names[i]); 393 if (IS_ERR(msm_host->bus_clks[i])) { 394 ret = PTR_ERR(msm_host->bus_clks[i]); 395 pr_err("%s: Unable to get %s clock, ret = %d\n", 396 __func__, cfg->bus_clk_names[i], ret); 397 goto exit; 398 } 399 } 400 401 /* get link and source clocks */ 402 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 403 if (IS_ERR(msm_host->byte_clk)) { 404 ret = PTR_ERR(msm_host->byte_clk); 405 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 406 __func__, ret); 407 msm_host->byte_clk = NULL; 408 goto exit; 409 } 410 411 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 412 if (IS_ERR(msm_host->pixel_clk)) { 413 ret = PTR_ERR(msm_host->pixel_clk); 414 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 415 __func__, ret); 416 msm_host->pixel_clk = NULL; 417 goto exit; 418 } 419 420 msm_host->esc_clk = msm_clk_get(pdev, "core"); 421 if (IS_ERR(msm_host->esc_clk)) { 422 ret = PTR_ERR(msm_host->esc_clk); 423 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 424 __func__, ret); 425 msm_host->esc_clk = NULL; 426 goto exit; 427 } 428 429 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 430 if (IS_ERR(msm_host->byte_clk_src)) { 431 ret = PTR_ERR(msm_host->byte_clk_src); 432 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); 433 goto exit; 434 } 435 436 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 437 if (IS_ERR(msm_host->pixel_clk_src)) { 438 ret = PTR_ERR(msm_host->pixel_clk_src); 439 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); 440 goto exit; 441 } 442 443 if (cfg_hnd->ops->clk_init_ver) 444 ret = cfg_hnd->ops->clk_init_ver(msm_host); 445 exit: 446 return ret; 447 } 448 449 static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) 450 { 451 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 452 int i, ret; 453 454 DBG("id=%d", msm_host->id); 455 456 for (i = 0; i < cfg->num_bus_clks; i++) { 457 ret = clk_prepare_enable(msm_host->bus_clks[i]); 458 if (ret) { 459 pr_err("%s: failed to enable bus clock %d ret %d\n", 460 __func__, i, ret); 461 goto err; 462 } 463 } 464 465 return 0; 466 err: 467 for (; i > 0; i--) 468 clk_disable_unprepare(msm_host->bus_clks[i]); 469 470 return ret; 471 } 472 473 static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) 474 { 475 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 476 int i; 477 478 DBG(""); 479 480 for (i = cfg->num_bus_clks - 1; i >= 0; i--) 481 clk_disable_unprepare(msm_host->bus_clks[i]); 482 } 483 484 int msm_dsi_runtime_suspend(struct device *dev) 485 { 486 struct platform_device *pdev = to_platform_device(dev); 487 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 488 struct mipi_dsi_host *host = msm_dsi->host; 489 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 490 491 if (!msm_host->cfg_hnd) 492 return 0; 493 494 dsi_bus_clk_disable(msm_host); 495 496 return 0; 497 } 498 499 int msm_dsi_runtime_resume(struct device *dev) 500 { 501 struct platform_device *pdev = to_platform_device(dev); 502 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 503 struct mipi_dsi_host *host = msm_dsi->host; 504 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 505 506 if (!msm_host->cfg_hnd) 507 return 0; 508 509 return dsi_bus_clk_enable(msm_host); 510 } 511 512 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 513 { 514 int ret; 515 516 DBG("Set clk rates: pclk=%d, byteclk=%d", 517 msm_host->mode->clock, msm_host->byte_clk_rate); 518 519 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 520 msm_host->byte_clk_rate); 521 if (ret) { 522 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 523 return ret; 524 } 525 526 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 527 if (ret) { 528 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 529 return ret; 530 } 531 532 if (msm_host->byte_intf_clk) { 533 ret = clk_set_rate(msm_host->byte_intf_clk, 534 msm_host->byte_clk_rate / 2); 535 if (ret) { 536 pr_err("%s: Failed to set rate byte intf clk, %d\n", 537 __func__, ret); 538 return ret; 539 } 540 } 541 542 return 0; 543 } 544 545 546 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 547 { 548 int ret; 549 550 ret = clk_prepare_enable(msm_host->esc_clk); 551 if (ret) { 552 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 553 goto error; 554 } 555 556 ret = clk_prepare_enable(msm_host->byte_clk); 557 if (ret) { 558 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 559 goto byte_clk_err; 560 } 561 562 ret = clk_prepare_enable(msm_host->pixel_clk); 563 if (ret) { 564 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 565 goto pixel_clk_err; 566 } 567 568 if (msm_host->byte_intf_clk) { 569 ret = clk_prepare_enable(msm_host->byte_intf_clk); 570 if (ret) { 571 pr_err("%s: Failed to enable byte intf clk\n", 572 __func__); 573 goto byte_intf_clk_err; 574 } 575 } 576 577 return 0; 578 579 byte_intf_clk_err: 580 clk_disable_unprepare(msm_host->pixel_clk); 581 pixel_clk_err: 582 clk_disable_unprepare(msm_host->byte_clk); 583 byte_clk_err: 584 clk_disable_unprepare(msm_host->esc_clk); 585 error: 586 return ret; 587 } 588 589 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 590 { 591 int ret; 592 593 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d", 594 msm_host->mode->clock, msm_host->byte_clk_rate, 595 msm_host->esc_clk_rate, msm_host->src_clk_rate); 596 597 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 598 if (ret) { 599 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 600 return ret; 601 } 602 603 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 604 if (ret) { 605 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 606 return ret; 607 } 608 609 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 610 if (ret) { 611 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 612 return ret; 613 } 614 615 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 616 if (ret) { 617 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 618 return ret; 619 } 620 621 return 0; 622 } 623 624 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 625 { 626 int ret; 627 628 ret = clk_prepare_enable(msm_host->byte_clk); 629 if (ret) { 630 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 631 goto error; 632 } 633 634 ret = clk_prepare_enable(msm_host->esc_clk); 635 if (ret) { 636 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 637 goto esc_clk_err; 638 } 639 640 ret = clk_prepare_enable(msm_host->src_clk); 641 if (ret) { 642 pr_err("%s: Failed to enable dsi src clk\n", __func__); 643 goto src_clk_err; 644 } 645 646 ret = clk_prepare_enable(msm_host->pixel_clk); 647 if (ret) { 648 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 649 goto pixel_clk_err; 650 } 651 652 return 0; 653 654 pixel_clk_err: 655 clk_disable_unprepare(msm_host->src_clk); 656 src_clk_err: 657 clk_disable_unprepare(msm_host->esc_clk); 658 esc_clk_err: 659 clk_disable_unprepare(msm_host->byte_clk); 660 error: 661 return ret; 662 } 663 664 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 665 { 666 /* Drop the performance state vote */ 667 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 668 clk_disable_unprepare(msm_host->esc_clk); 669 clk_disable_unprepare(msm_host->pixel_clk); 670 if (msm_host->byte_intf_clk) 671 clk_disable_unprepare(msm_host->byte_intf_clk); 672 clk_disable_unprepare(msm_host->byte_clk); 673 } 674 675 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 676 { 677 clk_disable_unprepare(msm_host->pixel_clk); 678 clk_disable_unprepare(msm_host->src_clk); 679 clk_disable_unprepare(msm_host->esc_clk); 680 clk_disable_unprepare(msm_host->byte_clk); 681 } 682 683 static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) 684 { 685 struct drm_display_mode *mode = msm_host->mode; 686 u32 pclk_rate; 687 688 pclk_rate = mode->clock * 1000; 689 690 /* 691 * For dual DSI mode, the current DRM mode has the complete width of the 692 * panel. Since, the complete panel is driven by two DSI controllers, 693 * the clock rates have to be split between the two dsi controllers. 694 * Adjust the byte and pixel clock rates for each dsi host accordingly. 695 */ 696 if (is_dual_dsi) 697 pclk_rate /= 2; 698 699 return pclk_rate; 700 } 701 702 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi) 703 { 704 u8 lanes = msm_host->lanes; 705 u32 bpp = dsi_get_bpp(msm_host->format); 706 u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi); 707 u64 pclk_bpp = (u64)pclk_rate * bpp; 708 709 if (lanes == 0) { 710 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 711 lanes = 1; 712 } 713 714 do_div(pclk_bpp, (8 * lanes)); 715 716 msm_host->pixel_clk_rate = pclk_rate; 717 msm_host->byte_clk_rate = pclk_bpp; 718 719 DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, 720 msm_host->byte_clk_rate); 721 722 } 723 724 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) 725 { 726 if (!msm_host->mode) { 727 pr_err("%s: mode not set\n", __func__); 728 return -EINVAL; 729 } 730 731 dsi_calc_pclk(msm_host, is_dual_dsi); 732 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 733 return 0; 734 } 735 736 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) 737 { 738 u32 bpp = dsi_get_bpp(msm_host->format); 739 u64 pclk_bpp; 740 unsigned int esc_mhz, esc_div; 741 unsigned long byte_mhz; 742 743 dsi_calc_pclk(msm_host, is_dual_dsi); 744 745 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp; 746 do_div(pclk_bpp, 8); 747 msm_host->src_clk_rate = pclk_bpp; 748 749 /* 750 * esc clock is byte clock followed by a 4 bit divider, 751 * we need to find an escape clock frequency within the 752 * mipi DSI spec range within the maximum divider limit 753 * We iterate here between an escape clock frequencey 754 * between 20 Mhz to 5 Mhz and pick up the first one 755 * that can be supported by our divider 756 */ 757 758 byte_mhz = msm_host->byte_clk_rate / 1000000; 759 760 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 761 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 762 763 /* 764 * TODO: Ideally, we shouldn't know what sort of divider 765 * is available in mmss_cc, we're just assuming that 766 * it'll always be a 4 bit divider. Need to come up with 767 * a better way here. 768 */ 769 if (esc_div >= 1 && esc_div <= 16) 770 break; 771 } 772 773 if (esc_mhz < 5) 774 return -EINVAL; 775 776 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 777 778 DBG("esc=%d, src=%d", msm_host->esc_clk_rate, 779 msm_host->src_clk_rate); 780 781 return 0; 782 } 783 784 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 785 { 786 u32 intr; 787 unsigned long flags; 788 789 spin_lock_irqsave(&msm_host->intr_lock, flags); 790 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 791 792 if (enable) 793 intr |= mask; 794 else 795 intr &= ~mask; 796 797 DBG("intr=%x enable=%d", intr, enable); 798 799 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 800 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 801 } 802 803 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 804 { 805 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 806 return BURST_MODE; 807 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 808 return NON_BURST_SYNCH_PULSE; 809 810 return NON_BURST_SYNCH_EVENT; 811 } 812 813 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 814 const enum mipi_dsi_pixel_format mipi_fmt) 815 { 816 switch (mipi_fmt) { 817 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 818 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 819 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 820 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 821 default: return VID_DST_FORMAT_RGB888; 822 } 823 } 824 825 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 826 const enum mipi_dsi_pixel_format mipi_fmt) 827 { 828 switch (mipi_fmt) { 829 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 830 case MIPI_DSI_FMT_RGB666_PACKED: 831 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 832 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 833 default: return CMD_DST_FORMAT_RGB888; 834 } 835 } 836 837 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 838 struct msm_dsi_phy_shared_timings *phy_shared_timings) 839 { 840 u32 flags = msm_host->mode_flags; 841 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 842 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 843 u32 data = 0, lane_ctrl = 0; 844 845 if (!enable) { 846 dsi_write(msm_host, REG_DSI_CTRL, 0); 847 return; 848 } 849 850 if (flags & MIPI_DSI_MODE_VIDEO) { 851 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 852 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 853 if (flags & MIPI_DSI_MODE_VIDEO_HFP) 854 data |= DSI_VID_CFG0_HFP_POWER_STOP; 855 if (flags & MIPI_DSI_MODE_VIDEO_HBP) 856 data |= DSI_VID_CFG0_HBP_POWER_STOP; 857 if (flags & MIPI_DSI_MODE_VIDEO_HSA) 858 data |= DSI_VID_CFG0_HSA_POWER_STOP; 859 /* Always set low power stop mode for BLLP 860 * to let command engine send packets 861 */ 862 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 863 DSI_VID_CFG0_BLLP_POWER_STOP; 864 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 865 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 866 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 867 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 868 869 /* Do not swap RGB colors */ 870 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 871 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 872 } else { 873 /* Do not swap RGB colors */ 874 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 875 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 876 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 877 878 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 879 DSI_CMD_CFG1_WR_MEM_CONTINUE( 880 MIPI_DCS_WRITE_MEMORY_CONTINUE); 881 /* Always insert DCS command */ 882 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 883 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 884 } 885 886 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 887 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 888 DSI_CMD_DMA_CTRL_LOW_POWER); 889 890 data = 0; 891 /* Always assume dedicated TE pin */ 892 data |= DSI_TRIG_CTRL_TE; 893 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 894 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 895 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 896 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 897 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 898 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 899 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 900 901 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 902 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 903 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 904 905 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 906 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 907 phy_shared_timings->clk_pre_inc_by_2) 908 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 909 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 910 911 data = 0; 912 if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) 913 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 914 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 915 916 /* allow only ack-err-status to generate interrupt */ 917 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 918 919 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 920 921 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 922 923 data = DSI_CTRL_CLK_EN; 924 925 DBG("lane number=%d", msm_host->lanes); 926 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 927 928 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 929 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 930 931 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 932 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 933 dsi_write(msm_host, REG_DSI_LANE_CTRL, 934 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 935 } 936 937 data |= DSI_CTRL_ENABLE; 938 939 dsi_write(msm_host, REG_DSI_CTRL, data); 940 } 941 942 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) 943 { 944 struct drm_display_mode *mode = msm_host->mode; 945 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 946 u32 h_total = mode->htotal; 947 u32 v_total = mode->vtotal; 948 u32 hs_end = mode->hsync_end - mode->hsync_start; 949 u32 vs_end = mode->vsync_end - mode->vsync_start; 950 u32 ha_start = h_total - mode->hsync_start; 951 u32 ha_end = ha_start + mode->hdisplay; 952 u32 va_start = v_total - mode->vsync_start; 953 u32 va_end = va_start + mode->vdisplay; 954 u32 hdisplay = mode->hdisplay; 955 u32 wc; 956 957 DBG(""); 958 959 /* 960 * For dual DSI mode, the current DRM mode has 961 * the complete width of the panel. Since, the complete 962 * panel is driven by two DSI controllers, the horizontal 963 * timings have to be split between the two dsi controllers. 964 * Adjust the DSI host timing values accordingly. 965 */ 966 if (is_dual_dsi) { 967 h_total /= 2; 968 hs_end /= 2; 969 ha_start /= 2; 970 ha_end /= 2; 971 hdisplay /= 2; 972 } 973 974 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 975 dsi_write(msm_host, REG_DSI_ACTIVE_H, 976 DSI_ACTIVE_H_START(ha_start) | 977 DSI_ACTIVE_H_END(ha_end)); 978 dsi_write(msm_host, REG_DSI_ACTIVE_V, 979 DSI_ACTIVE_V_START(va_start) | 980 DSI_ACTIVE_V_END(va_end)); 981 dsi_write(msm_host, REG_DSI_TOTAL, 982 DSI_TOTAL_H_TOTAL(h_total - 1) | 983 DSI_TOTAL_V_TOTAL(v_total - 1)); 984 985 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 986 DSI_ACTIVE_HSYNC_START(hs_start) | 987 DSI_ACTIVE_HSYNC_END(hs_end)); 988 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 989 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 990 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 991 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 992 } else { /* command mode */ 993 /* image data and 1 byte write_memory_start cmd */ 994 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 995 996 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 997 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 998 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 999 msm_host->channel) | 1000 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1001 MIPI_DSI_DCS_LONG_WRITE)); 1002 1003 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1004 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1005 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1006 } 1007 } 1008 1009 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1010 { 1011 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1012 wmb(); /* clocks need to be enabled before reset */ 1013 1014 dsi_write(msm_host, REG_DSI_RESET, 1); 1015 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1016 dsi_write(msm_host, REG_DSI_RESET, 0); 1017 } 1018 1019 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1020 bool video_mode, bool enable) 1021 { 1022 u32 dsi_ctrl; 1023 1024 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1025 1026 if (!enable) { 1027 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1028 DSI_CTRL_CMD_MODE_EN); 1029 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1030 DSI_IRQ_MASK_VIDEO_DONE, 0); 1031 } else { 1032 if (video_mode) { 1033 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1034 } else { /* command mode */ 1035 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1036 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1037 } 1038 dsi_ctrl |= DSI_CTRL_ENABLE; 1039 } 1040 1041 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1042 } 1043 1044 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1045 { 1046 u32 data; 1047 1048 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1049 1050 if (mode == 0) 1051 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1052 else 1053 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1054 1055 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1056 } 1057 1058 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1059 { 1060 u32 ret = 0; 1061 struct device *dev = &msm_host->pdev->dev; 1062 1063 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1064 1065 reinit_completion(&msm_host->video_comp); 1066 1067 ret = wait_for_completion_timeout(&msm_host->video_comp, 1068 msecs_to_jiffies(70)); 1069 1070 if (ret == 0) 1071 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1072 1073 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1074 } 1075 1076 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1077 { 1078 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1079 return; 1080 1081 if (msm_host->power_on && msm_host->enabled) { 1082 dsi_wait4video_done(msm_host); 1083 /* delay 4 ms to skip BLLP */ 1084 usleep_range(2000, 4000); 1085 } 1086 } 1087 1088 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1089 { 1090 struct drm_device *dev = msm_host->dev; 1091 struct msm_drm_private *priv = dev->dev_private; 1092 uint64_t iova; 1093 u8 *data; 1094 1095 data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED, 1096 priv->kms->aspace, 1097 &msm_host->tx_gem_obj, &iova); 1098 1099 if (IS_ERR(data)) { 1100 msm_host->tx_gem_obj = NULL; 1101 return PTR_ERR(data); 1102 } 1103 1104 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1105 1106 msm_host->tx_size = msm_host->tx_gem_obj->size; 1107 1108 return 0; 1109 } 1110 1111 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1112 { 1113 struct drm_device *dev = msm_host->dev; 1114 1115 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1116 &msm_host->tx_buf_paddr, GFP_KERNEL); 1117 if (!msm_host->tx_buf) 1118 return -ENOMEM; 1119 1120 msm_host->tx_size = size; 1121 1122 return 0; 1123 } 1124 1125 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1126 { 1127 struct drm_device *dev = msm_host->dev; 1128 struct msm_drm_private *priv; 1129 1130 /* 1131 * This is possible if we're tearing down before we've had a chance to 1132 * fully initialize. A very real possibility if our probe is deferred, 1133 * in which case we'll hit msm_dsi_host_destroy() without having run 1134 * through the dsi_tx_buf_alloc(). 1135 */ 1136 if (!dev) 1137 return; 1138 1139 priv = dev->dev_private; 1140 if (msm_host->tx_gem_obj) { 1141 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); 1142 drm_gem_object_put(msm_host->tx_gem_obj); 1143 msm_host->tx_gem_obj = NULL; 1144 } 1145 1146 if (msm_host->tx_buf) 1147 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1148 msm_host->tx_buf_paddr); 1149 } 1150 1151 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1152 { 1153 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1154 } 1155 1156 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1157 { 1158 return msm_host->tx_buf; 1159 } 1160 1161 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1162 { 1163 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1164 } 1165 1166 /* 1167 * prepare cmd buffer to be txed 1168 */ 1169 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1170 const struct mipi_dsi_msg *msg) 1171 { 1172 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1173 struct mipi_dsi_packet packet; 1174 int len; 1175 int ret; 1176 u8 *data; 1177 1178 ret = mipi_dsi_create_packet(&packet, msg); 1179 if (ret) { 1180 pr_err("%s: create packet failed, %d\n", __func__, ret); 1181 return ret; 1182 } 1183 len = (packet.size + 3) & (~0x3); 1184 1185 if (len > msm_host->tx_size) { 1186 pr_err("%s: packet size is too big\n", __func__); 1187 return -EINVAL; 1188 } 1189 1190 data = cfg_hnd->ops->tx_buf_get(msm_host); 1191 if (IS_ERR(data)) { 1192 ret = PTR_ERR(data); 1193 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1194 return ret; 1195 } 1196 1197 /* MSM specific command format in memory */ 1198 data[0] = packet.header[1]; 1199 data[1] = packet.header[2]; 1200 data[2] = packet.header[0]; 1201 data[3] = BIT(7); /* Last packet */ 1202 if (mipi_dsi_packet_format_is_long(msg->type)) 1203 data[3] |= BIT(6); 1204 if (msg->rx_buf && msg->rx_len) 1205 data[3] |= BIT(5); 1206 1207 /* Long packet */ 1208 if (packet.payload && packet.payload_length) 1209 memcpy(data + 4, packet.payload, packet.payload_length); 1210 1211 /* Append 0xff to the end */ 1212 if (packet.size < len) 1213 memset(data + packet.size, 0xff, len - packet.size); 1214 1215 if (cfg_hnd->ops->tx_buf_put) 1216 cfg_hnd->ops->tx_buf_put(msm_host); 1217 1218 return len; 1219 } 1220 1221 /* 1222 * dsi_short_read1_resp: 1 parameter 1223 */ 1224 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1225 { 1226 u8 *data = msg->rx_buf; 1227 if (data && (msg->rx_len >= 1)) { 1228 *data = buf[1]; /* strip out dcs type */ 1229 return 1; 1230 } else { 1231 pr_err("%s: read data does not match with rx_buf len %zu\n", 1232 __func__, msg->rx_len); 1233 return -EINVAL; 1234 } 1235 } 1236 1237 /* 1238 * dsi_short_read2_resp: 2 parameter 1239 */ 1240 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1241 { 1242 u8 *data = msg->rx_buf; 1243 if (data && (msg->rx_len >= 2)) { 1244 data[0] = buf[1]; /* strip out dcs type */ 1245 data[1] = buf[2]; 1246 return 2; 1247 } else { 1248 pr_err("%s: read data does not match with rx_buf len %zu\n", 1249 __func__, msg->rx_len); 1250 return -EINVAL; 1251 } 1252 } 1253 1254 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1255 { 1256 /* strip out 4 byte dcs header */ 1257 if (msg->rx_buf && msg->rx_len) 1258 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1259 1260 return msg->rx_len; 1261 } 1262 1263 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1264 { 1265 struct drm_device *dev = msm_host->dev; 1266 struct msm_drm_private *priv = dev->dev_private; 1267 1268 if (!dma_base) 1269 return -EINVAL; 1270 1271 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1272 priv->kms->aspace, dma_base); 1273 } 1274 1275 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1276 { 1277 if (!dma_base) 1278 return -EINVAL; 1279 1280 *dma_base = msm_host->tx_buf_paddr; 1281 return 0; 1282 } 1283 1284 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1285 { 1286 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1287 int ret; 1288 uint64_t dma_base; 1289 bool triggered; 1290 1291 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1292 if (ret) { 1293 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1294 return ret; 1295 } 1296 1297 reinit_completion(&msm_host->dma_comp); 1298 1299 dsi_wait4video_eng_busy(msm_host); 1300 1301 triggered = msm_dsi_manager_cmd_xfer_trigger( 1302 msm_host->id, dma_base, len); 1303 if (triggered) { 1304 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1305 msecs_to_jiffies(200)); 1306 DBG("ret=%d", ret); 1307 if (ret == 0) 1308 ret = -ETIMEDOUT; 1309 else 1310 ret = len; 1311 } else 1312 ret = len; 1313 1314 return ret; 1315 } 1316 1317 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1318 u8 *buf, int rx_byte, int pkt_size) 1319 { 1320 u32 *temp, data; 1321 int i, j = 0, cnt; 1322 u32 read_cnt; 1323 u8 reg[16]; 1324 int repeated_bytes = 0; 1325 int buf_offset = buf - msm_host->rx_buf; 1326 1327 temp = (u32 *)reg; 1328 cnt = (rx_byte + 3) >> 2; 1329 if (cnt > 4) 1330 cnt = 4; /* 4 x 32 bits registers only */ 1331 1332 if (rx_byte == 4) 1333 read_cnt = 4; 1334 else 1335 read_cnt = pkt_size + 6; 1336 1337 /* 1338 * In case of multiple reads from the panel, after the first read, there 1339 * is possibility that there are some bytes in the payload repeating in 1340 * the RDBK_DATA registers. Since we read all the parameters from the 1341 * panel right from the first byte for every pass. We need to skip the 1342 * repeating bytes and then append the new parameters to the rx buffer. 1343 */ 1344 if (read_cnt > 16) { 1345 int bytes_shifted; 1346 /* Any data more than 16 bytes will be shifted out. 1347 * The temp read buffer should already contain these bytes. 1348 * The remaining bytes in read buffer are the repeated bytes. 1349 */ 1350 bytes_shifted = read_cnt - 16; 1351 repeated_bytes = buf_offset - bytes_shifted; 1352 } 1353 1354 for (i = cnt - 1; i >= 0; i--) { 1355 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1356 *temp++ = ntohl(data); /* to host byte order */ 1357 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1358 } 1359 1360 for (i = repeated_bytes; i < 16; i++) 1361 buf[j++] = reg[i]; 1362 1363 return j; 1364 } 1365 1366 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1367 const struct mipi_dsi_msg *msg) 1368 { 1369 int len, ret; 1370 int bllp_len = msm_host->mode->hdisplay * 1371 dsi_get_bpp(msm_host->format) / 8; 1372 1373 len = dsi_cmd_dma_add(msm_host, msg); 1374 if (!len) { 1375 pr_err("%s: failed to add cmd type = 0x%x\n", 1376 __func__, msg->type); 1377 return -EINVAL; 1378 } 1379 1380 /* for video mode, do not send cmds more than 1381 * one pixel line, since it only transmit it 1382 * during BLLP. 1383 */ 1384 /* TODO: if the command is sent in LP mode, the bit rate is only 1385 * half of esc clk rate. In this case, if the video is already 1386 * actively streaming, we need to check more carefully if the 1387 * command can be fit into one BLLP. 1388 */ 1389 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1390 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1391 __func__, len); 1392 return -EINVAL; 1393 } 1394 1395 ret = dsi_cmd_dma_tx(msm_host, len); 1396 if (ret < len) { 1397 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", 1398 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); 1399 return -ECOMM; 1400 } 1401 1402 return len; 1403 } 1404 1405 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1406 { 1407 u32 data0, data1; 1408 1409 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1410 data1 = data0; 1411 data1 &= ~DSI_CTRL_ENABLE; 1412 dsi_write(msm_host, REG_DSI_CTRL, data1); 1413 /* 1414 * dsi controller need to be disabled before 1415 * clocks turned on 1416 */ 1417 wmb(); 1418 1419 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1420 wmb(); /* make sure clocks enabled */ 1421 1422 /* dsi controller can only be reset while clocks are running */ 1423 dsi_write(msm_host, REG_DSI_RESET, 1); 1424 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1425 dsi_write(msm_host, REG_DSI_RESET, 0); 1426 wmb(); /* controller out of reset */ 1427 dsi_write(msm_host, REG_DSI_CTRL, data0); 1428 wmb(); /* make sure dsi controller enabled again */ 1429 } 1430 1431 static void dsi_hpd_worker(struct work_struct *work) 1432 { 1433 struct msm_dsi_host *msm_host = 1434 container_of(work, struct msm_dsi_host, hpd_work); 1435 1436 drm_helper_hpd_irq_event(msm_host->dev); 1437 } 1438 1439 static void dsi_err_worker(struct work_struct *work) 1440 { 1441 struct msm_dsi_host *msm_host = 1442 container_of(work, struct msm_dsi_host, err_work); 1443 u32 status = msm_host->err_work_state; 1444 1445 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1446 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1447 dsi_sw_reset_restore(msm_host); 1448 1449 /* It is safe to clear here because error irq is disabled. */ 1450 msm_host->err_work_state = 0; 1451 1452 /* enable dsi error interrupt */ 1453 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1454 } 1455 1456 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1457 { 1458 u32 status; 1459 1460 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1461 1462 if (status) { 1463 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1464 /* Writing of an extra 0 needed to clear error bits */ 1465 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1466 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1467 } 1468 } 1469 1470 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1471 { 1472 u32 status; 1473 1474 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1475 1476 if (status) { 1477 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1478 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1479 } 1480 } 1481 1482 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1483 { 1484 u32 status; 1485 1486 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1487 1488 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1489 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1490 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1491 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1492 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1493 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1494 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1495 } 1496 } 1497 1498 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1499 { 1500 u32 status; 1501 1502 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1503 1504 /* fifo underflow, overflow */ 1505 if (status) { 1506 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1507 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1508 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1509 msm_host->err_work_state |= 1510 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1511 } 1512 } 1513 1514 static void dsi_status(struct msm_dsi_host *msm_host) 1515 { 1516 u32 status; 1517 1518 status = dsi_read(msm_host, REG_DSI_STATUS0); 1519 1520 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1521 dsi_write(msm_host, REG_DSI_STATUS0, status); 1522 msm_host->err_work_state |= 1523 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1524 } 1525 } 1526 1527 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1528 { 1529 u32 status; 1530 1531 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1532 1533 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1534 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1535 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1536 } 1537 } 1538 1539 static void dsi_error(struct msm_dsi_host *msm_host) 1540 { 1541 /* disable dsi error interrupt */ 1542 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1543 1544 dsi_clk_status(msm_host); 1545 dsi_fifo_status(msm_host); 1546 dsi_ack_err_status(msm_host); 1547 dsi_timeout_status(msm_host); 1548 dsi_status(msm_host); 1549 dsi_dln0_phy_err(msm_host); 1550 1551 queue_work(msm_host->workqueue, &msm_host->err_work); 1552 } 1553 1554 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1555 { 1556 struct msm_dsi_host *msm_host = ptr; 1557 u32 isr; 1558 unsigned long flags; 1559 1560 if (!msm_host->ctrl_base) 1561 return IRQ_HANDLED; 1562 1563 spin_lock_irqsave(&msm_host->intr_lock, flags); 1564 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1565 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1566 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1567 1568 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1569 1570 if (isr & DSI_IRQ_ERROR) 1571 dsi_error(msm_host); 1572 1573 if (isr & DSI_IRQ_VIDEO_DONE) 1574 complete(&msm_host->video_comp); 1575 1576 if (isr & DSI_IRQ_CMD_DMA_DONE) 1577 complete(&msm_host->dma_comp); 1578 1579 return IRQ_HANDLED; 1580 } 1581 1582 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1583 struct device *panel_device) 1584 { 1585 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1586 "disp-enable", 1587 GPIOD_OUT_LOW); 1588 if (IS_ERR(msm_host->disp_en_gpio)) { 1589 DBG("cannot get disp-enable-gpios %ld", 1590 PTR_ERR(msm_host->disp_en_gpio)); 1591 return PTR_ERR(msm_host->disp_en_gpio); 1592 } 1593 1594 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1595 GPIOD_IN); 1596 if (IS_ERR(msm_host->te_gpio)) { 1597 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1598 return PTR_ERR(msm_host->te_gpio); 1599 } 1600 1601 return 0; 1602 } 1603 1604 static int dsi_host_attach(struct mipi_dsi_host *host, 1605 struct mipi_dsi_device *dsi) 1606 { 1607 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1608 int ret; 1609 1610 if (dsi->lanes > msm_host->num_data_lanes) 1611 return -EINVAL; 1612 1613 msm_host->channel = dsi->channel; 1614 msm_host->lanes = dsi->lanes; 1615 msm_host->format = dsi->format; 1616 msm_host->mode_flags = dsi->mode_flags; 1617 1618 /* Some gpios defined in panel DT need to be controlled by host */ 1619 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1620 if (ret) 1621 return ret; 1622 1623 DBG("id=%d", msm_host->id); 1624 if (msm_host->dev) 1625 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1626 1627 return 0; 1628 } 1629 1630 static int dsi_host_detach(struct mipi_dsi_host *host, 1631 struct mipi_dsi_device *dsi) 1632 { 1633 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1634 1635 msm_host->device_node = NULL; 1636 1637 DBG("id=%d", msm_host->id); 1638 if (msm_host->dev) 1639 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1640 1641 return 0; 1642 } 1643 1644 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1645 const struct mipi_dsi_msg *msg) 1646 { 1647 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1648 int ret; 1649 1650 if (!msg || !msm_host->power_on) 1651 return -EINVAL; 1652 1653 mutex_lock(&msm_host->cmd_mutex); 1654 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1655 mutex_unlock(&msm_host->cmd_mutex); 1656 1657 return ret; 1658 } 1659 1660 static const struct mipi_dsi_host_ops dsi_host_ops = { 1661 .attach = dsi_host_attach, 1662 .detach = dsi_host_detach, 1663 .transfer = dsi_host_transfer, 1664 }; 1665 1666 /* 1667 * List of supported physical to logical lane mappings. 1668 * For example, the 2nd entry represents the following mapping: 1669 * 1670 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1671 */ 1672 static const int supported_data_lane_swaps[][4] = { 1673 { 0, 1, 2, 3 }, 1674 { 3, 0, 1, 2 }, 1675 { 2, 3, 0, 1 }, 1676 { 1, 2, 3, 0 }, 1677 { 0, 3, 2, 1 }, 1678 { 1, 0, 3, 2 }, 1679 { 2, 1, 0, 3 }, 1680 { 3, 2, 1, 0 }, 1681 }; 1682 1683 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1684 struct device_node *ep) 1685 { 1686 struct device *dev = &msm_host->pdev->dev; 1687 struct property *prop; 1688 u32 lane_map[4]; 1689 int ret, i, len, num_lanes; 1690 1691 prop = of_find_property(ep, "data-lanes", &len); 1692 if (!prop) { 1693 DRM_DEV_DEBUG(dev, 1694 "failed to find data lane mapping, using default\n"); 1695 return 0; 1696 } 1697 1698 num_lanes = len / sizeof(u32); 1699 1700 if (num_lanes < 1 || num_lanes > 4) { 1701 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1702 return -EINVAL; 1703 } 1704 1705 msm_host->num_data_lanes = num_lanes; 1706 1707 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1708 num_lanes); 1709 if (ret) { 1710 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1711 return ret; 1712 } 1713 1714 /* 1715 * compare DT specified physical-logical lane mappings with the ones 1716 * supported by hardware 1717 */ 1718 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1719 const int *swap = supported_data_lane_swaps[i]; 1720 int j; 1721 1722 /* 1723 * the data-lanes array we get from DT has a logical->physical 1724 * mapping. The "data lane swap" register field represents 1725 * supported configurations in a physical->logical mapping. 1726 * Translate the DT mapping to what we understand and find a 1727 * configuration that works. 1728 */ 1729 for (j = 0; j < num_lanes; j++) { 1730 if (lane_map[j] < 0 || lane_map[j] > 3) 1731 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1732 lane_map[j]); 1733 1734 if (swap[lane_map[j]] != j) 1735 break; 1736 } 1737 1738 if (j == num_lanes) { 1739 msm_host->dlane_swap = i; 1740 return 0; 1741 } 1742 } 1743 1744 return -EINVAL; 1745 } 1746 1747 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1748 { 1749 struct device *dev = &msm_host->pdev->dev; 1750 struct device_node *np = dev->of_node; 1751 struct device_node *endpoint, *device_node; 1752 int ret = 0; 1753 1754 /* 1755 * Get the endpoint of the output port of the DSI host. In our case, 1756 * this is mapped to port number with reg = 1. Don't return an error if 1757 * the remote endpoint isn't defined. It's possible that there is 1758 * nothing connected to the dsi output. 1759 */ 1760 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1761 if (!endpoint) { 1762 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1763 return 0; 1764 } 1765 1766 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1767 if (ret) { 1768 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1769 __func__, ret); 1770 ret = -EINVAL; 1771 goto err; 1772 } 1773 1774 /* Get panel node from the output port's endpoint data */ 1775 device_node = of_graph_get_remote_node(np, 1, 0); 1776 if (!device_node) { 1777 DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__); 1778 ret = -ENODEV; 1779 goto err; 1780 } 1781 1782 msm_host->device_node = device_node; 1783 1784 if (of_property_read_bool(np, "syscon-sfpb")) { 1785 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1786 "syscon-sfpb"); 1787 if (IS_ERR(msm_host->sfpb)) { 1788 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1789 __func__); 1790 ret = PTR_ERR(msm_host->sfpb); 1791 } 1792 } 1793 1794 of_node_put(device_node); 1795 1796 err: 1797 of_node_put(endpoint); 1798 1799 return ret; 1800 } 1801 1802 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1803 { 1804 struct platform_device *pdev = msm_host->pdev; 1805 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1806 struct resource *res; 1807 int i; 1808 1809 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1810 if (!res) 1811 return -EINVAL; 1812 1813 for (i = 0; i < cfg->num_dsi; i++) { 1814 if (cfg->io_start[i] == res->start) 1815 return i; 1816 } 1817 1818 return -EINVAL; 1819 } 1820 1821 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1822 { 1823 struct msm_dsi_host *msm_host = NULL; 1824 struct platform_device *pdev = msm_dsi->pdev; 1825 int ret; 1826 1827 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1828 if (!msm_host) { 1829 pr_err("%s: FAILED: cannot alloc dsi host\n", 1830 __func__); 1831 ret = -ENOMEM; 1832 goto fail; 1833 } 1834 1835 msm_host->pdev = pdev; 1836 msm_dsi->host = &msm_host->base; 1837 1838 ret = dsi_host_parse_dt(msm_host); 1839 if (ret) { 1840 pr_err("%s: failed to parse dt\n", __func__); 1841 goto fail; 1842 } 1843 1844 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); 1845 if (IS_ERR(msm_host->ctrl_base)) { 1846 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1847 ret = PTR_ERR(msm_host->ctrl_base); 1848 goto fail; 1849 } 1850 1851 pm_runtime_enable(&pdev->dev); 1852 1853 msm_host->cfg_hnd = dsi_get_config(msm_host); 1854 if (!msm_host->cfg_hnd) { 1855 ret = -EINVAL; 1856 pr_err("%s: get config failed\n", __func__); 1857 goto fail; 1858 } 1859 1860 msm_host->id = dsi_host_get_id(msm_host); 1861 if (msm_host->id < 0) { 1862 ret = msm_host->id; 1863 pr_err("%s: unable to identify DSI host index\n", __func__); 1864 goto fail; 1865 } 1866 1867 /* fixup base address by io offset */ 1868 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; 1869 1870 ret = dsi_regulator_init(msm_host); 1871 if (ret) { 1872 pr_err("%s: regulator init failed\n", __func__); 1873 goto fail; 1874 } 1875 1876 ret = dsi_clk_init(msm_host); 1877 if (ret) { 1878 pr_err("%s: unable to initialize dsi clks\n", __func__); 1879 goto fail; 1880 } 1881 1882 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1883 if (!msm_host->rx_buf) { 1884 ret = -ENOMEM; 1885 pr_err("%s: alloc rx temp buf failed\n", __func__); 1886 goto fail; 1887 } 1888 1889 msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "byte"); 1890 if (IS_ERR(msm_host->opp_table)) 1891 return PTR_ERR(msm_host->opp_table); 1892 /* OPP table is optional */ 1893 ret = dev_pm_opp_of_add_table(&pdev->dev); 1894 if (ret && ret != -ENODEV) { 1895 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1896 dev_pm_opp_put_clkname(msm_host->opp_table); 1897 return ret; 1898 } 1899 1900 init_completion(&msm_host->dma_comp); 1901 init_completion(&msm_host->video_comp); 1902 mutex_init(&msm_host->dev_mutex); 1903 mutex_init(&msm_host->cmd_mutex); 1904 spin_lock_init(&msm_host->intr_lock); 1905 1906 /* setup workqueue */ 1907 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1908 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1909 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); 1910 1911 msm_dsi->id = msm_host->id; 1912 1913 DBG("Dsi Host %d initialized", msm_host->id); 1914 return 0; 1915 1916 fail: 1917 return ret; 1918 } 1919 1920 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1921 { 1922 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1923 1924 DBG(""); 1925 dsi_tx_buf_free(msm_host); 1926 if (msm_host->workqueue) { 1927 flush_workqueue(msm_host->workqueue); 1928 destroy_workqueue(msm_host->workqueue); 1929 msm_host->workqueue = NULL; 1930 } 1931 1932 mutex_destroy(&msm_host->cmd_mutex); 1933 mutex_destroy(&msm_host->dev_mutex); 1934 1935 dev_pm_opp_of_remove_table(&msm_host->pdev->dev); 1936 dev_pm_opp_put_clkname(msm_host->opp_table); 1937 pm_runtime_disable(&msm_host->pdev->dev); 1938 } 1939 1940 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1941 struct drm_device *dev) 1942 { 1943 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1944 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1945 struct platform_device *pdev = msm_host->pdev; 1946 int ret; 1947 1948 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1949 if (msm_host->irq < 0) { 1950 ret = msm_host->irq; 1951 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); 1952 return ret; 1953 } 1954 1955 ret = devm_request_irq(&pdev->dev, msm_host->irq, 1956 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1957 "dsi_isr", msm_host); 1958 if (ret < 0) { 1959 DRM_DEV_ERROR(&pdev->dev, "failed to request IRQ%u: %d\n", 1960 msm_host->irq, ret); 1961 return ret; 1962 } 1963 1964 msm_host->dev = dev; 1965 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 1966 if (ret) { 1967 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1968 return ret; 1969 } 1970 1971 return 0; 1972 } 1973 1974 int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) 1975 { 1976 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1977 int ret; 1978 1979 /* Register mipi dsi host */ 1980 if (!msm_host->registered) { 1981 host->dev = &msm_host->pdev->dev; 1982 host->ops = &dsi_host_ops; 1983 ret = mipi_dsi_host_register(host); 1984 if (ret) 1985 return ret; 1986 1987 msm_host->registered = true; 1988 1989 /* If the panel driver has not been probed after host register, 1990 * we should defer the host's probe. 1991 * It makes sure panel is connected when fbcon detects 1992 * connector status and gets the proper display mode to 1993 * create framebuffer. 1994 * Don't try to defer if there is nothing connected to the dsi 1995 * output 1996 */ 1997 if (check_defer && msm_host->device_node) { 1998 if (IS_ERR(of_drm_find_panel(msm_host->device_node))) 1999 if (!of_drm_find_bridge(msm_host->device_node)) 2000 return -EPROBE_DEFER; 2001 } 2002 } 2003 2004 return 0; 2005 } 2006 2007 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2008 { 2009 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2010 2011 if (msm_host->registered) { 2012 mipi_dsi_host_unregister(host); 2013 host->dev = NULL; 2014 host->ops = NULL; 2015 msm_host->registered = false; 2016 } 2017 } 2018 2019 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2020 const struct mipi_dsi_msg *msg) 2021 { 2022 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2023 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2024 2025 /* TODO: make sure dsi_cmd_mdp is idle. 2026 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2027 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2028 * How to handle the old versions? Wait for mdp cmd done? 2029 */ 2030 2031 /* 2032 * mdss interrupt is generated in mdp core clock domain 2033 * mdp clock need to be enabled to receive dsi interrupt 2034 */ 2035 pm_runtime_get_sync(&msm_host->pdev->dev); 2036 cfg_hnd->ops->link_clk_set_rate(msm_host); 2037 cfg_hnd->ops->link_clk_enable(msm_host); 2038 2039 /* TODO: vote for bus bandwidth */ 2040 2041 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2042 dsi_set_tx_power_mode(0, msm_host); 2043 2044 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2045 dsi_write(msm_host, REG_DSI_CTRL, 2046 msm_host->dma_cmd_ctrl_restore | 2047 DSI_CTRL_CMD_MODE_EN | 2048 DSI_CTRL_ENABLE); 2049 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2050 2051 return 0; 2052 } 2053 2054 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2055 const struct mipi_dsi_msg *msg) 2056 { 2057 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2058 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2059 2060 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2061 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2062 2063 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2064 dsi_set_tx_power_mode(1, msm_host); 2065 2066 /* TODO: unvote for bus bandwidth */ 2067 2068 cfg_hnd->ops->link_clk_disable(msm_host); 2069 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2070 } 2071 2072 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2073 const struct mipi_dsi_msg *msg) 2074 { 2075 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2076 2077 return dsi_cmds2buf_tx(msm_host, msg); 2078 } 2079 2080 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2081 const struct mipi_dsi_msg *msg) 2082 { 2083 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2084 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2085 int data_byte, rx_byte, dlen, end; 2086 int short_response, diff, pkt_size, ret = 0; 2087 char cmd; 2088 int rlen = msg->rx_len; 2089 u8 *buf; 2090 2091 if (rlen <= 2) { 2092 short_response = 1; 2093 pkt_size = rlen; 2094 rx_byte = 4; 2095 } else { 2096 short_response = 0; 2097 data_byte = 10; /* first read */ 2098 if (rlen < data_byte) 2099 pkt_size = rlen; 2100 else 2101 pkt_size = data_byte; 2102 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2103 } 2104 2105 buf = msm_host->rx_buf; 2106 end = 0; 2107 while (!end) { 2108 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2109 struct mipi_dsi_msg max_pkt_size_msg = { 2110 .channel = msg->channel, 2111 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2112 .tx_len = 2, 2113 .tx_buf = tx, 2114 }; 2115 2116 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2117 rlen, pkt_size, rx_byte); 2118 2119 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2120 if (ret < 2) { 2121 pr_err("%s: Set max pkt size failed, %d\n", 2122 __func__, ret); 2123 return -EINVAL; 2124 } 2125 2126 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2127 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2128 /* Clear the RDBK_DATA registers */ 2129 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2130 DSI_RDBK_DATA_CTRL_CLR); 2131 wmb(); /* make sure the RDBK registers are cleared */ 2132 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2133 wmb(); /* release cleared status before transfer */ 2134 } 2135 2136 ret = dsi_cmds2buf_tx(msm_host, msg); 2137 if (ret < msg->tx_len) { 2138 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2139 return ret; 2140 } 2141 2142 /* 2143 * once cmd_dma_done interrupt received, 2144 * return data from client is ready and stored 2145 * at RDBK_DATA register already 2146 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2147 * after that dcs header lost during shift into registers 2148 */ 2149 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2150 2151 if (dlen <= 0) 2152 return 0; 2153 2154 if (short_response) 2155 break; 2156 2157 if (rlen <= data_byte) { 2158 diff = data_byte - rlen; 2159 end = 1; 2160 } else { 2161 diff = 0; 2162 rlen -= data_byte; 2163 } 2164 2165 if (!end) { 2166 dlen -= 2; /* 2 crc */ 2167 dlen -= diff; 2168 buf += dlen; /* next start position */ 2169 data_byte = 14; /* NOT first read */ 2170 if (rlen < data_byte) 2171 pkt_size += rlen; 2172 else 2173 pkt_size += data_byte; 2174 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2175 } 2176 } 2177 2178 /* 2179 * For single Long read, if the requested rlen < 10, 2180 * we need to shift the start position of rx 2181 * data buffer to skip the bytes which are not 2182 * updated. 2183 */ 2184 if (pkt_size < 10 && !short_response) 2185 buf = msm_host->rx_buf + (10 - rlen); 2186 else 2187 buf = msm_host->rx_buf; 2188 2189 cmd = buf[0]; 2190 switch (cmd) { 2191 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2192 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2193 ret = 0; 2194 break; 2195 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2196 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2197 ret = dsi_short_read1_resp(buf, msg); 2198 break; 2199 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2200 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2201 ret = dsi_short_read2_resp(buf, msg); 2202 break; 2203 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2204 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2205 ret = dsi_long_read_resp(buf, msg); 2206 break; 2207 default: 2208 pr_warn("%s:Invalid response cmd\n", __func__); 2209 ret = 0; 2210 } 2211 2212 return ret; 2213 } 2214 2215 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2216 u32 len) 2217 { 2218 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2219 2220 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2221 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2222 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2223 2224 /* Make sure trigger happens */ 2225 wmb(); 2226 } 2227 2228 int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, 2229 struct msm_dsi_pll *src_pll) 2230 { 2231 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2232 struct clk *byte_clk_provider, *pixel_clk_provider; 2233 int ret; 2234 2235 ret = msm_dsi_pll_get_clk_provider(src_pll, 2236 &byte_clk_provider, &pixel_clk_provider); 2237 if (ret) { 2238 pr_info("%s: can't get provider from pll, don't set parent\n", 2239 __func__); 2240 return 0; 2241 } 2242 2243 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); 2244 if (ret) { 2245 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", 2246 __func__, ret); 2247 goto exit; 2248 } 2249 2250 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); 2251 if (ret) { 2252 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", 2253 __func__, ret); 2254 goto exit; 2255 } 2256 2257 if (msm_host->dsi_clk_src) { 2258 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); 2259 if (ret) { 2260 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", 2261 __func__, ret); 2262 goto exit; 2263 } 2264 } 2265 2266 if (msm_host->esc_clk_src) { 2267 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); 2268 if (ret) { 2269 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", 2270 __func__, ret); 2271 goto exit; 2272 } 2273 } 2274 2275 exit: 2276 return ret; 2277 } 2278 2279 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2280 { 2281 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2282 2283 DBG(""); 2284 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2285 /* Make sure fully reset */ 2286 wmb(); 2287 udelay(1000); 2288 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2289 udelay(100); 2290 } 2291 2292 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2293 struct msm_dsi_phy_clk_request *clk_req, 2294 bool is_dual_dsi) 2295 { 2296 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2297 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2298 int ret; 2299 2300 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi); 2301 if (ret) { 2302 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2303 return; 2304 } 2305 2306 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2307 clk_req->escclk_rate = msm_host->esc_clk_rate; 2308 } 2309 2310 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2311 { 2312 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2313 2314 dsi_op_mode_config(msm_host, 2315 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2316 2317 /* TODO: clock should be turned off for command mode, 2318 * and only turned on before MDP START. 2319 * This part of code should be enabled once mdp driver support it. 2320 */ 2321 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2322 * dsi_link_clk_disable(msm_host); 2323 * pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2324 * } 2325 */ 2326 msm_host->enabled = true; 2327 return 0; 2328 } 2329 2330 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2331 { 2332 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2333 2334 msm_host->enabled = false; 2335 dsi_op_mode_config(msm_host, 2336 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2337 2338 /* Since we have disabled INTF, the video engine won't stop so that 2339 * the cmd engine will be blocked. 2340 * Reset to disable video engine so that we can send off cmd. 2341 */ 2342 dsi_sw_reset(msm_host); 2343 2344 return 0; 2345 } 2346 2347 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2348 { 2349 enum sfpb_ahb_arb_master_port_en en; 2350 2351 if (!msm_host->sfpb) 2352 return; 2353 2354 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2355 2356 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2357 SFPB_GPREG_MASTER_PORT_EN__MASK, 2358 SFPB_GPREG_MASTER_PORT_EN(en)); 2359 } 2360 2361 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2362 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2363 bool is_dual_dsi) 2364 { 2365 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2366 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2367 int ret = 0; 2368 2369 mutex_lock(&msm_host->dev_mutex); 2370 if (msm_host->power_on) { 2371 DBG("dsi host already on"); 2372 goto unlock_ret; 2373 } 2374 2375 msm_dsi_sfpb_config(msm_host, true); 2376 2377 ret = dsi_host_regulator_enable(msm_host); 2378 if (ret) { 2379 pr_err("%s:Failed to enable vregs.ret=%d\n", 2380 __func__, ret); 2381 goto unlock_ret; 2382 } 2383 2384 pm_runtime_get_sync(&msm_host->pdev->dev); 2385 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2386 if (!ret) 2387 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2388 if (ret) { 2389 pr_err("%s: failed to enable link clocks. ret=%d\n", 2390 __func__, ret); 2391 goto fail_disable_reg; 2392 } 2393 2394 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2395 if (ret) { 2396 pr_err("%s: failed to set pinctrl default state, %d\n", 2397 __func__, ret); 2398 goto fail_disable_clk; 2399 } 2400 2401 dsi_timing_setup(msm_host, is_dual_dsi); 2402 dsi_sw_reset(msm_host); 2403 dsi_ctrl_config(msm_host, true, phy_shared_timings); 2404 2405 if (msm_host->disp_en_gpio) 2406 gpiod_set_value(msm_host->disp_en_gpio, 1); 2407 2408 msm_host->power_on = true; 2409 mutex_unlock(&msm_host->dev_mutex); 2410 2411 return 0; 2412 2413 fail_disable_clk: 2414 cfg_hnd->ops->link_clk_disable(msm_host); 2415 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2416 fail_disable_reg: 2417 dsi_host_regulator_disable(msm_host); 2418 unlock_ret: 2419 mutex_unlock(&msm_host->dev_mutex); 2420 return ret; 2421 } 2422 2423 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2424 { 2425 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2426 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2427 2428 mutex_lock(&msm_host->dev_mutex); 2429 if (!msm_host->power_on) { 2430 DBG("dsi host already off"); 2431 goto unlock_ret; 2432 } 2433 2434 dsi_ctrl_config(msm_host, false, NULL); 2435 2436 if (msm_host->disp_en_gpio) 2437 gpiod_set_value(msm_host->disp_en_gpio, 0); 2438 2439 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2440 2441 cfg_hnd->ops->link_clk_disable(msm_host); 2442 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2443 2444 dsi_host_regulator_disable(msm_host); 2445 2446 msm_dsi_sfpb_config(msm_host, false); 2447 2448 DBG("-"); 2449 2450 msm_host->power_on = false; 2451 2452 unlock_ret: 2453 mutex_unlock(&msm_host->dev_mutex); 2454 return 0; 2455 } 2456 2457 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2458 const struct drm_display_mode *mode) 2459 { 2460 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2461 2462 if (msm_host->mode) { 2463 drm_mode_destroy(msm_host->dev, msm_host->mode); 2464 msm_host->mode = NULL; 2465 } 2466 2467 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2468 if (!msm_host->mode) { 2469 pr_err("%s: cannot duplicate mode\n", __func__); 2470 return -ENOMEM; 2471 } 2472 2473 return 0; 2474 } 2475 2476 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host) 2477 { 2478 return of_drm_find_panel(to_msm_dsi_host(host)->device_node); 2479 } 2480 2481 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2482 { 2483 return to_msm_dsi_host(host)->mode_flags; 2484 } 2485 2486 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) 2487 { 2488 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2489 2490 return of_drm_find_bridge(msm_host->device_node); 2491 } 2492