1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of.h> 13 #include <linux/of_graph.h> 14 #include <linux/of_irq.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/pm_opp.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spinlock.h> 20 21 #include <video/mipi_display.h> 22 23 #include <drm/display/drm_dsc_helper.h> 24 #include <drm/drm_of.h> 25 26 #include "dsi.h" 27 #include "dsi.xml.h" 28 #include "sfpb.xml.h" 29 #include "dsi_cfg.h" 30 #include "msm_dsc_helper.h" 31 #include "msm_kms.h" 32 #include "msm_gem.h" 33 #include "phy/dsi_phy.h" 34 35 #define DSI_RESET_TOGGLE_DELAY_MS 20 36 37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 38 39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 40 { 41 u32 ver; 42 43 if (!major || !minor) 44 return -EINVAL; 45 46 /* 47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 48 * makes all other registers 4-byte shifted down. 49 * 50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 51 * older, we read the DSI_VERSION register without any shift(offset 52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 53 * the case of DSI6G, this has to be zero (the offset points to a 54 * scratch register which we never touch) 55 */ 56 57 ver = readl(base + REG_DSI_VERSION); 58 if (ver) { 59 /* older dsi host, there is no register shift */ 60 ver = FIELD(ver, DSI_VERSION_MAJOR); 61 if (ver <= MSM_DSI_VER_MAJOR_V2) { 62 /* old versions */ 63 *major = ver; 64 *minor = 0; 65 return 0; 66 } else { 67 return -EINVAL; 68 } 69 } else { 70 /* 71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 72 * registers are shifted down, read DSI_VERSION again with 73 * the shifted offset 74 */ 75 ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 76 ver = FIELD(ver, DSI_VERSION_MAJOR); 77 if (ver == MSM_DSI_VER_MAJOR_6G) { 78 /* 6G version */ 79 *major = ver; 80 *minor = readl(base + REG_DSI_6G_HW_VERSION); 81 return 0; 82 } else { 83 return -EINVAL; 84 } 85 } 86 } 87 88 #define DSI_ERR_STATE_ACK 0x0000 89 #define DSI_ERR_STATE_TIMEOUT 0x0001 90 #define DSI_ERR_STATE_DLN0_PHY 0x0002 91 #define DSI_ERR_STATE_FIFO 0x0004 92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 95 96 #define DSI_CLK_CTRL_ENABLE_CLKS \ 97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 101 102 struct msm_dsi_host { 103 struct mipi_dsi_host base; 104 105 struct platform_device *pdev; 106 struct drm_device *dev; 107 108 int id; 109 110 void __iomem *ctrl_base; 111 phys_addr_t ctrl_size; 112 struct regulator_bulk_data *supplies; 113 114 int num_bus_clks; 115 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 116 117 struct clk *byte_clk; 118 struct clk *esc_clk; 119 struct clk *pixel_clk; 120 struct clk *byte_intf_clk; 121 122 /* 123 * Clocks which needs to be properly parented between DISPCC and DSI PHY 124 * PLL: 125 */ 126 struct clk *byte_src_clk; 127 struct clk *pixel_src_clk; 128 struct clk *dsi_pll_byte_clk; 129 struct clk *dsi_pll_pixel_clk; 130 131 unsigned long byte_clk_rate; 132 unsigned long byte_intf_clk_rate; 133 unsigned long pixel_clk_rate; 134 unsigned long esc_clk_rate; 135 136 /* DSI v2 specific clocks */ 137 struct clk *src_clk; 138 139 unsigned long src_clk_rate; 140 141 const struct msm_dsi_cfg_handler *cfg_hnd; 142 143 struct completion dma_comp; 144 struct completion video_comp; 145 struct mutex dev_mutex; 146 struct mutex cmd_mutex; 147 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 148 149 u32 err_work_state; 150 struct work_struct err_work; 151 struct workqueue_struct *workqueue; 152 153 /* DSI 6G TX buffer*/ 154 struct drm_gem_object *tx_gem_obj; 155 struct drm_gpuvm *vm; 156 157 /* DSI v2 TX buffer */ 158 void *tx_buf; 159 dma_addr_t tx_buf_paddr; 160 161 int tx_size; 162 163 u8 *rx_buf; 164 165 struct regmap *sfpb; 166 167 struct drm_display_mode *mode; 168 struct drm_dsc_config *dsc; 169 unsigned int dsc_slice_per_pkt; 170 171 /* connected device info */ 172 unsigned int channel; 173 unsigned int lanes; 174 enum mipi_dsi_pixel_format format; 175 unsigned long mode_flags; 176 177 /* lane data parsed via DT */ 178 int dlane_swap; 179 int num_data_lanes; 180 181 /* from phy DT */ 182 bool cphy_mode; 183 184 u32 dma_cmd_ctrl_restore; 185 186 bool registered; 187 bool power_on; 188 bool enabled; 189 int irq; 190 }; 191 192 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 193 { 194 return readl(msm_host->ctrl_base + reg); 195 } 196 197 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 198 { 199 writel(data, msm_host->ctrl_base + reg); 200 } 201 202 static const struct msm_dsi_cfg_handler * 203 dsi_get_config(struct msm_dsi_host *msm_host) 204 { 205 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 206 struct device *dev = &msm_host->pdev->dev; 207 struct clk *ahb_clk; 208 int ret; 209 u32 major = 0, minor = 0; 210 211 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 212 if (IS_ERR(ahb_clk)) { 213 dev_err_probe(dev, PTR_ERR(ahb_clk), "%s: cannot get interface clock\n", 214 __func__); 215 goto exit; 216 } 217 218 pm_runtime_get_sync(dev); 219 220 ret = clk_prepare_enable(ahb_clk); 221 if (ret) { 222 dev_err_probe(dev, ret, "%s: unable to enable ahb_clk\n", __func__); 223 goto runtime_put; 224 } 225 226 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 227 if (ret) { 228 dev_err_probe(dev, ret, "%s: Invalid version\n", __func__); 229 goto disable_clks; 230 } 231 232 cfg_hnd = msm_dsi_cfg_get(major, minor); 233 234 DBG("%s: Version %x:%x\n", __func__, major, minor); 235 236 disable_clks: 237 clk_disable_unprepare(ahb_clk); 238 runtime_put: 239 pm_runtime_put_sync(dev); 240 exit: 241 return cfg_hnd; 242 } 243 244 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 245 { 246 return container_of(host, struct msm_dsi_host, base); 247 } 248 249 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 250 { 251 struct platform_device *pdev = msm_host->pdev; 252 int ret = 0; 253 254 msm_host->src_clk = msm_clk_get(pdev, "src"); 255 256 if (IS_ERR(msm_host->src_clk)) { 257 ret = PTR_ERR(msm_host->src_clk); 258 pr_err("%s: can't find src clock. ret=%d\n", 259 __func__, ret); 260 msm_host->src_clk = NULL; 261 return ret; 262 } 263 264 return ret; 265 } 266 267 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 268 { 269 struct platform_device *pdev = msm_host->pdev; 270 int ret = 0; 271 272 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 273 if (IS_ERR(msm_host->byte_intf_clk)) { 274 ret = PTR_ERR(msm_host->byte_intf_clk); 275 pr_err("%s: can't find byte_intf clock. ret=%d\n", 276 __func__, ret); 277 } 278 279 return ret; 280 } 281 282 int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host) 283 { 284 struct device *dev = &msm_host->pdev->dev; 285 int ret; 286 287 ret = dsi_clk_init_6g_v2(msm_host); 288 if (ret) 289 return ret; 290 291 msm_host->byte_src_clk = devm_clk_get(dev, "byte_src"); 292 if (IS_ERR(msm_host->byte_src_clk)) 293 return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk), 294 "can't get byte_src clock\n"); 295 296 msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte"); 297 if (IS_ERR(msm_host->dsi_pll_byte_clk)) 298 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk), 299 "can't get dsi_pll_byte clock\n"); 300 301 msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src"); 302 if (IS_ERR(msm_host->pixel_src_clk)) 303 return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk), 304 "can't get pixel_src clock\n"); 305 306 msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel"); 307 if (IS_ERR(msm_host->dsi_pll_pixel_clk)) 308 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk), 309 "can't get dsi_pll_pixel clock\n"); 310 311 return 0; 312 } 313 314 static int dsi_clk_init(struct msm_dsi_host *msm_host) 315 { 316 struct platform_device *pdev = msm_host->pdev; 317 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 318 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 319 int i, ret = 0; 320 321 /* get bus clocks */ 322 for (i = 0; i < cfg->num_bus_clks; i++) 323 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 324 msm_host->num_bus_clks = cfg->num_bus_clks; 325 326 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 327 if (ret < 0) 328 return dev_err_probe(&pdev->dev, ret, "Unable to get clocks\n"); 329 330 /* get link and source clocks */ 331 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 332 if (IS_ERR(msm_host->byte_clk)) 333 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->byte_clk), 334 "%s: can't find dsi_byte clock\n", 335 __func__); 336 337 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 338 if (IS_ERR(msm_host->pixel_clk)) 339 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->pixel_clk), 340 "%s: can't find dsi_pixel clock\n", 341 __func__); 342 343 msm_host->esc_clk = msm_clk_get(pdev, "core"); 344 if (IS_ERR(msm_host->esc_clk)) 345 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->esc_clk), 346 "%s: can't find dsi_esc clock\n", 347 __func__); 348 349 if (cfg_hnd->ops->clk_init_ver) 350 ret = cfg_hnd->ops->clk_init_ver(msm_host); 351 352 return ret; 353 } 354 355 int msm_dsi_runtime_suspend(struct device *dev) 356 { 357 struct platform_device *pdev = to_platform_device(dev); 358 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 359 struct mipi_dsi_host *host = msm_dsi->host; 360 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 361 362 if (!msm_host->cfg_hnd) 363 return 0; 364 365 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 366 367 return 0; 368 } 369 370 int msm_dsi_runtime_resume(struct device *dev) 371 { 372 struct platform_device *pdev = to_platform_device(dev); 373 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 374 struct mipi_dsi_host *host = msm_dsi->host; 375 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 376 377 if (!msm_host->cfg_hnd) 378 return 0; 379 380 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 381 } 382 383 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 384 { 385 int ret; 386 387 DBG("Set clk rates: pclk=%lu, byteclk=%lu", 388 msm_host->pixel_clk_rate, msm_host->byte_clk_rate); 389 390 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 391 msm_host->byte_clk_rate); 392 if (ret) { 393 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 394 return ret; 395 } 396 397 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 398 if (ret) { 399 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 400 return ret; 401 } 402 403 if (msm_host->byte_intf_clk) { 404 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); 405 if (ret) { 406 pr_err("%s: Failed to set rate byte intf clk, %d\n", 407 __func__, ret); 408 return ret; 409 } 410 } 411 412 return 0; 413 } 414 415 int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host) 416 { 417 struct device *dev = &msm_host->pdev->dev; 418 int ret; 419 420 /* 421 * DSI PHY PLLs have to be enabled to allow reparenting to them, so 422 * cannot use assigned-clock-parents. 423 */ 424 ret = clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk); 425 if (ret) 426 dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret); 427 428 ret = clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_clk); 429 if (ret) 430 dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret); 431 432 return dsi_link_clk_set_rate_6g(msm_host); 433 } 434 435 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 436 { 437 int ret; 438 439 ret = clk_prepare_enable(msm_host->esc_clk); 440 if (ret) { 441 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 442 goto error; 443 } 444 445 ret = clk_prepare_enable(msm_host->byte_clk); 446 if (ret) { 447 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 448 goto byte_clk_err; 449 } 450 451 ret = clk_prepare_enable(msm_host->pixel_clk); 452 if (ret) { 453 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 454 goto pixel_clk_err; 455 } 456 457 ret = clk_prepare_enable(msm_host->byte_intf_clk); 458 if (ret) { 459 pr_err("%s: Failed to enable byte intf clk\n", 460 __func__); 461 goto byte_intf_clk_err; 462 } 463 464 return 0; 465 466 byte_intf_clk_err: 467 clk_disable_unprepare(msm_host->pixel_clk); 468 pixel_clk_err: 469 clk_disable_unprepare(msm_host->byte_clk); 470 byte_clk_err: 471 clk_disable_unprepare(msm_host->esc_clk); 472 error: 473 return ret; 474 } 475 476 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 477 { 478 int ret; 479 480 DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 481 msm_host->pixel_clk_rate, msm_host->byte_clk_rate, 482 msm_host->esc_clk_rate, msm_host->src_clk_rate); 483 484 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 485 if (ret) { 486 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 487 return ret; 488 } 489 490 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 491 if (ret) { 492 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 493 return ret; 494 } 495 496 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 497 if (ret) { 498 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 499 return ret; 500 } 501 502 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 503 if (ret) { 504 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 505 return ret; 506 } 507 508 return 0; 509 } 510 511 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 512 { 513 int ret; 514 515 ret = clk_prepare_enable(msm_host->byte_clk); 516 if (ret) { 517 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 518 goto error; 519 } 520 521 ret = clk_prepare_enable(msm_host->esc_clk); 522 if (ret) { 523 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 524 goto esc_clk_err; 525 } 526 527 ret = clk_prepare_enable(msm_host->src_clk); 528 if (ret) { 529 pr_err("%s: Failed to enable dsi src clk\n", __func__); 530 goto src_clk_err; 531 } 532 533 ret = clk_prepare_enable(msm_host->pixel_clk); 534 if (ret) { 535 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 536 goto pixel_clk_err; 537 } 538 539 return 0; 540 541 pixel_clk_err: 542 clk_disable_unprepare(msm_host->src_clk); 543 src_clk_err: 544 clk_disable_unprepare(msm_host->esc_clk); 545 esc_clk_err: 546 clk_disable_unprepare(msm_host->byte_clk); 547 error: 548 return ret; 549 } 550 551 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 552 { 553 clk_disable_unprepare(msm_host->esc_clk); 554 clk_disable_unprepare(msm_host->pixel_clk); 555 clk_disable_unprepare(msm_host->byte_intf_clk); 556 clk_disable_unprepare(msm_host->byte_clk); 557 } 558 559 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 560 { 561 clk_disable_unprepare(msm_host->pixel_clk); 562 clk_disable_unprepare(msm_host->src_clk); 563 clk_disable_unprepare(msm_host->esc_clk); 564 clk_disable_unprepare(msm_host->byte_clk); 565 } 566 567 /** 568 * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case 569 * @mode: The selected mode for the DSI output 570 * @dsc: DRM DSC configuration for this DSI output 571 * @is_bonded_dsi: True if two DSI controllers are bonded 572 * 573 * Adjust the pclk rate by calculating a new hdisplay proportional to 574 * the compression ratio such that: 575 * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp 576 * 577 * Porches do not need to be adjusted: 578 * - For VIDEO mode they are not compressed by DSC and are passed as is. 579 * - For CMD mode there are no actual porches. Instead these fields 580 * currently represent the overhead to the image data transfer. As such, they 581 * are calculated for the final mode parameters (after the compression) and 582 * are not to be adjusted too. 583 * 584 * FIXME: Reconsider this if/when CMD mode handling is rewritten to use 585 * transfer time and data overhead as a starting point of the calculations. 586 */ 587 static unsigned long 588 dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, 589 const struct drm_dsc_config *dsc, 590 bool is_bonded_dsi) 591 { 592 int hdisplay, new_hdisplay, new_htotal; 593 594 /* 595 * For bonded DSI, split hdisplay across two links and round up each 596 * half separately, passing the full hdisplay would only round up once. 597 * This also aligns with the hdisplay we program later in 598 * dsi_timing_setup() 599 */ 600 hdisplay = mode->hdisplay; 601 if (is_bonded_dsi) 602 hdisplay /= 2; 603 604 new_hdisplay = DIV_ROUND_UP(hdisplay * drm_dsc_get_bpp_int(dsc), 605 dsc->bits_per_component * 3); 606 607 if (is_bonded_dsi) 608 new_hdisplay *= 2; 609 610 new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; 611 612 return mult_frac(mode->clock * 1000u, new_htotal, mode->htotal); 613 } 614 615 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, 616 const struct drm_dsc_config *dsc, bool is_bonded_dsi) 617 { 618 unsigned long pclk_rate; 619 620 pclk_rate = mode->clock * 1000u; 621 622 if (dsc) 623 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc, is_bonded_dsi); 624 625 /* 626 * For bonded DSI mode, the current DRM mode has the complete width of the 627 * panel. Since, the complete panel is driven by two DSI controllers, 628 * the clock rates have to be split between the two dsi controllers. 629 * Adjust the byte and pixel clock rates for each dsi host accordingly. 630 */ 631 if (is_bonded_dsi) 632 pclk_rate /= 2; 633 634 return pclk_rate; 635 } 636 637 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 638 const struct drm_display_mode *mode) 639 { 640 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 641 u8 lanes = msm_host->lanes; 642 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 643 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); 644 unsigned long pclk_bpp; 645 646 if (lanes == 0) { 647 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 648 lanes = 1; 649 } 650 651 /* CPHY "byte_clk" is in units of 16 bits */ 652 if (msm_host->cphy_mode) 653 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); 654 else 655 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); 656 657 return pclk_bpp; 658 } 659 660 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 661 { 662 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); 663 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 664 msm_host->mode); 665 666 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 667 msm_host->byte_clk_rate); 668 } 669 670 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 671 { 672 long rounded_byte_clk_rate; 673 674 if (!msm_host->mode) { 675 pr_err("%s: mode not set\n", __func__); 676 return -EINVAL; 677 } 678 679 dsi_calc_pclk(msm_host, is_bonded_dsi); 680 681 rounded_byte_clk_rate = clk_round_rate(msm_host->byte_clk, 682 msm_host->byte_clk_rate); 683 if (rounded_byte_clk_rate < 0) { 684 pr_err("%s: failed to round byte clock rate, %ld\n", 685 __func__, rounded_byte_clk_rate); 686 return rounded_byte_clk_rate; 687 } 688 689 msm_host->byte_clk_rate = rounded_byte_clk_rate; 690 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 691 return 0; 692 } 693 694 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 695 { 696 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 697 unsigned int esc_mhz, esc_div; 698 unsigned long byte_mhz; 699 700 dsi_calc_pclk(msm_host, is_bonded_dsi); 701 702 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); 703 704 /* 705 * esc clock is byte clock followed by a 4 bit divider, 706 * we need to find an escape clock frequency within the 707 * mipi DSI spec range within the maximum divider limit 708 * We iterate here between an escape clock frequencey 709 * between 20 Mhz to 5 Mhz and pick up the first one 710 * that can be supported by our divider 711 */ 712 713 byte_mhz = msm_host->byte_clk_rate / 1000000; 714 715 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 716 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 717 718 /* 719 * TODO: Ideally, we shouldn't know what sort of divider 720 * is available in mmss_cc, we're just assuming that 721 * it'll always be a 4 bit divider. Need to come up with 722 * a better way here. 723 */ 724 if (esc_div >= 1 && esc_div <= 16) 725 break; 726 } 727 728 if (esc_mhz < 5) 729 return -EINVAL; 730 731 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 732 733 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 734 msm_host->src_clk_rate); 735 736 return 0; 737 } 738 739 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 740 { 741 u32 intr; 742 unsigned long flags; 743 744 spin_lock_irqsave(&msm_host->intr_lock, flags); 745 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 746 747 if (enable) 748 intr |= mask; 749 else 750 intr &= ~mask; 751 752 DBG("intr=%x enable=%d", intr, enable); 753 754 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 755 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 756 } 757 758 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 759 { 760 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 761 return BURST_MODE; 762 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 763 return NON_BURST_SYNCH_PULSE; 764 765 return NON_BURST_SYNCH_EVENT; 766 } 767 768 static inline enum dsi_vid_dst_format 769 dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 770 { 771 switch (mipi_fmt) { 772 case MIPI_DSI_FMT_RGB101010: return VID_DST_FORMAT_RGB101010; 773 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 774 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 775 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 776 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 777 default: return VID_DST_FORMAT_RGB888; 778 } 779 } 780 781 static inline enum dsi_cmd_dst_format 782 dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 783 { 784 switch (mipi_fmt) { 785 case MIPI_DSI_FMT_RGB101010: return CMD_DST_FORMAT_RGB101010; 786 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 787 case MIPI_DSI_FMT_RGB666_PACKED: 788 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 789 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 790 default: return CMD_DST_FORMAT_RGB888; 791 } 792 } 793 794 static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) 795 { 796 dsi_write(msm_host, REG_DSI_CTRL, 0); 797 } 798 799 static bool msm_dsi_host_version_geq(struct msm_dsi_host *msm_host, 800 u32 major, u32 minor) 801 { 802 return msm_host->cfg_hnd->major > major || 803 (msm_host->cfg_hnd->major == major && 804 msm_host->cfg_hnd->minor >= minor); 805 } 806 807 bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host) 808 { 809 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 810 811 return msm_host->dsc && 812 msm_dsi_host_version_geq(msm_host, MSM_DSI_VER_MAJOR_6G, 813 MSM_DSI_6G_VER_MINOR_V2_5_0); 814 } 815 816 static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, 817 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 818 { 819 u32 flags = msm_host->mode_flags; 820 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 821 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 822 u32 data = 0, lane_ctrl = 0; 823 824 if (flags & MIPI_DSI_MODE_VIDEO) { 825 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 826 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 827 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 828 data |= DSI_VID_CFG0_HFP_POWER_STOP; 829 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 830 data |= DSI_VID_CFG0_HBP_POWER_STOP; 831 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 832 data |= DSI_VID_CFG0_HSA_POWER_STOP; 833 /* Always set low power stop mode for BLLP 834 * to let command engine send packets 835 */ 836 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 837 DSI_VID_CFG0_BLLP_POWER_STOP; 838 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 839 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 840 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 841 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 842 data |= DSI_VID_CFG0_DATABUS_WIDEN; 843 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 844 845 /* Do not swap RGB colors */ 846 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 847 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 848 } else { 849 /* Do not swap RGB colors */ 850 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 851 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 852 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 853 854 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 855 DSI_CMD_CFG1_WR_MEM_CONTINUE( 856 MIPI_DCS_WRITE_MEMORY_CONTINUE); 857 /* Always insert DCS command */ 858 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 859 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 860 861 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 862 data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); 863 864 if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) 865 data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; 866 867 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 868 data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; 869 870 dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); 871 } 872 } 873 874 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 875 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 876 DSI_CMD_DMA_CTRL_LOW_POWER); 877 878 data = 0; 879 /* Always assume dedicated TE pin */ 880 data |= DSI_TRIG_CTRL_TE; 881 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 882 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 883 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 884 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 885 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 886 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 887 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 888 889 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 890 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 891 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 892 893 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 894 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 895 phy_shared_timings->clk_pre_inc_by_2) 896 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 897 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 898 899 data = 0; 900 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 901 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 902 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 903 904 /* allow only ack-err-status to generate interrupt */ 905 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 906 907 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 908 909 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 910 911 data = DSI_CTRL_CLK_EN; 912 913 DBG("lane number=%d", msm_host->lanes); 914 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 915 916 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 917 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 918 919 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 920 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 921 922 if (msm_dsi_phy_set_continuous_clock(phy, true)) 923 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 924 925 dsi_write(msm_host, REG_DSI_LANE_CTRL, 926 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 927 } 928 929 data |= DSI_CTRL_ENABLE; 930 931 dsi_write(msm_host, REG_DSI_CTRL, data); 932 933 if (msm_host->cphy_mode) 934 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 935 } 936 937 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode) 938 { 939 struct drm_dsc_config *dsc = msm_host->dsc; 940 u32 reg, reg_ctrl, reg_ctrl2; 941 u32 slice_per_intf, total_bytes_per_intf; 942 u32 pkt_per_line; 943 u32 eol_byte_num; 944 u32 bytes_per_pkt; 945 946 /* first calculate dsc parameters and then program 947 * compress mode registers 948 */ 949 slice_per_intf = dsc->slice_count; 950 951 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 952 bytes_per_pkt = dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt; 953 954 eol_byte_num = total_bytes_per_intf % 3; 955 pkt_per_line = slice_per_intf / msm_host->dsc_slice_per_pkt; 956 957 if (is_cmd_mode) /* packet data type */ 958 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 959 else 960 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 961 962 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 963 * registers have similar offsets, so for below common code use 964 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 965 * 966 * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) 967 */ 968 if (pkt_per_line > 4) 969 drm_warn_once(msm_host->dev, "pkt_per_line too big"); 970 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 971 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 972 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 973 974 if (is_cmd_mode) { 975 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 976 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 977 978 reg_ctrl &= ~0xffff; 979 reg_ctrl |= reg; 980 981 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 982 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 983 984 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 985 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 986 } else { 987 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); 988 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 989 } 990 } 991 992 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 993 { 994 struct drm_display_mode *mode = msm_host->mode; 995 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 996 u32 h_total = mode->htotal; 997 u32 v_total = mode->vtotal; 998 u32 hs_end = mode->hsync_end - mode->hsync_start; 999 u32 vs_end = mode->vsync_end - mode->vsync_start; 1000 u32 ha_start = h_total - mode->hsync_start; 1001 u32 ha_end = ha_start + mode->hdisplay; 1002 u32 va_start = v_total - mode->vsync_start; 1003 u32 va_end = va_start + mode->vdisplay; 1004 u32 hdisplay = mode->hdisplay; 1005 u32 wc; 1006 int ret; 1007 bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base); 1008 1009 DBG(""); 1010 1011 /* 1012 * For bonded DSI mode, the current DRM mode has 1013 * the complete width of the panel. Since, the complete 1014 * panel is driven by two DSI controllers, the horizontal 1015 * timings have to be split between the two dsi controllers. 1016 * Adjust the DSI host timing values accordingly. 1017 */ 1018 if (is_bonded_dsi) { 1019 h_total /= 2; 1020 hs_end /= 2; 1021 ha_start /= 2; 1022 ha_end /= 2; 1023 hdisplay /= 2; 1024 } 1025 1026 if (msm_host->dsc) { 1027 struct drm_dsc_config *dsc = msm_host->dsc; 1028 u32 bits_per_pclk; 1029 1030 /* update dsc params with timing params */ 1031 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 1032 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 1033 mode->hdisplay, mode->vdisplay); 1034 return; 1035 } 1036 1037 dsc->pic_width = mode->hdisplay; 1038 dsc->pic_height = mode->vdisplay; 1039 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 1040 1041 /* we do the calculations for dsc parameters here so that 1042 * panel can use these parameters 1043 */ 1044 ret = dsi_populate_dsc_params(msm_host, dsc); 1045 if (ret) 1046 return; 1047 1048 /* 1049 * DPU sends 3 bytes per pclk cycle to DSI. If widebus is 1050 * enabled, MDP always sends out 48-bit compressed data per 1051 * pclk and on average, for video mode, DSI consumes only an 1052 * amount of compressed data equivalent to the uncompressed 1053 * pixel depth per pclk. 1054 * 1055 * Calculate the number of pclks needed to transmit one line of 1056 * the compressed data. 1057 1058 * The back/font porch and pulse width are kept intact. For 1059 * VIDEO mode they represent timing parameters rather than 1060 * actual data transfer, see the documentation for 1061 * dsi_adjust_pclk_for_compression(). For CMD mode they are 1062 * unused anyway. 1063 */ 1064 h_total -= hdisplay; 1065 if (wide_bus_enabled) { 1066 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) 1067 bits_per_pclk = dsc->bits_per_component * 3; 1068 else 1069 bits_per_pclk = 48; 1070 } else { 1071 bits_per_pclk = 24; 1072 } 1073 1074 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc) * 8, bits_per_pclk); 1075 1076 h_total += hdisplay; 1077 ha_end = ha_start + hdisplay; 1078 } 1079 1080 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 1081 if (msm_host->dsc) 1082 dsi_update_dsc_timing(msm_host, false); 1083 1084 dsi_write(msm_host, REG_DSI_ACTIVE_H, 1085 DSI_ACTIVE_H_START(ha_start) | 1086 DSI_ACTIVE_H_END(ha_end)); 1087 dsi_write(msm_host, REG_DSI_ACTIVE_V, 1088 DSI_ACTIVE_V_START(va_start) | 1089 DSI_ACTIVE_V_END(va_end)); 1090 dsi_write(msm_host, REG_DSI_TOTAL, 1091 DSI_TOTAL_H_TOTAL(h_total - 1) | 1092 DSI_TOTAL_V_TOTAL(v_total - 1)); 1093 1094 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 1095 DSI_ACTIVE_HSYNC_START(hs_start) | 1096 DSI_ACTIVE_HSYNC_END(hs_end)); 1097 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 1098 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 1099 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1100 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1101 } else { /* command mode */ 1102 if (msm_host->dsc) 1103 dsi_update_dsc_timing(msm_host, true); 1104 1105 /* image data and 1 byte write_memory_start cmd */ 1106 if (!msm_host->dsc) 1107 wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; 1108 else 1109 /* 1110 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. 1111 */ 1112 wc = msm_host->dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt + 1; 1113 1114 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1115 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1116 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1117 msm_host->channel) | 1118 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1119 MIPI_DSI_DCS_LONG_WRITE)); 1120 1121 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1122 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1123 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1124 } 1125 } 1126 1127 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1128 { 1129 u32 ctrl; 1130 1131 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1132 1133 if (ctrl & DSI_CTRL_ENABLE) { 1134 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1135 /* 1136 * dsi controller need to be disabled before 1137 * clocks turned on 1138 */ 1139 wmb(); 1140 } 1141 1142 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1143 wmb(); /* clocks need to be enabled before reset */ 1144 1145 /* dsi controller can only be reset while clocks are running */ 1146 dsi_write(msm_host, REG_DSI_RESET, 1); 1147 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1148 dsi_write(msm_host, REG_DSI_RESET, 0); 1149 wmb(); /* controller out of reset */ 1150 1151 if (ctrl & DSI_CTRL_ENABLE) { 1152 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1153 wmb(); /* make sure dsi controller enabled again */ 1154 } 1155 } 1156 1157 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1158 bool video_mode, bool enable) 1159 { 1160 u32 dsi_ctrl; 1161 1162 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1163 1164 if (!enable) { 1165 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1166 DSI_CTRL_CMD_MODE_EN); 1167 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1168 DSI_IRQ_MASK_VIDEO_DONE, 0); 1169 } else { 1170 if (video_mode) { 1171 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1172 } else { /* command mode */ 1173 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1174 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1175 } 1176 dsi_ctrl |= DSI_CTRL_ENABLE; 1177 } 1178 1179 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1180 } 1181 1182 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1183 { 1184 u32 data; 1185 1186 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1187 1188 if (mode == 0) 1189 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1190 else 1191 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1192 1193 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1194 } 1195 1196 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1197 { 1198 u32 ret = 0; 1199 struct device *dev = &msm_host->pdev->dev; 1200 1201 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1202 1203 reinit_completion(&msm_host->video_comp); 1204 1205 ret = wait_for_completion_timeout(&msm_host->video_comp, 1206 msecs_to_jiffies(70)); 1207 1208 if (ret == 0) 1209 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1210 1211 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1212 } 1213 1214 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1215 { 1216 u32 data; 1217 1218 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1219 return; 1220 1221 data = dsi_read(msm_host, REG_DSI_STATUS0); 1222 1223 /* if video mode engine is not busy, its because 1224 * either timing engine was not turned on or the 1225 * DSI controller has finished transmitting the video 1226 * data already, so no need to wait in those cases 1227 */ 1228 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1229 return; 1230 1231 if (msm_host->power_on && msm_host->enabled) { 1232 dsi_wait4video_done(msm_host); 1233 /* delay 4 ms to skip BLLP */ 1234 usleep_range(2000, 4000); 1235 } 1236 } 1237 1238 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1239 { 1240 struct drm_device *dev = msm_host->dev; 1241 struct msm_drm_private *priv = dev->dev_private; 1242 uint64_t iova; 1243 u8 *data; 1244 1245 msm_host->vm = drm_gpuvm_get(priv->kms->vm); 1246 1247 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1248 msm_host->vm, 1249 &msm_host->tx_gem_obj, &iova); 1250 1251 if (IS_ERR(data)) { 1252 msm_host->tx_gem_obj = NULL; 1253 return PTR_ERR(data); 1254 } 1255 1256 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1257 1258 msm_host->tx_size = msm_host->tx_gem_obj->size; 1259 1260 return 0; 1261 } 1262 1263 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1264 { 1265 struct drm_device *dev = msm_host->dev; 1266 1267 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1268 &msm_host->tx_buf_paddr, GFP_KERNEL); 1269 if (!msm_host->tx_buf) 1270 return -ENOMEM; 1271 1272 msm_host->tx_size = size; 1273 1274 return 0; 1275 } 1276 1277 void msm_dsi_tx_buf_free(struct mipi_dsi_host *host) 1278 { 1279 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1280 struct drm_device *dev = msm_host->dev; 1281 1282 /* 1283 * This is possible if we're tearing down before we've had a chance to 1284 * fully initialize. A very real possibility if our probe is deferred, 1285 * in which case we'll hit msm_dsi_host_destroy() without having run 1286 * through the dsi_tx_buf_alloc(). 1287 */ 1288 if (!dev) 1289 return; 1290 1291 if (msm_host->tx_gem_obj) { 1292 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->vm); 1293 drm_gpuvm_put(msm_host->vm); 1294 msm_host->tx_gem_obj = NULL; 1295 msm_host->vm = NULL; 1296 } 1297 1298 if (msm_host->tx_buf) 1299 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1300 msm_host->tx_buf_paddr); 1301 } 1302 1303 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1304 { 1305 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1306 } 1307 1308 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1309 { 1310 return msm_host->tx_buf; 1311 } 1312 1313 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1314 { 1315 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1316 } 1317 1318 /* 1319 * prepare cmd buffer to be txed 1320 */ 1321 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1322 const struct mipi_dsi_msg *msg) 1323 { 1324 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1325 struct mipi_dsi_packet packet; 1326 int len; 1327 int ret; 1328 u8 *data; 1329 1330 ret = mipi_dsi_create_packet(&packet, msg); 1331 if (ret) { 1332 pr_err("%s: create packet failed, %d\n", __func__, ret); 1333 return ret; 1334 } 1335 len = (packet.size + 3) & (~0x3); 1336 1337 if (len > msm_host->tx_size) { 1338 pr_err("%s: packet size is too big\n", __func__); 1339 return -EINVAL; 1340 } 1341 1342 data = cfg_hnd->ops->tx_buf_get(msm_host); 1343 if (IS_ERR(data)) { 1344 ret = PTR_ERR(data); 1345 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1346 return ret; 1347 } 1348 1349 /* MSM specific command format in memory */ 1350 data[0] = packet.header[1]; 1351 data[1] = packet.header[2]; 1352 data[2] = packet.header[0]; 1353 data[3] = BIT(7); /* Last packet */ 1354 if (mipi_dsi_packet_format_is_long(msg->type)) 1355 data[3] |= BIT(6); 1356 if (msg->rx_buf && msg->rx_len) 1357 data[3] |= BIT(5); 1358 1359 /* Long packet */ 1360 if (packet.payload && packet.payload_length) 1361 memcpy(data + 4, packet.payload, packet.payload_length); 1362 1363 /* Append 0xff to the end */ 1364 if (packet.size < len) 1365 memset(data + packet.size, 0xff, len - packet.size); 1366 1367 if (cfg_hnd->ops->tx_buf_put) 1368 cfg_hnd->ops->tx_buf_put(msm_host); 1369 1370 return len; 1371 } 1372 1373 /* 1374 * dsi_short_read1_resp: 1 parameter 1375 */ 1376 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1377 { 1378 u8 *data = msg->rx_buf; 1379 1380 if (data && (msg->rx_len >= 1)) { 1381 *data = buf[1]; /* strip out dcs type */ 1382 return 1; 1383 } 1384 1385 pr_err("%s: read data does not match with rx_buf len %zu\n", 1386 __func__, msg->rx_len); 1387 return -EINVAL; 1388 } 1389 1390 /* 1391 * dsi_short_read2_resp: 2 parameter 1392 */ 1393 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1394 { 1395 u8 *data = msg->rx_buf; 1396 1397 if (data && (msg->rx_len >= 2)) { 1398 data[0] = buf[1]; /* strip out dcs type */ 1399 data[1] = buf[2]; 1400 return 2; 1401 } 1402 1403 pr_err("%s: read data does not match with rx_buf len %zu\n", 1404 __func__, msg->rx_len); 1405 return -EINVAL; 1406 } 1407 1408 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1409 { 1410 /* strip out 4 byte dcs header */ 1411 if (msg->rx_buf && msg->rx_len) 1412 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1413 1414 return msg->rx_len; 1415 } 1416 1417 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1418 { 1419 struct drm_device *dev = msm_host->dev; 1420 struct msm_drm_private *priv = dev->dev_private; 1421 1422 if (!dma_base) 1423 return -EINVAL; 1424 1425 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1426 priv->kms->vm, dma_base); 1427 } 1428 1429 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1430 { 1431 if (!dma_base) 1432 return -EINVAL; 1433 1434 *dma_base = msm_host->tx_buf_paddr; 1435 return 0; 1436 } 1437 1438 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1439 { 1440 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1441 int ret; 1442 uint64_t dma_base; 1443 bool triggered; 1444 1445 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1446 if (ret) { 1447 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1448 return ret; 1449 } 1450 1451 reinit_completion(&msm_host->dma_comp); 1452 1453 dsi_wait4video_eng_busy(msm_host); 1454 1455 triggered = msm_dsi_manager_cmd_xfer_trigger( 1456 msm_host->id, dma_base, len); 1457 if (triggered) { 1458 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1459 msecs_to_jiffies(200)); 1460 DBG("ret=%d", ret); 1461 if (ret == 0) 1462 ret = -ETIMEDOUT; 1463 else 1464 ret = len; 1465 } else { 1466 ret = len; 1467 } 1468 1469 return ret; 1470 } 1471 1472 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1473 u8 *buf, int rx_byte, int pkt_size) 1474 { 1475 u32 *temp, data; 1476 int i, j = 0, cnt; 1477 u32 read_cnt; 1478 u8 reg[16]; 1479 int repeated_bytes = 0; 1480 int buf_offset = buf - msm_host->rx_buf; 1481 1482 temp = (u32 *)reg; 1483 cnt = (rx_byte + 3) >> 2; 1484 if (cnt > 4) 1485 cnt = 4; /* 4 x 32 bits registers only */ 1486 1487 if (rx_byte == 4) 1488 read_cnt = 4; 1489 else 1490 read_cnt = pkt_size + 6; 1491 1492 /* 1493 * In case of multiple reads from the panel, after the first read, there 1494 * is possibility that there are some bytes in the payload repeating in 1495 * the RDBK_DATA registers. Since we read all the parameters from the 1496 * panel right from the first byte for every pass. We need to skip the 1497 * repeating bytes and then append the new parameters to the rx buffer. 1498 */ 1499 if (read_cnt > 16) { 1500 int bytes_shifted; 1501 /* Any data more than 16 bytes will be shifted out. 1502 * The temp read buffer should already contain these bytes. 1503 * The remaining bytes in read buffer are the repeated bytes. 1504 */ 1505 bytes_shifted = read_cnt - 16; 1506 repeated_bytes = buf_offset - bytes_shifted; 1507 } 1508 1509 for (i = cnt - 1; i >= 0; i--) { 1510 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1511 *temp++ = ntohl(data); /* to host byte order */ 1512 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1513 } 1514 1515 for (i = repeated_bytes; i < 16; i++) 1516 buf[j++] = reg[i]; 1517 1518 return j; 1519 } 1520 1521 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1522 const struct mipi_dsi_msg *msg) 1523 { 1524 int len, ret; 1525 int bllp_len = msm_host->mode->hdisplay * 1526 mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; 1527 1528 len = dsi_cmd_dma_add(msm_host, msg); 1529 if (len < 0) { 1530 pr_err("%s: failed to add cmd type = 0x%x\n", 1531 __func__, msg->type); 1532 return len; 1533 } 1534 1535 /* 1536 * for video mode, do not send cmds more than 1537 * one pixel line, since it only transmit it 1538 * during BLLP. 1539 * 1540 * TODO: if the command is sent in LP mode, the bit rate is only 1541 * half of esc clk rate. In this case, if the video is already 1542 * actively streaming, we need to check more carefully if the 1543 * command can be fit into one BLLP. 1544 */ 1545 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1546 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1547 __func__, len); 1548 return -EINVAL; 1549 } 1550 1551 ret = dsi_cmd_dma_tx(msm_host, len); 1552 if (ret < 0) { 1553 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1554 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1555 return ret; 1556 } else if (ret < len) { 1557 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1558 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1559 return -EIO; 1560 } 1561 1562 return len; 1563 } 1564 1565 static void dsi_err_worker(struct work_struct *work) 1566 { 1567 struct msm_dsi_host *msm_host = 1568 container_of(work, struct msm_dsi_host, err_work); 1569 u32 status = msm_host->err_work_state; 1570 1571 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1572 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1573 dsi_sw_reset(msm_host); 1574 1575 /* It is safe to clear here because error irq is disabled. */ 1576 msm_host->err_work_state = 0; 1577 1578 /* enable dsi error interrupt */ 1579 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1580 } 1581 1582 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1583 { 1584 u32 status; 1585 1586 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1587 1588 if (status) { 1589 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1590 /* Writing of an extra 0 needed to clear error bits */ 1591 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1592 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1593 } 1594 } 1595 1596 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1597 { 1598 u32 status; 1599 1600 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1601 1602 if (status) { 1603 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1604 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1605 } 1606 } 1607 1608 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1609 { 1610 u32 status; 1611 1612 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1613 1614 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1615 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1616 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1617 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1618 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1619 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1620 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1621 } 1622 } 1623 1624 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1625 { 1626 u32 status; 1627 1628 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1629 1630 /* fifo underflow, overflow */ 1631 if (status) { 1632 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1633 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1634 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1635 msm_host->err_work_state |= 1636 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1637 } 1638 } 1639 1640 static void dsi_status(struct msm_dsi_host *msm_host) 1641 { 1642 u32 status; 1643 1644 status = dsi_read(msm_host, REG_DSI_STATUS0); 1645 1646 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1647 dsi_write(msm_host, REG_DSI_STATUS0, status); 1648 msm_host->err_work_state |= 1649 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1650 } 1651 } 1652 1653 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1654 { 1655 u32 status; 1656 1657 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1658 1659 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1660 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1661 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1662 } 1663 } 1664 1665 static void dsi_error(struct msm_dsi_host *msm_host) 1666 { 1667 /* disable dsi error interrupt */ 1668 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1669 1670 dsi_clk_status(msm_host); 1671 dsi_fifo_status(msm_host); 1672 dsi_ack_err_status(msm_host); 1673 dsi_timeout_status(msm_host); 1674 dsi_status(msm_host); 1675 dsi_dln0_phy_err(msm_host); 1676 1677 queue_work(msm_host->workqueue, &msm_host->err_work); 1678 } 1679 1680 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1681 { 1682 struct msm_dsi_host *msm_host = ptr; 1683 u32 isr; 1684 unsigned long flags; 1685 1686 if (!msm_host->ctrl_base) 1687 return IRQ_HANDLED; 1688 1689 spin_lock_irqsave(&msm_host->intr_lock, flags); 1690 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1691 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1692 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1693 1694 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1695 1696 if (isr & DSI_IRQ_ERROR) 1697 dsi_error(msm_host); 1698 1699 if (isr & DSI_IRQ_VIDEO_DONE) 1700 complete(&msm_host->video_comp); 1701 1702 if (isr & DSI_IRQ_CMD_DMA_DONE) 1703 complete(&msm_host->dma_comp); 1704 1705 return IRQ_HANDLED; 1706 } 1707 1708 static int dsi_host_attach(struct mipi_dsi_host *host, 1709 struct mipi_dsi_device *dsi) 1710 { 1711 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1712 int ret; 1713 1714 if (dsi->lanes > msm_host->num_data_lanes) 1715 return -EINVAL; 1716 1717 msm_host->channel = dsi->channel; 1718 msm_host->lanes = dsi->lanes; 1719 msm_host->format = dsi->format; 1720 msm_host->mode_flags = dsi->mode_flags; 1721 if (dsi->dsc) { 1722 msm_host->dsc = dsi->dsc; 1723 if (dsi->mode_flags & MIPI_DSI_MODE_DSC_ALL_SLICES_IN_PKT) 1724 msm_host->dsc_slice_per_pkt = dsi->dsc->slice_count; 1725 else 1726 msm_host->dsc_slice_per_pkt = 1; 1727 } 1728 1729 if (msm_host->format == MIPI_DSI_FMT_RGB101010) { 1730 if (!msm_dsi_host_version_geq(msm_host, MSM_DSI_VER_MAJOR_6G, 1731 MSM_DSI_6G_VER_MINOR_V2_1_0)) { 1732 DRM_DEV_ERROR(&msm_host->pdev->dev, 1733 "RGB101010 not supported on this DSI controller\n"); 1734 return -EINVAL; 1735 } 1736 1737 /* 1738 * Downstream overrides RGB101010 back to RGB888 when DSC is enabled 1739 * but widebus is not. Using RGB101010 in this case may require some 1740 * extra changes. 1741 */ 1742 if (msm_host->dsc && 1743 !msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) { 1744 dev_warn(&msm_host->pdev->dev, 1745 "RGB101010 with DSC but without widebus, may need extra changes\n"); 1746 } 1747 } 1748 1749 ret = dsi_dev_attach(msm_host->pdev); 1750 if (ret) 1751 return ret; 1752 1753 DBG("id=%d", msm_host->id); 1754 1755 return 0; 1756 } 1757 1758 static int dsi_host_detach(struct mipi_dsi_host *host, 1759 struct mipi_dsi_device *dsi) 1760 { 1761 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1762 1763 dsi_dev_detach(msm_host->pdev); 1764 1765 DBG("id=%d", msm_host->id); 1766 1767 return 0; 1768 } 1769 1770 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1771 const struct mipi_dsi_msg *msg) 1772 { 1773 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1774 int ret; 1775 1776 if (!msg || !msm_host->power_on) 1777 return -EINVAL; 1778 1779 mutex_lock(&msm_host->cmd_mutex); 1780 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1781 mutex_unlock(&msm_host->cmd_mutex); 1782 1783 return ret; 1784 } 1785 1786 static const struct mipi_dsi_host_ops dsi_host_ops = { 1787 .attach = dsi_host_attach, 1788 .detach = dsi_host_detach, 1789 .transfer = dsi_host_transfer, 1790 }; 1791 1792 /* 1793 * List of supported physical to logical lane mappings. 1794 * For example, the 2nd entry represents the following mapping: 1795 * 1796 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1797 */ 1798 static const int supported_data_lane_swaps[][4] = { 1799 { 0, 1, 2, 3 }, 1800 { 3, 0, 1, 2 }, 1801 { 2, 3, 0, 1 }, 1802 { 1, 2, 3, 0 }, 1803 { 0, 3, 2, 1 }, 1804 { 1, 0, 3, 2 }, 1805 { 2, 1, 0, 3 }, 1806 { 3, 2, 1, 0 }, 1807 }; 1808 1809 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1810 struct device_node *ep) 1811 { 1812 struct device *dev = &msm_host->pdev->dev; 1813 struct property *prop; 1814 u32 lane_map[4]; 1815 int ret, i, len, num_lanes; 1816 1817 prop = of_find_property(ep, "data-lanes", &len); 1818 if (!prop) { 1819 DRM_DEV_DEBUG(dev, 1820 "failed to find data lane mapping, using default\n"); 1821 /* Set the number of date lanes to 4 by default. */ 1822 msm_host->num_data_lanes = 4; 1823 return 0; 1824 } 1825 1826 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1827 if (num_lanes < 0) { 1828 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1829 return num_lanes; 1830 } 1831 1832 msm_host->num_data_lanes = num_lanes; 1833 1834 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1835 num_lanes); 1836 if (ret) { 1837 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1838 return ret; 1839 } 1840 1841 /* 1842 * compare DT specified physical-logical lane mappings with the ones 1843 * supported by hardware 1844 */ 1845 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1846 const int *swap = supported_data_lane_swaps[i]; 1847 int j; 1848 1849 /* 1850 * the data-lanes array we get from DT has a logical->physical 1851 * mapping. The "data lane swap" register field represents 1852 * supported configurations in a physical->logical mapping. 1853 * Translate the DT mapping to what we understand and find a 1854 * configuration that works. 1855 */ 1856 for (j = 0; j < num_lanes; j++) { 1857 if (lane_map[j] < 0 || lane_map[j] > 3) 1858 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1859 lane_map[j]); 1860 1861 if (swap[lane_map[j]] != j) 1862 break; 1863 } 1864 1865 if (j == num_lanes) { 1866 msm_host->dlane_swap = i; 1867 return 0; 1868 } 1869 } 1870 1871 return -EINVAL; 1872 } 1873 1874 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1875 { 1876 int ret; 1877 1878 if (dsc->bits_per_pixel & 0xf) { 1879 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1880 return -EINVAL; 1881 } 1882 1883 switch (dsc->bits_per_component) { 1884 case 8: 1885 case 10: 1886 case 12: 1887 /* 1888 * Only 8, 10, and 12 bpc are supported for DSC 1.1 block. 1889 * If additional bpc values need to be supported, update 1890 * this quard with the appropriate DSC version verification. 1891 */ 1892 break; 1893 default: 1894 DRM_DEV_ERROR(&msm_host->pdev->dev, 1895 "Unsupported bits_per_component value: %d\n", 1896 dsc->bits_per_component); 1897 return -EOPNOTSUPP; 1898 } 1899 1900 dsc->simple_422 = 0; 1901 dsc->convert_rgb = 1; 1902 dsc->vbr_enable = 0; 1903 1904 drm_dsc_set_const_params(dsc); 1905 drm_dsc_set_rc_buf_thresh(dsc); 1906 1907 /* DPU supports only pre-SCR panels */ 1908 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); 1909 if (ret) { 1910 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); 1911 return ret; 1912 } 1913 1914 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); 1915 dsc->line_buf_depth = dsc->bits_per_component + 1; 1916 1917 return drm_dsc_compute_rc_parameters(dsc); 1918 } 1919 1920 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1921 { 1922 struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev); 1923 struct device *dev = &msm_host->pdev->dev; 1924 struct device_node *np = dev->of_node; 1925 struct device_node *endpoint; 1926 const char *te_source; 1927 int ret = 0; 1928 1929 /* 1930 * Get the endpoint of the output port of the DSI host. In our case, 1931 * this is mapped to port number with reg = 1. Don't return an error if 1932 * the remote endpoint isn't defined. It's possible that there is 1933 * nothing connected to the dsi output. 1934 */ 1935 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1936 if (!endpoint) { 1937 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1938 return 0; 1939 } 1940 1941 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1942 if (ret) { 1943 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1944 __func__, ret); 1945 ret = -EINVAL; 1946 goto err; 1947 } 1948 1949 ret = of_property_read_string(endpoint, "qcom,te-source", &te_source); 1950 if (ret && ret != -EINVAL) { 1951 DRM_DEV_ERROR(dev, "%s: invalid TE source configuration %d\n", 1952 __func__, ret); 1953 goto err; 1954 } 1955 if (!ret) { 1956 msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL); 1957 if (!msm_dsi->te_source) { 1958 DRM_DEV_ERROR(dev, "%s: failed to allocate te_source\n", 1959 __func__); 1960 ret = -ENOMEM; 1961 goto err; 1962 } 1963 } 1964 ret = 0; 1965 1966 if (of_property_present(np, "syscon-sfpb")) { 1967 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1968 "syscon-sfpb"); 1969 if (IS_ERR(msm_host->sfpb)) { 1970 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1971 __func__); 1972 ret = PTR_ERR(msm_host->sfpb); 1973 } 1974 } 1975 1976 err: 1977 of_node_put(endpoint); 1978 1979 return ret; 1980 } 1981 1982 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1983 { 1984 struct platform_device *pdev = msm_host->pdev; 1985 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1986 struct resource *res; 1987 int i, j; 1988 1989 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1990 if (!res) 1991 return -EINVAL; 1992 1993 for (i = 0; i < VARIANTS_MAX; i++) 1994 for (j = 0; j < DSI_MAX; j++) 1995 if (cfg->io_start[i][j] == res->start) 1996 return j; 1997 1998 return -EINVAL; 1999 } 2000 2001 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 2002 { 2003 struct msm_dsi_host *msm_host = NULL; 2004 struct platform_device *pdev = msm_dsi->pdev; 2005 const struct msm_dsi_config *cfg; 2006 int ret; 2007 2008 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 2009 if (!msm_host) 2010 return -ENOMEM; 2011 2012 msm_host->pdev = pdev; 2013 msm_dsi->host = &msm_host->base; 2014 2015 ret = dsi_host_parse_dt(msm_host); 2016 if (ret) 2017 return dev_err_probe(&pdev->dev, ret, "%s: failed to parse dt\n", 2018 __func__); 2019 2020 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 2021 if (IS_ERR(msm_host->ctrl_base)) 2022 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->ctrl_base), 2023 "%s: unable to map Dsi ctrl base\n", __func__); 2024 2025 pm_runtime_enable(&pdev->dev); 2026 2027 msm_host->cfg_hnd = dsi_get_config(msm_host); 2028 if (!msm_host->cfg_hnd) 2029 return dev_err_probe(&pdev->dev, -EINVAL, 2030 "%s: get config failed\n", __func__); 2031 cfg = msm_host->cfg_hnd->cfg; 2032 2033 msm_host->id = dsi_host_get_id(msm_host); 2034 if (msm_host->id < 0) 2035 return dev_err_probe(&pdev->dev, msm_host->id, 2036 "%s: unable to identify DSI host index\n", 2037 __func__); 2038 2039 /* fixup base address by io offset */ 2040 msm_host->ctrl_base += cfg->io_offset; 2041 msm_host->ctrl_size -= cfg->io_offset; 2042 2043 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 2044 cfg->regulator_data, 2045 &msm_host->supplies); 2046 if (ret) 2047 return ret; 2048 2049 ret = dsi_clk_init(msm_host); 2050 if (ret) 2051 return dev_err_probe(&pdev->dev, ret, "%s: unable to initialize dsi clks\n", __func__); 2052 2053 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 2054 if (!msm_host->rx_buf) 2055 return -ENOMEM; 2056 2057 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 2058 if (ret) 2059 return ret; 2060 /* OPP table is optional */ 2061 ret = devm_pm_opp_of_add_table(&pdev->dev); 2062 if (ret && ret != -ENODEV) 2063 return dev_err_probe(&pdev->dev, ret, "invalid OPP table in device tree\n"); 2064 2065 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 2066 if (!msm_host->irq) 2067 return dev_err_probe(&pdev->dev, -EINVAL, "failed to get irq\n"); 2068 2069 /* do not autoenable, will be enabled later */ 2070 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 2071 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 2072 "dsi_isr", msm_host); 2073 if (ret < 0) 2074 return dev_err_probe(&pdev->dev, ret, "failed to request IRQ%u\n", 2075 msm_host->irq); 2076 2077 init_completion(&msm_host->dma_comp); 2078 init_completion(&msm_host->video_comp); 2079 mutex_init(&msm_host->dev_mutex); 2080 mutex_init(&msm_host->cmd_mutex); 2081 spin_lock_init(&msm_host->intr_lock); 2082 2083 /* setup workqueue */ 2084 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 2085 if (!msm_host->workqueue) 2086 return -ENOMEM; 2087 2088 INIT_WORK(&msm_host->err_work, dsi_err_worker); 2089 2090 msm_dsi->id = msm_host->id; 2091 2092 DBG("Dsi Host %d initialized", msm_host->id); 2093 return 0; 2094 } 2095 2096 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 2097 { 2098 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2099 2100 DBG(""); 2101 if (msm_host->workqueue) { 2102 destroy_workqueue(msm_host->workqueue); 2103 msm_host->workqueue = NULL; 2104 } 2105 2106 mutex_destroy(&msm_host->cmd_mutex); 2107 mutex_destroy(&msm_host->dev_mutex); 2108 2109 pm_runtime_disable(&msm_host->pdev->dev); 2110 } 2111 2112 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 2113 struct drm_device *dev) 2114 { 2115 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2116 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2117 int ret; 2118 2119 msm_host->dev = dev; 2120 2121 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2122 if (ret) { 2123 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2124 return ret; 2125 } 2126 2127 return 0; 2128 } 2129 2130 int msm_dsi_host_register(struct mipi_dsi_host *host) 2131 { 2132 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2133 int ret; 2134 2135 /* Register mipi dsi host */ 2136 if (!msm_host->registered) { 2137 host->dev = &msm_host->pdev->dev; 2138 host->ops = &dsi_host_ops; 2139 ret = mipi_dsi_host_register(host); 2140 if (ret) 2141 return ret; 2142 2143 msm_host->registered = true; 2144 } 2145 2146 return 0; 2147 } 2148 2149 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2150 { 2151 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2152 2153 if (msm_host->registered) { 2154 mipi_dsi_host_unregister(host); 2155 host->dev = NULL; 2156 host->ops = NULL; 2157 msm_host->registered = false; 2158 } 2159 } 2160 2161 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2162 const struct mipi_dsi_msg *msg) 2163 { 2164 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2165 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2166 2167 /* TODO: make sure dsi_cmd_mdp is idle. 2168 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2169 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2170 * How to handle the old versions? Wait for mdp cmd done? 2171 */ 2172 2173 /* 2174 * mdss interrupt is generated in mdp core clock domain 2175 * mdp clock need to be enabled to receive dsi interrupt 2176 */ 2177 pm_runtime_get_sync(&msm_host->pdev->dev); 2178 cfg_hnd->ops->link_clk_set_rate(msm_host); 2179 cfg_hnd->ops->link_clk_enable(msm_host); 2180 2181 /* TODO: vote for bus bandwidth */ 2182 2183 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2184 dsi_set_tx_power_mode(0, msm_host); 2185 2186 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2187 dsi_write(msm_host, REG_DSI_CTRL, 2188 msm_host->dma_cmd_ctrl_restore | 2189 DSI_CTRL_CMD_MODE_EN | 2190 DSI_CTRL_ENABLE); 2191 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2192 2193 return 0; 2194 } 2195 2196 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2197 const struct mipi_dsi_msg *msg) 2198 { 2199 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2200 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2201 2202 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2203 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2204 2205 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2206 dsi_set_tx_power_mode(1, msm_host); 2207 2208 /* TODO: unvote for bus bandwidth */ 2209 2210 cfg_hnd->ops->link_clk_disable(msm_host); 2211 pm_runtime_put(&msm_host->pdev->dev); 2212 } 2213 2214 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2215 const struct mipi_dsi_msg *msg) 2216 { 2217 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2218 2219 return dsi_cmds2buf_tx(msm_host, msg); 2220 } 2221 2222 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2223 const struct mipi_dsi_msg *msg) 2224 { 2225 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2226 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2227 int data_byte, rx_byte, dlen, end; 2228 int short_response, diff, pkt_size, ret = 0; 2229 char cmd; 2230 int rlen = msg->rx_len; 2231 u8 *buf; 2232 2233 if (rlen <= 2) { 2234 short_response = 1; 2235 pkt_size = rlen; 2236 rx_byte = 4; 2237 } else { 2238 short_response = 0; 2239 data_byte = 10; /* first read */ 2240 if (rlen < data_byte) 2241 pkt_size = rlen; 2242 else 2243 pkt_size = data_byte; 2244 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2245 } 2246 2247 buf = msm_host->rx_buf; 2248 end = 0; 2249 while (!end) { 2250 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2251 struct mipi_dsi_msg max_pkt_size_msg = { 2252 .channel = msg->channel, 2253 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2254 .tx_len = 2, 2255 .tx_buf = tx, 2256 }; 2257 2258 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2259 rlen, pkt_size, rx_byte); 2260 2261 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2262 if (ret < 2) { 2263 pr_err("%s: Set max pkt size failed, %d\n", 2264 __func__, ret); 2265 return -EINVAL; 2266 } 2267 2268 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2269 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2270 /* Clear the RDBK_DATA registers */ 2271 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2272 DSI_RDBK_DATA_CTRL_CLR); 2273 wmb(); /* make sure the RDBK registers are cleared */ 2274 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2275 wmb(); /* release cleared status before transfer */ 2276 } 2277 2278 ret = dsi_cmds2buf_tx(msm_host, msg); 2279 if (ret < 0) { 2280 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2281 return ret; 2282 } else if (ret < msg->tx_len) { 2283 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2284 return -ECOMM; 2285 } 2286 2287 /* 2288 * once cmd_dma_done interrupt received, 2289 * return data from client is ready and stored 2290 * at RDBK_DATA register already 2291 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2292 * after that dcs header lost during shift into registers 2293 */ 2294 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2295 2296 if (dlen <= 0) 2297 return 0; 2298 2299 if (short_response) 2300 break; 2301 2302 if (rlen <= data_byte) { 2303 diff = data_byte - rlen; 2304 end = 1; 2305 } else { 2306 diff = 0; 2307 rlen -= data_byte; 2308 } 2309 2310 if (!end) { 2311 dlen -= 2; /* 2 crc */ 2312 dlen -= diff; 2313 buf += dlen; /* next start position */ 2314 data_byte = 14; /* NOT first read */ 2315 if (rlen < data_byte) 2316 pkt_size += rlen; 2317 else 2318 pkt_size += data_byte; 2319 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2320 } 2321 } 2322 2323 /* 2324 * For single Long read, if the requested rlen < 10, 2325 * we need to shift the start position of rx 2326 * data buffer to skip the bytes which are not 2327 * updated. 2328 */ 2329 if (pkt_size < 10 && !short_response) 2330 buf = msm_host->rx_buf + (10 - rlen); 2331 else 2332 buf = msm_host->rx_buf; 2333 2334 cmd = buf[0]; 2335 switch (cmd) { 2336 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2337 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2338 ret = 0; 2339 break; 2340 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2341 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2342 ret = dsi_short_read1_resp(buf, msg); 2343 break; 2344 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2345 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2346 ret = dsi_short_read2_resp(buf, msg); 2347 break; 2348 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2349 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2350 ret = dsi_long_read_resp(buf, msg); 2351 break; 2352 default: 2353 pr_warn("%s:Invalid response cmd\n", __func__); 2354 ret = 0; 2355 } 2356 2357 return ret; 2358 } 2359 2360 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2361 u32 len) 2362 { 2363 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2364 2365 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2366 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2367 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2368 2369 /* Make sure trigger happens */ 2370 wmb(); 2371 } 2372 2373 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2374 struct msm_dsi_phy *src_phy) 2375 { 2376 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2377 2378 msm_host->cphy_mode = src_phy->cphy_mode; 2379 } 2380 2381 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2382 { 2383 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2384 2385 DBG(""); 2386 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2387 /* Make sure fully reset */ 2388 wmb(); 2389 udelay(1000); 2390 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2391 udelay(100); 2392 } 2393 2394 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2395 struct msm_dsi_phy_clk_request *clk_req, 2396 bool is_bonded_dsi) 2397 { 2398 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2399 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2400 int ret; 2401 2402 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2403 if (ret) { 2404 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2405 return; 2406 } 2407 2408 /* CPHY transmits 16 bits over 7 clock cycles 2409 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2410 * so multiply by 7 to get the "bitclk rate" 2411 */ 2412 if (msm_host->cphy_mode) 2413 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2414 else 2415 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2416 clk_req->escclk_rate = msm_host->esc_clk_rate; 2417 } 2418 2419 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2420 { 2421 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2422 2423 enable_irq(msm_host->irq); 2424 } 2425 2426 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2427 { 2428 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2429 2430 disable_irq(msm_host->irq); 2431 } 2432 2433 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2434 { 2435 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2436 2437 dsi_op_mode_config(msm_host, 2438 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2439 2440 /* TODO: clock should be turned off for command mode, 2441 * and only turned on before MDP START. 2442 * This part of code should be enabled once mdp driver support it. 2443 */ 2444 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2445 * dsi_link_clk_disable(msm_host); 2446 * pm_runtime_put(&msm_host->pdev->dev); 2447 * } 2448 */ 2449 msm_host->enabled = true; 2450 return 0; 2451 } 2452 2453 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2454 { 2455 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2456 2457 msm_host->enabled = false; 2458 dsi_op_mode_config(msm_host, 2459 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2460 2461 /* Since we have disabled INTF, the video engine won't stop so that 2462 * the cmd engine will be blocked. 2463 * Reset to disable video engine so that we can send off cmd. 2464 */ 2465 dsi_sw_reset(msm_host); 2466 2467 return 0; 2468 } 2469 2470 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2471 { 2472 enum sfpb_ahb_arb_master_port_en en; 2473 2474 if (!msm_host->sfpb) 2475 return; 2476 2477 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2478 2479 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2480 SFPB_GPREG_MASTER_PORT_EN__MASK, 2481 SFPB_GPREG_MASTER_PORT_EN(en)); 2482 } 2483 2484 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2485 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2486 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2487 { 2488 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2489 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2490 int ret = 0; 2491 2492 mutex_lock(&msm_host->dev_mutex); 2493 if (msm_host->power_on) { 2494 DBG("dsi host already on"); 2495 goto unlock_ret; 2496 } 2497 2498 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; 2499 if (phy_shared_timings->byte_intf_clk_div_2) 2500 msm_host->byte_intf_clk_rate /= 2; 2501 2502 msm_dsi_sfpb_config(msm_host, true); 2503 2504 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2505 msm_host->supplies); 2506 if (ret) { 2507 pr_err("%s:Failed to enable vregs.ret=%d\n", 2508 __func__, ret); 2509 goto unlock_ret; 2510 } 2511 2512 pm_runtime_get_sync(&msm_host->pdev->dev); 2513 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2514 if (!ret) 2515 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2516 if (ret) { 2517 pr_err("%s: failed to enable link clocks. ret=%d\n", 2518 __func__, ret); 2519 goto fail_disable_reg; 2520 } 2521 2522 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2523 if (ret) { 2524 pr_err("%s: failed to set pinctrl default state, %d\n", 2525 __func__, ret); 2526 goto fail_disable_clk; 2527 } 2528 2529 dsi_timing_setup(msm_host, is_bonded_dsi); 2530 dsi_sw_reset(msm_host); 2531 dsi_ctrl_enable(msm_host, phy_shared_timings, phy); 2532 2533 msm_host->power_on = true; 2534 mutex_unlock(&msm_host->dev_mutex); 2535 2536 return 0; 2537 2538 fail_disable_clk: 2539 cfg_hnd->ops->link_clk_disable(msm_host); 2540 pm_runtime_put(&msm_host->pdev->dev); 2541 fail_disable_reg: 2542 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2543 msm_host->supplies); 2544 unlock_ret: 2545 mutex_unlock(&msm_host->dev_mutex); 2546 return ret; 2547 } 2548 2549 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2550 { 2551 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2552 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2553 2554 mutex_lock(&msm_host->dev_mutex); 2555 if (!msm_host->power_on) { 2556 DBG("dsi host already off"); 2557 goto unlock_ret; 2558 } 2559 2560 dsi_ctrl_disable(msm_host); 2561 2562 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2563 2564 cfg_hnd->ops->link_clk_disable(msm_host); 2565 pm_runtime_put(&msm_host->pdev->dev); 2566 2567 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2568 msm_host->supplies); 2569 2570 msm_dsi_sfpb_config(msm_host, false); 2571 2572 DBG("-"); 2573 2574 msm_host->power_on = false; 2575 2576 unlock_ret: 2577 mutex_unlock(&msm_host->dev_mutex); 2578 return 0; 2579 } 2580 2581 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2582 const struct drm_display_mode *mode) 2583 { 2584 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2585 2586 if (msm_host->mode) { 2587 drm_mode_destroy(msm_host->dev, msm_host->mode); 2588 msm_host->mode = NULL; 2589 } 2590 2591 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2592 if (!msm_host->mode) { 2593 pr_err("%s: cannot duplicate mode\n", __func__); 2594 return -ENOMEM; 2595 } 2596 2597 return 0; 2598 } 2599 2600 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2601 const struct drm_display_mode *mode) 2602 { 2603 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2604 struct drm_dsc_config *dsc = msm_host->dsc; 2605 int pic_width = mode->hdisplay; 2606 int pic_height = mode->vdisplay; 2607 2608 if (!msm_host->dsc) 2609 return MODE_OK; 2610 2611 if (pic_width % dsc->slice_width) { 2612 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2613 pic_width, dsc->slice_width); 2614 return MODE_H_ILLEGAL; 2615 } 2616 2617 if (pic_height % dsc->slice_height) { 2618 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2619 pic_height, dsc->slice_height); 2620 return MODE_V_ILLEGAL; 2621 } 2622 2623 return MODE_OK; 2624 } 2625 2626 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2627 { 2628 return to_msm_dsi_host(host)->mode_flags; 2629 } 2630 2631 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2632 { 2633 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2634 2635 pm_runtime_get_sync(&msm_host->pdev->dev); 2636 2637 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2638 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2639 2640 pm_runtime_put_sync(&msm_host->pdev->dev); 2641 } 2642 2643 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2644 { 2645 u32 reg; 2646 2647 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2648 2649 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2650 /* draw checkered rectangle pattern */ 2651 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2652 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2653 /* use 24-bit RGB test pttern */ 2654 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2655 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2656 DSI_TPG_VIDEO_CONFIG_RGB); 2657 2658 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2659 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2660 2661 DBG("Video test pattern setup done\n"); 2662 } 2663 2664 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2665 { 2666 u32 reg; 2667 2668 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2669 2670 /* initial value for test pattern */ 2671 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2672 2673 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2674 2675 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2676 /* draw checkered rectangle pattern */ 2677 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2678 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2679 2680 DBG("Cmd test pattern setup done\n"); 2681 } 2682 2683 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2684 { 2685 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2686 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2687 u32 reg; 2688 2689 if (is_video_mode) 2690 msm_dsi_host_video_test_pattern_setup(msm_host); 2691 else 2692 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2693 2694 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2695 /* enable the test pattern generator */ 2696 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2697 2698 /* for command mode need to trigger one frame from tpg */ 2699 if (!is_video_mode) 2700 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2701 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2702 } 2703 2704 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2705 { 2706 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2707 2708 return msm_host->dsc; 2709 } 2710