1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/interrupt.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/of_irq.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_opp.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spinlock.h> 21 22 #include <video/mipi_display.h> 23 24 #include "dsi.h" 25 #include "dsi.xml.h" 26 #include "sfpb.xml.h" 27 #include "dsi_cfg.h" 28 #include "msm_kms.h" 29 #include "msm_gem.h" 30 #include "phy/dsi_phy.h" 31 32 #define DSI_RESET_TOGGLE_DELAY_MS 20 33 34 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 35 { 36 u32 ver; 37 38 if (!major || !minor) 39 return -EINVAL; 40 41 /* 42 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 43 * makes all other registers 4-byte shifted down. 44 * 45 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 46 * older, we read the DSI_VERSION register without any shift(offset 47 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 48 * the case of DSI6G, this has to be zero (the offset points to a 49 * scratch register which we never touch) 50 */ 51 52 ver = msm_readl(base + REG_DSI_VERSION); 53 if (ver) { 54 /* older dsi host, there is no register shift */ 55 ver = FIELD(ver, DSI_VERSION_MAJOR); 56 if (ver <= MSM_DSI_VER_MAJOR_V2) { 57 /* old versions */ 58 *major = ver; 59 *minor = 0; 60 return 0; 61 } else { 62 return -EINVAL; 63 } 64 } else { 65 /* 66 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 67 * registers are shifted down, read DSI_VERSION again with 68 * the shifted offset 69 */ 70 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 71 ver = FIELD(ver, DSI_VERSION_MAJOR); 72 if (ver == MSM_DSI_VER_MAJOR_6G) { 73 /* 6G version */ 74 *major = ver; 75 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 76 return 0; 77 } else { 78 return -EINVAL; 79 } 80 } 81 } 82 83 #define DSI_ERR_STATE_ACK 0x0000 84 #define DSI_ERR_STATE_TIMEOUT 0x0001 85 #define DSI_ERR_STATE_DLN0_PHY 0x0002 86 #define DSI_ERR_STATE_FIFO 0x0004 87 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 88 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 89 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 90 91 #define DSI_CLK_CTRL_ENABLE_CLKS \ 92 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 93 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 94 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 95 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 96 97 struct msm_dsi_host { 98 struct mipi_dsi_host base; 99 100 struct platform_device *pdev; 101 struct drm_device *dev; 102 103 int id; 104 105 void __iomem *ctrl_base; 106 phys_addr_t ctrl_size; 107 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 108 109 int num_bus_clks; 110 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 111 112 struct clk *byte_clk; 113 struct clk *esc_clk; 114 struct clk *pixel_clk; 115 struct clk *byte_clk_src; 116 struct clk *pixel_clk_src; 117 struct clk *byte_intf_clk; 118 119 unsigned long byte_clk_rate; 120 unsigned long pixel_clk_rate; 121 unsigned long esc_clk_rate; 122 123 /* DSI v2 specific clocks */ 124 struct clk *src_clk; 125 struct clk *esc_clk_src; 126 struct clk *dsi_clk_src; 127 128 unsigned long src_clk_rate; 129 130 struct gpio_desc *disp_en_gpio; 131 struct gpio_desc *te_gpio; 132 133 const struct msm_dsi_cfg_handler *cfg_hnd; 134 135 struct completion dma_comp; 136 struct completion video_comp; 137 struct mutex dev_mutex; 138 struct mutex cmd_mutex; 139 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 140 141 u32 err_work_state; 142 struct work_struct err_work; 143 struct work_struct hpd_work; 144 struct workqueue_struct *workqueue; 145 146 /* DSI 6G TX buffer*/ 147 struct drm_gem_object *tx_gem_obj; 148 149 /* DSI v2 TX buffer */ 150 void *tx_buf; 151 dma_addr_t tx_buf_paddr; 152 153 int tx_size; 154 155 u8 *rx_buf; 156 157 struct regmap *sfpb; 158 159 struct drm_display_mode *mode; 160 161 /* connected device info */ 162 struct device_node *device_node; 163 unsigned int channel; 164 unsigned int lanes; 165 enum mipi_dsi_pixel_format format; 166 unsigned long mode_flags; 167 168 /* lane data parsed via DT */ 169 int dlane_swap; 170 int num_data_lanes; 171 172 /* from phy DT */ 173 bool cphy_mode; 174 175 u32 dma_cmd_ctrl_restore; 176 177 bool registered; 178 bool power_on; 179 bool enabled; 180 int irq; 181 }; 182 183 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 184 { 185 switch (fmt) { 186 case MIPI_DSI_FMT_RGB565: return 16; 187 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 188 case MIPI_DSI_FMT_RGB666: 189 case MIPI_DSI_FMT_RGB888: 190 default: return 24; 191 } 192 } 193 194 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 195 { 196 return msm_readl(msm_host->ctrl_base + reg); 197 } 198 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 199 { 200 msm_writel(data, msm_host->ctrl_base + reg); 201 } 202 203 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 204 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 205 206 static const struct msm_dsi_cfg_handler *dsi_get_config( 207 struct msm_dsi_host *msm_host) 208 { 209 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 210 struct device *dev = &msm_host->pdev->dev; 211 struct clk *ahb_clk; 212 int ret; 213 u32 major = 0, minor = 0; 214 215 cfg_hnd = device_get_match_data(dev); 216 if (cfg_hnd) 217 return cfg_hnd; 218 219 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 220 if (IS_ERR(ahb_clk)) { 221 pr_err("%s: cannot get interface clock\n", __func__); 222 goto exit; 223 } 224 225 pm_runtime_get_sync(dev); 226 227 ret = clk_prepare_enable(ahb_clk); 228 if (ret) { 229 pr_err("%s: unable to enable ahb_clk\n", __func__); 230 goto runtime_put; 231 } 232 233 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 234 if (ret) { 235 pr_err("%s: Invalid version\n", __func__); 236 goto disable_clks; 237 } 238 239 cfg_hnd = msm_dsi_cfg_get(major, minor); 240 241 DBG("%s: Version %x:%x\n", __func__, major, minor); 242 243 disable_clks: 244 clk_disable_unprepare(ahb_clk); 245 runtime_put: 246 pm_runtime_put_sync(dev); 247 exit: 248 return cfg_hnd; 249 } 250 251 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 252 { 253 return container_of(host, struct msm_dsi_host, base); 254 } 255 256 static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 257 { 258 struct regulator_bulk_data *s = msm_host->supplies; 259 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 260 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 261 int i; 262 263 DBG(""); 264 for (i = num - 1; i >= 0; i--) 265 if (regs[i].disable_load >= 0) 266 regulator_set_load(s[i].consumer, 267 regs[i].disable_load); 268 269 regulator_bulk_disable(num, s); 270 } 271 272 static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 273 { 274 struct regulator_bulk_data *s = msm_host->supplies; 275 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 276 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 277 int ret, i; 278 279 DBG(""); 280 for (i = 0; i < num; i++) { 281 if (regs[i].enable_load >= 0) { 282 ret = regulator_set_load(s[i].consumer, 283 regs[i].enable_load); 284 if (ret < 0) { 285 pr_err("regulator %d set op mode failed, %d\n", 286 i, ret); 287 goto fail; 288 } 289 } 290 } 291 292 ret = regulator_bulk_enable(num, s); 293 if (ret < 0) { 294 pr_err("regulator enable failed, %d\n", ret); 295 goto fail; 296 } 297 298 return 0; 299 300 fail: 301 for (i--; i >= 0; i--) 302 regulator_set_load(s[i].consumer, regs[i].disable_load); 303 return ret; 304 } 305 306 static int dsi_regulator_init(struct msm_dsi_host *msm_host) 307 { 308 struct regulator_bulk_data *s = msm_host->supplies; 309 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 310 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 311 int i, ret; 312 313 for (i = 0; i < num; i++) 314 s[i].supply = regs[i].name; 315 316 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 317 if (ret < 0) { 318 pr_err("%s: failed to init regulator, ret=%d\n", 319 __func__, ret); 320 return ret; 321 } 322 323 return 0; 324 } 325 326 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 327 { 328 struct platform_device *pdev = msm_host->pdev; 329 int ret = 0; 330 331 msm_host->src_clk = msm_clk_get(pdev, "src"); 332 333 if (IS_ERR(msm_host->src_clk)) { 334 ret = PTR_ERR(msm_host->src_clk); 335 pr_err("%s: can't find src clock. ret=%d\n", 336 __func__, ret); 337 msm_host->src_clk = NULL; 338 return ret; 339 } 340 341 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 342 if (!msm_host->esc_clk_src) { 343 ret = -ENODEV; 344 pr_err("%s: can't get esc clock parent. ret=%d\n", 345 __func__, ret); 346 return ret; 347 } 348 349 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 350 if (!msm_host->dsi_clk_src) { 351 ret = -ENODEV; 352 pr_err("%s: can't get src clock parent. ret=%d\n", 353 __func__, ret); 354 } 355 356 return ret; 357 } 358 359 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 360 { 361 struct platform_device *pdev = msm_host->pdev; 362 int ret = 0; 363 364 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 365 if (IS_ERR(msm_host->byte_intf_clk)) { 366 ret = PTR_ERR(msm_host->byte_intf_clk); 367 pr_err("%s: can't find byte_intf clock. ret=%d\n", 368 __func__, ret); 369 } 370 371 return ret; 372 } 373 374 static int dsi_clk_init(struct msm_dsi_host *msm_host) 375 { 376 struct platform_device *pdev = msm_host->pdev; 377 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 378 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 379 int i, ret = 0; 380 381 /* get bus clocks */ 382 for (i = 0; i < cfg->num_bus_clks; i++) 383 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 384 msm_host->num_bus_clks = cfg->num_bus_clks; 385 386 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 387 if (ret < 0) { 388 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret); 389 goto exit; 390 } 391 392 /* get link and source clocks */ 393 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 394 if (IS_ERR(msm_host->byte_clk)) { 395 ret = PTR_ERR(msm_host->byte_clk); 396 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 397 __func__, ret); 398 msm_host->byte_clk = NULL; 399 goto exit; 400 } 401 402 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 403 if (IS_ERR(msm_host->pixel_clk)) { 404 ret = PTR_ERR(msm_host->pixel_clk); 405 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 406 __func__, ret); 407 msm_host->pixel_clk = NULL; 408 goto exit; 409 } 410 411 msm_host->esc_clk = msm_clk_get(pdev, "core"); 412 if (IS_ERR(msm_host->esc_clk)) { 413 ret = PTR_ERR(msm_host->esc_clk); 414 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 415 __func__, ret); 416 msm_host->esc_clk = NULL; 417 goto exit; 418 } 419 420 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 421 if (IS_ERR(msm_host->byte_clk_src)) { 422 ret = PTR_ERR(msm_host->byte_clk_src); 423 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); 424 goto exit; 425 } 426 427 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 428 if (IS_ERR(msm_host->pixel_clk_src)) { 429 ret = PTR_ERR(msm_host->pixel_clk_src); 430 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); 431 goto exit; 432 } 433 434 if (cfg_hnd->ops->clk_init_ver) 435 ret = cfg_hnd->ops->clk_init_ver(msm_host); 436 exit: 437 return ret; 438 } 439 440 int msm_dsi_runtime_suspend(struct device *dev) 441 { 442 struct platform_device *pdev = to_platform_device(dev); 443 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 444 struct mipi_dsi_host *host = msm_dsi->host; 445 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 446 447 if (!msm_host->cfg_hnd) 448 return 0; 449 450 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 451 452 return 0; 453 } 454 455 int msm_dsi_runtime_resume(struct device *dev) 456 { 457 struct platform_device *pdev = to_platform_device(dev); 458 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 459 struct mipi_dsi_host *host = msm_dsi->host; 460 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 461 462 if (!msm_host->cfg_hnd) 463 return 0; 464 465 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 466 } 467 468 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 469 { 470 unsigned long byte_intf_rate; 471 int ret; 472 473 DBG("Set clk rates: pclk=%d, byteclk=%lu", 474 msm_host->mode->clock, msm_host->byte_clk_rate); 475 476 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 477 msm_host->byte_clk_rate); 478 if (ret) { 479 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 480 return ret; 481 } 482 483 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 484 if (ret) { 485 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 486 return ret; 487 } 488 489 if (msm_host->byte_intf_clk) { 490 /* For CPHY, byte_intf_clk is same as byte_clk */ 491 if (msm_host->cphy_mode) 492 byte_intf_rate = msm_host->byte_clk_rate; 493 else 494 byte_intf_rate = msm_host->byte_clk_rate / 2; 495 496 ret = clk_set_rate(msm_host->byte_intf_clk, byte_intf_rate); 497 if (ret) { 498 pr_err("%s: Failed to set rate byte intf clk, %d\n", 499 __func__, ret); 500 return ret; 501 } 502 } 503 504 return 0; 505 } 506 507 508 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 509 { 510 int ret; 511 512 ret = clk_prepare_enable(msm_host->esc_clk); 513 if (ret) { 514 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 515 goto error; 516 } 517 518 ret = clk_prepare_enable(msm_host->byte_clk); 519 if (ret) { 520 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 521 goto byte_clk_err; 522 } 523 524 ret = clk_prepare_enable(msm_host->pixel_clk); 525 if (ret) { 526 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 527 goto pixel_clk_err; 528 } 529 530 ret = clk_prepare_enable(msm_host->byte_intf_clk); 531 if (ret) { 532 pr_err("%s: Failed to enable byte intf clk\n", 533 __func__); 534 goto byte_intf_clk_err; 535 } 536 537 return 0; 538 539 byte_intf_clk_err: 540 clk_disable_unprepare(msm_host->pixel_clk); 541 pixel_clk_err: 542 clk_disable_unprepare(msm_host->byte_clk); 543 byte_clk_err: 544 clk_disable_unprepare(msm_host->esc_clk); 545 error: 546 return ret; 547 } 548 549 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 550 { 551 int ret; 552 553 DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 554 msm_host->mode->clock, msm_host->byte_clk_rate, 555 msm_host->esc_clk_rate, msm_host->src_clk_rate); 556 557 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 558 if (ret) { 559 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 560 return ret; 561 } 562 563 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 564 if (ret) { 565 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 566 return ret; 567 } 568 569 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 570 if (ret) { 571 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 572 return ret; 573 } 574 575 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 576 if (ret) { 577 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 578 return ret; 579 } 580 581 return 0; 582 } 583 584 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 585 { 586 int ret; 587 588 ret = clk_prepare_enable(msm_host->byte_clk); 589 if (ret) { 590 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 591 goto error; 592 } 593 594 ret = clk_prepare_enable(msm_host->esc_clk); 595 if (ret) { 596 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 597 goto esc_clk_err; 598 } 599 600 ret = clk_prepare_enable(msm_host->src_clk); 601 if (ret) { 602 pr_err("%s: Failed to enable dsi src clk\n", __func__); 603 goto src_clk_err; 604 } 605 606 ret = clk_prepare_enable(msm_host->pixel_clk); 607 if (ret) { 608 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 609 goto pixel_clk_err; 610 } 611 612 return 0; 613 614 pixel_clk_err: 615 clk_disable_unprepare(msm_host->src_clk); 616 src_clk_err: 617 clk_disable_unprepare(msm_host->esc_clk); 618 esc_clk_err: 619 clk_disable_unprepare(msm_host->byte_clk); 620 error: 621 return ret; 622 } 623 624 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 625 { 626 /* Drop the performance state vote */ 627 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 628 clk_disable_unprepare(msm_host->esc_clk); 629 clk_disable_unprepare(msm_host->pixel_clk); 630 clk_disable_unprepare(msm_host->byte_intf_clk); 631 clk_disable_unprepare(msm_host->byte_clk); 632 } 633 634 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 635 { 636 clk_disable_unprepare(msm_host->pixel_clk); 637 clk_disable_unprepare(msm_host->src_clk); 638 clk_disable_unprepare(msm_host->esc_clk); 639 clk_disable_unprepare(msm_host->byte_clk); 640 } 641 642 static unsigned long dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 643 { 644 struct drm_display_mode *mode = msm_host->mode; 645 unsigned long pclk_rate; 646 647 pclk_rate = mode->clock * 1000; 648 649 /* 650 * For bonded DSI mode, the current DRM mode has the complete width of the 651 * panel. Since, the complete panel is driven by two DSI controllers, 652 * the clock rates have to be split between the two dsi controllers. 653 * Adjust the byte and pixel clock rates for each dsi host accordingly. 654 */ 655 if (is_bonded_dsi) 656 pclk_rate /= 2; 657 658 return pclk_rate; 659 } 660 661 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 662 { 663 u8 lanes = msm_host->lanes; 664 u32 bpp = dsi_get_bpp(msm_host->format); 665 unsigned long pclk_rate = dsi_get_pclk_rate(msm_host, is_bonded_dsi); 666 u64 pclk_bpp = (u64)pclk_rate * bpp; 667 668 if (lanes == 0) { 669 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 670 lanes = 1; 671 } 672 673 /* CPHY "byte_clk" is in units of 16 bits */ 674 if (msm_host->cphy_mode) 675 do_div(pclk_bpp, (16 * lanes)); 676 else 677 do_div(pclk_bpp, (8 * lanes)); 678 679 msm_host->pixel_clk_rate = pclk_rate; 680 msm_host->byte_clk_rate = pclk_bpp; 681 682 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 683 msm_host->byte_clk_rate); 684 685 } 686 687 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 688 { 689 if (!msm_host->mode) { 690 pr_err("%s: mode not set\n", __func__); 691 return -EINVAL; 692 } 693 694 dsi_calc_pclk(msm_host, is_bonded_dsi); 695 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 696 return 0; 697 } 698 699 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 700 { 701 u32 bpp = dsi_get_bpp(msm_host->format); 702 u64 pclk_bpp; 703 unsigned int esc_mhz, esc_div; 704 unsigned long byte_mhz; 705 706 dsi_calc_pclk(msm_host, is_bonded_dsi); 707 708 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_bonded_dsi) * bpp; 709 do_div(pclk_bpp, 8); 710 msm_host->src_clk_rate = pclk_bpp; 711 712 /* 713 * esc clock is byte clock followed by a 4 bit divider, 714 * we need to find an escape clock frequency within the 715 * mipi DSI spec range within the maximum divider limit 716 * We iterate here between an escape clock frequencey 717 * between 20 Mhz to 5 Mhz and pick up the first one 718 * that can be supported by our divider 719 */ 720 721 byte_mhz = msm_host->byte_clk_rate / 1000000; 722 723 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 724 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 725 726 /* 727 * TODO: Ideally, we shouldn't know what sort of divider 728 * is available in mmss_cc, we're just assuming that 729 * it'll always be a 4 bit divider. Need to come up with 730 * a better way here. 731 */ 732 if (esc_div >= 1 && esc_div <= 16) 733 break; 734 } 735 736 if (esc_mhz < 5) 737 return -EINVAL; 738 739 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 740 741 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 742 msm_host->src_clk_rate); 743 744 return 0; 745 } 746 747 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 748 { 749 u32 intr; 750 unsigned long flags; 751 752 spin_lock_irqsave(&msm_host->intr_lock, flags); 753 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 754 755 if (enable) 756 intr |= mask; 757 else 758 intr &= ~mask; 759 760 DBG("intr=%x enable=%d", intr, enable); 761 762 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 763 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 764 } 765 766 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 767 { 768 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 769 return BURST_MODE; 770 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 771 return NON_BURST_SYNCH_PULSE; 772 773 return NON_BURST_SYNCH_EVENT; 774 } 775 776 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 777 const enum mipi_dsi_pixel_format mipi_fmt) 778 { 779 switch (mipi_fmt) { 780 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 781 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 782 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 783 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 784 default: return VID_DST_FORMAT_RGB888; 785 } 786 } 787 788 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 789 const enum mipi_dsi_pixel_format mipi_fmt) 790 { 791 switch (mipi_fmt) { 792 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 793 case MIPI_DSI_FMT_RGB666_PACKED: 794 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 795 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 796 default: return CMD_DST_FORMAT_RGB888; 797 } 798 } 799 800 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 801 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 802 { 803 u32 flags = msm_host->mode_flags; 804 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 805 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 806 u32 data = 0, lane_ctrl = 0; 807 808 if (!enable) { 809 dsi_write(msm_host, REG_DSI_CTRL, 0); 810 return; 811 } 812 813 if (flags & MIPI_DSI_MODE_VIDEO) { 814 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 815 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 816 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 817 data |= DSI_VID_CFG0_HFP_POWER_STOP; 818 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 819 data |= DSI_VID_CFG0_HBP_POWER_STOP; 820 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 821 data |= DSI_VID_CFG0_HSA_POWER_STOP; 822 /* Always set low power stop mode for BLLP 823 * to let command engine send packets 824 */ 825 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 826 DSI_VID_CFG0_BLLP_POWER_STOP; 827 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 828 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 829 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 830 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 831 832 /* Do not swap RGB colors */ 833 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 834 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 835 } else { 836 /* Do not swap RGB colors */ 837 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 838 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 839 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 840 841 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 842 DSI_CMD_CFG1_WR_MEM_CONTINUE( 843 MIPI_DCS_WRITE_MEMORY_CONTINUE); 844 /* Always insert DCS command */ 845 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 846 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 847 } 848 849 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 850 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 851 DSI_CMD_DMA_CTRL_LOW_POWER); 852 853 data = 0; 854 /* Always assume dedicated TE pin */ 855 data |= DSI_TRIG_CTRL_TE; 856 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 857 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 858 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 859 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 860 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 861 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 862 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 863 864 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 865 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 866 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 867 868 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 869 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 870 phy_shared_timings->clk_pre_inc_by_2) 871 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 872 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 873 874 data = 0; 875 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 876 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 877 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 878 879 /* allow only ack-err-status to generate interrupt */ 880 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 881 882 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 883 884 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 885 886 data = DSI_CTRL_CLK_EN; 887 888 DBG("lane number=%d", msm_host->lanes); 889 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 890 891 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 892 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 893 894 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 895 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 896 897 if (msm_dsi_phy_set_continuous_clock(phy, enable)) 898 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 899 900 dsi_write(msm_host, REG_DSI_LANE_CTRL, 901 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 902 } 903 904 data |= DSI_CTRL_ENABLE; 905 906 dsi_write(msm_host, REG_DSI_CTRL, data); 907 908 if (msm_host->cphy_mode) 909 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 910 } 911 912 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 913 { 914 struct drm_display_mode *mode = msm_host->mode; 915 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 916 u32 h_total = mode->htotal; 917 u32 v_total = mode->vtotal; 918 u32 hs_end = mode->hsync_end - mode->hsync_start; 919 u32 vs_end = mode->vsync_end - mode->vsync_start; 920 u32 ha_start = h_total - mode->hsync_start; 921 u32 ha_end = ha_start + mode->hdisplay; 922 u32 va_start = v_total - mode->vsync_start; 923 u32 va_end = va_start + mode->vdisplay; 924 u32 hdisplay = mode->hdisplay; 925 u32 wc; 926 927 DBG(""); 928 929 /* 930 * For bonded DSI mode, the current DRM mode has 931 * the complete width of the panel. Since, the complete 932 * panel is driven by two DSI controllers, the horizontal 933 * timings have to be split between the two dsi controllers. 934 * Adjust the DSI host timing values accordingly. 935 */ 936 if (is_bonded_dsi) { 937 h_total /= 2; 938 hs_end /= 2; 939 ha_start /= 2; 940 ha_end /= 2; 941 hdisplay /= 2; 942 } 943 944 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 945 dsi_write(msm_host, REG_DSI_ACTIVE_H, 946 DSI_ACTIVE_H_START(ha_start) | 947 DSI_ACTIVE_H_END(ha_end)); 948 dsi_write(msm_host, REG_DSI_ACTIVE_V, 949 DSI_ACTIVE_V_START(va_start) | 950 DSI_ACTIVE_V_END(va_end)); 951 dsi_write(msm_host, REG_DSI_TOTAL, 952 DSI_TOTAL_H_TOTAL(h_total - 1) | 953 DSI_TOTAL_V_TOTAL(v_total - 1)); 954 955 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 956 DSI_ACTIVE_HSYNC_START(hs_start) | 957 DSI_ACTIVE_HSYNC_END(hs_end)); 958 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 959 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 960 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 961 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 962 } else { /* command mode */ 963 /* image data and 1 byte write_memory_start cmd */ 964 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 965 966 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 967 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 968 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 969 msm_host->channel) | 970 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 971 MIPI_DSI_DCS_LONG_WRITE)); 972 973 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 974 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 975 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 976 } 977 } 978 979 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 980 { 981 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 982 wmb(); /* clocks need to be enabled before reset */ 983 984 dsi_write(msm_host, REG_DSI_RESET, 1); 985 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 986 dsi_write(msm_host, REG_DSI_RESET, 0); 987 } 988 989 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 990 bool video_mode, bool enable) 991 { 992 u32 dsi_ctrl; 993 994 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 995 996 if (!enable) { 997 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 998 DSI_CTRL_CMD_MODE_EN); 999 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1000 DSI_IRQ_MASK_VIDEO_DONE, 0); 1001 } else { 1002 if (video_mode) { 1003 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1004 } else { /* command mode */ 1005 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1006 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1007 } 1008 dsi_ctrl |= DSI_CTRL_ENABLE; 1009 } 1010 1011 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1012 } 1013 1014 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1015 { 1016 u32 data; 1017 1018 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1019 1020 if (mode == 0) 1021 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1022 else 1023 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1024 1025 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1026 } 1027 1028 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1029 { 1030 u32 ret = 0; 1031 struct device *dev = &msm_host->pdev->dev; 1032 1033 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1034 1035 reinit_completion(&msm_host->video_comp); 1036 1037 ret = wait_for_completion_timeout(&msm_host->video_comp, 1038 msecs_to_jiffies(70)); 1039 1040 if (ret == 0) 1041 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1042 1043 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1044 } 1045 1046 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1047 { 1048 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1049 return; 1050 1051 if (msm_host->power_on && msm_host->enabled) { 1052 dsi_wait4video_done(msm_host); 1053 /* delay 4 ms to skip BLLP */ 1054 usleep_range(2000, 4000); 1055 } 1056 } 1057 1058 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1059 { 1060 struct drm_device *dev = msm_host->dev; 1061 struct msm_drm_private *priv = dev->dev_private; 1062 uint64_t iova; 1063 u8 *data; 1064 1065 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1066 priv->kms->aspace, 1067 &msm_host->tx_gem_obj, &iova); 1068 1069 if (IS_ERR(data)) { 1070 msm_host->tx_gem_obj = NULL; 1071 return PTR_ERR(data); 1072 } 1073 1074 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1075 1076 msm_host->tx_size = msm_host->tx_gem_obj->size; 1077 1078 return 0; 1079 } 1080 1081 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1082 { 1083 struct drm_device *dev = msm_host->dev; 1084 1085 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1086 &msm_host->tx_buf_paddr, GFP_KERNEL); 1087 if (!msm_host->tx_buf) 1088 return -ENOMEM; 1089 1090 msm_host->tx_size = size; 1091 1092 return 0; 1093 } 1094 1095 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1096 { 1097 struct drm_device *dev = msm_host->dev; 1098 struct msm_drm_private *priv; 1099 1100 /* 1101 * This is possible if we're tearing down before we've had a chance to 1102 * fully initialize. A very real possibility if our probe is deferred, 1103 * in which case we'll hit msm_dsi_host_destroy() without having run 1104 * through the dsi_tx_buf_alloc(). 1105 */ 1106 if (!dev) 1107 return; 1108 1109 priv = dev->dev_private; 1110 if (msm_host->tx_gem_obj) { 1111 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); 1112 drm_gem_object_put(msm_host->tx_gem_obj); 1113 msm_host->tx_gem_obj = NULL; 1114 } 1115 1116 if (msm_host->tx_buf) 1117 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1118 msm_host->tx_buf_paddr); 1119 } 1120 1121 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1122 { 1123 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1124 } 1125 1126 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1127 { 1128 return msm_host->tx_buf; 1129 } 1130 1131 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1132 { 1133 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1134 } 1135 1136 /* 1137 * prepare cmd buffer to be txed 1138 */ 1139 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1140 const struct mipi_dsi_msg *msg) 1141 { 1142 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1143 struct mipi_dsi_packet packet; 1144 int len; 1145 int ret; 1146 u8 *data; 1147 1148 ret = mipi_dsi_create_packet(&packet, msg); 1149 if (ret) { 1150 pr_err("%s: create packet failed, %d\n", __func__, ret); 1151 return ret; 1152 } 1153 len = (packet.size + 3) & (~0x3); 1154 1155 if (len > msm_host->tx_size) { 1156 pr_err("%s: packet size is too big\n", __func__); 1157 return -EINVAL; 1158 } 1159 1160 data = cfg_hnd->ops->tx_buf_get(msm_host); 1161 if (IS_ERR(data)) { 1162 ret = PTR_ERR(data); 1163 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1164 return ret; 1165 } 1166 1167 /* MSM specific command format in memory */ 1168 data[0] = packet.header[1]; 1169 data[1] = packet.header[2]; 1170 data[2] = packet.header[0]; 1171 data[3] = BIT(7); /* Last packet */ 1172 if (mipi_dsi_packet_format_is_long(msg->type)) 1173 data[3] |= BIT(6); 1174 if (msg->rx_buf && msg->rx_len) 1175 data[3] |= BIT(5); 1176 1177 /* Long packet */ 1178 if (packet.payload && packet.payload_length) 1179 memcpy(data + 4, packet.payload, packet.payload_length); 1180 1181 /* Append 0xff to the end */ 1182 if (packet.size < len) 1183 memset(data + packet.size, 0xff, len - packet.size); 1184 1185 if (cfg_hnd->ops->tx_buf_put) 1186 cfg_hnd->ops->tx_buf_put(msm_host); 1187 1188 return len; 1189 } 1190 1191 /* 1192 * dsi_short_read1_resp: 1 parameter 1193 */ 1194 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1195 { 1196 u8 *data = msg->rx_buf; 1197 if (data && (msg->rx_len >= 1)) { 1198 *data = buf[1]; /* strip out dcs type */ 1199 return 1; 1200 } else { 1201 pr_err("%s: read data does not match with rx_buf len %zu\n", 1202 __func__, msg->rx_len); 1203 return -EINVAL; 1204 } 1205 } 1206 1207 /* 1208 * dsi_short_read2_resp: 2 parameter 1209 */ 1210 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1211 { 1212 u8 *data = msg->rx_buf; 1213 if (data && (msg->rx_len >= 2)) { 1214 data[0] = buf[1]; /* strip out dcs type */ 1215 data[1] = buf[2]; 1216 return 2; 1217 } else { 1218 pr_err("%s: read data does not match with rx_buf len %zu\n", 1219 __func__, msg->rx_len); 1220 return -EINVAL; 1221 } 1222 } 1223 1224 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1225 { 1226 /* strip out 4 byte dcs header */ 1227 if (msg->rx_buf && msg->rx_len) 1228 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1229 1230 return msg->rx_len; 1231 } 1232 1233 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1234 { 1235 struct drm_device *dev = msm_host->dev; 1236 struct msm_drm_private *priv = dev->dev_private; 1237 1238 if (!dma_base) 1239 return -EINVAL; 1240 1241 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1242 priv->kms->aspace, dma_base); 1243 } 1244 1245 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1246 { 1247 if (!dma_base) 1248 return -EINVAL; 1249 1250 *dma_base = msm_host->tx_buf_paddr; 1251 return 0; 1252 } 1253 1254 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1255 { 1256 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1257 int ret; 1258 uint64_t dma_base; 1259 bool triggered; 1260 1261 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1262 if (ret) { 1263 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1264 return ret; 1265 } 1266 1267 reinit_completion(&msm_host->dma_comp); 1268 1269 dsi_wait4video_eng_busy(msm_host); 1270 1271 triggered = msm_dsi_manager_cmd_xfer_trigger( 1272 msm_host->id, dma_base, len); 1273 if (triggered) { 1274 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1275 msecs_to_jiffies(200)); 1276 DBG("ret=%d", ret); 1277 if (ret == 0) 1278 ret = -ETIMEDOUT; 1279 else 1280 ret = len; 1281 } else 1282 ret = len; 1283 1284 return ret; 1285 } 1286 1287 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1288 u8 *buf, int rx_byte, int pkt_size) 1289 { 1290 u32 *temp, data; 1291 int i, j = 0, cnt; 1292 u32 read_cnt; 1293 u8 reg[16]; 1294 int repeated_bytes = 0; 1295 int buf_offset = buf - msm_host->rx_buf; 1296 1297 temp = (u32 *)reg; 1298 cnt = (rx_byte + 3) >> 2; 1299 if (cnt > 4) 1300 cnt = 4; /* 4 x 32 bits registers only */ 1301 1302 if (rx_byte == 4) 1303 read_cnt = 4; 1304 else 1305 read_cnt = pkt_size + 6; 1306 1307 /* 1308 * In case of multiple reads from the panel, after the first read, there 1309 * is possibility that there are some bytes in the payload repeating in 1310 * the RDBK_DATA registers. Since we read all the parameters from the 1311 * panel right from the first byte for every pass. We need to skip the 1312 * repeating bytes and then append the new parameters to the rx buffer. 1313 */ 1314 if (read_cnt > 16) { 1315 int bytes_shifted; 1316 /* Any data more than 16 bytes will be shifted out. 1317 * The temp read buffer should already contain these bytes. 1318 * The remaining bytes in read buffer are the repeated bytes. 1319 */ 1320 bytes_shifted = read_cnt - 16; 1321 repeated_bytes = buf_offset - bytes_shifted; 1322 } 1323 1324 for (i = cnt - 1; i >= 0; i--) { 1325 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1326 *temp++ = ntohl(data); /* to host byte order */ 1327 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1328 } 1329 1330 for (i = repeated_bytes; i < 16; i++) 1331 buf[j++] = reg[i]; 1332 1333 return j; 1334 } 1335 1336 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1337 const struct mipi_dsi_msg *msg) 1338 { 1339 int len, ret; 1340 int bllp_len = msm_host->mode->hdisplay * 1341 dsi_get_bpp(msm_host->format) / 8; 1342 1343 len = dsi_cmd_dma_add(msm_host, msg); 1344 if (!len) { 1345 pr_err("%s: failed to add cmd type = 0x%x\n", 1346 __func__, msg->type); 1347 return -EINVAL; 1348 } 1349 1350 /* for video mode, do not send cmds more than 1351 * one pixel line, since it only transmit it 1352 * during BLLP. 1353 */ 1354 /* TODO: if the command is sent in LP mode, the bit rate is only 1355 * half of esc clk rate. In this case, if the video is already 1356 * actively streaming, we need to check more carefully if the 1357 * command can be fit into one BLLP. 1358 */ 1359 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1360 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1361 __func__, len); 1362 return -EINVAL; 1363 } 1364 1365 ret = dsi_cmd_dma_tx(msm_host, len); 1366 if (ret < len) { 1367 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", 1368 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); 1369 return -ECOMM; 1370 } 1371 1372 return len; 1373 } 1374 1375 static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1376 { 1377 u32 data0, data1; 1378 1379 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1380 data1 = data0; 1381 data1 &= ~DSI_CTRL_ENABLE; 1382 dsi_write(msm_host, REG_DSI_CTRL, data1); 1383 /* 1384 * dsi controller need to be disabled before 1385 * clocks turned on 1386 */ 1387 wmb(); 1388 1389 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1390 wmb(); /* make sure clocks enabled */ 1391 1392 /* dsi controller can only be reset while clocks are running */ 1393 dsi_write(msm_host, REG_DSI_RESET, 1); 1394 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1395 dsi_write(msm_host, REG_DSI_RESET, 0); 1396 wmb(); /* controller out of reset */ 1397 dsi_write(msm_host, REG_DSI_CTRL, data0); 1398 wmb(); /* make sure dsi controller enabled again */ 1399 } 1400 1401 static void dsi_hpd_worker(struct work_struct *work) 1402 { 1403 struct msm_dsi_host *msm_host = 1404 container_of(work, struct msm_dsi_host, hpd_work); 1405 1406 drm_helper_hpd_irq_event(msm_host->dev); 1407 } 1408 1409 static void dsi_err_worker(struct work_struct *work) 1410 { 1411 struct msm_dsi_host *msm_host = 1412 container_of(work, struct msm_dsi_host, err_work); 1413 u32 status = msm_host->err_work_state; 1414 1415 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1416 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1417 dsi_sw_reset_restore(msm_host); 1418 1419 /* It is safe to clear here because error irq is disabled. */ 1420 msm_host->err_work_state = 0; 1421 1422 /* enable dsi error interrupt */ 1423 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1424 } 1425 1426 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1427 { 1428 u32 status; 1429 1430 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1431 1432 if (status) { 1433 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1434 /* Writing of an extra 0 needed to clear error bits */ 1435 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1436 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1437 } 1438 } 1439 1440 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1441 { 1442 u32 status; 1443 1444 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1445 1446 if (status) { 1447 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1448 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1449 } 1450 } 1451 1452 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1453 { 1454 u32 status; 1455 1456 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1457 1458 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1459 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1460 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1461 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1462 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1463 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1464 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1465 } 1466 } 1467 1468 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1469 { 1470 u32 status; 1471 1472 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1473 1474 /* fifo underflow, overflow */ 1475 if (status) { 1476 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1477 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1478 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1479 msm_host->err_work_state |= 1480 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1481 } 1482 } 1483 1484 static void dsi_status(struct msm_dsi_host *msm_host) 1485 { 1486 u32 status; 1487 1488 status = dsi_read(msm_host, REG_DSI_STATUS0); 1489 1490 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1491 dsi_write(msm_host, REG_DSI_STATUS0, status); 1492 msm_host->err_work_state |= 1493 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1494 } 1495 } 1496 1497 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1498 { 1499 u32 status; 1500 1501 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1502 1503 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1504 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1505 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1506 } 1507 } 1508 1509 static void dsi_error(struct msm_dsi_host *msm_host) 1510 { 1511 /* disable dsi error interrupt */ 1512 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1513 1514 dsi_clk_status(msm_host); 1515 dsi_fifo_status(msm_host); 1516 dsi_ack_err_status(msm_host); 1517 dsi_timeout_status(msm_host); 1518 dsi_status(msm_host); 1519 dsi_dln0_phy_err(msm_host); 1520 1521 queue_work(msm_host->workqueue, &msm_host->err_work); 1522 } 1523 1524 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1525 { 1526 struct msm_dsi_host *msm_host = ptr; 1527 u32 isr; 1528 unsigned long flags; 1529 1530 if (!msm_host->ctrl_base) 1531 return IRQ_HANDLED; 1532 1533 spin_lock_irqsave(&msm_host->intr_lock, flags); 1534 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1535 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1536 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1537 1538 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1539 1540 if (isr & DSI_IRQ_ERROR) 1541 dsi_error(msm_host); 1542 1543 if (isr & DSI_IRQ_VIDEO_DONE) 1544 complete(&msm_host->video_comp); 1545 1546 if (isr & DSI_IRQ_CMD_DMA_DONE) 1547 complete(&msm_host->dma_comp); 1548 1549 return IRQ_HANDLED; 1550 } 1551 1552 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1553 struct device *panel_device) 1554 { 1555 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1556 "disp-enable", 1557 GPIOD_OUT_LOW); 1558 if (IS_ERR(msm_host->disp_en_gpio)) { 1559 DBG("cannot get disp-enable-gpios %ld", 1560 PTR_ERR(msm_host->disp_en_gpio)); 1561 return PTR_ERR(msm_host->disp_en_gpio); 1562 } 1563 1564 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1565 GPIOD_IN); 1566 if (IS_ERR(msm_host->te_gpio)) { 1567 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1568 return PTR_ERR(msm_host->te_gpio); 1569 } 1570 1571 return 0; 1572 } 1573 1574 static int dsi_host_attach(struct mipi_dsi_host *host, 1575 struct mipi_dsi_device *dsi) 1576 { 1577 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1578 int ret; 1579 1580 if (dsi->lanes > msm_host->num_data_lanes) 1581 return -EINVAL; 1582 1583 msm_host->channel = dsi->channel; 1584 msm_host->lanes = dsi->lanes; 1585 msm_host->format = dsi->format; 1586 msm_host->mode_flags = dsi->mode_flags; 1587 1588 /* Some gpios defined in panel DT need to be controlled by host */ 1589 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1590 if (ret) 1591 return ret; 1592 1593 ret = dsi_dev_attach(msm_host->pdev); 1594 if (ret) 1595 return ret; 1596 1597 DBG("id=%d", msm_host->id); 1598 if (msm_host->dev) 1599 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1600 1601 return 0; 1602 } 1603 1604 static int dsi_host_detach(struct mipi_dsi_host *host, 1605 struct mipi_dsi_device *dsi) 1606 { 1607 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1608 1609 dsi_dev_detach(msm_host->pdev); 1610 1611 msm_host->device_node = NULL; 1612 1613 DBG("id=%d", msm_host->id); 1614 if (msm_host->dev) 1615 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1616 1617 return 0; 1618 } 1619 1620 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1621 const struct mipi_dsi_msg *msg) 1622 { 1623 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1624 int ret; 1625 1626 if (!msg || !msm_host->power_on) 1627 return -EINVAL; 1628 1629 mutex_lock(&msm_host->cmd_mutex); 1630 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1631 mutex_unlock(&msm_host->cmd_mutex); 1632 1633 return ret; 1634 } 1635 1636 static const struct mipi_dsi_host_ops dsi_host_ops = { 1637 .attach = dsi_host_attach, 1638 .detach = dsi_host_detach, 1639 .transfer = dsi_host_transfer, 1640 }; 1641 1642 /* 1643 * List of supported physical to logical lane mappings. 1644 * For example, the 2nd entry represents the following mapping: 1645 * 1646 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1647 */ 1648 static const int supported_data_lane_swaps[][4] = { 1649 { 0, 1, 2, 3 }, 1650 { 3, 0, 1, 2 }, 1651 { 2, 3, 0, 1 }, 1652 { 1, 2, 3, 0 }, 1653 { 0, 3, 2, 1 }, 1654 { 1, 0, 3, 2 }, 1655 { 2, 1, 0, 3 }, 1656 { 3, 2, 1, 0 }, 1657 }; 1658 1659 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1660 struct device_node *ep) 1661 { 1662 struct device *dev = &msm_host->pdev->dev; 1663 struct property *prop; 1664 u32 lane_map[4]; 1665 int ret, i, len, num_lanes; 1666 1667 prop = of_find_property(ep, "data-lanes", &len); 1668 if (!prop) { 1669 DRM_DEV_DEBUG(dev, 1670 "failed to find data lane mapping, using default\n"); 1671 /* Set the number of date lanes to 4 by default. */ 1672 msm_host->num_data_lanes = 4; 1673 return 0; 1674 } 1675 1676 num_lanes = len / sizeof(u32); 1677 1678 if (num_lanes < 1 || num_lanes > 4) { 1679 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1680 return -EINVAL; 1681 } 1682 1683 msm_host->num_data_lanes = num_lanes; 1684 1685 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1686 num_lanes); 1687 if (ret) { 1688 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1689 return ret; 1690 } 1691 1692 /* 1693 * compare DT specified physical-logical lane mappings with the ones 1694 * supported by hardware 1695 */ 1696 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1697 const int *swap = supported_data_lane_swaps[i]; 1698 int j; 1699 1700 /* 1701 * the data-lanes array we get from DT has a logical->physical 1702 * mapping. The "data lane swap" register field represents 1703 * supported configurations in a physical->logical mapping. 1704 * Translate the DT mapping to what we understand and find a 1705 * configuration that works. 1706 */ 1707 for (j = 0; j < num_lanes; j++) { 1708 if (lane_map[j] < 0 || lane_map[j] > 3) 1709 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1710 lane_map[j]); 1711 1712 if (swap[lane_map[j]] != j) 1713 break; 1714 } 1715 1716 if (j == num_lanes) { 1717 msm_host->dlane_swap = i; 1718 return 0; 1719 } 1720 } 1721 1722 return -EINVAL; 1723 } 1724 1725 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1726 { 1727 struct device *dev = &msm_host->pdev->dev; 1728 struct device_node *np = dev->of_node; 1729 struct device_node *endpoint, *device_node; 1730 int ret = 0; 1731 1732 /* 1733 * Get the endpoint of the output port of the DSI host. In our case, 1734 * this is mapped to port number with reg = 1. Don't return an error if 1735 * the remote endpoint isn't defined. It's possible that there is 1736 * nothing connected to the dsi output. 1737 */ 1738 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1739 if (!endpoint) { 1740 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1741 return 0; 1742 } 1743 1744 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1745 if (ret) { 1746 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1747 __func__, ret); 1748 ret = -EINVAL; 1749 goto err; 1750 } 1751 1752 /* Get panel node from the output port's endpoint data */ 1753 device_node = of_graph_get_remote_node(np, 1, 0); 1754 if (!device_node) { 1755 DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__); 1756 ret = -ENODEV; 1757 goto err; 1758 } 1759 1760 msm_host->device_node = device_node; 1761 1762 if (of_property_read_bool(np, "syscon-sfpb")) { 1763 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1764 "syscon-sfpb"); 1765 if (IS_ERR(msm_host->sfpb)) { 1766 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1767 __func__); 1768 ret = PTR_ERR(msm_host->sfpb); 1769 } 1770 } 1771 1772 of_node_put(device_node); 1773 1774 err: 1775 of_node_put(endpoint); 1776 1777 return ret; 1778 } 1779 1780 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1781 { 1782 struct platform_device *pdev = msm_host->pdev; 1783 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1784 struct resource *res; 1785 int i; 1786 1787 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1788 if (!res) 1789 return -EINVAL; 1790 1791 for (i = 0; i < cfg->num_dsi; i++) { 1792 if (cfg->io_start[i] == res->start) 1793 return i; 1794 } 1795 1796 return -EINVAL; 1797 } 1798 1799 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1800 { 1801 struct msm_dsi_host *msm_host = NULL; 1802 struct platform_device *pdev = msm_dsi->pdev; 1803 int ret; 1804 1805 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1806 if (!msm_host) { 1807 ret = -ENOMEM; 1808 goto fail; 1809 } 1810 1811 msm_host->pdev = pdev; 1812 msm_dsi->host = &msm_host->base; 1813 1814 ret = dsi_host_parse_dt(msm_host); 1815 if (ret) { 1816 pr_err("%s: failed to parse dt\n", __func__); 1817 goto fail; 1818 } 1819 1820 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 1821 if (IS_ERR(msm_host->ctrl_base)) { 1822 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1823 ret = PTR_ERR(msm_host->ctrl_base); 1824 goto fail; 1825 } 1826 1827 pm_runtime_enable(&pdev->dev); 1828 1829 msm_host->cfg_hnd = dsi_get_config(msm_host); 1830 if (!msm_host->cfg_hnd) { 1831 ret = -EINVAL; 1832 pr_err("%s: get config failed\n", __func__); 1833 goto fail; 1834 } 1835 1836 msm_host->id = dsi_host_get_id(msm_host); 1837 if (msm_host->id < 0) { 1838 ret = msm_host->id; 1839 pr_err("%s: unable to identify DSI host index\n", __func__); 1840 goto fail; 1841 } 1842 1843 /* fixup base address by io offset */ 1844 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; 1845 1846 ret = dsi_regulator_init(msm_host); 1847 if (ret) { 1848 pr_err("%s: regulator init failed\n", __func__); 1849 goto fail; 1850 } 1851 1852 ret = dsi_clk_init(msm_host); 1853 if (ret) { 1854 pr_err("%s: unable to initialize dsi clks\n", __func__); 1855 goto fail; 1856 } 1857 1858 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1859 if (!msm_host->rx_buf) { 1860 ret = -ENOMEM; 1861 pr_err("%s: alloc rx temp buf failed\n", __func__); 1862 goto fail; 1863 } 1864 1865 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 1866 if (ret) 1867 return ret; 1868 /* OPP table is optional */ 1869 ret = devm_pm_opp_of_add_table(&pdev->dev); 1870 if (ret && ret != -ENODEV) { 1871 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1872 return ret; 1873 } 1874 1875 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1876 if (msm_host->irq < 0) { 1877 ret = msm_host->irq; 1878 dev_err(&pdev->dev, "failed to get irq: %d\n", ret); 1879 return ret; 1880 } 1881 1882 /* do not autoenable, will be enabled later */ 1883 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 1884 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 1885 "dsi_isr", msm_host); 1886 if (ret < 0) { 1887 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1888 msm_host->irq, ret); 1889 return ret; 1890 } 1891 1892 init_completion(&msm_host->dma_comp); 1893 init_completion(&msm_host->video_comp); 1894 mutex_init(&msm_host->dev_mutex); 1895 mutex_init(&msm_host->cmd_mutex); 1896 spin_lock_init(&msm_host->intr_lock); 1897 1898 /* setup workqueue */ 1899 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1900 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1901 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); 1902 1903 msm_dsi->id = msm_host->id; 1904 1905 DBG("Dsi Host %d initialized", msm_host->id); 1906 return 0; 1907 1908 fail: 1909 return ret; 1910 } 1911 1912 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1913 { 1914 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1915 1916 DBG(""); 1917 dsi_tx_buf_free(msm_host); 1918 if (msm_host->workqueue) { 1919 destroy_workqueue(msm_host->workqueue); 1920 msm_host->workqueue = NULL; 1921 } 1922 1923 mutex_destroy(&msm_host->cmd_mutex); 1924 mutex_destroy(&msm_host->dev_mutex); 1925 1926 pm_runtime_disable(&msm_host->pdev->dev); 1927 } 1928 1929 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1930 struct drm_device *dev) 1931 { 1932 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1933 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1934 int ret; 1935 1936 msm_host->dev = dev; 1937 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 1938 if (ret) { 1939 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1940 return ret; 1941 } 1942 1943 return 0; 1944 } 1945 1946 int msm_dsi_host_register(struct mipi_dsi_host *host) 1947 { 1948 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1949 int ret; 1950 1951 /* Register mipi dsi host */ 1952 if (!msm_host->registered) { 1953 host->dev = &msm_host->pdev->dev; 1954 host->ops = &dsi_host_ops; 1955 ret = mipi_dsi_host_register(host); 1956 if (ret) 1957 return ret; 1958 1959 msm_host->registered = true; 1960 } 1961 1962 return 0; 1963 } 1964 1965 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 1966 { 1967 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1968 1969 if (msm_host->registered) { 1970 mipi_dsi_host_unregister(host); 1971 host->dev = NULL; 1972 host->ops = NULL; 1973 msm_host->registered = false; 1974 } 1975 } 1976 1977 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 1978 const struct mipi_dsi_msg *msg) 1979 { 1980 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1981 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1982 1983 /* TODO: make sure dsi_cmd_mdp is idle. 1984 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 1985 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 1986 * How to handle the old versions? Wait for mdp cmd done? 1987 */ 1988 1989 /* 1990 * mdss interrupt is generated in mdp core clock domain 1991 * mdp clock need to be enabled to receive dsi interrupt 1992 */ 1993 pm_runtime_get_sync(&msm_host->pdev->dev); 1994 cfg_hnd->ops->link_clk_set_rate(msm_host); 1995 cfg_hnd->ops->link_clk_enable(msm_host); 1996 1997 /* TODO: vote for bus bandwidth */ 1998 1999 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2000 dsi_set_tx_power_mode(0, msm_host); 2001 2002 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2003 dsi_write(msm_host, REG_DSI_CTRL, 2004 msm_host->dma_cmd_ctrl_restore | 2005 DSI_CTRL_CMD_MODE_EN | 2006 DSI_CTRL_ENABLE); 2007 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2008 2009 return 0; 2010 } 2011 2012 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2013 const struct mipi_dsi_msg *msg) 2014 { 2015 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2016 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2017 2018 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2019 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2020 2021 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2022 dsi_set_tx_power_mode(1, msm_host); 2023 2024 /* TODO: unvote for bus bandwidth */ 2025 2026 cfg_hnd->ops->link_clk_disable(msm_host); 2027 pm_runtime_put(&msm_host->pdev->dev); 2028 } 2029 2030 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2031 const struct mipi_dsi_msg *msg) 2032 { 2033 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2034 2035 return dsi_cmds2buf_tx(msm_host, msg); 2036 } 2037 2038 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2039 const struct mipi_dsi_msg *msg) 2040 { 2041 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2042 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2043 int data_byte, rx_byte, dlen, end; 2044 int short_response, diff, pkt_size, ret = 0; 2045 char cmd; 2046 int rlen = msg->rx_len; 2047 u8 *buf; 2048 2049 if (rlen <= 2) { 2050 short_response = 1; 2051 pkt_size = rlen; 2052 rx_byte = 4; 2053 } else { 2054 short_response = 0; 2055 data_byte = 10; /* first read */ 2056 if (rlen < data_byte) 2057 pkt_size = rlen; 2058 else 2059 pkt_size = data_byte; 2060 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2061 } 2062 2063 buf = msm_host->rx_buf; 2064 end = 0; 2065 while (!end) { 2066 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2067 struct mipi_dsi_msg max_pkt_size_msg = { 2068 .channel = msg->channel, 2069 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2070 .tx_len = 2, 2071 .tx_buf = tx, 2072 }; 2073 2074 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2075 rlen, pkt_size, rx_byte); 2076 2077 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2078 if (ret < 2) { 2079 pr_err("%s: Set max pkt size failed, %d\n", 2080 __func__, ret); 2081 return -EINVAL; 2082 } 2083 2084 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2085 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2086 /* Clear the RDBK_DATA registers */ 2087 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2088 DSI_RDBK_DATA_CTRL_CLR); 2089 wmb(); /* make sure the RDBK registers are cleared */ 2090 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2091 wmb(); /* release cleared status before transfer */ 2092 } 2093 2094 ret = dsi_cmds2buf_tx(msm_host, msg); 2095 if (ret < msg->tx_len) { 2096 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2097 return ret; 2098 } 2099 2100 /* 2101 * once cmd_dma_done interrupt received, 2102 * return data from client is ready and stored 2103 * at RDBK_DATA register already 2104 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2105 * after that dcs header lost during shift into registers 2106 */ 2107 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2108 2109 if (dlen <= 0) 2110 return 0; 2111 2112 if (short_response) 2113 break; 2114 2115 if (rlen <= data_byte) { 2116 diff = data_byte - rlen; 2117 end = 1; 2118 } else { 2119 diff = 0; 2120 rlen -= data_byte; 2121 } 2122 2123 if (!end) { 2124 dlen -= 2; /* 2 crc */ 2125 dlen -= diff; 2126 buf += dlen; /* next start position */ 2127 data_byte = 14; /* NOT first read */ 2128 if (rlen < data_byte) 2129 pkt_size += rlen; 2130 else 2131 pkt_size += data_byte; 2132 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2133 } 2134 } 2135 2136 /* 2137 * For single Long read, if the requested rlen < 10, 2138 * we need to shift the start position of rx 2139 * data buffer to skip the bytes which are not 2140 * updated. 2141 */ 2142 if (pkt_size < 10 && !short_response) 2143 buf = msm_host->rx_buf + (10 - rlen); 2144 else 2145 buf = msm_host->rx_buf; 2146 2147 cmd = buf[0]; 2148 switch (cmd) { 2149 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2150 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2151 ret = 0; 2152 break; 2153 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2154 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2155 ret = dsi_short_read1_resp(buf, msg); 2156 break; 2157 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2158 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2159 ret = dsi_short_read2_resp(buf, msg); 2160 break; 2161 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2162 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2163 ret = dsi_long_read_resp(buf, msg); 2164 break; 2165 default: 2166 pr_warn("%s:Invalid response cmd\n", __func__); 2167 ret = 0; 2168 } 2169 2170 return ret; 2171 } 2172 2173 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2174 u32 len) 2175 { 2176 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2177 2178 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2179 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2180 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2181 2182 /* Make sure trigger happens */ 2183 wmb(); 2184 } 2185 2186 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2187 struct msm_dsi_phy *src_phy) 2188 { 2189 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2190 2191 msm_host->cphy_mode = src_phy->cphy_mode; 2192 } 2193 2194 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2195 { 2196 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2197 2198 DBG(""); 2199 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2200 /* Make sure fully reset */ 2201 wmb(); 2202 udelay(1000); 2203 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2204 udelay(100); 2205 } 2206 2207 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2208 struct msm_dsi_phy_clk_request *clk_req, 2209 bool is_bonded_dsi) 2210 { 2211 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2212 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2213 int ret; 2214 2215 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2216 if (ret) { 2217 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2218 return; 2219 } 2220 2221 /* CPHY transmits 16 bits over 7 clock cycles 2222 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2223 * so multiply by 7 to get the "bitclk rate" 2224 */ 2225 if (msm_host->cphy_mode) 2226 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2227 else 2228 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2229 clk_req->escclk_rate = msm_host->esc_clk_rate; 2230 } 2231 2232 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2233 { 2234 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2235 2236 enable_irq(msm_host->irq); 2237 } 2238 2239 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2240 { 2241 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2242 2243 disable_irq(msm_host->irq); 2244 } 2245 2246 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2247 { 2248 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2249 2250 dsi_op_mode_config(msm_host, 2251 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2252 2253 /* TODO: clock should be turned off for command mode, 2254 * and only turned on before MDP START. 2255 * This part of code should be enabled once mdp driver support it. 2256 */ 2257 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2258 * dsi_link_clk_disable(msm_host); 2259 * pm_runtime_put(&msm_host->pdev->dev); 2260 * } 2261 */ 2262 msm_host->enabled = true; 2263 return 0; 2264 } 2265 2266 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2267 { 2268 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2269 2270 msm_host->enabled = false; 2271 dsi_op_mode_config(msm_host, 2272 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2273 2274 /* Since we have disabled INTF, the video engine won't stop so that 2275 * the cmd engine will be blocked. 2276 * Reset to disable video engine so that we can send off cmd. 2277 */ 2278 dsi_sw_reset(msm_host); 2279 2280 return 0; 2281 } 2282 2283 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2284 { 2285 enum sfpb_ahb_arb_master_port_en en; 2286 2287 if (!msm_host->sfpb) 2288 return; 2289 2290 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2291 2292 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2293 SFPB_GPREG_MASTER_PORT_EN__MASK, 2294 SFPB_GPREG_MASTER_PORT_EN(en)); 2295 } 2296 2297 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2298 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2299 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2300 { 2301 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2302 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2303 int ret = 0; 2304 2305 mutex_lock(&msm_host->dev_mutex); 2306 if (msm_host->power_on) { 2307 DBG("dsi host already on"); 2308 goto unlock_ret; 2309 } 2310 2311 msm_dsi_sfpb_config(msm_host, true); 2312 2313 ret = dsi_host_regulator_enable(msm_host); 2314 if (ret) { 2315 pr_err("%s:Failed to enable vregs.ret=%d\n", 2316 __func__, ret); 2317 goto unlock_ret; 2318 } 2319 2320 pm_runtime_get_sync(&msm_host->pdev->dev); 2321 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2322 if (!ret) 2323 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2324 if (ret) { 2325 pr_err("%s: failed to enable link clocks. ret=%d\n", 2326 __func__, ret); 2327 goto fail_disable_reg; 2328 } 2329 2330 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2331 if (ret) { 2332 pr_err("%s: failed to set pinctrl default state, %d\n", 2333 __func__, ret); 2334 goto fail_disable_clk; 2335 } 2336 2337 dsi_timing_setup(msm_host, is_bonded_dsi); 2338 dsi_sw_reset(msm_host); 2339 dsi_ctrl_config(msm_host, true, phy_shared_timings, phy); 2340 2341 if (msm_host->disp_en_gpio) 2342 gpiod_set_value(msm_host->disp_en_gpio, 1); 2343 2344 msm_host->power_on = true; 2345 mutex_unlock(&msm_host->dev_mutex); 2346 2347 return 0; 2348 2349 fail_disable_clk: 2350 cfg_hnd->ops->link_clk_disable(msm_host); 2351 pm_runtime_put(&msm_host->pdev->dev); 2352 fail_disable_reg: 2353 dsi_host_regulator_disable(msm_host); 2354 unlock_ret: 2355 mutex_unlock(&msm_host->dev_mutex); 2356 return ret; 2357 } 2358 2359 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2360 { 2361 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2362 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2363 2364 mutex_lock(&msm_host->dev_mutex); 2365 if (!msm_host->power_on) { 2366 DBG("dsi host already off"); 2367 goto unlock_ret; 2368 } 2369 2370 dsi_ctrl_config(msm_host, false, NULL, NULL); 2371 2372 if (msm_host->disp_en_gpio) 2373 gpiod_set_value(msm_host->disp_en_gpio, 0); 2374 2375 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2376 2377 cfg_hnd->ops->link_clk_disable(msm_host); 2378 pm_runtime_put(&msm_host->pdev->dev); 2379 2380 dsi_host_regulator_disable(msm_host); 2381 2382 msm_dsi_sfpb_config(msm_host, false); 2383 2384 DBG("-"); 2385 2386 msm_host->power_on = false; 2387 2388 unlock_ret: 2389 mutex_unlock(&msm_host->dev_mutex); 2390 return 0; 2391 } 2392 2393 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2394 const struct drm_display_mode *mode) 2395 { 2396 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2397 2398 if (msm_host->mode) { 2399 drm_mode_destroy(msm_host->dev, msm_host->mode); 2400 msm_host->mode = NULL; 2401 } 2402 2403 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2404 if (!msm_host->mode) { 2405 pr_err("%s: cannot duplicate mode\n", __func__); 2406 return -ENOMEM; 2407 } 2408 2409 return 0; 2410 } 2411 2412 struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host) 2413 { 2414 return of_drm_find_panel(to_msm_dsi_host(host)->device_node); 2415 } 2416 2417 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2418 { 2419 return to_msm_dsi_host(host)->mode_flags; 2420 } 2421 2422 struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) 2423 { 2424 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2425 2426 return of_drm_find_bridge(msm_host->device_node); 2427 } 2428 2429 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2430 { 2431 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2432 2433 pm_runtime_get_sync(&msm_host->pdev->dev); 2434 2435 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2436 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2437 2438 pm_runtime_put_sync(&msm_host->pdev->dev); 2439 } 2440 2441 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2442 { 2443 u32 reg; 2444 2445 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2446 2447 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2448 /* draw checkered rectangle pattern */ 2449 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2450 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2451 /* use 24-bit RGB test pttern */ 2452 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2453 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2454 DSI_TPG_VIDEO_CONFIG_RGB); 2455 2456 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2457 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2458 2459 DBG("Video test pattern setup done\n"); 2460 } 2461 2462 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2463 { 2464 u32 reg; 2465 2466 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2467 2468 /* initial value for test pattern */ 2469 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2470 2471 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2472 2473 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2474 /* draw checkered rectangle pattern */ 2475 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2476 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2477 2478 DBG("Cmd test pattern setup done\n"); 2479 } 2480 2481 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2482 { 2483 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2484 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2485 u32 reg; 2486 2487 if (is_video_mode) 2488 msm_dsi_host_video_test_pattern_setup(msm_host); 2489 else 2490 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2491 2492 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2493 /* enable the test pattern generator */ 2494 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2495 2496 /* for command mode need to trigger one frame from tpg */ 2497 if (!is_video_mode) 2498 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2499 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2500 } 2501