1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of.h> 13 #include <linux/of_graph.h> 14 #include <linux/of_irq.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/pm_opp.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spinlock.h> 20 21 #include <video/mipi_display.h> 22 23 #include <drm/display/drm_dsc_helper.h> 24 #include <drm/drm_of.h> 25 26 #include "dsi.h" 27 #include "dsi.xml.h" 28 #include "sfpb.xml.h" 29 #include "dsi_cfg.h" 30 #include "msm_dsc_helper.h" 31 #include "msm_kms.h" 32 #include "msm_gem.h" 33 #include "phy/dsi_phy.h" 34 35 #define DSI_RESET_TOGGLE_DELAY_MS 20 36 37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 38 39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 40 { 41 u32 ver; 42 43 if (!major || !minor) 44 return -EINVAL; 45 46 /* 47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 48 * makes all other registers 4-byte shifted down. 49 * 50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 51 * older, we read the DSI_VERSION register without any shift(offset 52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 53 * the case of DSI6G, this has to be zero (the offset points to a 54 * scratch register which we never touch) 55 */ 56 57 ver = readl(base + REG_DSI_VERSION); 58 if (ver) { 59 /* older dsi host, there is no register shift */ 60 ver = FIELD(ver, DSI_VERSION_MAJOR); 61 if (ver <= MSM_DSI_VER_MAJOR_V2) { 62 /* old versions */ 63 *major = ver; 64 *minor = 0; 65 return 0; 66 } else { 67 return -EINVAL; 68 } 69 } else { 70 /* 71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 72 * registers are shifted down, read DSI_VERSION again with 73 * the shifted offset 74 */ 75 ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 76 ver = FIELD(ver, DSI_VERSION_MAJOR); 77 if (ver == MSM_DSI_VER_MAJOR_6G) { 78 /* 6G version */ 79 *major = ver; 80 *minor = readl(base + REG_DSI_6G_HW_VERSION); 81 return 0; 82 } else { 83 return -EINVAL; 84 } 85 } 86 } 87 88 #define DSI_ERR_STATE_ACK 0x0000 89 #define DSI_ERR_STATE_TIMEOUT 0x0001 90 #define DSI_ERR_STATE_DLN0_PHY 0x0002 91 #define DSI_ERR_STATE_FIFO 0x0004 92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 95 96 #define DSI_CLK_CTRL_ENABLE_CLKS \ 97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 101 102 struct msm_dsi_host { 103 struct mipi_dsi_host base; 104 105 struct platform_device *pdev; 106 struct drm_device *dev; 107 108 int id; 109 110 void __iomem *ctrl_base; 111 phys_addr_t ctrl_size; 112 struct regulator_bulk_data *supplies; 113 114 int num_bus_clks; 115 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 116 117 struct clk *byte_clk; 118 struct clk *esc_clk; 119 struct clk *pixel_clk; 120 struct clk *byte_intf_clk; 121 122 /* 123 * Clocks which needs to be properly parented between DISPCC and DSI PHY 124 * PLL: 125 */ 126 struct clk *byte_src_clk; 127 struct clk *pixel_src_clk; 128 struct clk *dsi_pll_byte_clk; 129 struct clk *dsi_pll_pixel_clk; 130 131 unsigned long byte_clk_rate; 132 unsigned long byte_intf_clk_rate; 133 unsigned long pixel_clk_rate; 134 unsigned long esc_clk_rate; 135 136 /* DSI v2 specific clocks */ 137 struct clk *src_clk; 138 139 unsigned long src_clk_rate; 140 141 const struct msm_dsi_cfg_handler *cfg_hnd; 142 143 struct completion dma_comp; 144 struct completion video_comp; 145 struct mutex dev_mutex; 146 struct mutex cmd_mutex; 147 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 148 149 u32 err_work_state; 150 struct work_struct err_work; 151 struct workqueue_struct *workqueue; 152 153 /* DSI 6G TX buffer*/ 154 struct drm_gem_object *tx_gem_obj; 155 struct drm_gpuvm *vm; 156 157 /* DSI v2 TX buffer */ 158 void *tx_buf; 159 dma_addr_t tx_buf_paddr; 160 161 int tx_size; 162 163 u8 *rx_buf; 164 165 struct regmap *sfpb; 166 167 struct drm_display_mode *mode; 168 struct drm_dsc_config *dsc; 169 170 /* connected device info */ 171 unsigned int channel; 172 unsigned int lanes; 173 enum mipi_dsi_pixel_format format; 174 unsigned long mode_flags; 175 176 /* lane data parsed via DT */ 177 int dlane_swap; 178 int num_data_lanes; 179 180 /* from phy DT */ 181 bool cphy_mode; 182 183 u32 dma_cmd_ctrl_restore; 184 185 bool registered; 186 bool power_on; 187 bool enabled; 188 int irq; 189 }; 190 191 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 192 { 193 return readl(msm_host->ctrl_base + reg); 194 } 195 196 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 197 { 198 writel(data, msm_host->ctrl_base + reg); 199 } 200 201 static const struct msm_dsi_cfg_handler * 202 dsi_get_config(struct msm_dsi_host *msm_host) 203 { 204 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 205 struct device *dev = &msm_host->pdev->dev; 206 struct clk *ahb_clk; 207 int ret; 208 u32 major = 0, minor = 0; 209 210 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 211 if (IS_ERR(ahb_clk)) { 212 dev_err_probe(dev, PTR_ERR(ahb_clk), "%s: cannot get interface clock\n", 213 __func__); 214 goto exit; 215 } 216 217 pm_runtime_get_sync(dev); 218 219 ret = clk_prepare_enable(ahb_clk); 220 if (ret) { 221 dev_err_probe(dev, ret, "%s: unable to enable ahb_clk\n", __func__); 222 goto runtime_put; 223 } 224 225 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 226 if (ret) { 227 dev_err_probe(dev, ret, "%s: Invalid version\n", __func__); 228 goto disable_clks; 229 } 230 231 cfg_hnd = msm_dsi_cfg_get(major, minor); 232 233 DBG("%s: Version %x:%x\n", __func__, major, minor); 234 235 disable_clks: 236 clk_disable_unprepare(ahb_clk); 237 runtime_put: 238 pm_runtime_put_sync(dev); 239 exit: 240 return cfg_hnd; 241 } 242 243 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 244 { 245 return container_of(host, struct msm_dsi_host, base); 246 } 247 248 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 249 { 250 struct platform_device *pdev = msm_host->pdev; 251 int ret = 0; 252 253 msm_host->src_clk = msm_clk_get(pdev, "src"); 254 255 if (IS_ERR(msm_host->src_clk)) { 256 ret = PTR_ERR(msm_host->src_clk); 257 pr_err("%s: can't find src clock. ret=%d\n", 258 __func__, ret); 259 msm_host->src_clk = NULL; 260 return ret; 261 } 262 263 return ret; 264 } 265 266 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 267 { 268 struct platform_device *pdev = msm_host->pdev; 269 int ret = 0; 270 271 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 272 if (IS_ERR(msm_host->byte_intf_clk)) { 273 ret = PTR_ERR(msm_host->byte_intf_clk); 274 pr_err("%s: can't find byte_intf clock. ret=%d\n", 275 __func__, ret); 276 } 277 278 return ret; 279 } 280 281 int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host) 282 { 283 struct device *dev = &msm_host->pdev->dev; 284 int ret; 285 286 ret = dsi_clk_init_6g_v2(msm_host); 287 if (ret) 288 return ret; 289 290 msm_host->byte_src_clk = devm_clk_get(dev, "byte_src"); 291 if (IS_ERR(msm_host->byte_src_clk)) 292 return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk), 293 "can't get byte_src clock\n"); 294 295 msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte"); 296 if (IS_ERR(msm_host->dsi_pll_byte_clk)) 297 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk), 298 "can't get dsi_pll_byte clock\n"); 299 300 msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src"); 301 if (IS_ERR(msm_host->pixel_src_clk)) 302 return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk), 303 "can't get pixel_src clock\n"); 304 305 msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel"); 306 if (IS_ERR(msm_host->dsi_pll_pixel_clk)) 307 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk), 308 "can't get dsi_pll_pixel clock\n"); 309 310 return 0; 311 } 312 313 static int dsi_clk_init(struct msm_dsi_host *msm_host) 314 { 315 struct platform_device *pdev = msm_host->pdev; 316 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 317 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 318 int i, ret = 0; 319 320 /* get bus clocks */ 321 for (i = 0; i < cfg->num_bus_clks; i++) 322 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 323 msm_host->num_bus_clks = cfg->num_bus_clks; 324 325 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 326 if (ret < 0) 327 return dev_err_probe(&pdev->dev, ret, "Unable to get clocks\n"); 328 329 /* get link and source clocks */ 330 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 331 if (IS_ERR(msm_host->byte_clk)) 332 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->byte_clk), 333 "%s: can't find dsi_byte clock\n", 334 __func__); 335 336 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 337 if (IS_ERR(msm_host->pixel_clk)) 338 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->pixel_clk), 339 "%s: can't find dsi_pixel clock\n", 340 __func__); 341 342 msm_host->esc_clk = msm_clk_get(pdev, "core"); 343 if (IS_ERR(msm_host->esc_clk)) 344 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->esc_clk), 345 "%s: can't find dsi_esc clock\n", 346 __func__); 347 348 if (cfg_hnd->ops->clk_init_ver) 349 ret = cfg_hnd->ops->clk_init_ver(msm_host); 350 351 return ret; 352 } 353 354 int msm_dsi_runtime_suspend(struct device *dev) 355 { 356 struct platform_device *pdev = to_platform_device(dev); 357 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 358 struct mipi_dsi_host *host = msm_dsi->host; 359 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 360 361 if (!msm_host->cfg_hnd) 362 return 0; 363 364 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 365 366 return 0; 367 } 368 369 int msm_dsi_runtime_resume(struct device *dev) 370 { 371 struct platform_device *pdev = to_platform_device(dev); 372 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 373 struct mipi_dsi_host *host = msm_dsi->host; 374 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 375 376 if (!msm_host->cfg_hnd) 377 return 0; 378 379 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 380 } 381 382 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 383 { 384 int ret; 385 386 DBG("Set clk rates: pclk=%lu, byteclk=%lu", 387 msm_host->pixel_clk_rate, msm_host->byte_clk_rate); 388 389 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 390 msm_host->byte_clk_rate); 391 if (ret) { 392 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 393 return ret; 394 } 395 396 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 397 if (ret) { 398 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 399 return ret; 400 } 401 402 if (msm_host->byte_intf_clk) { 403 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); 404 if (ret) { 405 pr_err("%s: Failed to set rate byte intf clk, %d\n", 406 __func__, ret); 407 return ret; 408 } 409 } 410 411 return 0; 412 } 413 414 int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host) 415 { 416 struct device *dev = &msm_host->pdev->dev; 417 int ret; 418 419 /* 420 * DSI PHY PLLs have to be enabled to allow reparenting to them, so 421 * cannot use assigned-clock-parents. 422 */ 423 ret = clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk); 424 if (ret) 425 dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret); 426 427 ret = clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_clk); 428 if (ret) 429 dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret); 430 431 return dsi_link_clk_set_rate_6g(msm_host); 432 } 433 434 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 435 { 436 int ret; 437 438 ret = clk_prepare_enable(msm_host->esc_clk); 439 if (ret) { 440 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 441 goto error; 442 } 443 444 ret = clk_prepare_enable(msm_host->byte_clk); 445 if (ret) { 446 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 447 goto byte_clk_err; 448 } 449 450 ret = clk_prepare_enable(msm_host->pixel_clk); 451 if (ret) { 452 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 453 goto pixel_clk_err; 454 } 455 456 ret = clk_prepare_enable(msm_host->byte_intf_clk); 457 if (ret) { 458 pr_err("%s: Failed to enable byte intf clk\n", 459 __func__); 460 goto byte_intf_clk_err; 461 } 462 463 return 0; 464 465 byte_intf_clk_err: 466 clk_disable_unprepare(msm_host->pixel_clk); 467 pixel_clk_err: 468 clk_disable_unprepare(msm_host->byte_clk); 469 byte_clk_err: 470 clk_disable_unprepare(msm_host->esc_clk); 471 error: 472 return ret; 473 } 474 475 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 476 { 477 int ret; 478 479 DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 480 msm_host->pixel_clk_rate, msm_host->byte_clk_rate, 481 msm_host->esc_clk_rate, msm_host->src_clk_rate); 482 483 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 484 if (ret) { 485 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 486 return ret; 487 } 488 489 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 490 if (ret) { 491 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 492 return ret; 493 } 494 495 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 496 if (ret) { 497 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 498 return ret; 499 } 500 501 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 502 if (ret) { 503 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 504 return ret; 505 } 506 507 return 0; 508 } 509 510 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 511 { 512 int ret; 513 514 ret = clk_prepare_enable(msm_host->byte_clk); 515 if (ret) { 516 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 517 goto error; 518 } 519 520 ret = clk_prepare_enable(msm_host->esc_clk); 521 if (ret) { 522 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 523 goto esc_clk_err; 524 } 525 526 ret = clk_prepare_enable(msm_host->src_clk); 527 if (ret) { 528 pr_err("%s: Failed to enable dsi src clk\n", __func__); 529 goto src_clk_err; 530 } 531 532 ret = clk_prepare_enable(msm_host->pixel_clk); 533 if (ret) { 534 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 535 goto pixel_clk_err; 536 } 537 538 return 0; 539 540 pixel_clk_err: 541 clk_disable_unprepare(msm_host->src_clk); 542 src_clk_err: 543 clk_disable_unprepare(msm_host->esc_clk); 544 esc_clk_err: 545 clk_disable_unprepare(msm_host->byte_clk); 546 error: 547 return ret; 548 } 549 550 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 551 { 552 /* Drop the performance state vote */ 553 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 554 clk_disable_unprepare(msm_host->esc_clk); 555 clk_disable_unprepare(msm_host->pixel_clk); 556 clk_disable_unprepare(msm_host->byte_intf_clk); 557 clk_disable_unprepare(msm_host->byte_clk); 558 } 559 560 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 561 { 562 clk_disable_unprepare(msm_host->pixel_clk); 563 clk_disable_unprepare(msm_host->src_clk); 564 clk_disable_unprepare(msm_host->esc_clk); 565 clk_disable_unprepare(msm_host->byte_clk); 566 } 567 568 /** 569 * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case 570 * @mode: The selected mode for the DSI output 571 * @dsc: DRM DSC configuration for this DSI output 572 * 573 * Adjust the pclk rate by calculating a new hdisplay proportional to 574 * the compression ratio such that: 575 * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp 576 * 577 * Porches do not need to be adjusted: 578 * - For VIDEO mode they are not compressed by DSC and are passed as is. 579 * - For CMD mode there are no actual porches. Instead these fields 580 * currently represent the overhead to the image data transfer. As such, they 581 * are calculated for the final mode parameters (after the compression) and 582 * are not to be adjusted too. 583 * 584 * FIXME: Reconsider this if/when CMD mode handling is rewritten to use 585 * transfer time and data overhead as a starting point of the calculations. 586 */ 587 static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, 588 const struct drm_dsc_config *dsc) 589 { 590 int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc), 591 dsc->bits_per_component * 3); 592 593 int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; 594 595 return mult_frac(mode->clock * 1000u, new_htotal, mode->htotal); 596 } 597 598 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, 599 const struct drm_dsc_config *dsc, bool is_bonded_dsi) 600 { 601 unsigned long pclk_rate; 602 603 pclk_rate = mode->clock * 1000u; 604 605 if (dsc) 606 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc); 607 608 /* 609 * For bonded DSI mode, the current DRM mode has the complete width of the 610 * panel. Since, the complete panel is driven by two DSI controllers, 611 * the clock rates have to be split between the two dsi controllers. 612 * Adjust the byte and pixel clock rates for each dsi host accordingly. 613 */ 614 if (is_bonded_dsi) 615 pclk_rate /= 2; 616 617 return pclk_rate; 618 } 619 620 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 621 const struct drm_display_mode *mode) 622 { 623 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 624 u8 lanes = msm_host->lanes; 625 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 626 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); 627 unsigned long pclk_bpp; 628 629 if (lanes == 0) { 630 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 631 lanes = 1; 632 } 633 634 /* CPHY "byte_clk" is in units of 16 bits */ 635 if (msm_host->cphy_mode) 636 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); 637 else 638 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); 639 640 return pclk_bpp; 641 } 642 643 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 644 { 645 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); 646 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 647 msm_host->mode); 648 649 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 650 msm_host->byte_clk_rate); 651 } 652 653 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 654 { 655 if (!msm_host->mode) { 656 pr_err("%s: mode not set\n", __func__); 657 return -EINVAL; 658 } 659 660 dsi_calc_pclk(msm_host, is_bonded_dsi); 661 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 662 return 0; 663 } 664 665 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 666 { 667 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 668 unsigned int esc_mhz, esc_div; 669 unsigned long byte_mhz; 670 671 dsi_calc_pclk(msm_host, is_bonded_dsi); 672 673 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); 674 675 /* 676 * esc clock is byte clock followed by a 4 bit divider, 677 * we need to find an escape clock frequency within the 678 * mipi DSI spec range within the maximum divider limit 679 * We iterate here between an escape clock frequencey 680 * between 20 Mhz to 5 Mhz and pick up the first one 681 * that can be supported by our divider 682 */ 683 684 byte_mhz = msm_host->byte_clk_rate / 1000000; 685 686 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 687 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 688 689 /* 690 * TODO: Ideally, we shouldn't know what sort of divider 691 * is available in mmss_cc, we're just assuming that 692 * it'll always be a 4 bit divider. Need to come up with 693 * a better way here. 694 */ 695 if (esc_div >= 1 && esc_div <= 16) 696 break; 697 } 698 699 if (esc_mhz < 5) 700 return -EINVAL; 701 702 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 703 704 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 705 msm_host->src_clk_rate); 706 707 return 0; 708 } 709 710 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 711 { 712 u32 intr; 713 unsigned long flags; 714 715 spin_lock_irqsave(&msm_host->intr_lock, flags); 716 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 717 718 if (enable) 719 intr |= mask; 720 else 721 intr &= ~mask; 722 723 DBG("intr=%x enable=%d", intr, enable); 724 725 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 726 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 727 } 728 729 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 730 { 731 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 732 return BURST_MODE; 733 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 734 return NON_BURST_SYNCH_PULSE; 735 736 return NON_BURST_SYNCH_EVENT; 737 } 738 739 static inline enum dsi_vid_dst_format 740 dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 741 { 742 switch (mipi_fmt) { 743 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 744 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 745 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 746 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 747 default: return VID_DST_FORMAT_RGB888; 748 } 749 } 750 751 static inline enum dsi_cmd_dst_format 752 dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 753 { 754 switch (mipi_fmt) { 755 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 756 case MIPI_DSI_FMT_RGB666_PACKED: 757 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 758 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 759 default: return CMD_DST_FORMAT_RGB888; 760 } 761 } 762 763 static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) 764 { 765 dsi_write(msm_host, REG_DSI_CTRL, 0); 766 } 767 768 bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host) 769 { 770 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 771 772 return msm_host->dsc && 773 (msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && 774 msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0); 775 } 776 777 static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, 778 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 779 { 780 u32 flags = msm_host->mode_flags; 781 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 782 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 783 u32 data = 0, lane_ctrl = 0; 784 785 if (flags & MIPI_DSI_MODE_VIDEO) { 786 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 787 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 788 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 789 data |= DSI_VID_CFG0_HFP_POWER_STOP; 790 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 791 data |= DSI_VID_CFG0_HBP_POWER_STOP; 792 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 793 data |= DSI_VID_CFG0_HSA_POWER_STOP; 794 /* Always set low power stop mode for BLLP 795 * to let command engine send packets 796 */ 797 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 798 DSI_VID_CFG0_BLLP_POWER_STOP; 799 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 800 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 801 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 802 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 803 data |= DSI_VID_CFG0_DATABUS_WIDEN; 804 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 805 806 /* Do not swap RGB colors */ 807 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 808 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 809 } else { 810 /* Do not swap RGB colors */ 811 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 812 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 813 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 814 815 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 816 DSI_CMD_CFG1_WR_MEM_CONTINUE( 817 MIPI_DCS_WRITE_MEMORY_CONTINUE); 818 /* Always insert DCS command */ 819 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 820 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 821 822 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 823 data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); 824 825 if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) 826 data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; 827 828 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 829 data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; 830 831 dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); 832 } 833 } 834 835 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 836 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 837 DSI_CMD_DMA_CTRL_LOW_POWER); 838 839 data = 0; 840 /* Always assume dedicated TE pin */ 841 data |= DSI_TRIG_CTRL_TE; 842 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 843 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 844 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 845 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 846 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 847 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 848 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 849 850 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 851 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 852 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 853 854 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 855 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 856 phy_shared_timings->clk_pre_inc_by_2) 857 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 858 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 859 860 data = 0; 861 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 862 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 863 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 864 865 /* allow only ack-err-status to generate interrupt */ 866 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 867 868 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 869 870 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 871 872 data = DSI_CTRL_CLK_EN; 873 874 DBG("lane number=%d", msm_host->lanes); 875 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 876 877 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 878 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 879 880 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 881 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 882 883 if (msm_dsi_phy_set_continuous_clock(phy, true)) 884 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 885 886 dsi_write(msm_host, REG_DSI_LANE_CTRL, 887 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 888 } 889 890 data |= DSI_CTRL_ENABLE; 891 892 dsi_write(msm_host, REG_DSI_CTRL, data); 893 894 if (msm_host->cphy_mode) 895 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 896 } 897 898 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode) 899 { 900 struct drm_dsc_config *dsc = msm_host->dsc; 901 u32 reg, reg_ctrl, reg_ctrl2; 902 u32 slice_per_intf, total_bytes_per_intf; 903 u32 pkt_per_line; 904 u32 eol_byte_num; 905 u32 bytes_per_pkt; 906 907 /* first calculate dsc parameters and then program 908 * compress mode registers 909 */ 910 slice_per_intf = dsc->slice_count; 911 912 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 913 bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ 914 915 eol_byte_num = total_bytes_per_intf % 3; 916 917 /* 918 * Typically, pkt_per_line = slice_per_intf * slice_per_pkt. 919 * 920 * Since the current driver only supports slice_per_pkt = 1, 921 * pkt_per_line will be equal to slice per intf for now. 922 */ 923 pkt_per_line = slice_per_intf; 924 925 if (is_cmd_mode) /* packet data type */ 926 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 927 else 928 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 929 930 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 931 * registers have similar offsets, so for below common code use 932 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 933 * 934 * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) 935 */ 936 if (pkt_per_line > 4) 937 drm_warn_once(msm_host->dev, "pkt_per_line too big"); 938 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 939 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 940 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 941 942 if (is_cmd_mode) { 943 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 944 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 945 946 reg_ctrl &= ~0xffff; 947 reg_ctrl |= reg; 948 949 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 950 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 951 952 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 953 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 954 } else { 955 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); 956 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 957 } 958 } 959 960 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 961 { 962 struct drm_display_mode *mode = msm_host->mode; 963 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 964 u32 h_total = mode->htotal; 965 u32 v_total = mode->vtotal; 966 u32 hs_end = mode->hsync_end - mode->hsync_start; 967 u32 vs_end = mode->vsync_end - mode->vsync_start; 968 u32 ha_start = h_total - mode->hsync_start; 969 u32 ha_end = ha_start + mode->hdisplay; 970 u32 va_start = v_total - mode->vsync_start; 971 u32 va_end = va_start + mode->vdisplay; 972 u32 hdisplay = mode->hdisplay; 973 u32 wc; 974 int ret; 975 bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base); 976 977 DBG(""); 978 979 /* 980 * For bonded DSI mode, the current DRM mode has 981 * the complete width of the panel. Since, the complete 982 * panel is driven by two DSI controllers, the horizontal 983 * timings have to be split between the two dsi controllers. 984 * Adjust the DSI host timing values accordingly. 985 */ 986 if (is_bonded_dsi) { 987 h_total /= 2; 988 hs_end /= 2; 989 ha_start /= 2; 990 ha_end /= 2; 991 hdisplay /= 2; 992 } 993 994 if (msm_host->dsc) { 995 struct drm_dsc_config *dsc = msm_host->dsc; 996 u32 bytes_per_pclk; 997 998 /* update dsc params with timing params */ 999 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 1000 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 1001 mode->hdisplay, mode->vdisplay); 1002 return; 1003 } 1004 1005 dsc->pic_width = mode->hdisplay; 1006 dsc->pic_height = mode->vdisplay; 1007 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 1008 1009 /* we do the calculations for dsc parameters here so that 1010 * panel can use these parameters 1011 */ 1012 ret = dsi_populate_dsc_params(msm_host, dsc); 1013 if (ret) 1014 return; 1015 1016 /* 1017 * DPU sends 3 bytes per pclk cycle to DSI. If widebus is 1018 * enabled, bus width is extended to 6 bytes. 1019 * 1020 * Calculate the number of pclks needed to transmit one line of 1021 * the compressed data. 1022 1023 * The back/font porch and pulse width are kept intact. For 1024 * VIDEO mode they represent timing parameters rather than 1025 * actual data transfer, see the documentation for 1026 * dsi_adjust_pclk_for_compression(). For CMD mode they are 1027 * unused anyway. 1028 */ 1029 h_total -= hdisplay; 1030 if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1031 bytes_per_pclk = 6; 1032 else 1033 bytes_per_pclk = 3; 1034 1035 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), bytes_per_pclk); 1036 1037 h_total += hdisplay; 1038 ha_end = ha_start + hdisplay; 1039 } 1040 1041 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 1042 if (msm_host->dsc) 1043 dsi_update_dsc_timing(msm_host, false); 1044 1045 dsi_write(msm_host, REG_DSI_ACTIVE_H, 1046 DSI_ACTIVE_H_START(ha_start) | 1047 DSI_ACTIVE_H_END(ha_end)); 1048 dsi_write(msm_host, REG_DSI_ACTIVE_V, 1049 DSI_ACTIVE_V_START(va_start) | 1050 DSI_ACTIVE_V_END(va_end)); 1051 dsi_write(msm_host, REG_DSI_TOTAL, 1052 DSI_TOTAL_H_TOTAL(h_total - 1) | 1053 DSI_TOTAL_V_TOTAL(v_total - 1)); 1054 1055 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 1056 DSI_ACTIVE_HSYNC_START(hs_start) | 1057 DSI_ACTIVE_HSYNC_END(hs_end)); 1058 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 1059 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 1060 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1061 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1062 } else { /* command mode */ 1063 if (msm_host->dsc) 1064 dsi_update_dsc_timing(msm_host, true); 1065 1066 /* image data and 1 byte write_memory_start cmd */ 1067 if (!msm_host->dsc) 1068 wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; 1069 else 1070 /* 1071 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. 1072 * Currently, the driver only supports default value of slice_per_pkt = 1 1073 * 1074 * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info 1075 * and adjust DSC math to account for slice_per_pkt. 1076 */ 1077 wc = msm_host->dsc->slice_chunk_size + 1; 1078 1079 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1080 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1081 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1082 msm_host->channel) | 1083 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1084 MIPI_DSI_DCS_LONG_WRITE)); 1085 1086 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1087 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1088 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1089 } 1090 } 1091 1092 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1093 { 1094 u32 ctrl; 1095 1096 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1097 1098 if (ctrl & DSI_CTRL_ENABLE) { 1099 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1100 /* 1101 * dsi controller need to be disabled before 1102 * clocks turned on 1103 */ 1104 wmb(); 1105 } 1106 1107 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1108 wmb(); /* clocks need to be enabled before reset */ 1109 1110 /* dsi controller can only be reset while clocks are running */ 1111 dsi_write(msm_host, REG_DSI_RESET, 1); 1112 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1113 dsi_write(msm_host, REG_DSI_RESET, 0); 1114 wmb(); /* controller out of reset */ 1115 1116 if (ctrl & DSI_CTRL_ENABLE) { 1117 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1118 wmb(); /* make sure dsi controller enabled again */ 1119 } 1120 } 1121 1122 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1123 bool video_mode, bool enable) 1124 { 1125 u32 dsi_ctrl; 1126 1127 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1128 1129 if (!enable) { 1130 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1131 DSI_CTRL_CMD_MODE_EN); 1132 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1133 DSI_IRQ_MASK_VIDEO_DONE, 0); 1134 } else { 1135 if (video_mode) { 1136 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1137 } else { /* command mode */ 1138 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1139 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1140 } 1141 dsi_ctrl |= DSI_CTRL_ENABLE; 1142 } 1143 1144 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1145 } 1146 1147 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1148 { 1149 u32 data; 1150 1151 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1152 1153 if (mode == 0) 1154 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1155 else 1156 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1157 1158 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1159 } 1160 1161 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1162 { 1163 u32 ret = 0; 1164 struct device *dev = &msm_host->pdev->dev; 1165 1166 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1167 1168 reinit_completion(&msm_host->video_comp); 1169 1170 ret = wait_for_completion_timeout(&msm_host->video_comp, 1171 msecs_to_jiffies(70)); 1172 1173 if (ret == 0) 1174 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1175 1176 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1177 } 1178 1179 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1180 { 1181 u32 data; 1182 1183 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1184 return; 1185 1186 data = dsi_read(msm_host, REG_DSI_STATUS0); 1187 1188 /* if video mode engine is not busy, its because 1189 * either timing engine was not turned on or the 1190 * DSI controller has finished transmitting the video 1191 * data already, so no need to wait in those cases 1192 */ 1193 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1194 return; 1195 1196 if (msm_host->power_on && msm_host->enabled) { 1197 dsi_wait4video_done(msm_host); 1198 /* delay 4 ms to skip BLLP */ 1199 usleep_range(2000, 4000); 1200 } 1201 } 1202 1203 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1204 { 1205 struct drm_device *dev = msm_host->dev; 1206 struct msm_drm_private *priv = dev->dev_private; 1207 uint64_t iova; 1208 u8 *data; 1209 1210 msm_host->vm = drm_gpuvm_get(priv->kms->vm); 1211 1212 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1213 msm_host->vm, 1214 &msm_host->tx_gem_obj, &iova); 1215 1216 if (IS_ERR(data)) { 1217 msm_host->tx_gem_obj = NULL; 1218 return PTR_ERR(data); 1219 } 1220 1221 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1222 1223 msm_host->tx_size = msm_host->tx_gem_obj->size; 1224 1225 return 0; 1226 } 1227 1228 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1229 { 1230 struct drm_device *dev = msm_host->dev; 1231 1232 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1233 &msm_host->tx_buf_paddr, GFP_KERNEL); 1234 if (!msm_host->tx_buf) 1235 return -ENOMEM; 1236 1237 msm_host->tx_size = size; 1238 1239 return 0; 1240 } 1241 1242 void msm_dsi_tx_buf_free(struct mipi_dsi_host *host) 1243 { 1244 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1245 struct drm_device *dev = msm_host->dev; 1246 1247 /* 1248 * This is possible if we're tearing down before we've had a chance to 1249 * fully initialize. A very real possibility if our probe is deferred, 1250 * in which case we'll hit msm_dsi_host_destroy() without having run 1251 * through the dsi_tx_buf_alloc(). 1252 */ 1253 if (!dev) 1254 return; 1255 1256 if (msm_host->tx_gem_obj) { 1257 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->vm); 1258 drm_gpuvm_put(msm_host->vm); 1259 msm_host->tx_gem_obj = NULL; 1260 msm_host->vm = NULL; 1261 } 1262 1263 if (msm_host->tx_buf) 1264 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1265 msm_host->tx_buf_paddr); 1266 } 1267 1268 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1269 { 1270 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1271 } 1272 1273 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1274 { 1275 return msm_host->tx_buf; 1276 } 1277 1278 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1279 { 1280 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1281 } 1282 1283 /* 1284 * prepare cmd buffer to be txed 1285 */ 1286 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1287 const struct mipi_dsi_msg *msg) 1288 { 1289 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1290 struct mipi_dsi_packet packet; 1291 int len; 1292 int ret; 1293 u8 *data; 1294 1295 ret = mipi_dsi_create_packet(&packet, msg); 1296 if (ret) { 1297 pr_err("%s: create packet failed, %d\n", __func__, ret); 1298 return ret; 1299 } 1300 len = (packet.size + 3) & (~0x3); 1301 1302 if (len > msm_host->tx_size) { 1303 pr_err("%s: packet size is too big\n", __func__); 1304 return -EINVAL; 1305 } 1306 1307 data = cfg_hnd->ops->tx_buf_get(msm_host); 1308 if (IS_ERR(data)) { 1309 ret = PTR_ERR(data); 1310 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1311 return ret; 1312 } 1313 1314 /* MSM specific command format in memory */ 1315 data[0] = packet.header[1]; 1316 data[1] = packet.header[2]; 1317 data[2] = packet.header[0]; 1318 data[3] = BIT(7); /* Last packet */ 1319 if (mipi_dsi_packet_format_is_long(msg->type)) 1320 data[3] |= BIT(6); 1321 if (msg->rx_buf && msg->rx_len) 1322 data[3] |= BIT(5); 1323 1324 /* Long packet */ 1325 if (packet.payload && packet.payload_length) 1326 memcpy(data + 4, packet.payload, packet.payload_length); 1327 1328 /* Append 0xff to the end */ 1329 if (packet.size < len) 1330 memset(data + packet.size, 0xff, len - packet.size); 1331 1332 if (cfg_hnd->ops->tx_buf_put) 1333 cfg_hnd->ops->tx_buf_put(msm_host); 1334 1335 return len; 1336 } 1337 1338 /* 1339 * dsi_short_read1_resp: 1 parameter 1340 */ 1341 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1342 { 1343 u8 *data = msg->rx_buf; 1344 1345 if (data && (msg->rx_len >= 1)) { 1346 *data = buf[1]; /* strip out dcs type */ 1347 return 1; 1348 } 1349 1350 pr_err("%s: read data does not match with rx_buf len %zu\n", 1351 __func__, msg->rx_len); 1352 return -EINVAL; 1353 } 1354 1355 /* 1356 * dsi_short_read2_resp: 2 parameter 1357 */ 1358 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1359 { 1360 u8 *data = msg->rx_buf; 1361 1362 if (data && (msg->rx_len >= 2)) { 1363 data[0] = buf[1]; /* strip out dcs type */ 1364 data[1] = buf[2]; 1365 return 2; 1366 } 1367 1368 pr_err("%s: read data does not match with rx_buf len %zu\n", 1369 __func__, msg->rx_len); 1370 return -EINVAL; 1371 } 1372 1373 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1374 { 1375 /* strip out 4 byte dcs header */ 1376 if (msg->rx_buf && msg->rx_len) 1377 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1378 1379 return msg->rx_len; 1380 } 1381 1382 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1383 { 1384 struct drm_device *dev = msm_host->dev; 1385 struct msm_drm_private *priv = dev->dev_private; 1386 1387 if (!dma_base) 1388 return -EINVAL; 1389 1390 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1391 priv->kms->vm, dma_base); 1392 } 1393 1394 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1395 { 1396 if (!dma_base) 1397 return -EINVAL; 1398 1399 *dma_base = msm_host->tx_buf_paddr; 1400 return 0; 1401 } 1402 1403 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1404 { 1405 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1406 int ret; 1407 uint64_t dma_base; 1408 bool triggered; 1409 1410 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1411 if (ret) { 1412 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1413 return ret; 1414 } 1415 1416 reinit_completion(&msm_host->dma_comp); 1417 1418 dsi_wait4video_eng_busy(msm_host); 1419 1420 triggered = msm_dsi_manager_cmd_xfer_trigger( 1421 msm_host->id, dma_base, len); 1422 if (triggered) { 1423 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1424 msecs_to_jiffies(200)); 1425 DBG("ret=%d", ret); 1426 if (ret == 0) 1427 ret = -ETIMEDOUT; 1428 else 1429 ret = len; 1430 } else { 1431 ret = len; 1432 } 1433 1434 return ret; 1435 } 1436 1437 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1438 u8 *buf, int rx_byte, int pkt_size) 1439 { 1440 u32 *temp, data; 1441 int i, j = 0, cnt; 1442 u32 read_cnt; 1443 u8 reg[16]; 1444 int repeated_bytes = 0; 1445 int buf_offset = buf - msm_host->rx_buf; 1446 1447 temp = (u32 *)reg; 1448 cnt = (rx_byte + 3) >> 2; 1449 if (cnt > 4) 1450 cnt = 4; /* 4 x 32 bits registers only */ 1451 1452 if (rx_byte == 4) 1453 read_cnt = 4; 1454 else 1455 read_cnt = pkt_size + 6; 1456 1457 /* 1458 * In case of multiple reads from the panel, after the first read, there 1459 * is possibility that there are some bytes in the payload repeating in 1460 * the RDBK_DATA registers. Since we read all the parameters from the 1461 * panel right from the first byte for every pass. We need to skip the 1462 * repeating bytes and then append the new parameters to the rx buffer. 1463 */ 1464 if (read_cnt > 16) { 1465 int bytes_shifted; 1466 /* Any data more than 16 bytes will be shifted out. 1467 * The temp read buffer should already contain these bytes. 1468 * The remaining bytes in read buffer are the repeated bytes. 1469 */ 1470 bytes_shifted = read_cnt - 16; 1471 repeated_bytes = buf_offset - bytes_shifted; 1472 } 1473 1474 for (i = cnt - 1; i >= 0; i--) { 1475 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1476 *temp++ = ntohl(data); /* to host byte order */ 1477 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1478 } 1479 1480 for (i = repeated_bytes; i < 16; i++) 1481 buf[j++] = reg[i]; 1482 1483 return j; 1484 } 1485 1486 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1487 const struct mipi_dsi_msg *msg) 1488 { 1489 int len, ret; 1490 int bllp_len = msm_host->mode->hdisplay * 1491 mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; 1492 1493 len = dsi_cmd_dma_add(msm_host, msg); 1494 if (len < 0) { 1495 pr_err("%s: failed to add cmd type = 0x%x\n", 1496 __func__, msg->type); 1497 return len; 1498 } 1499 1500 /* 1501 * for video mode, do not send cmds more than 1502 * one pixel line, since it only transmit it 1503 * during BLLP. 1504 * 1505 * TODO: if the command is sent in LP mode, the bit rate is only 1506 * half of esc clk rate. In this case, if the video is already 1507 * actively streaming, we need to check more carefully if the 1508 * command can be fit into one BLLP. 1509 */ 1510 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1511 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1512 __func__, len); 1513 return -EINVAL; 1514 } 1515 1516 ret = dsi_cmd_dma_tx(msm_host, len); 1517 if (ret < 0) { 1518 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1519 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1520 return ret; 1521 } else if (ret < len) { 1522 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1523 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1524 return -EIO; 1525 } 1526 1527 return len; 1528 } 1529 1530 static void dsi_err_worker(struct work_struct *work) 1531 { 1532 struct msm_dsi_host *msm_host = 1533 container_of(work, struct msm_dsi_host, err_work); 1534 u32 status = msm_host->err_work_state; 1535 1536 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1537 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1538 dsi_sw_reset(msm_host); 1539 1540 /* It is safe to clear here because error irq is disabled. */ 1541 msm_host->err_work_state = 0; 1542 1543 /* enable dsi error interrupt */ 1544 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1545 } 1546 1547 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1548 { 1549 u32 status; 1550 1551 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1552 1553 if (status) { 1554 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1555 /* Writing of an extra 0 needed to clear error bits */ 1556 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1557 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1558 } 1559 } 1560 1561 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1562 { 1563 u32 status; 1564 1565 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1566 1567 if (status) { 1568 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1569 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1570 } 1571 } 1572 1573 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1574 { 1575 u32 status; 1576 1577 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1578 1579 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1580 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1581 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1582 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1583 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1584 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1585 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1586 } 1587 } 1588 1589 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1590 { 1591 u32 status; 1592 1593 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1594 1595 /* fifo underflow, overflow */ 1596 if (status) { 1597 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1598 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1599 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1600 msm_host->err_work_state |= 1601 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1602 } 1603 } 1604 1605 static void dsi_status(struct msm_dsi_host *msm_host) 1606 { 1607 u32 status; 1608 1609 status = dsi_read(msm_host, REG_DSI_STATUS0); 1610 1611 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1612 dsi_write(msm_host, REG_DSI_STATUS0, status); 1613 msm_host->err_work_state |= 1614 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1615 } 1616 } 1617 1618 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1619 { 1620 u32 status; 1621 1622 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1623 1624 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1625 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1626 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1627 } 1628 } 1629 1630 static void dsi_error(struct msm_dsi_host *msm_host) 1631 { 1632 /* disable dsi error interrupt */ 1633 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1634 1635 dsi_clk_status(msm_host); 1636 dsi_fifo_status(msm_host); 1637 dsi_ack_err_status(msm_host); 1638 dsi_timeout_status(msm_host); 1639 dsi_status(msm_host); 1640 dsi_dln0_phy_err(msm_host); 1641 1642 queue_work(msm_host->workqueue, &msm_host->err_work); 1643 } 1644 1645 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1646 { 1647 struct msm_dsi_host *msm_host = ptr; 1648 u32 isr; 1649 unsigned long flags; 1650 1651 if (!msm_host->ctrl_base) 1652 return IRQ_HANDLED; 1653 1654 spin_lock_irqsave(&msm_host->intr_lock, flags); 1655 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1656 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1657 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1658 1659 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1660 1661 if (isr & DSI_IRQ_ERROR) 1662 dsi_error(msm_host); 1663 1664 if (isr & DSI_IRQ_VIDEO_DONE) 1665 complete(&msm_host->video_comp); 1666 1667 if (isr & DSI_IRQ_CMD_DMA_DONE) 1668 complete(&msm_host->dma_comp); 1669 1670 return IRQ_HANDLED; 1671 } 1672 1673 static int dsi_host_attach(struct mipi_dsi_host *host, 1674 struct mipi_dsi_device *dsi) 1675 { 1676 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1677 int ret; 1678 1679 if (dsi->lanes > msm_host->num_data_lanes) 1680 return -EINVAL; 1681 1682 msm_host->channel = dsi->channel; 1683 msm_host->lanes = dsi->lanes; 1684 msm_host->format = dsi->format; 1685 msm_host->mode_flags = dsi->mode_flags; 1686 if (dsi->dsc) 1687 msm_host->dsc = dsi->dsc; 1688 1689 ret = dsi_dev_attach(msm_host->pdev); 1690 if (ret) 1691 return ret; 1692 1693 DBG("id=%d", msm_host->id); 1694 1695 return 0; 1696 } 1697 1698 static int dsi_host_detach(struct mipi_dsi_host *host, 1699 struct mipi_dsi_device *dsi) 1700 { 1701 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1702 1703 dsi_dev_detach(msm_host->pdev); 1704 1705 DBG("id=%d", msm_host->id); 1706 1707 return 0; 1708 } 1709 1710 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1711 const struct mipi_dsi_msg *msg) 1712 { 1713 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1714 int ret; 1715 1716 if (!msg || !msm_host->power_on) 1717 return -EINVAL; 1718 1719 mutex_lock(&msm_host->cmd_mutex); 1720 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1721 mutex_unlock(&msm_host->cmd_mutex); 1722 1723 return ret; 1724 } 1725 1726 static const struct mipi_dsi_host_ops dsi_host_ops = { 1727 .attach = dsi_host_attach, 1728 .detach = dsi_host_detach, 1729 .transfer = dsi_host_transfer, 1730 }; 1731 1732 /* 1733 * List of supported physical to logical lane mappings. 1734 * For example, the 2nd entry represents the following mapping: 1735 * 1736 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1737 */ 1738 static const int supported_data_lane_swaps[][4] = { 1739 { 0, 1, 2, 3 }, 1740 { 3, 0, 1, 2 }, 1741 { 2, 3, 0, 1 }, 1742 { 1, 2, 3, 0 }, 1743 { 0, 3, 2, 1 }, 1744 { 1, 0, 3, 2 }, 1745 { 2, 1, 0, 3 }, 1746 { 3, 2, 1, 0 }, 1747 }; 1748 1749 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1750 struct device_node *ep) 1751 { 1752 struct device *dev = &msm_host->pdev->dev; 1753 struct property *prop; 1754 u32 lane_map[4]; 1755 int ret, i, len, num_lanes; 1756 1757 prop = of_find_property(ep, "data-lanes", &len); 1758 if (!prop) { 1759 DRM_DEV_DEBUG(dev, 1760 "failed to find data lane mapping, using default\n"); 1761 /* Set the number of date lanes to 4 by default. */ 1762 msm_host->num_data_lanes = 4; 1763 return 0; 1764 } 1765 1766 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1767 if (num_lanes < 0) { 1768 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1769 return num_lanes; 1770 } 1771 1772 msm_host->num_data_lanes = num_lanes; 1773 1774 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1775 num_lanes); 1776 if (ret) { 1777 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1778 return ret; 1779 } 1780 1781 /* 1782 * compare DT specified physical-logical lane mappings with the ones 1783 * supported by hardware 1784 */ 1785 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1786 const int *swap = supported_data_lane_swaps[i]; 1787 int j; 1788 1789 /* 1790 * the data-lanes array we get from DT has a logical->physical 1791 * mapping. The "data lane swap" register field represents 1792 * supported configurations in a physical->logical mapping. 1793 * Translate the DT mapping to what we understand and find a 1794 * configuration that works. 1795 */ 1796 for (j = 0; j < num_lanes; j++) { 1797 if (lane_map[j] < 0 || lane_map[j] > 3) 1798 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1799 lane_map[j]); 1800 1801 if (swap[lane_map[j]] != j) 1802 break; 1803 } 1804 1805 if (j == num_lanes) { 1806 msm_host->dlane_swap = i; 1807 return 0; 1808 } 1809 } 1810 1811 return -EINVAL; 1812 } 1813 1814 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1815 { 1816 int ret; 1817 1818 if (dsc->bits_per_pixel & 0xf) { 1819 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1820 return -EINVAL; 1821 } 1822 1823 switch (dsc->bits_per_component) { 1824 case 8: 1825 case 10: 1826 case 12: 1827 /* 1828 * Only 8, 10, and 12 bpc are supported for DSC 1.1 block. 1829 * If additional bpc values need to be supported, update 1830 * this quard with the appropriate DSC version verification. 1831 */ 1832 break; 1833 default: 1834 DRM_DEV_ERROR(&msm_host->pdev->dev, 1835 "Unsupported bits_per_component value: %d\n", 1836 dsc->bits_per_component); 1837 return -EOPNOTSUPP; 1838 } 1839 1840 dsc->simple_422 = 0; 1841 dsc->convert_rgb = 1; 1842 dsc->vbr_enable = 0; 1843 1844 drm_dsc_set_const_params(dsc); 1845 drm_dsc_set_rc_buf_thresh(dsc); 1846 1847 /* DPU supports only pre-SCR panels */ 1848 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); 1849 if (ret) { 1850 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); 1851 return ret; 1852 } 1853 1854 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); 1855 dsc->line_buf_depth = dsc->bits_per_component + 1; 1856 1857 return drm_dsc_compute_rc_parameters(dsc); 1858 } 1859 1860 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1861 { 1862 struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev); 1863 struct device *dev = &msm_host->pdev->dev; 1864 struct device_node *np = dev->of_node; 1865 struct device_node *endpoint; 1866 const char *te_source; 1867 int ret = 0; 1868 1869 /* 1870 * Get the endpoint of the output port of the DSI host. In our case, 1871 * this is mapped to port number with reg = 1. Don't return an error if 1872 * the remote endpoint isn't defined. It's possible that there is 1873 * nothing connected to the dsi output. 1874 */ 1875 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1876 if (!endpoint) { 1877 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1878 return 0; 1879 } 1880 1881 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1882 if (ret) { 1883 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1884 __func__, ret); 1885 ret = -EINVAL; 1886 goto err; 1887 } 1888 1889 ret = of_property_read_string(endpoint, "qcom,te-source", &te_source); 1890 if (ret && ret != -EINVAL) { 1891 DRM_DEV_ERROR(dev, "%s: invalid TE source configuration %d\n", 1892 __func__, ret); 1893 goto err; 1894 } 1895 if (!ret) { 1896 msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL); 1897 if (!msm_dsi->te_source) { 1898 DRM_DEV_ERROR(dev, "%s: failed to allocate te_source\n", 1899 __func__); 1900 ret = -ENOMEM; 1901 goto err; 1902 } 1903 } 1904 ret = 0; 1905 1906 if (of_property_present(np, "syscon-sfpb")) { 1907 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1908 "syscon-sfpb"); 1909 if (IS_ERR(msm_host->sfpb)) { 1910 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1911 __func__); 1912 ret = PTR_ERR(msm_host->sfpb); 1913 } 1914 } 1915 1916 err: 1917 of_node_put(endpoint); 1918 1919 return ret; 1920 } 1921 1922 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1923 { 1924 struct platform_device *pdev = msm_host->pdev; 1925 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1926 struct resource *res; 1927 int i, j; 1928 1929 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1930 if (!res) 1931 return -EINVAL; 1932 1933 for (i = 0; i < VARIANTS_MAX; i++) 1934 for (j = 0; j < DSI_MAX; j++) 1935 if (cfg->io_start[i][j] == res->start) 1936 return j; 1937 1938 return -EINVAL; 1939 } 1940 1941 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1942 { 1943 struct msm_dsi_host *msm_host = NULL; 1944 struct platform_device *pdev = msm_dsi->pdev; 1945 const struct msm_dsi_config *cfg; 1946 int ret; 1947 1948 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1949 if (!msm_host) 1950 return -ENOMEM; 1951 1952 msm_host->pdev = pdev; 1953 msm_dsi->host = &msm_host->base; 1954 1955 ret = dsi_host_parse_dt(msm_host); 1956 if (ret) 1957 return dev_err_probe(&pdev->dev, ret, "%s: failed to parse dt\n", 1958 __func__); 1959 1960 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 1961 if (IS_ERR(msm_host->ctrl_base)) 1962 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->ctrl_base), 1963 "%s: unable to map Dsi ctrl base\n", __func__); 1964 1965 pm_runtime_enable(&pdev->dev); 1966 1967 msm_host->cfg_hnd = dsi_get_config(msm_host); 1968 if (!msm_host->cfg_hnd) 1969 return dev_err_probe(&pdev->dev, -EINVAL, 1970 "%s: get config failed\n", __func__); 1971 cfg = msm_host->cfg_hnd->cfg; 1972 1973 msm_host->id = dsi_host_get_id(msm_host); 1974 if (msm_host->id < 0) 1975 return dev_err_probe(&pdev->dev, msm_host->id, 1976 "%s: unable to identify DSI host index\n", 1977 __func__); 1978 1979 /* fixup base address by io offset */ 1980 msm_host->ctrl_base += cfg->io_offset; 1981 1982 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 1983 cfg->regulator_data, 1984 &msm_host->supplies); 1985 if (ret) 1986 return ret; 1987 1988 ret = dsi_clk_init(msm_host); 1989 if (ret) 1990 return dev_err_probe(&pdev->dev, ret, "%s: unable to initialize dsi clks\n", __func__); 1991 1992 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1993 if (!msm_host->rx_buf) 1994 return -ENOMEM; 1995 1996 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 1997 if (ret) 1998 return ret; 1999 /* OPP table is optional */ 2000 ret = devm_pm_opp_of_add_table(&pdev->dev); 2001 if (ret && ret != -ENODEV) 2002 return dev_err_probe(&pdev->dev, ret, "invalid OPP table in device tree\n"); 2003 2004 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 2005 if (!msm_host->irq) 2006 return dev_err_probe(&pdev->dev, -EINVAL, "failed to get irq\n"); 2007 2008 /* do not autoenable, will be enabled later */ 2009 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 2010 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 2011 "dsi_isr", msm_host); 2012 if (ret < 0) 2013 return dev_err_probe(&pdev->dev, ret, "failed to request IRQ%u\n", 2014 msm_host->irq); 2015 2016 init_completion(&msm_host->dma_comp); 2017 init_completion(&msm_host->video_comp); 2018 mutex_init(&msm_host->dev_mutex); 2019 mutex_init(&msm_host->cmd_mutex); 2020 spin_lock_init(&msm_host->intr_lock); 2021 2022 /* setup workqueue */ 2023 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 2024 if (!msm_host->workqueue) 2025 return -ENOMEM; 2026 2027 INIT_WORK(&msm_host->err_work, dsi_err_worker); 2028 2029 msm_dsi->id = msm_host->id; 2030 2031 DBG("Dsi Host %d initialized", msm_host->id); 2032 return 0; 2033 } 2034 2035 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 2036 { 2037 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2038 2039 DBG(""); 2040 if (msm_host->workqueue) { 2041 destroy_workqueue(msm_host->workqueue); 2042 msm_host->workqueue = NULL; 2043 } 2044 2045 mutex_destroy(&msm_host->cmd_mutex); 2046 mutex_destroy(&msm_host->dev_mutex); 2047 2048 pm_runtime_disable(&msm_host->pdev->dev); 2049 } 2050 2051 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 2052 struct drm_device *dev) 2053 { 2054 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2055 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2056 int ret; 2057 2058 msm_host->dev = dev; 2059 2060 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2061 if (ret) { 2062 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2063 return ret; 2064 } 2065 2066 return 0; 2067 } 2068 2069 int msm_dsi_host_register(struct mipi_dsi_host *host) 2070 { 2071 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2072 int ret; 2073 2074 /* Register mipi dsi host */ 2075 if (!msm_host->registered) { 2076 host->dev = &msm_host->pdev->dev; 2077 host->ops = &dsi_host_ops; 2078 ret = mipi_dsi_host_register(host); 2079 if (ret) 2080 return ret; 2081 2082 msm_host->registered = true; 2083 } 2084 2085 return 0; 2086 } 2087 2088 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2089 { 2090 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2091 2092 if (msm_host->registered) { 2093 mipi_dsi_host_unregister(host); 2094 host->dev = NULL; 2095 host->ops = NULL; 2096 msm_host->registered = false; 2097 } 2098 } 2099 2100 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2101 const struct mipi_dsi_msg *msg) 2102 { 2103 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2104 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2105 2106 /* TODO: make sure dsi_cmd_mdp is idle. 2107 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2108 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2109 * How to handle the old versions? Wait for mdp cmd done? 2110 */ 2111 2112 /* 2113 * mdss interrupt is generated in mdp core clock domain 2114 * mdp clock need to be enabled to receive dsi interrupt 2115 */ 2116 pm_runtime_get_sync(&msm_host->pdev->dev); 2117 cfg_hnd->ops->link_clk_set_rate(msm_host); 2118 cfg_hnd->ops->link_clk_enable(msm_host); 2119 2120 /* TODO: vote for bus bandwidth */ 2121 2122 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2123 dsi_set_tx_power_mode(0, msm_host); 2124 2125 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2126 dsi_write(msm_host, REG_DSI_CTRL, 2127 msm_host->dma_cmd_ctrl_restore | 2128 DSI_CTRL_CMD_MODE_EN | 2129 DSI_CTRL_ENABLE); 2130 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2131 2132 return 0; 2133 } 2134 2135 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2136 const struct mipi_dsi_msg *msg) 2137 { 2138 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2139 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2140 2141 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2142 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2143 2144 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2145 dsi_set_tx_power_mode(1, msm_host); 2146 2147 /* TODO: unvote for bus bandwidth */ 2148 2149 cfg_hnd->ops->link_clk_disable(msm_host); 2150 pm_runtime_put(&msm_host->pdev->dev); 2151 } 2152 2153 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2154 const struct mipi_dsi_msg *msg) 2155 { 2156 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2157 2158 return dsi_cmds2buf_tx(msm_host, msg); 2159 } 2160 2161 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2162 const struct mipi_dsi_msg *msg) 2163 { 2164 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2165 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2166 int data_byte, rx_byte, dlen, end; 2167 int short_response, diff, pkt_size, ret = 0; 2168 char cmd; 2169 int rlen = msg->rx_len; 2170 u8 *buf; 2171 2172 if (rlen <= 2) { 2173 short_response = 1; 2174 pkt_size = rlen; 2175 rx_byte = 4; 2176 } else { 2177 short_response = 0; 2178 data_byte = 10; /* first read */ 2179 if (rlen < data_byte) 2180 pkt_size = rlen; 2181 else 2182 pkt_size = data_byte; 2183 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2184 } 2185 2186 buf = msm_host->rx_buf; 2187 end = 0; 2188 while (!end) { 2189 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2190 struct mipi_dsi_msg max_pkt_size_msg = { 2191 .channel = msg->channel, 2192 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2193 .tx_len = 2, 2194 .tx_buf = tx, 2195 }; 2196 2197 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2198 rlen, pkt_size, rx_byte); 2199 2200 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2201 if (ret < 2) { 2202 pr_err("%s: Set max pkt size failed, %d\n", 2203 __func__, ret); 2204 return -EINVAL; 2205 } 2206 2207 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2208 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2209 /* Clear the RDBK_DATA registers */ 2210 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2211 DSI_RDBK_DATA_CTRL_CLR); 2212 wmb(); /* make sure the RDBK registers are cleared */ 2213 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2214 wmb(); /* release cleared status before transfer */ 2215 } 2216 2217 ret = dsi_cmds2buf_tx(msm_host, msg); 2218 if (ret < 0) { 2219 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2220 return ret; 2221 } else if (ret < msg->tx_len) { 2222 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2223 return -ECOMM; 2224 } 2225 2226 /* 2227 * once cmd_dma_done interrupt received, 2228 * return data from client is ready and stored 2229 * at RDBK_DATA register already 2230 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2231 * after that dcs header lost during shift into registers 2232 */ 2233 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2234 2235 if (dlen <= 0) 2236 return 0; 2237 2238 if (short_response) 2239 break; 2240 2241 if (rlen <= data_byte) { 2242 diff = data_byte - rlen; 2243 end = 1; 2244 } else { 2245 diff = 0; 2246 rlen -= data_byte; 2247 } 2248 2249 if (!end) { 2250 dlen -= 2; /* 2 crc */ 2251 dlen -= diff; 2252 buf += dlen; /* next start position */ 2253 data_byte = 14; /* NOT first read */ 2254 if (rlen < data_byte) 2255 pkt_size += rlen; 2256 else 2257 pkt_size += data_byte; 2258 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2259 } 2260 } 2261 2262 /* 2263 * For single Long read, if the requested rlen < 10, 2264 * we need to shift the start position of rx 2265 * data buffer to skip the bytes which are not 2266 * updated. 2267 */ 2268 if (pkt_size < 10 && !short_response) 2269 buf = msm_host->rx_buf + (10 - rlen); 2270 else 2271 buf = msm_host->rx_buf; 2272 2273 cmd = buf[0]; 2274 switch (cmd) { 2275 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2276 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2277 ret = 0; 2278 break; 2279 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2280 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2281 ret = dsi_short_read1_resp(buf, msg); 2282 break; 2283 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2284 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2285 ret = dsi_short_read2_resp(buf, msg); 2286 break; 2287 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2288 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2289 ret = dsi_long_read_resp(buf, msg); 2290 break; 2291 default: 2292 pr_warn("%s:Invalid response cmd\n", __func__); 2293 ret = 0; 2294 } 2295 2296 return ret; 2297 } 2298 2299 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2300 u32 len) 2301 { 2302 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2303 2304 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2305 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2306 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2307 2308 /* Make sure trigger happens */ 2309 wmb(); 2310 } 2311 2312 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2313 struct msm_dsi_phy *src_phy) 2314 { 2315 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2316 2317 msm_host->cphy_mode = src_phy->cphy_mode; 2318 } 2319 2320 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2321 { 2322 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2323 2324 DBG(""); 2325 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2326 /* Make sure fully reset */ 2327 wmb(); 2328 udelay(1000); 2329 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2330 udelay(100); 2331 } 2332 2333 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2334 struct msm_dsi_phy_clk_request *clk_req, 2335 bool is_bonded_dsi) 2336 { 2337 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2338 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2339 int ret; 2340 2341 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2342 if (ret) { 2343 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2344 return; 2345 } 2346 2347 /* CPHY transmits 16 bits over 7 clock cycles 2348 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2349 * so multiply by 7 to get the "bitclk rate" 2350 */ 2351 if (msm_host->cphy_mode) 2352 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2353 else 2354 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2355 clk_req->escclk_rate = msm_host->esc_clk_rate; 2356 } 2357 2358 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2359 { 2360 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2361 2362 enable_irq(msm_host->irq); 2363 } 2364 2365 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2366 { 2367 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2368 2369 disable_irq(msm_host->irq); 2370 } 2371 2372 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2373 { 2374 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2375 2376 dsi_op_mode_config(msm_host, 2377 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2378 2379 /* TODO: clock should be turned off for command mode, 2380 * and only turned on before MDP START. 2381 * This part of code should be enabled once mdp driver support it. 2382 */ 2383 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2384 * dsi_link_clk_disable(msm_host); 2385 * pm_runtime_put(&msm_host->pdev->dev); 2386 * } 2387 */ 2388 msm_host->enabled = true; 2389 return 0; 2390 } 2391 2392 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2393 { 2394 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2395 2396 msm_host->enabled = false; 2397 dsi_op_mode_config(msm_host, 2398 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2399 2400 /* Since we have disabled INTF, the video engine won't stop so that 2401 * the cmd engine will be blocked. 2402 * Reset to disable video engine so that we can send off cmd. 2403 */ 2404 dsi_sw_reset(msm_host); 2405 2406 return 0; 2407 } 2408 2409 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2410 { 2411 enum sfpb_ahb_arb_master_port_en en; 2412 2413 if (!msm_host->sfpb) 2414 return; 2415 2416 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2417 2418 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2419 SFPB_GPREG_MASTER_PORT_EN__MASK, 2420 SFPB_GPREG_MASTER_PORT_EN(en)); 2421 } 2422 2423 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2424 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2425 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2426 { 2427 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2428 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2429 int ret = 0; 2430 2431 mutex_lock(&msm_host->dev_mutex); 2432 if (msm_host->power_on) { 2433 DBG("dsi host already on"); 2434 goto unlock_ret; 2435 } 2436 2437 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; 2438 if (phy_shared_timings->byte_intf_clk_div_2) 2439 msm_host->byte_intf_clk_rate /= 2; 2440 2441 msm_dsi_sfpb_config(msm_host, true); 2442 2443 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2444 msm_host->supplies); 2445 if (ret) { 2446 pr_err("%s:Failed to enable vregs.ret=%d\n", 2447 __func__, ret); 2448 goto unlock_ret; 2449 } 2450 2451 pm_runtime_get_sync(&msm_host->pdev->dev); 2452 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2453 if (!ret) 2454 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2455 if (ret) { 2456 pr_err("%s: failed to enable link clocks. ret=%d\n", 2457 __func__, ret); 2458 goto fail_disable_reg; 2459 } 2460 2461 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2462 if (ret) { 2463 pr_err("%s: failed to set pinctrl default state, %d\n", 2464 __func__, ret); 2465 goto fail_disable_clk; 2466 } 2467 2468 dsi_timing_setup(msm_host, is_bonded_dsi); 2469 dsi_sw_reset(msm_host); 2470 dsi_ctrl_enable(msm_host, phy_shared_timings, phy); 2471 2472 msm_host->power_on = true; 2473 mutex_unlock(&msm_host->dev_mutex); 2474 2475 return 0; 2476 2477 fail_disable_clk: 2478 cfg_hnd->ops->link_clk_disable(msm_host); 2479 pm_runtime_put(&msm_host->pdev->dev); 2480 fail_disable_reg: 2481 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2482 msm_host->supplies); 2483 unlock_ret: 2484 mutex_unlock(&msm_host->dev_mutex); 2485 return ret; 2486 } 2487 2488 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2489 { 2490 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2491 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2492 2493 mutex_lock(&msm_host->dev_mutex); 2494 if (!msm_host->power_on) { 2495 DBG("dsi host already off"); 2496 goto unlock_ret; 2497 } 2498 2499 dsi_ctrl_disable(msm_host); 2500 2501 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2502 2503 cfg_hnd->ops->link_clk_disable(msm_host); 2504 pm_runtime_put(&msm_host->pdev->dev); 2505 2506 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2507 msm_host->supplies); 2508 2509 msm_dsi_sfpb_config(msm_host, false); 2510 2511 DBG("-"); 2512 2513 msm_host->power_on = false; 2514 2515 unlock_ret: 2516 mutex_unlock(&msm_host->dev_mutex); 2517 return 0; 2518 } 2519 2520 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2521 const struct drm_display_mode *mode) 2522 { 2523 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2524 2525 if (msm_host->mode) { 2526 drm_mode_destroy(msm_host->dev, msm_host->mode); 2527 msm_host->mode = NULL; 2528 } 2529 2530 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2531 if (!msm_host->mode) { 2532 pr_err("%s: cannot duplicate mode\n", __func__); 2533 return -ENOMEM; 2534 } 2535 2536 return 0; 2537 } 2538 2539 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2540 const struct drm_display_mode *mode) 2541 { 2542 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2543 struct drm_dsc_config *dsc = msm_host->dsc; 2544 int pic_width = mode->hdisplay; 2545 int pic_height = mode->vdisplay; 2546 2547 if (!msm_host->dsc) 2548 return MODE_OK; 2549 2550 if (pic_width % dsc->slice_width) { 2551 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2552 pic_width, dsc->slice_width); 2553 return MODE_H_ILLEGAL; 2554 } 2555 2556 if (pic_height % dsc->slice_height) { 2557 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2558 pic_height, dsc->slice_height); 2559 return MODE_V_ILLEGAL; 2560 } 2561 2562 return MODE_OK; 2563 } 2564 2565 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2566 { 2567 return to_msm_dsi_host(host)->mode_flags; 2568 } 2569 2570 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2571 { 2572 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2573 2574 pm_runtime_get_sync(&msm_host->pdev->dev); 2575 2576 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2577 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2578 2579 pm_runtime_put_sync(&msm_host->pdev->dev); 2580 } 2581 2582 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2583 { 2584 u32 reg; 2585 2586 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2587 2588 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2589 /* draw checkered rectangle pattern */ 2590 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2591 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2592 /* use 24-bit RGB test pttern */ 2593 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2594 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2595 DSI_TPG_VIDEO_CONFIG_RGB); 2596 2597 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2598 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2599 2600 DBG("Video test pattern setup done\n"); 2601 } 2602 2603 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2604 { 2605 u32 reg; 2606 2607 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2608 2609 /* initial value for test pattern */ 2610 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2611 2612 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2613 2614 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2615 /* draw checkered rectangle pattern */ 2616 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2617 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2618 2619 DBG("Cmd test pattern setup done\n"); 2620 } 2621 2622 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2623 { 2624 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2625 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2626 u32 reg; 2627 2628 if (is_video_mode) 2629 msm_dsi_host_video_test_pattern_setup(msm_host); 2630 else 2631 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2632 2633 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2634 /* enable the test pattern generator */ 2635 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2636 2637 /* for command mode need to trigger one frame from tpg */ 2638 if (!is_video_mode) 2639 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2640 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2641 } 2642 2643 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2644 { 2645 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2646 2647 return msm_host->dsc; 2648 } 2649