1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/of.h> 13 #include <linux/of_graph.h> 14 #include <linux/of_irq.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/pm_opp.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/spinlock.h> 20 21 #include <video/mipi_display.h> 22 23 #include <drm/display/drm_dsc_helper.h> 24 #include <drm/drm_of.h> 25 26 #include "dsi.h" 27 #include "dsi.xml.h" 28 #include "sfpb.xml.h" 29 #include "dsi_cfg.h" 30 #include "msm_dsc_helper.h" 31 #include "msm_kms.h" 32 #include "msm_gem.h" 33 #include "phy/dsi_phy.h" 34 35 #define DSI_RESET_TOGGLE_DELAY_MS 20 36 37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 38 39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 40 { 41 u32 ver; 42 43 if (!major || !minor) 44 return -EINVAL; 45 46 /* 47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 48 * makes all other registers 4-byte shifted down. 49 * 50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 51 * older, we read the DSI_VERSION register without any shift(offset 52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 53 * the case of DSI6G, this has to be zero (the offset points to a 54 * scratch register which we never touch) 55 */ 56 57 ver = readl(base + REG_DSI_VERSION); 58 if (ver) { 59 /* older dsi host, there is no register shift */ 60 ver = FIELD(ver, DSI_VERSION_MAJOR); 61 if (ver <= MSM_DSI_VER_MAJOR_V2) { 62 /* old versions */ 63 *major = ver; 64 *minor = 0; 65 return 0; 66 } else { 67 return -EINVAL; 68 } 69 } else { 70 /* 71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 72 * registers are shifted down, read DSI_VERSION again with 73 * the shifted offset 74 */ 75 ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 76 ver = FIELD(ver, DSI_VERSION_MAJOR); 77 if (ver == MSM_DSI_VER_MAJOR_6G) { 78 /* 6G version */ 79 *major = ver; 80 *minor = readl(base + REG_DSI_6G_HW_VERSION); 81 return 0; 82 } else { 83 return -EINVAL; 84 } 85 } 86 } 87 88 #define DSI_ERR_STATE_ACK 0x0000 89 #define DSI_ERR_STATE_TIMEOUT 0x0001 90 #define DSI_ERR_STATE_DLN0_PHY 0x0002 91 #define DSI_ERR_STATE_FIFO 0x0004 92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 95 96 #define DSI_CLK_CTRL_ENABLE_CLKS \ 97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 101 102 struct msm_dsi_host { 103 struct mipi_dsi_host base; 104 105 struct platform_device *pdev; 106 struct drm_device *dev; 107 108 int id; 109 110 void __iomem *ctrl_base; 111 phys_addr_t ctrl_size; 112 struct regulator_bulk_data *supplies; 113 114 int num_bus_clks; 115 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 116 117 struct clk *byte_clk; 118 struct clk *esc_clk; 119 struct clk *pixel_clk; 120 struct clk *byte_intf_clk; 121 122 /* 123 * Clocks which needs to be properly parented between DISPCC and DSI PHY 124 * PLL: 125 */ 126 struct clk *byte_src_clk; 127 struct clk *pixel_src_clk; 128 struct clk *dsi_pll_byte_clk; 129 struct clk *dsi_pll_pixel_clk; 130 131 unsigned long byte_clk_rate; 132 bool byte_intf_clk_div_2; 133 unsigned long pixel_clk_rate; 134 unsigned long esc_clk_rate; 135 136 /* DSI v2 specific clocks */ 137 struct clk *src_clk; 138 139 unsigned long src_clk_rate; 140 141 const struct msm_dsi_cfg_handler *cfg_hnd; 142 143 struct completion dma_comp; 144 struct completion video_comp; 145 struct mutex dev_mutex; 146 struct mutex cmd_mutex; 147 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 148 149 u32 err_work_state; 150 struct work_struct err_work; 151 struct workqueue_struct *workqueue; 152 153 /* DSI 6G TX buffer*/ 154 struct drm_gem_object *tx_gem_obj; 155 struct drm_gpuvm *vm; 156 157 /* DSI v2 TX buffer */ 158 void *tx_buf; 159 dma_addr_t tx_buf_paddr; 160 161 int tx_size; 162 163 u8 *rx_buf; 164 165 struct regmap *sfpb; 166 167 struct drm_display_mode *mode; 168 struct drm_dsc_config *dsc; 169 unsigned int dsc_slice_per_pkt; 170 171 /* connected device info */ 172 unsigned int channel; 173 unsigned int lanes; 174 enum mipi_dsi_pixel_format format; 175 unsigned long mode_flags; 176 177 /* lane data parsed via DT */ 178 int dlane_swap; 179 int num_data_lanes; 180 181 /* from phy DT */ 182 bool cphy_mode; 183 184 u32 dma_cmd_ctrl_restore; 185 186 bool registered; 187 bool power_on; 188 bool enabled; 189 int irq; 190 }; 191 192 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 193 { 194 return readl(msm_host->ctrl_base + reg); 195 } 196 197 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 198 { 199 writel(data, msm_host->ctrl_base + reg); 200 } 201 202 static const struct msm_dsi_cfg_handler * 203 dsi_get_config(struct msm_dsi_host *msm_host) 204 { 205 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 206 struct device *dev = &msm_host->pdev->dev; 207 struct clk *ahb_clk; 208 int ret; 209 u32 major = 0, minor = 0; 210 211 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 212 if (IS_ERR(ahb_clk)) { 213 dev_err_probe(dev, PTR_ERR(ahb_clk), "%s: cannot get interface clock\n", 214 __func__); 215 goto exit; 216 } 217 218 pm_runtime_get_sync(dev); 219 220 ret = clk_prepare_enable(ahb_clk); 221 if (ret) { 222 dev_err_probe(dev, ret, "%s: unable to enable ahb_clk\n", __func__); 223 goto runtime_put; 224 } 225 226 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 227 if (ret) { 228 dev_err_probe(dev, ret, "%s: Invalid version\n", __func__); 229 goto disable_clks; 230 } 231 232 cfg_hnd = msm_dsi_cfg_get(major, minor); 233 234 DBG("%s: Version %x:%x\n", __func__, major, minor); 235 236 disable_clks: 237 clk_disable_unprepare(ahb_clk); 238 runtime_put: 239 pm_runtime_put_sync(dev); 240 exit: 241 return cfg_hnd; 242 } 243 244 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 245 { 246 return container_of(host, struct msm_dsi_host, base); 247 } 248 249 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 250 { 251 struct platform_device *pdev = msm_host->pdev; 252 int ret = 0; 253 254 msm_host->src_clk = msm_clk_get(pdev, "src"); 255 256 if (IS_ERR(msm_host->src_clk)) { 257 ret = PTR_ERR(msm_host->src_clk); 258 pr_err("%s: can't find src clock. ret=%d\n", 259 __func__, ret); 260 msm_host->src_clk = NULL; 261 return ret; 262 } 263 264 return ret; 265 } 266 267 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 268 { 269 struct platform_device *pdev = msm_host->pdev; 270 int ret = 0; 271 272 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 273 if (IS_ERR(msm_host->byte_intf_clk)) { 274 ret = PTR_ERR(msm_host->byte_intf_clk); 275 pr_err("%s: can't find byte_intf clock. ret=%d\n", 276 __func__, ret); 277 } 278 279 return ret; 280 } 281 282 int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host) 283 { 284 struct device *dev = &msm_host->pdev->dev; 285 int ret; 286 287 ret = dsi_clk_init_6g_v2(msm_host); 288 if (ret) 289 return ret; 290 291 msm_host->byte_src_clk = devm_clk_get(dev, "byte_src"); 292 if (IS_ERR(msm_host->byte_src_clk)) 293 return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk), 294 "can't get byte_src clock\n"); 295 296 msm_host->dsi_pll_byte_clk = devm_clk_get(dev, "dsi_pll_byte"); 297 if (IS_ERR(msm_host->dsi_pll_byte_clk)) 298 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk), 299 "can't get dsi_pll_byte clock\n"); 300 301 msm_host->pixel_src_clk = devm_clk_get(dev, "pixel_src"); 302 if (IS_ERR(msm_host->pixel_src_clk)) 303 return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk), 304 "can't get pixel_src clock\n"); 305 306 msm_host->dsi_pll_pixel_clk = devm_clk_get(dev, "dsi_pll_pixel"); 307 if (IS_ERR(msm_host->dsi_pll_pixel_clk)) 308 return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk), 309 "can't get dsi_pll_pixel clock\n"); 310 311 return 0; 312 } 313 314 static int dsi_clk_init(struct msm_dsi_host *msm_host) 315 { 316 struct platform_device *pdev = msm_host->pdev; 317 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 318 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 319 int i, ret = 0; 320 321 /* get bus clocks */ 322 for (i = 0; i < cfg->num_bus_clks; i++) 323 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 324 msm_host->num_bus_clks = cfg->num_bus_clks; 325 326 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 327 if (ret < 0) 328 return dev_err_probe(&pdev->dev, ret, "Unable to get clocks\n"); 329 330 /* get link and source clocks */ 331 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 332 if (IS_ERR(msm_host->byte_clk)) 333 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->byte_clk), 334 "%s: can't find dsi_byte clock\n", 335 __func__); 336 337 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 338 if (IS_ERR(msm_host->pixel_clk)) 339 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->pixel_clk), 340 "%s: can't find dsi_pixel clock\n", 341 __func__); 342 343 msm_host->esc_clk = msm_clk_get(pdev, "core"); 344 if (IS_ERR(msm_host->esc_clk)) 345 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->esc_clk), 346 "%s: can't find dsi_esc clock\n", 347 __func__); 348 349 if (cfg_hnd->ops->clk_init_ver) 350 ret = cfg_hnd->ops->clk_init_ver(msm_host); 351 352 return ret; 353 } 354 355 int msm_dsi_runtime_suspend(struct device *dev) 356 { 357 struct platform_device *pdev = to_platform_device(dev); 358 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 359 struct mipi_dsi_host *host = msm_dsi->host; 360 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 361 362 if (!msm_host->cfg_hnd) 363 return 0; 364 365 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 366 367 return 0; 368 } 369 370 int msm_dsi_runtime_resume(struct device *dev) 371 { 372 struct platform_device *pdev = to_platform_device(dev); 373 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 374 struct mipi_dsi_host *host = msm_dsi->host; 375 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 376 377 if (!msm_host->cfg_hnd) 378 return 0; 379 380 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 381 } 382 383 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 384 { 385 unsigned long byte_intf_clk_rate; 386 long rounded_byte_clk_rate; 387 int ret; 388 389 rounded_byte_clk_rate = clk_round_rate(msm_host->byte_clk, 390 msm_host->byte_clk_rate); 391 if (rounded_byte_clk_rate < 0) { 392 pr_err("%s: failed to round byte clock rate, %ld\n", 393 __func__, rounded_byte_clk_rate); 394 return rounded_byte_clk_rate; 395 } 396 397 msm_host->byte_clk_rate = rounded_byte_clk_rate; 398 399 DBG("Set clk rates: pclk=%lu, byteclk=%lu", 400 msm_host->pixel_clk_rate, msm_host->byte_clk_rate); 401 402 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 403 msm_host->byte_clk_rate); 404 if (ret) { 405 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 406 return ret; 407 } 408 409 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 410 if (ret) { 411 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 412 return ret; 413 } 414 415 if (msm_host->byte_intf_clk) { 416 byte_intf_clk_rate = msm_host->byte_clk_rate; 417 if (msm_host->byte_intf_clk_div_2) 418 byte_intf_clk_rate /= 2; 419 420 ret = clk_set_rate(msm_host->byte_intf_clk, byte_intf_clk_rate); 421 if (ret) { 422 pr_err("%s: Failed to set rate byte intf clk, %d\n", 423 __func__, ret); 424 return ret; 425 } 426 } 427 428 return 0; 429 } 430 431 int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host) 432 { 433 struct device *dev = &msm_host->pdev->dev; 434 int ret; 435 436 /* 437 * DSI PHY PLLs have to be enabled to allow reparenting to them, so 438 * cannot use assigned-clock-parents. 439 */ 440 ret = clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk); 441 if (ret) 442 dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret); 443 444 ret = clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_clk); 445 if (ret) 446 dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret); 447 448 return dsi_link_clk_set_rate_6g(msm_host); 449 } 450 451 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 452 { 453 int ret; 454 455 ret = clk_prepare_enable(msm_host->esc_clk); 456 if (ret) { 457 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 458 goto error; 459 } 460 461 ret = clk_prepare_enable(msm_host->byte_clk); 462 if (ret) { 463 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 464 goto byte_clk_err; 465 } 466 467 ret = clk_prepare_enable(msm_host->pixel_clk); 468 if (ret) { 469 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 470 goto pixel_clk_err; 471 } 472 473 ret = clk_prepare_enable(msm_host->byte_intf_clk); 474 if (ret) { 475 pr_err("%s: Failed to enable byte intf clk\n", 476 __func__); 477 goto byte_intf_clk_err; 478 } 479 480 return 0; 481 482 byte_intf_clk_err: 483 clk_disable_unprepare(msm_host->pixel_clk); 484 pixel_clk_err: 485 clk_disable_unprepare(msm_host->byte_clk); 486 byte_clk_err: 487 clk_disable_unprepare(msm_host->esc_clk); 488 error: 489 return ret; 490 } 491 492 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 493 { 494 int ret; 495 496 DBG("Set clk rates: pclk=%lu, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 497 msm_host->pixel_clk_rate, msm_host->byte_clk_rate, 498 msm_host->esc_clk_rate, msm_host->src_clk_rate); 499 500 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 501 if (ret) { 502 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 503 return ret; 504 } 505 506 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 507 if (ret) { 508 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 509 return ret; 510 } 511 512 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 513 if (ret) { 514 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 515 return ret; 516 } 517 518 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 519 if (ret) { 520 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 521 return ret; 522 } 523 524 return 0; 525 } 526 527 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 528 { 529 int ret; 530 531 ret = clk_prepare_enable(msm_host->byte_clk); 532 if (ret) { 533 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 534 goto error; 535 } 536 537 ret = clk_prepare_enable(msm_host->esc_clk); 538 if (ret) { 539 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 540 goto esc_clk_err; 541 } 542 543 ret = clk_prepare_enable(msm_host->src_clk); 544 if (ret) { 545 pr_err("%s: Failed to enable dsi src clk\n", __func__); 546 goto src_clk_err; 547 } 548 549 ret = clk_prepare_enable(msm_host->pixel_clk); 550 if (ret) { 551 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 552 goto pixel_clk_err; 553 } 554 555 return 0; 556 557 pixel_clk_err: 558 clk_disable_unprepare(msm_host->src_clk); 559 src_clk_err: 560 clk_disable_unprepare(msm_host->esc_clk); 561 esc_clk_err: 562 clk_disable_unprepare(msm_host->byte_clk); 563 error: 564 return ret; 565 } 566 567 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 568 { 569 clk_disable_unprepare(msm_host->esc_clk); 570 clk_disable_unprepare(msm_host->pixel_clk); 571 clk_disable_unprepare(msm_host->byte_intf_clk); 572 clk_disable_unprepare(msm_host->byte_clk); 573 } 574 575 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 576 { 577 clk_disable_unprepare(msm_host->pixel_clk); 578 clk_disable_unprepare(msm_host->src_clk); 579 clk_disable_unprepare(msm_host->esc_clk); 580 clk_disable_unprepare(msm_host->byte_clk); 581 } 582 583 /** 584 * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case 585 * @mode: The selected mode for the DSI output 586 * @dsc: DRM DSC configuration for this DSI output 587 * @is_bonded_dsi: True if two DSI controllers are bonded 588 * 589 * Adjust the pclk rate by calculating a new hdisplay proportional to 590 * the compression ratio such that: 591 * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp 592 * 593 * Porches do not need to be adjusted: 594 * - For VIDEO mode they are not compressed by DSC and are passed as is. 595 * - For CMD mode there are no actual porches. Instead these fields 596 * currently represent the overhead to the image data transfer. As such, they 597 * are calculated for the final mode parameters (after the compression) and 598 * are not to be adjusted too. 599 * 600 * FIXME: Reconsider this if/when CMD mode handling is rewritten to use 601 * transfer time and data overhead as a starting point of the calculations. 602 */ 603 static unsigned long 604 dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, 605 const struct drm_dsc_config *dsc, 606 bool is_bonded_dsi) 607 { 608 int hdisplay, new_hdisplay, new_htotal; 609 610 /* 611 * For bonded DSI, split hdisplay across two links and round up each 612 * half separately, passing the full hdisplay would only round up once. 613 * This also aligns with the hdisplay we program later in 614 * dsi_timing_setup() 615 */ 616 hdisplay = mode->hdisplay; 617 if (is_bonded_dsi) 618 hdisplay /= 2; 619 620 new_hdisplay = DIV_ROUND_UP(hdisplay * drm_dsc_get_bpp_int(dsc), 621 dsc->bits_per_component * 3); 622 623 if (is_bonded_dsi) 624 new_hdisplay *= 2; 625 626 new_htotal = mode->htotal - mode->hdisplay + new_hdisplay; 627 628 return mult_frac(mode->clock * 1000u, new_htotal, mode->htotal); 629 } 630 631 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, 632 const struct drm_dsc_config *dsc, bool is_bonded_dsi) 633 { 634 unsigned long pclk_rate; 635 636 pclk_rate = mode->clock * 1000u; 637 638 if (dsc) 639 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc, is_bonded_dsi); 640 641 /* 642 * For bonded DSI mode, the current DRM mode has the complete width of the 643 * panel. Since, the complete panel is driven by two DSI controllers, 644 * the clock rates have to be split between the two dsi controllers. 645 * Adjust the byte and pixel clock rates for each dsi host accordingly. 646 */ 647 if (is_bonded_dsi) 648 pclk_rate /= 2; 649 650 return pclk_rate; 651 } 652 653 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 654 const struct drm_display_mode *mode) 655 { 656 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 657 u8 lanes = msm_host->lanes; 658 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 659 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); 660 unsigned long pclk_bpp; 661 662 if (lanes == 0) { 663 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 664 lanes = 1; 665 } 666 667 /* CPHY "byte_clk" is in units of 16 bits */ 668 if (msm_host->cphy_mode) 669 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes); 670 else 671 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes); 672 673 return pclk_bpp; 674 } 675 676 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 677 { 678 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi); 679 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 680 msm_host->mode); 681 682 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 683 msm_host->byte_clk_rate); 684 } 685 686 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 687 { 688 if (!msm_host->mode) { 689 pr_err("%s: mode not set\n", __func__); 690 return -EINVAL; 691 } 692 693 dsi_calc_pclk(msm_host, is_bonded_dsi); 694 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 695 return 0; 696 } 697 698 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 699 { 700 u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); 701 unsigned int esc_mhz, esc_div; 702 unsigned long byte_mhz; 703 704 dsi_calc_pclk(msm_host, is_bonded_dsi); 705 706 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8); 707 708 /* 709 * esc clock is byte clock followed by a 4 bit divider, 710 * we need to find an escape clock frequency within the 711 * mipi DSI spec range within the maximum divider limit 712 * We iterate here between an escape clock frequencey 713 * between 20 Mhz to 5 Mhz and pick up the first one 714 * that can be supported by our divider 715 */ 716 717 byte_mhz = msm_host->byte_clk_rate / 1000000; 718 719 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 720 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 721 722 /* 723 * TODO: Ideally, we shouldn't know what sort of divider 724 * is available in mmss_cc, we're just assuming that 725 * it'll always be a 4 bit divider. Need to come up with 726 * a better way here. 727 */ 728 if (esc_div >= 1 && esc_div <= 16) 729 break; 730 } 731 732 if (esc_mhz < 5) 733 return -EINVAL; 734 735 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 736 737 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 738 msm_host->src_clk_rate); 739 740 return 0; 741 } 742 743 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 744 { 745 u32 intr; 746 unsigned long flags; 747 748 spin_lock_irqsave(&msm_host->intr_lock, flags); 749 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 750 751 if (enable) 752 intr |= mask; 753 else 754 intr &= ~mask; 755 756 DBG("intr=%x enable=%d", intr, enable); 757 758 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 759 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 760 } 761 762 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 763 { 764 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 765 return BURST_MODE; 766 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 767 return NON_BURST_SYNCH_PULSE; 768 769 return NON_BURST_SYNCH_EVENT; 770 } 771 772 static inline enum dsi_vid_dst_format 773 dsi_get_vid_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 774 { 775 switch (mipi_fmt) { 776 case MIPI_DSI_FMT_RGB101010: return VID_DST_FORMAT_RGB101010; 777 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 778 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 779 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 780 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 781 default: return VID_DST_FORMAT_RGB888; 782 } 783 } 784 785 static inline enum dsi_cmd_dst_format 786 dsi_get_cmd_fmt(const enum mipi_dsi_pixel_format mipi_fmt) 787 { 788 switch (mipi_fmt) { 789 case MIPI_DSI_FMT_RGB101010: return CMD_DST_FORMAT_RGB101010; 790 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 791 case MIPI_DSI_FMT_RGB666_PACKED: 792 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 793 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 794 default: return CMD_DST_FORMAT_RGB888; 795 } 796 } 797 798 static void dsi_ctrl_disable(struct msm_dsi_host *msm_host) 799 { 800 dsi_write(msm_host, REG_DSI_CTRL, 0); 801 } 802 803 static bool msm_dsi_host_version_geq(struct msm_dsi_host *msm_host, 804 u32 major, u32 minor) 805 { 806 return msm_host->cfg_hnd->major > major || 807 (msm_host->cfg_hnd->major == major && 808 msm_host->cfg_hnd->minor >= minor); 809 } 810 811 bool msm_dsi_host_is_wide_bus_enabled(struct mipi_dsi_host *host) 812 { 813 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 814 815 return msm_host->dsc && 816 msm_dsi_host_version_geq(msm_host, MSM_DSI_VER_MAJOR_6G, 817 MSM_DSI_6G_VER_MINOR_V2_5_0); 818 } 819 820 static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, 821 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 822 { 823 u32 flags = msm_host->mode_flags; 824 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 825 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 826 u32 data = 0, lane_ctrl = 0; 827 828 if (flags & MIPI_DSI_MODE_VIDEO) { 829 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 830 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 831 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 832 data |= DSI_VID_CFG0_HFP_POWER_STOP; 833 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 834 data |= DSI_VID_CFG0_HBP_POWER_STOP; 835 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 836 data |= DSI_VID_CFG0_HSA_POWER_STOP; 837 /* Always set low power stop mode for BLLP 838 * to let command engine send packets 839 */ 840 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 841 DSI_VID_CFG0_BLLP_POWER_STOP; 842 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 843 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 844 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 845 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 846 data |= DSI_VID_CFG0_DATABUS_WIDEN; 847 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 848 849 /* Do not swap RGB colors */ 850 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 851 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 852 } else { 853 /* Do not swap RGB colors */ 854 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 855 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 856 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 857 858 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 859 DSI_CMD_CFG1_WR_MEM_CONTINUE( 860 MIPI_DCS_WRITE_MEMORY_CONTINUE); 861 /* Always insert DCS command */ 862 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 863 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 864 865 if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) { 866 data = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); 867 868 if (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_3) 869 data |= DSI_CMD_MODE_MDP_CTRL2_BURST_MODE; 870 871 if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) 872 data |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; 873 874 dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, data); 875 } 876 } 877 878 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 879 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 880 DSI_CMD_DMA_CTRL_LOW_POWER); 881 882 data = 0; 883 /* Always assume dedicated TE pin */ 884 data |= DSI_TRIG_CTRL_TE; 885 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 886 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 887 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 888 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 889 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 890 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 891 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 892 893 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 894 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 895 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 896 897 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 898 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 899 phy_shared_timings->clk_pre_inc_by_2) 900 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 901 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 902 903 data = 0; 904 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 905 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 906 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 907 908 /* allow only ack-err-status to generate interrupt */ 909 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 910 911 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 912 913 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 914 915 data = DSI_CTRL_CLK_EN; 916 917 DBG("lane number=%d", msm_host->lanes); 918 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 919 920 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 921 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 922 923 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 924 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 925 926 if (msm_dsi_phy_set_continuous_clock(phy, true)) 927 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 928 929 dsi_write(msm_host, REG_DSI_LANE_CTRL, 930 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 931 } 932 933 data |= DSI_CTRL_ENABLE; 934 935 dsi_write(msm_host, REG_DSI_CTRL, data); 936 937 if (msm_host->cphy_mode) 938 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 939 } 940 941 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode) 942 { 943 struct drm_dsc_config *dsc = msm_host->dsc; 944 u32 reg, reg_ctrl, reg_ctrl2; 945 u32 slice_per_intf, total_bytes_per_intf; 946 u32 pkt_per_line; 947 u32 eol_byte_num; 948 u32 bytes_per_pkt; 949 950 /* first calculate dsc parameters and then program 951 * compress mode registers 952 */ 953 slice_per_intf = dsc->slice_count; 954 955 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 956 bytes_per_pkt = dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt; 957 958 eol_byte_num = total_bytes_per_intf % 3; 959 pkt_per_line = slice_per_intf / msm_host->dsc_slice_per_pkt; 960 961 if (is_cmd_mode) /* packet data type */ 962 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 963 else 964 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 965 966 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 967 * registers have similar offsets, so for below common code use 968 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 969 * 970 * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) 971 */ 972 if (pkt_per_line > 4) 973 drm_warn_once(msm_host->dev, "pkt_per_line too big"); 974 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 975 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 976 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 977 978 if (is_cmd_mode) { 979 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 980 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 981 982 reg_ctrl &= ~0xffff; 983 reg_ctrl |= reg; 984 985 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 986 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 987 988 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 989 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 990 } else { 991 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); 992 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 993 } 994 } 995 996 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 997 { 998 struct drm_display_mode *mode = msm_host->mode; 999 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 1000 u32 h_total = mode->htotal; 1001 u32 v_total = mode->vtotal; 1002 u32 hs_end = mode->hsync_end - mode->hsync_start; 1003 u32 vs_end = mode->vsync_end - mode->vsync_start; 1004 u32 ha_start = h_total - mode->hsync_start; 1005 u32 ha_end = ha_start + mode->hdisplay; 1006 u32 va_start = v_total - mode->vsync_start; 1007 u32 va_end = va_start + mode->vdisplay; 1008 u32 hdisplay = mode->hdisplay; 1009 u32 wc; 1010 int ret; 1011 bool wide_bus_enabled = msm_dsi_host_is_wide_bus_enabled(&msm_host->base); 1012 1013 DBG(""); 1014 1015 /* 1016 * For bonded DSI mode, the current DRM mode has 1017 * the complete width of the panel. Since, the complete 1018 * panel is driven by two DSI controllers, the horizontal 1019 * timings have to be split between the two dsi controllers. 1020 * Adjust the DSI host timing values accordingly. 1021 */ 1022 if (is_bonded_dsi) { 1023 h_total /= 2; 1024 hs_end /= 2; 1025 ha_start /= 2; 1026 ha_end /= 2; 1027 hdisplay /= 2; 1028 } 1029 1030 if (msm_host->dsc) { 1031 struct drm_dsc_config *dsc = msm_host->dsc; 1032 u32 bits_per_pclk; 1033 1034 /* update dsc params with timing params */ 1035 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 1036 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 1037 mode->hdisplay, mode->vdisplay); 1038 return; 1039 } 1040 1041 dsc->pic_width = mode->hdisplay; 1042 dsc->pic_height = mode->vdisplay; 1043 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 1044 1045 /* we do the calculations for dsc parameters here so that 1046 * panel can use these parameters 1047 */ 1048 ret = dsi_populate_dsc_params(msm_host, dsc); 1049 if (ret) 1050 return; 1051 1052 /* 1053 * DPU sends 3 bytes per pclk cycle to DSI. If widebus is 1054 * enabled, MDP always sends out 48-bit compressed data per 1055 * pclk and on average, for video mode, DSI consumes only an 1056 * amount of compressed data equivalent to the uncompressed 1057 * pixel depth per pclk. 1058 * 1059 * Calculate the number of pclks needed to transmit one line of 1060 * the compressed data. 1061 1062 * The back/font porch and pulse width are kept intact. For 1063 * VIDEO mode they represent timing parameters rather than 1064 * actual data transfer, see the documentation for 1065 * dsi_adjust_pclk_for_compression(). For CMD mode they are 1066 * unused anyway. 1067 */ 1068 h_total -= hdisplay; 1069 if (wide_bus_enabled) { 1070 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) 1071 bits_per_pclk = dsc->bits_per_component * 3; 1072 else 1073 bits_per_pclk = 48; 1074 } else { 1075 bits_per_pclk = 24; 1076 } 1077 1078 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc) * 8, bits_per_pclk); 1079 1080 h_total += hdisplay; 1081 ha_end = ha_start + hdisplay; 1082 } 1083 1084 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 1085 if (msm_host->dsc) 1086 dsi_update_dsc_timing(msm_host, false); 1087 1088 dsi_write(msm_host, REG_DSI_ACTIVE_H, 1089 DSI_ACTIVE_H_START(ha_start) | 1090 DSI_ACTIVE_H_END(ha_end)); 1091 dsi_write(msm_host, REG_DSI_ACTIVE_V, 1092 DSI_ACTIVE_V_START(va_start) | 1093 DSI_ACTIVE_V_END(va_end)); 1094 dsi_write(msm_host, REG_DSI_TOTAL, 1095 DSI_TOTAL_H_TOTAL(h_total - 1) | 1096 DSI_TOTAL_V_TOTAL(v_total - 1)); 1097 1098 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 1099 DSI_ACTIVE_HSYNC_START(hs_start) | 1100 DSI_ACTIVE_HSYNC_END(hs_end)); 1101 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 1102 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 1103 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 1104 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 1105 } else { /* command mode */ 1106 if (msm_host->dsc) 1107 dsi_update_dsc_timing(msm_host, true); 1108 1109 /* image data and 1 byte write_memory_start cmd */ 1110 if (!msm_host->dsc) 1111 wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; 1112 else 1113 /* 1114 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. 1115 */ 1116 wc = msm_host->dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt + 1; 1117 1118 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 1119 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 1120 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 1121 msm_host->channel) | 1122 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1123 MIPI_DSI_DCS_LONG_WRITE)); 1124 1125 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1126 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1127 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1128 } 1129 } 1130 1131 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1132 { 1133 u32 ctrl; 1134 1135 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1136 1137 if (ctrl & DSI_CTRL_ENABLE) { 1138 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1139 /* 1140 * dsi controller need to be disabled before 1141 * clocks turned on 1142 */ 1143 wmb(); 1144 } 1145 1146 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1147 wmb(); /* clocks need to be enabled before reset */ 1148 1149 /* dsi controller can only be reset while clocks are running */ 1150 dsi_write(msm_host, REG_DSI_RESET, 1); 1151 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1152 dsi_write(msm_host, REG_DSI_RESET, 0); 1153 wmb(); /* controller out of reset */ 1154 1155 if (ctrl & DSI_CTRL_ENABLE) { 1156 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1157 wmb(); /* make sure dsi controller enabled again */ 1158 } 1159 } 1160 1161 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1162 bool video_mode, bool enable) 1163 { 1164 u32 dsi_ctrl; 1165 1166 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1167 1168 if (!enable) { 1169 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1170 DSI_CTRL_CMD_MODE_EN); 1171 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1172 DSI_IRQ_MASK_VIDEO_DONE, 0); 1173 } else { 1174 if (video_mode) { 1175 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1176 } else { /* command mode */ 1177 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1178 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1179 } 1180 dsi_ctrl |= DSI_CTRL_ENABLE; 1181 } 1182 1183 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1184 } 1185 1186 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1187 { 1188 u32 data; 1189 1190 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1191 1192 if (mode == 0) 1193 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1194 else 1195 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1196 1197 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1198 } 1199 1200 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1201 { 1202 u32 ret = 0; 1203 struct device *dev = &msm_host->pdev->dev; 1204 1205 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1206 1207 reinit_completion(&msm_host->video_comp); 1208 1209 ret = wait_for_completion_timeout(&msm_host->video_comp, 1210 msecs_to_jiffies(70)); 1211 1212 if (ret == 0) 1213 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1214 1215 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1216 } 1217 1218 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1219 { 1220 u32 data; 1221 1222 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1223 return; 1224 1225 data = dsi_read(msm_host, REG_DSI_STATUS0); 1226 1227 /* if video mode engine is not busy, its because 1228 * either timing engine was not turned on or the 1229 * DSI controller has finished transmitting the video 1230 * data already, so no need to wait in those cases 1231 */ 1232 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1233 return; 1234 1235 if (msm_host->power_on && msm_host->enabled) { 1236 dsi_wait4video_done(msm_host); 1237 /* delay 4 ms to skip BLLP */ 1238 usleep_range(2000, 4000); 1239 } 1240 } 1241 1242 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1243 { 1244 struct drm_device *dev = msm_host->dev; 1245 struct msm_drm_private *priv = dev->dev_private; 1246 uint64_t iova; 1247 u8 *data; 1248 1249 msm_host->vm = drm_gpuvm_get(priv->kms->vm); 1250 1251 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1252 msm_host->vm, 1253 &msm_host->tx_gem_obj, &iova); 1254 1255 if (IS_ERR(data)) { 1256 msm_host->tx_gem_obj = NULL; 1257 return PTR_ERR(data); 1258 } 1259 1260 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1261 1262 msm_host->tx_size = msm_host->tx_gem_obj->size; 1263 1264 return 0; 1265 } 1266 1267 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1268 { 1269 struct drm_device *dev = msm_host->dev; 1270 1271 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1272 &msm_host->tx_buf_paddr, GFP_KERNEL); 1273 if (!msm_host->tx_buf) 1274 return -ENOMEM; 1275 1276 msm_host->tx_size = size; 1277 1278 return 0; 1279 } 1280 1281 void msm_dsi_tx_buf_free(struct mipi_dsi_host *host) 1282 { 1283 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1284 struct drm_device *dev = msm_host->dev; 1285 1286 /* 1287 * This is possible if we're tearing down before we've had a chance to 1288 * fully initialize. A very real possibility if our probe is deferred, 1289 * in which case we'll hit msm_dsi_host_destroy() without having run 1290 * through the dsi_tx_buf_alloc(). 1291 */ 1292 if (!dev) 1293 return; 1294 1295 if (msm_host->tx_gem_obj) { 1296 msm_gem_kernel_put(msm_host->tx_gem_obj, msm_host->vm); 1297 drm_gpuvm_put(msm_host->vm); 1298 msm_host->tx_gem_obj = NULL; 1299 msm_host->vm = NULL; 1300 } 1301 1302 if (msm_host->tx_buf) 1303 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1304 msm_host->tx_buf_paddr); 1305 } 1306 1307 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1308 { 1309 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1310 } 1311 1312 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1313 { 1314 return msm_host->tx_buf; 1315 } 1316 1317 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1318 { 1319 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1320 } 1321 1322 /* 1323 * prepare cmd buffer to be txed 1324 */ 1325 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1326 const struct mipi_dsi_msg *msg) 1327 { 1328 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1329 struct mipi_dsi_packet packet; 1330 int len; 1331 int ret; 1332 u8 *data; 1333 1334 ret = mipi_dsi_create_packet(&packet, msg); 1335 if (ret) { 1336 pr_err("%s: create packet failed, %d\n", __func__, ret); 1337 return ret; 1338 } 1339 len = (packet.size + 3) & (~0x3); 1340 1341 if (len > msm_host->tx_size) { 1342 pr_err("%s: packet size is too big\n", __func__); 1343 return -EINVAL; 1344 } 1345 1346 data = cfg_hnd->ops->tx_buf_get(msm_host); 1347 if (IS_ERR(data)) { 1348 ret = PTR_ERR(data); 1349 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1350 return ret; 1351 } 1352 1353 /* MSM specific command format in memory */ 1354 data[0] = packet.header[1]; 1355 data[1] = packet.header[2]; 1356 data[2] = packet.header[0]; 1357 data[3] = BIT(7); /* Last packet */ 1358 if (mipi_dsi_packet_format_is_long(msg->type)) 1359 data[3] |= BIT(6); 1360 if (msg->rx_buf && msg->rx_len) 1361 data[3] |= BIT(5); 1362 1363 /* Long packet */ 1364 if (packet.payload && packet.payload_length) 1365 memcpy(data + 4, packet.payload, packet.payload_length); 1366 1367 /* Append 0xff to the end */ 1368 if (packet.size < len) 1369 memset(data + packet.size, 0xff, len - packet.size); 1370 1371 if (cfg_hnd->ops->tx_buf_put) 1372 cfg_hnd->ops->tx_buf_put(msm_host); 1373 1374 return len; 1375 } 1376 1377 /* 1378 * dsi_short_read1_resp: 1 parameter 1379 */ 1380 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1381 { 1382 u8 *data = msg->rx_buf; 1383 1384 if (data && (msg->rx_len >= 1)) { 1385 *data = buf[1]; /* strip out dcs type */ 1386 return 1; 1387 } 1388 1389 pr_err("%s: read data does not match with rx_buf len %zu\n", 1390 __func__, msg->rx_len); 1391 return -EINVAL; 1392 } 1393 1394 /* 1395 * dsi_short_read2_resp: 2 parameter 1396 */ 1397 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1398 { 1399 u8 *data = msg->rx_buf; 1400 1401 if (data && (msg->rx_len >= 2)) { 1402 data[0] = buf[1]; /* strip out dcs type */ 1403 data[1] = buf[2]; 1404 return 2; 1405 } 1406 1407 pr_err("%s: read data does not match with rx_buf len %zu\n", 1408 __func__, msg->rx_len); 1409 return -EINVAL; 1410 } 1411 1412 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1413 { 1414 /* strip out 4 byte dcs header */ 1415 if (msg->rx_buf && msg->rx_len) 1416 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1417 1418 return msg->rx_len; 1419 } 1420 1421 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1422 { 1423 struct drm_device *dev = msm_host->dev; 1424 struct msm_drm_private *priv = dev->dev_private; 1425 1426 if (!dma_base) 1427 return -EINVAL; 1428 1429 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1430 priv->kms->vm, dma_base); 1431 } 1432 1433 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1434 { 1435 if (!dma_base) 1436 return -EINVAL; 1437 1438 *dma_base = msm_host->tx_buf_paddr; 1439 return 0; 1440 } 1441 1442 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1443 { 1444 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1445 int ret; 1446 uint64_t dma_base; 1447 bool triggered; 1448 1449 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1450 if (ret) { 1451 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1452 return ret; 1453 } 1454 1455 reinit_completion(&msm_host->dma_comp); 1456 1457 dsi_wait4video_eng_busy(msm_host); 1458 1459 triggered = msm_dsi_manager_cmd_xfer_trigger( 1460 msm_host->id, dma_base, len); 1461 if (triggered) { 1462 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1463 msecs_to_jiffies(200)); 1464 DBG("ret=%d", ret); 1465 if (ret == 0) 1466 ret = -ETIMEDOUT; 1467 else 1468 ret = len; 1469 } else { 1470 ret = len; 1471 } 1472 1473 return ret; 1474 } 1475 1476 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1477 u8 *buf, int rx_byte, int pkt_size) 1478 { 1479 u32 *temp, data; 1480 int i, j = 0, cnt; 1481 u32 read_cnt; 1482 u8 reg[16]; 1483 int repeated_bytes = 0; 1484 int buf_offset = buf - msm_host->rx_buf; 1485 1486 temp = (u32 *)reg; 1487 cnt = (rx_byte + 3) >> 2; 1488 if (cnt > 4) 1489 cnt = 4; /* 4 x 32 bits registers only */ 1490 1491 if (rx_byte == 4) 1492 read_cnt = 4; 1493 else 1494 read_cnt = pkt_size + 6; 1495 1496 /* 1497 * In case of multiple reads from the panel, after the first read, there 1498 * is possibility that there are some bytes in the payload repeating in 1499 * the RDBK_DATA registers. Since we read all the parameters from the 1500 * panel right from the first byte for every pass. We need to skip the 1501 * repeating bytes and then append the new parameters to the rx buffer. 1502 */ 1503 if (read_cnt > 16) { 1504 int bytes_shifted; 1505 /* Any data more than 16 bytes will be shifted out. 1506 * The temp read buffer should already contain these bytes. 1507 * The remaining bytes in read buffer are the repeated bytes. 1508 */ 1509 bytes_shifted = read_cnt - 16; 1510 repeated_bytes = buf_offset - bytes_shifted; 1511 } 1512 1513 for (i = cnt - 1; i >= 0; i--) { 1514 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1515 *temp++ = ntohl(data); /* to host byte order */ 1516 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1517 } 1518 1519 for (i = repeated_bytes; i < 16; i++) 1520 buf[j++] = reg[i]; 1521 1522 return j; 1523 } 1524 1525 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1526 const struct mipi_dsi_msg *msg) 1527 { 1528 int len, ret; 1529 int bllp_len = msm_host->mode->hdisplay * 1530 mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; 1531 1532 len = dsi_cmd_dma_add(msm_host, msg); 1533 if (len < 0) { 1534 pr_err("%s: failed to add cmd type = 0x%x\n", 1535 __func__, msg->type); 1536 return len; 1537 } 1538 1539 /* 1540 * for video mode, do not send cmds more than 1541 * one pixel line, since it only transmit it 1542 * during BLLP. 1543 * 1544 * TODO: if the command is sent in LP mode, the bit rate is only 1545 * half of esc clk rate. In this case, if the video is already 1546 * actively streaming, we need to check more carefully if the 1547 * command can be fit into one BLLP. 1548 */ 1549 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1550 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1551 __func__, len); 1552 return -EINVAL; 1553 } 1554 1555 ret = dsi_cmd_dma_tx(msm_host, len); 1556 if (ret < 0) { 1557 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1558 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1559 return ret; 1560 } else if (ret < len) { 1561 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1562 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1563 return -EIO; 1564 } 1565 1566 return len; 1567 } 1568 1569 static void dsi_err_worker(struct work_struct *work) 1570 { 1571 struct msm_dsi_host *msm_host = 1572 container_of(work, struct msm_dsi_host, err_work); 1573 u32 status = msm_host->err_work_state; 1574 1575 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1576 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1577 dsi_sw_reset(msm_host); 1578 1579 /* It is safe to clear here because error irq is disabled. */ 1580 msm_host->err_work_state = 0; 1581 1582 /* enable dsi error interrupt */ 1583 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1584 } 1585 1586 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1587 { 1588 u32 status; 1589 1590 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1591 1592 if (status) { 1593 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1594 /* Writing of an extra 0 needed to clear error bits */ 1595 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1596 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1597 } 1598 } 1599 1600 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1601 { 1602 u32 status; 1603 1604 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1605 1606 if (status) { 1607 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1608 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1609 } 1610 } 1611 1612 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1613 { 1614 u32 status; 1615 1616 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1617 1618 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1619 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1620 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1621 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1622 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1623 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1624 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1625 } 1626 } 1627 1628 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1629 { 1630 u32 status; 1631 1632 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1633 1634 /* fifo underflow, overflow */ 1635 if (status) { 1636 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1637 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1638 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1639 msm_host->err_work_state |= 1640 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1641 } 1642 } 1643 1644 static void dsi_status(struct msm_dsi_host *msm_host) 1645 { 1646 u32 status; 1647 1648 status = dsi_read(msm_host, REG_DSI_STATUS0); 1649 1650 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1651 dsi_write(msm_host, REG_DSI_STATUS0, status); 1652 msm_host->err_work_state |= 1653 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1654 } 1655 } 1656 1657 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1658 { 1659 u32 status; 1660 1661 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1662 1663 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1664 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1665 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1666 } 1667 } 1668 1669 static void dsi_error(struct msm_dsi_host *msm_host) 1670 { 1671 /* disable dsi error interrupt */ 1672 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1673 1674 dsi_clk_status(msm_host); 1675 dsi_fifo_status(msm_host); 1676 dsi_ack_err_status(msm_host); 1677 dsi_timeout_status(msm_host); 1678 dsi_status(msm_host); 1679 dsi_dln0_phy_err(msm_host); 1680 1681 queue_work(msm_host->workqueue, &msm_host->err_work); 1682 } 1683 1684 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1685 { 1686 struct msm_dsi_host *msm_host = ptr; 1687 u32 isr; 1688 unsigned long flags; 1689 1690 if (!msm_host->ctrl_base) 1691 return IRQ_HANDLED; 1692 1693 spin_lock_irqsave(&msm_host->intr_lock, flags); 1694 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1695 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1696 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1697 1698 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1699 1700 if (isr & DSI_IRQ_ERROR) 1701 dsi_error(msm_host); 1702 1703 if (isr & DSI_IRQ_VIDEO_DONE) 1704 complete(&msm_host->video_comp); 1705 1706 if (isr & DSI_IRQ_CMD_DMA_DONE) 1707 complete(&msm_host->dma_comp); 1708 1709 return IRQ_HANDLED; 1710 } 1711 1712 static int dsi_host_attach(struct mipi_dsi_host *host, 1713 struct mipi_dsi_device *dsi) 1714 { 1715 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1716 int ret; 1717 1718 if (dsi->lanes > msm_host->num_data_lanes) 1719 return -EINVAL; 1720 1721 msm_host->channel = dsi->channel; 1722 msm_host->lanes = dsi->lanes; 1723 msm_host->format = dsi->format; 1724 msm_host->mode_flags = dsi->mode_flags; 1725 if (dsi->dsc) { 1726 msm_host->dsc = dsi->dsc; 1727 if (dsi->mode_flags & MIPI_DSI_MODE_DSC_ALL_SLICES_IN_PKT) 1728 msm_host->dsc_slice_per_pkt = dsi->dsc->slice_count; 1729 else 1730 msm_host->dsc_slice_per_pkt = 1; 1731 } 1732 1733 if (msm_host->format == MIPI_DSI_FMT_RGB101010) { 1734 if (!msm_dsi_host_version_geq(msm_host, MSM_DSI_VER_MAJOR_6G, 1735 MSM_DSI_6G_VER_MINOR_V2_1_0)) { 1736 DRM_DEV_ERROR(&msm_host->pdev->dev, 1737 "RGB101010 not supported on this DSI controller\n"); 1738 return -EINVAL; 1739 } 1740 1741 /* 1742 * Downstream overrides RGB101010 back to RGB888 when DSC is enabled 1743 * but widebus is not. Using RGB101010 in this case may require some 1744 * extra changes. 1745 */ 1746 if (msm_host->dsc && 1747 !msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) { 1748 dev_warn(&msm_host->pdev->dev, 1749 "RGB101010 with DSC but without widebus, may need extra changes\n"); 1750 } 1751 } 1752 1753 ret = dsi_dev_attach(msm_host->pdev); 1754 if (ret) 1755 return ret; 1756 1757 DBG("id=%d", msm_host->id); 1758 1759 return 0; 1760 } 1761 1762 static int dsi_host_detach(struct mipi_dsi_host *host, 1763 struct mipi_dsi_device *dsi) 1764 { 1765 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1766 1767 dsi_dev_detach(msm_host->pdev); 1768 1769 DBG("id=%d", msm_host->id); 1770 1771 return 0; 1772 } 1773 1774 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1775 const struct mipi_dsi_msg *msg) 1776 { 1777 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1778 int ret; 1779 1780 if (!msg || !msm_host->power_on) 1781 return -EINVAL; 1782 1783 mutex_lock(&msm_host->cmd_mutex); 1784 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1785 mutex_unlock(&msm_host->cmd_mutex); 1786 1787 return ret; 1788 } 1789 1790 static const struct mipi_dsi_host_ops dsi_host_ops = { 1791 .attach = dsi_host_attach, 1792 .detach = dsi_host_detach, 1793 .transfer = dsi_host_transfer, 1794 }; 1795 1796 /* 1797 * List of supported physical to logical lane mappings. 1798 * For example, the 2nd entry represents the following mapping: 1799 * 1800 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1801 */ 1802 static const int supported_data_lane_swaps[][4] = { 1803 { 0, 1, 2, 3 }, 1804 { 3, 0, 1, 2 }, 1805 { 2, 3, 0, 1 }, 1806 { 1, 2, 3, 0 }, 1807 { 0, 3, 2, 1 }, 1808 { 1, 0, 3, 2 }, 1809 { 2, 1, 0, 3 }, 1810 { 3, 2, 1, 0 }, 1811 }; 1812 1813 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1814 struct device_node *ep) 1815 { 1816 struct device *dev = &msm_host->pdev->dev; 1817 struct property *prop; 1818 u32 lane_map[4]; 1819 int ret, i, len, num_lanes; 1820 1821 prop = of_find_property(ep, "data-lanes", &len); 1822 if (!prop) { 1823 DRM_DEV_DEBUG(dev, 1824 "failed to find data lane mapping, using default\n"); 1825 /* Set the number of date lanes to 4 by default. */ 1826 msm_host->num_data_lanes = 4; 1827 return 0; 1828 } 1829 1830 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1831 if (num_lanes < 0) { 1832 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1833 return num_lanes; 1834 } 1835 1836 msm_host->num_data_lanes = num_lanes; 1837 1838 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1839 num_lanes); 1840 if (ret) { 1841 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1842 return ret; 1843 } 1844 1845 /* 1846 * compare DT specified physical-logical lane mappings with the ones 1847 * supported by hardware 1848 */ 1849 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1850 const int *swap = supported_data_lane_swaps[i]; 1851 int j; 1852 1853 /* 1854 * the data-lanes array we get from DT has a logical->physical 1855 * mapping. The "data lane swap" register field represents 1856 * supported configurations in a physical->logical mapping. 1857 * Translate the DT mapping to what we understand and find a 1858 * configuration that works. 1859 */ 1860 for (j = 0; j < num_lanes; j++) { 1861 if (lane_map[j] < 0 || lane_map[j] > 3) 1862 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1863 lane_map[j]); 1864 1865 if (swap[lane_map[j]] != j) 1866 break; 1867 } 1868 1869 if (j == num_lanes) { 1870 msm_host->dlane_swap = i; 1871 return 0; 1872 } 1873 } 1874 1875 return -EINVAL; 1876 } 1877 1878 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1879 { 1880 int ret; 1881 1882 if (dsc->bits_per_pixel & 0xf) { 1883 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1884 return -EINVAL; 1885 } 1886 1887 switch (dsc->bits_per_component) { 1888 case 8: 1889 case 10: 1890 case 12: 1891 /* 1892 * Only 8, 10, and 12 bpc are supported for DSC 1.1 block. 1893 * If additional bpc values need to be supported, update 1894 * this quard with the appropriate DSC version verification. 1895 */ 1896 break; 1897 default: 1898 DRM_DEV_ERROR(&msm_host->pdev->dev, 1899 "Unsupported bits_per_component value: %d\n", 1900 dsc->bits_per_component); 1901 return -EOPNOTSUPP; 1902 } 1903 1904 dsc->simple_422 = 0; 1905 dsc->convert_rgb = 1; 1906 dsc->vbr_enable = 0; 1907 1908 drm_dsc_set_const_params(dsc); 1909 drm_dsc_set_rc_buf_thresh(dsc); 1910 1911 /* DPU supports only pre-SCR panels */ 1912 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); 1913 if (ret) { 1914 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); 1915 return ret; 1916 } 1917 1918 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc); 1919 dsc->line_buf_depth = dsc->bits_per_component + 1; 1920 1921 return drm_dsc_compute_rc_parameters(dsc); 1922 } 1923 1924 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1925 { 1926 struct msm_dsi *msm_dsi = platform_get_drvdata(msm_host->pdev); 1927 struct device *dev = &msm_host->pdev->dev; 1928 struct device_node *np = dev->of_node; 1929 struct device_node *endpoint; 1930 const char *te_source; 1931 int ret = 0; 1932 1933 /* 1934 * Get the endpoint of the output port of the DSI host. In our case, 1935 * this is mapped to port number with reg = 1. Don't return an error if 1936 * the remote endpoint isn't defined. It's possible that there is 1937 * nothing connected to the dsi output. 1938 */ 1939 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1940 if (!endpoint) { 1941 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1942 return 0; 1943 } 1944 1945 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1946 if (ret) { 1947 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1948 __func__, ret); 1949 ret = -EINVAL; 1950 goto err; 1951 } 1952 1953 ret = of_property_read_string(endpoint, "qcom,te-source", &te_source); 1954 if (ret && ret != -EINVAL) { 1955 DRM_DEV_ERROR(dev, "%s: invalid TE source configuration %d\n", 1956 __func__, ret); 1957 goto err; 1958 } 1959 if (!ret) { 1960 msm_dsi->te_source = devm_kstrdup(dev, te_source, GFP_KERNEL); 1961 if (!msm_dsi->te_source) { 1962 DRM_DEV_ERROR(dev, "%s: failed to allocate te_source\n", 1963 __func__); 1964 ret = -ENOMEM; 1965 goto err; 1966 } 1967 } 1968 ret = 0; 1969 1970 if (of_property_present(np, "syscon-sfpb")) { 1971 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1972 "syscon-sfpb"); 1973 if (IS_ERR(msm_host->sfpb)) { 1974 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1975 __func__); 1976 ret = PTR_ERR(msm_host->sfpb); 1977 } 1978 } 1979 1980 err: 1981 of_node_put(endpoint); 1982 1983 return ret; 1984 } 1985 1986 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1987 { 1988 struct platform_device *pdev = msm_host->pdev; 1989 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1990 struct resource *res; 1991 int i, j; 1992 1993 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1994 if (!res) 1995 return -EINVAL; 1996 1997 for (i = 0; i < VARIANTS_MAX; i++) 1998 for (j = 0; j < DSI_MAX; j++) 1999 if (cfg->io_start[i][j] == res->start) 2000 return j; 2001 2002 return -EINVAL; 2003 } 2004 2005 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 2006 { 2007 struct msm_dsi_host *msm_host = NULL; 2008 struct platform_device *pdev = msm_dsi->pdev; 2009 const struct msm_dsi_config *cfg; 2010 int ret; 2011 2012 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 2013 if (!msm_host) 2014 return -ENOMEM; 2015 2016 msm_host->pdev = pdev; 2017 msm_dsi->host = &msm_host->base; 2018 2019 ret = dsi_host_parse_dt(msm_host); 2020 if (ret) 2021 return dev_err_probe(&pdev->dev, ret, "%s: failed to parse dt\n", 2022 __func__); 2023 2024 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 2025 if (IS_ERR(msm_host->ctrl_base)) 2026 return dev_err_probe(&pdev->dev, PTR_ERR(msm_host->ctrl_base), 2027 "%s: unable to map Dsi ctrl base\n", __func__); 2028 2029 pm_runtime_enable(&pdev->dev); 2030 2031 msm_host->cfg_hnd = dsi_get_config(msm_host); 2032 if (!msm_host->cfg_hnd) 2033 return dev_err_probe(&pdev->dev, -EINVAL, 2034 "%s: get config failed\n", __func__); 2035 cfg = msm_host->cfg_hnd->cfg; 2036 2037 msm_host->id = dsi_host_get_id(msm_host); 2038 if (msm_host->id < 0) 2039 return dev_err_probe(&pdev->dev, msm_host->id, 2040 "%s: unable to identify DSI host index\n", 2041 __func__); 2042 2043 /* fixup base address by io offset */ 2044 msm_host->ctrl_base += cfg->io_offset; 2045 msm_host->ctrl_size -= cfg->io_offset; 2046 2047 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 2048 cfg->regulator_data, 2049 &msm_host->supplies); 2050 if (ret) 2051 return ret; 2052 2053 ret = dsi_clk_init(msm_host); 2054 if (ret) 2055 return dev_err_probe(&pdev->dev, ret, "%s: unable to initialize dsi clks\n", __func__); 2056 2057 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 2058 if (!msm_host->rx_buf) 2059 return -ENOMEM; 2060 2061 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 2062 if (ret) 2063 return ret; 2064 /* OPP table is optional */ 2065 ret = devm_pm_opp_of_add_table(&pdev->dev); 2066 if (ret && ret != -ENODEV) 2067 return dev_err_probe(&pdev->dev, ret, "invalid OPP table in device tree\n"); 2068 2069 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 2070 if (!msm_host->irq) 2071 return dev_err_probe(&pdev->dev, -EINVAL, "failed to get irq\n"); 2072 2073 /* do not autoenable, will be enabled later */ 2074 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 2075 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 2076 "dsi_isr", msm_host); 2077 if (ret < 0) 2078 return dev_err_probe(&pdev->dev, ret, "failed to request IRQ%u\n", 2079 msm_host->irq); 2080 2081 init_completion(&msm_host->dma_comp); 2082 init_completion(&msm_host->video_comp); 2083 mutex_init(&msm_host->dev_mutex); 2084 mutex_init(&msm_host->cmd_mutex); 2085 spin_lock_init(&msm_host->intr_lock); 2086 2087 /* setup workqueue */ 2088 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 2089 if (!msm_host->workqueue) 2090 return -ENOMEM; 2091 2092 INIT_WORK(&msm_host->err_work, dsi_err_worker); 2093 2094 msm_dsi->id = msm_host->id; 2095 2096 DBG("Dsi Host %d initialized", msm_host->id); 2097 return 0; 2098 } 2099 2100 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 2101 { 2102 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2103 2104 DBG(""); 2105 if (msm_host->workqueue) { 2106 destroy_workqueue(msm_host->workqueue); 2107 msm_host->workqueue = NULL; 2108 } 2109 2110 mutex_destroy(&msm_host->cmd_mutex); 2111 mutex_destroy(&msm_host->dev_mutex); 2112 2113 pm_runtime_disable(&msm_host->pdev->dev); 2114 } 2115 2116 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 2117 struct drm_device *dev) 2118 { 2119 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2120 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2121 int ret; 2122 2123 msm_host->dev = dev; 2124 2125 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2126 if (ret) { 2127 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2128 return ret; 2129 } 2130 2131 return 0; 2132 } 2133 2134 int msm_dsi_host_register(struct mipi_dsi_host *host) 2135 { 2136 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2137 int ret; 2138 2139 /* Register mipi dsi host */ 2140 if (!msm_host->registered) { 2141 host->dev = &msm_host->pdev->dev; 2142 host->ops = &dsi_host_ops; 2143 ret = mipi_dsi_host_register(host); 2144 if (ret) 2145 return ret; 2146 2147 msm_host->registered = true; 2148 } 2149 2150 return 0; 2151 } 2152 2153 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2154 { 2155 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2156 2157 if (msm_host->registered) { 2158 mipi_dsi_host_unregister(host); 2159 host->dev = NULL; 2160 host->ops = NULL; 2161 msm_host->registered = false; 2162 } 2163 } 2164 2165 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2166 const struct mipi_dsi_msg *msg) 2167 { 2168 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2169 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2170 2171 /* TODO: make sure dsi_cmd_mdp is idle. 2172 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2173 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2174 * How to handle the old versions? Wait for mdp cmd done? 2175 */ 2176 2177 /* 2178 * mdss interrupt is generated in mdp core clock domain 2179 * mdp clock need to be enabled to receive dsi interrupt 2180 */ 2181 pm_runtime_get_sync(&msm_host->pdev->dev); 2182 cfg_hnd->ops->link_clk_set_rate(msm_host); 2183 cfg_hnd->ops->link_clk_enable(msm_host); 2184 2185 /* TODO: vote for bus bandwidth */ 2186 2187 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2188 dsi_set_tx_power_mode(0, msm_host); 2189 2190 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2191 dsi_write(msm_host, REG_DSI_CTRL, 2192 msm_host->dma_cmd_ctrl_restore | 2193 DSI_CTRL_CMD_MODE_EN | 2194 DSI_CTRL_ENABLE); 2195 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2196 2197 return 0; 2198 } 2199 2200 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2201 const struct mipi_dsi_msg *msg) 2202 { 2203 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2204 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2205 2206 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2207 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2208 2209 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2210 dsi_set_tx_power_mode(1, msm_host); 2211 2212 /* TODO: unvote for bus bandwidth */ 2213 2214 cfg_hnd->ops->link_clk_disable(msm_host); 2215 pm_runtime_put(&msm_host->pdev->dev); 2216 } 2217 2218 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2219 const struct mipi_dsi_msg *msg) 2220 { 2221 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2222 2223 return dsi_cmds2buf_tx(msm_host, msg); 2224 } 2225 2226 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2227 const struct mipi_dsi_msg *msg) 2228 { 2229 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2230 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2231 int data_byte, rx_byte, dlen, end; 2232 int short_response, diff, pkt_size, ret = 0; 2233 char cmd; 2234 int rlen = msg->rx_len; 2235 u8 *buf; 2236 2237 if (rlen <= 2) { 2238 short_response = 1; 2239 pkt_size = rlen; 2240 rx_byte = 4; 2241 } else { 2242 short_response = 0; 2243 data_byte = 10; /* first read */ 2244 if (rlen < data_byte) 2245 pkt_size = rlen; 2246 else 2247 pkt_size = data_byte; 2248 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2249 } 2250 2251 buf = msm_host->rx_buf; 2252 end = 0; 2253 while (!end) { 2254 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2255 struct mipi_dsi_msg max_pkt_size_msg = { 2256 .channel = msg->channel, 2257 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2258 .tx_len = 2, 2259 .tx_buf = tx, 2260 }; 2261 2262 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2263 rlen, pkt_size, rx_byte); 2264 2265 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2266 if (ret < 2) { 2267 pr_err("%s: Set max pkt size failed, %d\n", 2268 __func__, ret); 2269 return -EINVAL; 2270 } 2271 2272 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2273 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2274 /* Clear the RDBK_DATA registers */ 2275 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2276 DSI_RDBK_DATA_CTRL_CLR); 2277 wmb(); /* make sure the RDBK registers are cleared */ 2278 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2279 wmb(); /* release cleared status before transfer */ 2280 } 2281 2282 ret = dsi_cmds2buf_tx(msm_host, msg); 2283 if (ret < 0) { 2284 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2285 return ret; 2286 } else if (ret < msg->tx_len) { 2287 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2288 return -ECOMM; 2289 } 2290 2291 /* 2292 * once cmd_dma_done interrupt received, 2293 * return data from client is ready and stored 2294 * at RDBK_DATA register already 2295 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2296 * after that dcs header lost during shift into registers 2297 */ 2298 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2299 2300 if (dlen <= 0) 2301 return 0; 2302 2303 if (short_response) 2304 break; 2305 2306 if (rlen <= data_byte) { 2307 diff = data_byte - rlen; 2308 end = 1; 2309 } else { 2310 diff = 0; 2311 rlen -= data_byte; 2312 } 2313 2314 if (!end) { 2315 dlen -= 2; /* 2 crc */ 2316 dlen -= diff; 2317 buf += dlen; /* next start position */ 2318 data_byte = 14; /* NOT first read */ 2319 if (rlen < data_byte) 2320 pkt_size += rlen; 2321 else 2322 pkt_size += data_byte; 2323 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2324 } 2325 } 2326 2327 /* 2328 * For single Long read, if the requested rlen < 10, 2329 * we need to shift the start position of rx 2330 * data buffer to skip the bytes which are not 2331 * updated. 2332 */ 2333 if (pkt_size < 10 && !short_response) 2334 buf = msm_host->rx_buf + (10 - rlen); 2335 else 2336 buf = msm_host->rx_buf; 2337 2338 cmd = buf[0]; 2339 switch (cmd) { 2340 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2341 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2342 ret = 0; 2343 break; 2344 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2345 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2346 ret = dsi_short_read1_resp(buf, msg); 2347 break; 2348 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2349 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2350 ret = dsi_short_read2_resp(buf, msg); 2351 break; 2352 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2353 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2354 ret = dsi_long_read_resp(buf, msg); 2355 break; 2356 default: 2357 pr_warn("%s:Invalid response cmd\n", __func__); 2358 ret = 0; 2359 } 2360 2361 return ret; 2362 } 2363 2364 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2365 u32 len) 2366 { 2367 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2368 2369 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2370 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2371 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2372 2373 /* Make sure trigger happens */ 2374 wmb(); 2375 } 2376 2377 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2378 struct msm_dsi_phy *src_phy) 2379 { 2380 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2381 2382 msm_host->cphy_mode = src_phy->cphy_mode; 2383 } 2384 2385 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2386 { 2387 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2388 2389 DBG(""); 2390 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2391 /* Make sure fully reset */ 2392 wmb(); 2393 udelay(1000); 2394 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2395 udelay(100); 2396 } 2397 2398 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2399 struct msm_dsi_phy_clk_request *clk_req, 2400 bool is_bonded_dsi) 2401 { 2402 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2403 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2404 int ret; 2405 2406 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2407 if (ret) { 2408 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2409 return; 2410 } 2411 2412 /* CPHY transmits 16 bits over 7 clock cycles 2413 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2414 * so multiply by 7 to get the "bitclk rate" 2415 */ 2416 if (msm_host->cphy_mode) 2417 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2418 else 2419 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2420 clk_req->escclk_rate = msm_host->esc_clk_rate; 2421 } 2422 2423 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2424 { 2425 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2426 2427 enable_irq(msm_host->irq); 2428 } 2429 2430 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2431 { 2432 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2433 2434 disable_irq(msm_host->irq); 2435 } 2436 2437 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2438 { 2439 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2440 2441 dsi_op_mode_config(msm_host, 2442 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2443 2444 /* TODO: clock should be turned off for command mode, 2445 * and only turned on before MDP START. 2446 * This part of code should be enabled once mdp driver support it. 2447 */ 2448 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2449 * dsi_link_clk_disable(msm_host); 2450 * pm_runtime_put(&msm_host->pdev->dev); 2451 * } 2452 */ 2453 msm_host->enabled = true; 2454 return 0; 2455 } 2456 2457 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2458 { 2459 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2460 2461 msm_host->enabled = false; 2462 dsi_op_mode_config(msm_host, 2463 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2464 2465 /* Since we have disabled INTF, the video engine won't stop so that 2466 * the cmd engine will be blocked. 2467 * Reset to disable video engine so that we can send off cmd. 2468 */ 2469 dsi_sw_reset(msm_host); 2470 2471 return 0; 2472 } 2473 2474 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2475 { 2476 enum sfpb_ahb_arb_master_port_en en; 2477 2478 if (!msm_host->sfpb) 2479 return; 2480 2481 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2482 2483 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2484 SFPB_GPREG_MASTER_PORT_EN__MASK, 2485 SFPB_GPREG_MASTER_PORT_EN(en)); 2486 } 2487 2488 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2489 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2490 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2491 { 2492 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2493 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2494 int ret = 0; 2495 2496 mutex_lock(&msm_host->dev_mutex); 2497 if (msm_host->power_on) { 2498 DBG("dsi host already on"); 2499 goto unlock_ret; 2500 } 2501 2502 msm_host->byte_intf_clk_div_2 = phy_shared_timings->byte_intf_clk_div_2; 2503 2504 msm_dsi_sfpb_config(msm_host, true); 2505 2506 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2507 msm_host->supplies); 2508 if (ret) { 2509 pr_err("%s:Failed to enable vregs.ret=%d\n", 2510 __func__, ret); 2511 goto unlock_ret; 2512 } 2513 2514 pm_runtime_get_sync(&msm_host->pdev->dev); 2515 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2516 if (!ret) 2517 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2518 if (ret) { 2519 pr_err("%s: failed to enable link clocks. ret=%d\n", 2520 __func__, ret); 2521 goto fail_disable_reg; 2522 } 2523 2524 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2525 if (ret) { 2526 pr_err("%s: failed to set pinctrl default state, %d\n", 2527 __func__, ret); 2528 goto fail_disable_clk; 2529 } 2530 2531 dsi_timing_setup(msm_host, is_bonded_dsi); 2532 dsi_sw_reset(msm_host); 2533 dsi_ctrl_enable(msm_host, phy_shared_timings, phy); 2534 2535 msm_host->power_on = true; 2536 mutex_unlock(&msm_host->dev_mutex); 2537 2538 return 0; 2539 2540 fail_disable_clk: 2541 cfg_hnd->ops->link_clk_disable(msm_host); 2542 pm_runtime_put(&msm_host->pdev->dev); 2543 fail_disable_reg: 2544 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2545 msm_host->supplies); 2546 unlock_ret: 2547 mutex_unlock(&msm_host->dev_mutex); 2548 return ret; 2549 } 2550 2551 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2552 { 2553 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2554 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2555 2556 mutex_lock(&msm_host->dev_mutex); 2557 if (!msm_host->power_on) { 2558 DBG("dsi host already off"); 2559 goto unlock_ret; 2560 } 2561 2562 dsi_ctrl_disable(msm_host); 2563 2564 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2565 2566 cfg_hnd->ops->link_clk_disable(msm_host); 2567 pm_runtime_put(&msm_host->pdev->dev); 2568 2569 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2570 msm_host->supplies); 2571 2572 msm_dsi_sfpb_config(msm_host, false); 2573 2574 DBG("-"); 2575 2576 msm_host->power_on = false; 2577 2578 unlock_ret: 2579 mutex_unlock(&msm_host->dev_mutex); 2580 return 0; 2581 } 2582 2583 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2584 const struct drm_display_mode *mode) 2585 { 2586 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2587 2588 if (msm_host->mode) { 2589 drm_mode_destroy(msm_host->dev, msm_host->mode); 2590 msm_host->mode = NULL; 2591 } 2592 2593 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2594 if (!msm_host->mode) { 2595 pr_err("%s: cannot duplicate mode\n", __func__); 2596 return -ENOMEM; 2597 } 2598 2599 return 0; 2600 } 2601 2602 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2603 const struct drm_display_mode *mode) 2604 { 2605 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2606 struct drm_dsc_config *dsc = msm_host->dsc; 2607 int pic_width = mode->hdisplay; 2608 int pic_height = mode->vdisplay; 2609 2610 if (!msm_host->dsc) 2611 return MODE_OK; 2612 2613 if (pic_width % dsc->slice_width) { 2614 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2615 pic_width, dsc->slice_width); 2616 return MODE_H_ILLEGAL; 2617 } 2618 2619 if (pic_height % dsc->slice_height) { 2620 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2621 pic_height, dsc->slice_height); 2622 return MODE_V_ILLEGAL; 2623 } 2624 2625 return MODE_OK; 2626 } 2627 2628 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2629 { 2630 return to_msm_dsi_host(host)->mode_flags; 2631 } 2632 2633 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2634 { 2635 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2636 2637 pm_runtime_get_sync(&msm_host->pdev->dev); 2638 2639 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2640 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2641 2642 pm_runtime_put_sync(&msm_host->pdev->dev); 2643 } 2644 2645 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2646 { 2647 u32 reg; 2648 2649 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2650 2651 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2652 /* draw checkered rectangle pattern */ 2653 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2654 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2655 /* use 24-bit RGB test pttern */ 2656 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2657 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2658 DSI_TPG_VIDEO_CONFIG_RGB); 2659 2660 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2661 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2662 2663 DBG("Video test pattern setup done\n"); 2664 } 2665 2666 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2667 { 2668 u32 reg; 2669 2670 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2671 2672 /* initial value for test pattern */ 2673 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2674 2675 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2676 2677 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2678 /* draw checkered rectangle pattern */ 2679 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2680 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2681 2682 DBG("Cmd test pattern setup done\n"); 2683 } 2684 2685 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2686 { 2687 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2688 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2689 u32 reg; 2690 2691 if (is_video_mode) 2692 msm_dsi_host_video_test_pattern_setup(msm_host); 2693 else 2694 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2695 2696 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2697 /* enable the test pattern generator */ 2698 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2699 2700 /* for command mode need to trigger one frame from tpg */ 2701 if (!is_video_mode) 2702 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2703 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2704 } 2705 2706 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2707 { 2708 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2709 2710 return msm_host->dsc; 2711 } 2712