1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/err.h> 10 #include <linux/gpio/consumer.h> 11 #include <linux/interrupt.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/of_irq.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_opp.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spinlock.h> 21 22 #include <video/mipi_display.h> 23 24 #include <drm/display/drm_dsc_helper.h> 25 #include <drm/drm_of.h> 26 27 #include "dsi.h" 28 #include "dsi.xml.h" 29 #include "sfpb.xml.h" 30 #include "dsi_cfg.h" 31 #include "msm_kms.h" 32 #include "msm_gem.h" 33 #include "phy/dsi_phy.h" 34 35 #define DSI_RESET_TOGGLE_DELAY_MS 20 36 37 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc); 38 39 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 40 { 41 u32 ver; 42 43 if (!major || !minor) 44 return -EINVAL; 45 46 /* 47 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 48 * makes all other registers 4-byte shifted down. 49 * 50 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 51 * older, we read the DSI_VERSION register without any shift(offset 52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 53 * the case of DSI6G, this has to be zero (the offset points to a 54 * scratch register which we never touch) 55 */ 56 57 ver = msm_readl(base + REG_DSI_VERSION); 58 if (ver) { 59 /* older dsi host, there is no register shift */ 60 ver = FIELD(ver, DSI_VERSION_MAJOR); 61 if (ver <= MSM_DSI_VER_MAJOR_V2) { 62 /* old versions */ 63 *major = ver; 64 *minor = 0; 65 return 0; 66 } else { 67 return -EINVAL; 68 } 69 } else { 70 /* 71 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 72 * registers are shifted down, read DSI_VERSION again with 73 * the shifted offset 74 */ 75 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 76 ver = FIELD(ver, DSI_VERSION_MAJOR); 77 if (ver == MSM_DSI_VER_MAJOR_6G) { 78 /* 6G version */ 79 *major = ver; 80 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 81 return 0; 82 } else { 83 return -EINVAL; 84 } 85 } 86 } 87 88 #define DSI_ERR_STATE_ACK 0x0000 89 #define DSI_ERR_STATE_TIMEOUT 0x0001 90 #define DSI_ERR_STATE_DLN0_PHY 0x0002 91 #define DSI_ERR_STATE_FIFO 0x0004 92 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 93 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 94 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 95 96 #define DSI_CLK_CTRL_ENABLE_CLKS \ 97 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 98 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 99 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 100 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 101 102 struct msm_dsi_host { 103 struct mipi_dsi_host base; 104 105 struct platform_device *pdev; 106 struct drm_device *dev; 107 108 int id; 109 110 void __iomem *ctrl_base; 111 phys_addr_t ctrl_size; 112 struct regulator_bulk_data *supplies; 113 114 int num_bus_clks; 115 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX]; 116 117 struct clk *byte_clk; 118 struct clk *esc_clk; 119 struct clk *pixel_clk; 120 struct clk *byte_clk_src; 121 struct clk *pixel_clk_src; 122 struct clk *byte_intf_clk; 123 124 unsigned long byte_clk_rate; 125 unsigned long byte_intf_clk_rate; 126 unsigned long pixel_clk_rate; 127 unsigned long esc_clk_rate; 128 129 /* DSI v2 specific clocks */ 130 struct clk *src_clk; 131 struct clk *esc_clk_src; 132 struct clk *dsi_clk_src; 133 134 unsigned long src_clk_rate; 135 136 struct gpio_desc *disp_en_gpio; 137 struct gpio_desc *te_gpio; 138 139 const struct msm_dsi_cfg_handler *cfg_hnd; 140 141 struct completion dma_comp; 142 struct completion video_comp; 143 struct mutex dev_mutex; 144 struct mutex cmd_mutex; 145 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 146 147 u32 err_work_state; 148 struct work_struct err_work; 149 struct workqueue_struct *workqueue; 150 151 /* DSI 6G TX buffer*/ 152 struct drm_gem_object *tx_gem_obj; 153 154 /* DSI v2 TX buffer */ 155 void *tx_buf; 156 dma_addr_t tx_buf_paddr; 157 158 int tx_size; 159 160 u8 *rx_buf; 161 162 struct regmap *sfpb; 163 164 struct drm_display_mode *mode; 165 struct drm_dsc_config *dsc; 166 167 /* connected device info */ 168 unsigned int channel; 169 unsigned int lanes; 170 enum mipi_dsi_pixel_format format; 171 unsigned long mode_flags; 172 173 /* lane data parsed via DT */ 174 int dlane_swap; 175 int num_data_lanes; 176 177 /* from phy DT */ 178 bool cphy_mode; 179 180 u32 dma_cmd_ctrl_restore; 181 182 bool registered; 183 bool power_on; 184 bool enabled; 185 int irq; 186 }; 187 188 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 189 { 190 switch (fmt) { 191 case MIPI_DSI_FMT_RGB565: return 16; 192 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 193 case MIPI_DSI_FMT_RGB666: 194 case MIPI_DSI_FMT_RGB888: 195 default: return 24; 196 } 197 } 198 199 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 200 { 201 return msm_readl(msm_host->ctrl_base + reg); 202 } 203 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 204 { 205 msm_writel(data, msm_host->ctrl_base + reg); 206 } 207 208 static const struct msm_dsi_cfg_handler *dsi_get_config( 209 struct msm_dsi_host *msm_host) 210 { 211 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 212 struct device *dev = &msm_host->pdev->dev; 213 struct clk *ahb_clk; 214 int ret; 215 u32 major = 0, minor = 0; 216 217 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 218 if (IS_ERR(ahb_clk)) { 219 pr_err("%s: cannot get interface clock\n", __func__); 220 goto exit; 221 } 222 223 pm_runtime_get_sync(dev); 224 225 ret = clk_prepare_enable(ahb_clk); 226 if (ret) { 227 pr_err("%s: unable to enable ahb_clk\n", __func__); 228 goto runtime_put; 229 } 230 231 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 232 if (ret) { 233 pr_err("%s: Invalid version\n", __func__); 234 goto disable_clks; 235 } 236 237 cfg_hnd = msm_dsi_cfg_get(major, minor); 238 239 DBG("%s: Version %x:%x\n", __func__, major, minor); 240 241 disable_clks: 242 clk_disable_unprepare(ahb_clk); 243 runtime_put: 244 pm_runtime_put_sync(dev); 245 exit: 246 return cfg_hnd; 247 } 248 249 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 250 { 251 return container_of(host, struct msm_dsi_host, base); 252 } 253 254 int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 255 { 256 struct platform_device *pdev = msm_host->pdev; 257 int ret = 0; 258 259 msm_host->src_clk = msm_clk_get(pdev, "src"); 260 261 if (IS_ERR(msm_host->src_clk)) { 262 ret = PTR_ERR(msm_host->src_clk); 263 pr_err("%s: can't find src clock. ret=%d\n", 264 __func__, ret); 265 msm_host->src_clk = NULL; 266 return ret; 267 } 268 269 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 270 if (!msm_host->esc_clk_src) { 271 ret = -ENODEV; 272 pr_err("%s: can't get esc clock parent. ret=%d\n", 273 __func__, ret); 274 return ret; 275 } 276 277 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 278 if (!msm_host->dsi_clk_src) { 279 ret = -ENODEV; 280 pr_err("%s: can't get src clock parent. ret=%d\n", 281 __func__, ret); 282 } 283 284 return ret; 285 } 286 287 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 288 { 289 struct platform_device *pdev = msm_host->pdev; 290 int ret = 0; 291 292 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 293 if (IS_ERR(msm_host->byte_intf_clk)) { 294 ret = PTR_ERR(msm_host->byte_intf_clk); 295 pr_err("%s: can't find byte_intf clock. ret=%d\n", 296 __func__, ret); 297 } 298 299 return ret; 300 } 301 302 static int dsi_clk_init(struct msm_dsi_host *msm_host) 303 { 304 struct platform_device *pdev = msm_host->pdev; 305 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 306 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 307 int i, ret = 0; 308 309 /* get bus clocks */ 310 for (i = 0; i < cfg->num_bus_clks; i++) 311 msm_host->bus_clks[i].id = cfg->bus_clk_names[i]; 312 msm_host->num_bus_clks = cfg->num_bus_clks; 313 314 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks); 315 if (ret < 0) { 316 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret); 317 goto exit; 318 } 319 320 /* get link and source clocks */ 321 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 322 if (IS_ERR(msm_host->byte_clk)) { 323 ret = PTR_ERR(msm_host->byte_clk); 324 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 325 __func__, ret); 326 msm_host->byte_clk = NULL; 327 goto exit; 328 } 329 330 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 331 if (IS_ERR(msm_host->pixel_clk)) { 332 ret = PTR_ERR(msm_host->pixel_clk); 333 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 334 __func__, ret); 335 msm_host->pixel_clk = NULL; 336 goto exit; 337 } 338 339 msm_host->esc_clk = msm_clk_get(pdev, "core"); 340 if (IS_ERR(msm_host->esc_clk)) { 341 ret = PTR_ERR(msm_host->esc_clk); 342 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 343 __func__, ret); 344 msm_host->esc_clk = NULL; 345 goto exit; 346 } 347 348 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 349 if (IS_ERR(msm_host->byte_clk_src)) { 350 ret = PTR_ERR(msm_host->byte_clk_src); 351 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); 352 goto exit; 353 } 354 355 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 356 if (IS_ERR(msm_host->pixel_clk_src)) { 357 ret = PTR_ERR(msm_host->pixel_clk_src); 358 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); 359 goto exit; 360 } 361 362 if (cfg_hnd->ops->clk_init_ver) 363 ret = cfg_hnd->ops->clk_init_ver(msm_host); 364 exit: 365 return ret; 366 } 367 368 int msm_dsi_runtime_suspend(struct device *dev) 369 { 370 struct platform_device *pdev = to_platform_device(dev); 371 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 372 struct mipi_dsi_host *host = msm_dsi->host; 373 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 374 375 if (!msm_host->cfg_hnd) 376 return 0; 377 378 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks); 379 380 return 0; 381 } 382 383 int msm_dsi_runtime_resume(struct device *dev) 384 { 385 struct platform_device *pdev = to_platform_device(dev); 386 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 387 struct mipi_dsi_host *host = msm_dsi->host; 388 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 389 390 if (!msm_host->cfg_hnd) 391 return 0; 392 393 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks); 394 } 395 396 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 397 { 398 int ret; 399 400 DBG("Set clk rates: pclk=%d, byteclk=%lu", 401 msm_host->mode->clock, msm_host->byte_clk_rate); 402 403 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 404 msm_host->byte_clk_rate); 405 if (ret) { 406 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 407 return ret; 408 } 409 410 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 411 if (ret) { 412 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 413 return ret; 414 } 415 416 if (msm_host->byte_intf_clk) { 417 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate); 418 if (ret) { 419 pr_err("%s: Failed to set rate byte intf clk, %d\n", 420 __func__, ret); 421 return ret; 422 } 423 } 424 425 return 0; 426 } 427 428 429 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 430 { 431 int ret; 432 433 ret = clk_prepare_enable(msm_host->esc_clk); 434 if (ret) { 435 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 436 goto error; 437 } 438 439 ret = clk_prepare_enable(msm_host->byte_clk); 440 if (ret) { 441 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 442 goto byte_clk_err; 443 } 444 445 ret = clk_prepare_enable(msm_host->pixel_clk); 446 if (ret) { 447 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 448 goto pixel_clk_err; 449 } 450 451 ret = clk_prepare_enable(msm_host->byte_intf_clk); 452 if (ret) { 453 pr_err("%s: Failed to enable byte intf clk\n", 454 __func__); 455 goto byte_intf_clk_err; 456 } 457 458 return 0; 459 460 byte_intf_clk_err: 461 clk_disable_unprepare(msm_host->pixel_clk); 462 pixel_clk_err: 463 clk_disable_unprepare(msm_host->byte_clk); 464 byte_clk_err: 465 clk_disable_unprepare(msm_host->esc_clk); 466 error: 467 return ret; 468 } 469 470 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 471 { 472 int ret; 473 474 DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", 475 msm_host->mode->clock, msm_host->byte_clk_rate, 476 msm_host->esc_clk_rate, msm_host->src_clk_rate); 477 478 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 479 if (ret) { 480 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 481 return ret; 482 } 483 484 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 485 if (ret) { 486 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 487 return ret; 488 } 489 490 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 491 if (ret) { 492 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 493 return ret; 494 } 495 496 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 497 if (ret) { 498 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 499 return ret; 500 } 501 502 return 0; 503 } 504 505 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 506 { 507 int ret; 508 509 ret = clk_prepare_enable(msm_host->byte_clk); 510 if (ret) { 511 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 512 goto error; 513 } 514 515 ret = clk_prepare_enable(msm_host->esc_clk); 516 if (ret) { 517 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 518 goto esc_clk_err; 519 } 520 521 ret = clk_prepare_enable(msm_host->src_clk); 522 if (ret) { 523 pr_err("%s: Failed to enable dsi src clk\n", __func__); 524 goto src_clk_err; 525 } 526 527 ret = clk_prepare_enable(msm_host->pixel_clk); 528 if (ret) { 529 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 530 goto pixel_clk_err; 531 } 532 533 return 0; 534 535 pixel_clk_err: 536 clk_disable_unprepare(msm_host->src_clk); 537 src_clk_err: 538 clk_disable_unprepare(msm_host->esc_clk); 539 esc_clk_err: 540 clk_disable_unprepare(msm_host->byte_clk); 541 error: 542 return ret; 543 } 544 545 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 546 { 547 /* Drop the performance state vote */ 548 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 549 clk_disable_unprepare(msm_host->esc_clk); 550 clk_disable_unprepare(msm_host->pixel_clk); 551 clk_disable_unprepare(msm_host->byte_intf_clk); 552 clk_disable_unprepare(msm_host->byte_clk); 553 } 554 555 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 556 { 557 clk_disable_unprepare(msm_host->pixel_clk); 558 clk_disable_unprepare(msm_host->src_clk); 559 clk_disable_unprepare(msm_host->esc_clk); 560 clk_disable_unprepare(msm_host->byte_clk); 561 } 562 563 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode, bool is_bonded_dsi) 564 { 565 unsigned long pclk_rate; 566 567 pclk_rate = mode->clock * 1000; 568 569 /* 570 * For bonded DSI mode, the current DRM mode has the complete width of the 571 * panel. Since, the complete panel is driven by two DSI controllers, 572 * the clock rates have to be split between the two dsi controllers. 573 * Adjust the byte and pixel clock rates for each dsi host accordingly. 574 */ 575 if (is_bonded_dsi) 576 pclk_rate /= 2; 577 578 return pclk_rate; 579 } 580 581 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi, 582 const struct drm_display_mode *mode) 583 { 584 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 585 u8 lanes = msm_host->lanes; 586 u32 bpp = dsi_get_bpp(msm_host->format); 587 unsigned long pclk_rate = dsi_get_pclk_rate(mode, is_bonded_dsi); 588 u64 pclk_bpp = (u64)pclk_rate * bpp; 589 590 if (lanes == 0) { 591 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 592 lanes = 1; 593 } 594 595 /* CPHY "byte_clk" is in units of 16 bits */ 596 if (msm_host->cphy_mode) 597 do_div(pclk_bpp, (16 * lanes)); 598 else 599 do_div(pclk_bpp, (8 * lanes)); 600 601 return pclk_bpp; 602 } 603 604 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 605 { 606 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi); 607 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi, 608 msm_host->mode); 609 610 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, 611 msm_host->byte_clk_rate); 612 613 } 614 615 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 616 { 617 if (!msm_host->mode) { 618 pr_err("%s: mode not set\n", __func__); 619 return -EINVAL; 620 } 621 622 dsi_calc_pclk(msm_host, is_bonded_dsi); 623 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 624 return 0; 625 } 626 627 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 628 { 629 u32 bpp = dsi_get_bpp(msm_host->format); 630 u64 pclk_bpp; 631 unsigned int esc_mhz, esc_div; 632 unsigned long byte_mhz; 633 634 dsi_calc_pclk(msm_host, is_bonded_dsi); 635 636 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host->mode, is_bonded_dsi) * bpp; 637 do_div(pclk_bpp, 8); 638 msm_host->src_clk_rate = pclk_bpp; 639 640 /* 641 * esc clock is byte clock followed by a 4 bit divider, 642 * we need to find an escape clock frequency within the 643 * mipi DSI spec range within the maximum divider limit 644 * We iterate here between an escape clock frequencey 645 * between 20 Mhz to 5 Mhz and pick up the first one 646 * that can be supported by our divider 647 */ 648 649 byte_mhz = msm_host->byte_clk_rate / 1000000; 650 651 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 652 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 653 654 /* 655 * TODO: Ideally, we shouldn't know what sort of divider 656 * is available in mmss_cc, we're just assuming that 657 * it'll always be a 4 bit divider. Need to come up with 658 * a better way here. 659 */ 660 if (esc_div >= 1 && esc_div <= 16) 661 break; 662 } 663 664 if (esc_mhz < 5) 665 return -EINVAL; 666 667 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 668 669 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, 670 msm_host->src_clk_rate); 671 672 return 0; 673 } 674 675 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 676 { 677 u32 intr; 678 unsigned long flags; 679 680 spin_lock_irqsave(&msm_host->intr_lock, flags); 681 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 682 683 if (enable) 684 intr |= mask; 685 else 686 intr &= ~mask; 687 688 DBG("intr=%x enable=%d", intr, enable); 689 690 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 691 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 692 } 693 694 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 695 { 696 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 697 return BURST_MODE; 698 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 699 return NON_BURST_SYNCH_PULSE; 700 701 return NON_BURST_SYNCH_EVENT; 702 } 703 704 static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 705 const enum mipi_dsi_pixel_format mipi_fmt) 706 { 707 switch (mipi_fmt) { 708 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 709 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 710 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 711 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 712 default: return VID_DST_FORMAT_RGB888; 713 } 714 } 715 716 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 717 const enum mipi_dsi_pixel_format mipi_fmt) 718 { 719 switch (mipi_fmt) { 720 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 721 case MIPI_DSI_FMT_RGB666_PACKED: 722 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 723 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 724 default: return CMD_DST_FORMAT_RGB888; 725 } 726 } 727 728 static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 729 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) 730 { 731 u32 flags = msm_host->mode_flags; 732 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 733 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 734 u32 data = 0, lane_ctrl = 0; 735 736 if (!enable) { 737 dsi_write(msm_host, REG_DSI_CTRL, 0); 738 return; 739 } 740 741 if (flags & MIPI_DSI_MODE_VIDEO) { 742 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 743 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 744 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 745 data |= DSI_VID_CFG0_HFP_POWER_STOP; 746 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 747 data |= DSI_VID_CFG0_HBP_POWER_STOP; 748 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 749 data |= DSI_VID_CFG0_HSA_POWER_STOP; 750 /* Always set low power stop mode for BLLP 751 * to let command engine send packets 752 */ 753 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 754 DSI_VID_CFG0_BLLP_POWER_STOP; 755 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 756 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 757 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 758 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 759 760 /* Do not swap RGB colors */ 761 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 762 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 763 } else { 764 /* Do not swap RGB colors */ 765 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 766 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 767 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 768 769 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 770 DSI_CMD_CFG1_WR_MEM_CONTINUE( 771 MIPI_DCS_WRITE_MEMORY_CONTINUE); 772 /* Always insert DCS command */ 773 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 774 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 775 } 776 777 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 778 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 779 DSI_CMD_DMA_CTRL_LOW_POWER); 780 781 data = 0; 782 /* Always assume dedicated TE pin */ 783 data |= DSI_TRIG_CTRL_TE; 784 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 785 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 786 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 787 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 788 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 789 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 790 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 791 792 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 793 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 794 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 795 796 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 797 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 798 phy_shared_timings->clk_pre_inc_by_2) 799 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 800 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 801 802 data = 0; 803 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) 804 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 805 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 806 807 /* allow only ack-err-status to generate interrupt */ 808 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 809 810 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 811 812 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 813 814 data = DSI_CTRL_CLK_EN; 815 816 DBG("lane number=%d", msm_host->lanes); 817 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 818 819 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 820 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 821 822 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 823 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 824 825 if (msm_dsi_phy_set_continuous_clock(phy, enable)) 826 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; 827 828 dsi_write(msm_host, REG_DSI_LANE_CTRL, 829 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 830 } 831 832 data |= DSI_CTRL_ENABLE; 833 834 dsi_write(msm_host, REG_DSI_CTRL, data); 835 836 if (msm_host->cphy_mode) 837 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); 838 } 839 840 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay) 841 { 842 struct drm_dsc_config *dsc = msm_host->dsc; 843 u32 reg, reg_ctrl, reg_ctrl2; 844 u32 slice_per_intf, total_bytes_per_intf; 845 u32 pkt_per_line; 846 u32 eol_byte_num; 847 848 /* first calculate dsc parameters and then program 849 * compress mode registers 850 */ 851 slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); 852 853 /* 854 * If slice_count is greater than slice_per_intf 855 * then default to 1. This can happen during partial 856 * update. 857 */ 858 if (dsc->slice_count > slice_per_intf) 859 dsc->slice_count = 1; 860 861 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; 862 863 eol_byte_num = total_bytes_per_intf % 3; 864 pkt_per_line = slice_per_intf / dsc->slice_count; 865 866 if (is_cmd_mode) /* packet data type */ 867 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); 868 else 869 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM); 870 871 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE 872 * registers have similar offsets, so for below common code use 873 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits 874 */ 875 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); 876 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); 877 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN; 878 879 if (is_cmd_mode) { 880 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL); 881 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); 882 883 reg_ctrl &= ~0xffff; 884 reg_ctrl |= reg; 885 886 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; 887 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); 888 889 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); 890 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); 891 } else { 892 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); 893 } 894 } 895 896 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) 897 { 898 struct drm_display_mode *mode = msm_host->mode; 899 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 900 u32 h_total = mode->htotal; 901 u32 v_total = mode->vtotal; 902 u32 hs_end = mode->hsync_end - mode->hsync_start; 903 u32 vs_end = mode->vsync_end - mode->vsync_start; 904 u32 ha_start = h_total - mode->hsync_start; 905 u32 ha_end = ha_start + mode->hdisplay; 906 u32 va_start = v_total - mode->vsync_start; 907 u32 va_end = va_start + mode->vdisplay; 908 u32 hdisplay = mode->hdisplay; 909 u32 wc; 910 int ret; 911 912 DBG(""); 913 914 /* 915 * For bonded DSI mode, the current DRM mode has 916 * the complete width of the panel. Since, the complete 917 * panel is driven by two DSI controllers, the horizontal 918 * timings have to be split between the two dsi controllers. 919 * Adjust the DSI host timing values accordingly. 920 */ 921 if (is_bonded_dsi) { 922 h_total /= 2; 923 hs_end /= 2; 924 ha_start /= 2; 925 ha_end /= 2; 926 hdisplay /= 2; 927 } 928 929 if (msm_host->dsc) { 930 struct drm_dsc_config *dsc = msm_host->dsc; 931 932 /* update dsc params with timing params */ 933 if (!dsc || !mode->hdisplay || !mode->vdisplay) { 934 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", 935 mode->hdisplay, mode->vdisplay); 936 return; 937 } 938 939 dsc->pic_width = mode->hdisplay; 940 dsc->pic_height = mode->vdisplay; 941 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); 942 943 /* we do the calculations for dsc parameters here so that 944 * panel can use these parameters 945 */ 946 ret = dsi_populate_dsc_params(msm_host, dsc); 947 if (ret) 948 return; 949 950 /* Divide the display by 3 but keep back/font porch and 951 * pulse width same 952 */ 953 h_total -= hdisplay; 954 hdisplay /= 3; 955 h_total += hdisplay; 956 ha_end = ha_start + hdisplay; 957 } 958 959 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 960 if (msm_host->dsc) 961 dsi_update_dsc_timing(msm_host, false, mode->hdisplay); 962 963 dsi_write(msm_host, REG_DSI_ACTIVE_H, 964 DSI_ACTIVE_H_START(ha_start) | 965 DSI_ACTIVE_H_END(ha_end)); 966 dsi_write(msm_host, REG_DSI_ACTIVE_V, 967 DSI_ACTIVE_V_START(va_start) | 968 DSI_ACTIVE_V_END(va_end)); 969 dsi_write(msm_host, REG_DSI_TOTAL, 970 DSI_TOTAL_H_TOTAL(h_total - 1) | 971 DSI_TOTAL_V_TOTAL(v_total - 1)); 972 973 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 974 DSI_ACTIVE_HSYNC_START(hs_start) | 975 DSI_ACTIVE_HSYNC_END(hs_end)); 976 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 977 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 978 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 979 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 980 } else { /* command mode */ 981 if (msm_host->dsc) 982 dsi_update_dsc_timing(msm_host, true, mode->hdisplay); 983 984 /* image data and 1 byte write_memory_start cmd */ 985 if (!msm_host->dsc) 986 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 987 else 988 wc = msm_host->dsc->slice_chunk_size * msm_host->dsc->slice_count + 1; 989 990 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 991 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 992 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 993 msm_host->channel) | 994 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 995 MIPI_DSI_DCS_LONG_WRITE)); 996 997 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 998 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 999 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1000 } 1001 } 1002 1003 static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1004 { 1005 u32 ctrl; 1006 1007 ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1008 1009 if (ctrl & DSI_CTRL_ENABLE) { 1010 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE); 1011 /* 1012 * dsi controller need to be disabled before 1013 * clocks turned on 1014 */ 1015 wmb(); 1016 } 1017 1018 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1019 wmb(); /* clocks need to be enabled before reset */ 1020 1021 /* dsi controller can only be reset while clocks are running */ 1022 dsi_write(msm_host, REG_DSI_RESET, 1); 1023 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1024 dsi_write(msm_host, REG_DSI_RESET, 0); 1025 wmb(); /* controller out of reset */ 1026 1027 if (ctrl & DSI_CTRL_ENABLE) { 1028 dsi_write(msm_host, REG_DSI_CTRL, ctrl); 1029 wmb(); /* make sure dsi controller enabled again */ 1030 } 1031 } 1032 1033 static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1034 bool video_mode, bool enable) 1035 { 1036 u32 dsi_ctrl; 1037 1038 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1039 1040 if (!enable) { 1041 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1042 DSI_CTRL_CMD_MODE_EN); 1043 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1044 DSI_IRQ_MASK_VIDEO_DONE, 0); 1045 } else { 1046 if (video_mode) { 1047 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1048 } else { /* command mode */ 1049 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1050 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1051 } 1052 dsi_ctrl |= DSI_CTRL_ENABLE; 1053 } 1054 1055 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1056 } 1057 1058 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1059 { 1060 u32 data; 1061 1062 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1063 1064 if (mode == 0) 1065 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1066 else 1067 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1068 1069 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1070 } 1071 1072 static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1073 { 1074 u32 ret = 0; 1075 struct device *dev = &msm_host->pdev->dev; 1076 1077 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1078 1079 reinit_completion(&msm_host->video_comp); 1080 1081 ret = wait_for_completion_timeout(&msm_host->video_comp, 1082 msecs_to_jiffies(70)); 1083 1084 if (ret == 0) 1085 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1086 1087 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1088 } 1089 1090 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1091 { 1092 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1093 return; 1094 1095 if (msm_host->power_on && msm_host->enabled) { 1096 dsi_wait4video_done(msm_host); 1097 /* delay 4 ms to skip BLLP */ 1098 usleep_range(2000, 4000); 1099 } 1100 } 1101 1102 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1103 { 1104 struct drm_device *dev = msm_host->dev; 1105 struct msm_drm_private *priv = dev->dev_private; 1106 uint64_t iova; 1107 u8 *data; 1108 1109 data = msm_gem_kernel_new(dev, size, MSM_BO_WC, 1110 priv->kms->aspace, 1111 &msm_host->tx_gem_obj, &iova); 1112 1113 if (IS_ERR(data)) { 1114 msm_host->tx_gem_obj = NULL; 1115 return PTR_ERR(data); 1116 } 1117 1118 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1119 1120 msm_host->tx_size = msm_host->tx_gem_obj->size; 1121 1122 return 0; 1123 } 1124 1125 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1126 { 1127 struct drm_device *dev = msm_host->dev; 1128 1129 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1130 &msm_host->tx_buf_paddr, GFP_KERNEL); 1131 if (!msm_host->tx_buf) 1132 return -ENOMEM; 1133 1134 msm_host->tx_size = size; 1135 1136 return 0; 1137 } 1138 1139 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1140 { 1141 struct drm_device *dev = msm_host->dev; 1142 struct msm_drm_private *priv; 1143 1144 /* 1145 * This is possible if we're tearing down before we've had a chance to 1146 * fully initialize. A very real possibility if our probe is deferred, 1147 * in which case we'll hit msm_dsi_host_destroy() without having run 1148 * through the dsi_tx_buf_alloc(). 1149 */ 1150 if (!dev) 1151 return; 1152 1153 priv = dev->dev_private; 1154 if (msm_host->tx_gem_obj) { 1155 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); 1156 drm_gem_object_put(msm_host->tx_gem_obj); 1157 msm_host->tx_gem_obj = NULL; 1158 } 1159 1160 if (msm_host->tx_buf) 1161 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1162 msm_host->tx_buf_paddr); 1163 } 1164 1165 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1166 { 1167 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1168 } 1169 1170 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1171 { 1172 return msm_host->tx_buf; 1173 } 1174 1175 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1176 { 1177 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1178 } 1179 1180 /* 1181 * prepare cmd buffer to be txed 1182 */ 1183 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1184 const struct mipi_dsi_msg *msg) 1185 { 1186 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1187 struct mipi_dsi_packet packet; 1188 int len; 1189 int ret; 1190 u8 *data; 1191 1192 ret = mipi_dsi_create_packet(&packet, msg); 1193 if (ret) { 1194 pr_err("%s: create packet failed, %d\n", __func__, ret); 1195 return ret; 1196 } 1197 len = (packet.size + 3) & (~0x3); 1198 1199 if (len > msm_host->tx_size) { 1200 pr_err("%s: packet size is too big\n", __func__); 1201 return -EINVAL; 1202 } 1203 1204 data = cfg_hnd->ops->tx_buf_get(msm_host); 1205 if (IS_ERR(data)) { 1206 ret = PTR_ERR(data); 1207 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1208 return ret; 1209 } 1210 1211 /* MSM specific command format in memory */ 1212 data[0] = packet.header[1]; 1213 data[1] = packet.header[2]; 1214 data[2] = packet.header[0]; 1215 data[3] = BIT(7); /* Last packet */ 1216 if (mipi_dsi_packet_format_is_long(msg->type)) 1217 data[3] |= BIT(6); 1218 if (msg->rx_buf && msg->rx_len) 1219 data[3] |= BIT(5); 1220 1221 /* Long packet */ 1222 if (packet.payload && packet.payload_length) 1223 memcpy(data + 4, packet.payload, packet.payload_length); 1224 1225 /* Append 0xff to the end */ 1226 if (packet.size < len) 1227 memset(data + packet.size, 0xff, len - packet.size); 1228 1229 if (cfg_hnd->ops->tx_buf_put) 1230 cfg_hnd->ops->tx_buf_put(msm_host); 1231 1232 return len; 1233 } 1234 1235 /* 1236 * dsi_short_read1_resp: 1 parameter 1237 */ 1238 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1239 { 1240 u8 *data = msg->rx_buf; 1241 if (data && (msg->rx_len >= 1)) { 1242 *data = buf[1]; /* strip out dcs type */ 1243 return 1; 1244 } else { 1245 pr_err("%s: read data does not match with rx_buf len %zu\n", 1246 __func__, msg->rx_len); 1247 return -EINVAL; 1248 } 1249 } 1250 1251 /* 1252 * dsi_short_read2_resp: 2 parameter 1253 */ 1254 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1255 { 1256 u8 *data = msg->rx_buf; 1257 if (data && (msg->rx_len >= 2)) { 1258 data[0] = buf[1]; /* strip out dcs type */ 1259 data[1] = buf[2]; 1260 return 2; 1261 } else { 1262 pr_err("%s: read data does not match with rx_buf len %zu\n", 1263 __func__, msg->rx_len); 1264 return -EINVAL; 1265 } 1266 } 1267 1268 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1269 { 1270 /* strip out 4 byte dcs header */ 1271 if (msg->rx_buf && msg->rx_len) 1272 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1273 1274 return msg->rx_len; 1275 } 1276 1277 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1278 { 1279 struct drm_device *dev = msm_host->dev; 1280 struct msm_drm_private *priv = dev->dev_private; 1281 1282 if (!dma_base) 1283 return -EINVAL; 1284 1285 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1286 priv->kms->aspace, dma_base); 1287 } 1288 1289 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1290 { 1291 if (!dma_base) 1292 return -EINVAL; 1293 1294 *dma_base = msm_host->tx_buf_paddr; 1295 return 0; 1296 } 1297 1298 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1299 { 1300 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1301 int ret; 1302 uint64_t dma_base; 1303 bool triggered; 1304 1305 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1306 if (ret) { 1307 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1308 return ret; 1309 } 1310 1311 reinit_completion(&msm_host->dma_comp); 1312 1313 dsi_wait4video_eng_busy(msm_host); 1314 1315 triggered = msm_dsi_manager_cmd_xfer_trigger( 1316 msm_host->id, dma_base, len); 1317 if (triggered) { 1318 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1319 msecs_to_jiffies(200)); 1320 DBG("ret=%d", ret); 1321 if (ret == 0) 1322 ret = -ETIMEDOUT; 1323 else 1324 ret = len; 1325 } else 1326 ret = len; 1327 1328 return ret; 1329 } 1330 1331 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1332 u8 *buf, int rx_byte, int pkt_size) 1333 { 1334 u32 *temp, data; 1335 int i, j = 0, cnt; 1336 u32 read_cnt; 1337 u8 reg[16]; 1338 int repeated_bytes = 0; 1339 int buf_offset = buf - msm_host->rx_buf; 1340 1341 temp = (u32 *)reg; 1342 cnt = (rx_byte + 3) >> 2; 1343 if (cnt > 4) 1344 cnt = 4; /* 4 x 32 bits registers only */ 1345 1346 if (rx_byte == 4) 1347 read_cnt = 4; 1348 else 1349 read_cnt = pkt_size + 6; 1350 1351 /* 1352 * In case of multiple reads from the panel, after the first read, there 1353 * is possibility that there are some bytes in the payload repeating in 1354 * the RDBK_DATA registers. Since we read all the parameters from the 1355 * panel right from the first byte for every pass. We need to skip the 1356 * repeating bytes and then append the new parameters to the rx buffer. 1357 */ 1358 if (read_cnt > 16) { 1359 int bytes_shifted; 1360 /* Any data more than 16 bytes will be shifted out. 1361 * The temp read buffer should already contain these bytes. 1362 * The remaining bytes in read buffer are the repeated bytes. 1363 */ 1364 bytes_shifted = read_cnt - 16; 1365 repeated_bytes = buf_offset - bytes_shifted; 1366 } 1367 1368 for (i = cnt - 1; i >= 0; i--) { 1369 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1370 *temp++ = ntohl(data); /* to host byte order */ 1371 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1372 } 1373 1374 for (i = repeated_bytes; i < 16; i++) 1375 buf[j++] = reg[i]; 1376 1377 return j; 1378 } 1379 1380 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1381 const struct mipi_dsi_msg *msg) 1382 { 1383 int len, ret; 1384 int bllp_len = msm_host->mode->hdisplay * 1385 dsi_get_bpp(msm_host->format) / 8; 1386 1387 len = dsi_cmd_dma_add(msm_host, msg); 1388 if (len < 0) { 1389 pr_err("%s: failed to add cmd type = 0x%x\n", 1390 __func__, msg->type); 1391 return len; 1392 } 1393 1394 /* for video mode, do not send cmds more than 1395 * one pixel line, since it only transmit it 1396 * during BLLP. 1397 */ 1398 /* TODO: if the command is sent in LP mode, the bit rate is only 1399 * half of esc clk rate. In this case, if the video is already 1400 * actively streaming, we need to check more carefully if the 1401 * command can be fit into one BLLP. 1402 */ 1403 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1404 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1405 __func__, len); 1406 return -EINVAL; 1407 } 1408 1409 ret = dsi_cmd_dma_tx(msm_host, len); 1410 if (ret < 0) { 1411 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1412 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1413 return ret; 1414 } else if (ret < len) { 1415 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1416 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1417 return -EIO; 1418 } 1419 1420 return len; 1421 } 1422 1423 static void dsi_err_worker(struct work_struct *work) 1424 { 1425 struct msm_dsi_host *msm_host = 1426 container_of(work, struct msm_dsi_host, err_work); 1427 u32 status = msm_host->err_work_state; 1428 1429 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1430 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1431 dsi_sw_reset(msm_host); 1432 1433 /* It is safe to clear here because error irq is disabled. */ 1434 msm_host->err_work_state = 0; 1435 1436 /* enable dsi error interrupt */ 1437 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1438 } 1439 1440 static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1441 { 1442 u32 status; 1443 1444 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1445 1446 if (status) { 1447 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1448 /* Writing of an extra 0 needed to clear error bits */ 1449 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1450 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1451 } 1452 } 1453 1454 static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1455 { 1456 u32 status; 1457 1458 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1459 1460 if (status) { 1461 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1462 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1463 } 1464 } 1465 1466 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1467 { 1468 u32 status; 1469 1470 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1471 1472 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1473 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1474 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1475 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1476 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1477 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1478 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1479 } 1480 } 1481 1482 static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1483 { 1484 u32 status; 1485 1486 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1487 1488 /* fifo underflow, overflow */ 1489 if (status) { 1490 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1491 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1492 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1493 msm_host->err_work_state |= 1494 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1495 } 1496 } 1497 1498 static void dsi_status(struct msm_dsi_host *msm_host) 1499 { 1500 u32 status; 1501 1502 status = dsi_read(msm_host, REG_DSI_STATUS0); 1503 1504 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1505 dsi_write(msm_host, REG_DSI_STATUS0, status); 1506 msm_host->err_work_state |= 1507 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1508 } 1509 } 1510 1511 static void dsi_clk_status(struct msm_dsi_host *msm_host) 1512 { 1513 u32 status; 1514 1515 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1516 1517 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1518 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1519 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1520 } 1521 } 1522 1523 static void dsi_error(struct msm_dsi_host *msm_host) 1524 { 1525 /* disable dsi error interrupt */ 1526 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1527 1528 dsi_clk_status(msm_host); 1529 dsi_fifo_status(msm_host); 1530 dsi_ack_err_status(msm_host); 1531 dsi_timeout_status(msm_host); 1532 dsi_status(msm_host); 1533 dsi_dln0_phy_err(msm_host); 1534 1535 queue_work(msm_host->workqueue, &msm_host->err_work); 1536 } 1537 1538 static irqreturn_t dsi_host_irq(int irq, void *ptr) 1539 { 1540 struct msm_dsi_host *msm_host = ptr; 1541 u32 isr; 1542 unsigned long flags; 1543 1544 if (!msm_host->ctrl_base) 1545 return IRQ_HANDLED; 1546 1547 spin_lock_irqsave(&msm_host->intr_lock, flags); 1548 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1549 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1550 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1551 1552 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1553 1554 if (isr & DSI_IRQ_ERROR) 1555 dsi_error(msm_host); 1556 1557 if (isr & DSI_IRQ_VIDEO_DONE) 1558 complete(&msm_host->video_comp); 1559 1560 if (isr & DSI_IRQ_CMD_DMA_DONE) 1561 complete(&msm_host->dma_comp); 1562 1563 return IRQ_HANDLED; 1564 } 1565 1566 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1567 struct device *panel_device) 1568 { 1569 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1570 "disp-enable", 1571 GPIOD_OUT_LOW); 1572 if (IS_ERR(msm_host->disp_en_gpio)) { 1573 DBG("cannot get disp-enable-gpios %ld", 1574 PTR_ERR(msm_host->disp_en_gpio)); 1575 return PTR_ERR(msm_host->disp_en_gpio); 1576 } 1577 1578 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1579 GPIOD_IN); 1580 if (IS_ERR(msm_host->te_gpio)) { 1581 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1582 return PTR_ERR(msm_host->te_gpio); 1583 } 1584 1585 return 0; 1586 } 1587 1588 static int dsi_host_attach(struct mipi_dsi_host *host, 1589 struct mipi_dsi_device *dsi) 1590 { 1591 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1592 int ret; 1593 1594 if (dsi->lanes > msm_host->num_data_lanes) 1595 return -EINVAL; 1596 1597 msm_host->channel = dsi->channel; 1598 msm_host->lanes = dsi->lanes; 1599 msm_host->format = dsi->format; 1600 msm_host->mode_flags = dsi->mode_flags; 1601 if (dsi->dsc) 1602 msm_host->dsc = dsi->dsc; 1603 1604 /* Some gpios defined in panel DT need to be controlled by host */ 1605 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1606 if (ret) 1607 return ret; 1608 1609 ret = dsi_dev_attach(msm_host->pdev); 1610 if (ret) 1611 return ret; 1612 1613 DBG("id=%d", msm_host->id); 1614 1615 return 0; 1616 } 1617 1618 static int dsi_host_detach(struct mipi_dsi_host *host, 1619 struct mipi_dsi_device *dsi) 1620 { 1621 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1622 1623 dsi_dev_detach(msm_host->pdev); 1624 1625 DBG("id=%d", msm_host->id); 1626 1627 return 0; 1628 } 1629 1630 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1631 const struct mipi_dsi_msg *msg) 1632 { 1633 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1634 int ret; 1635 1636 if (!msg || !msm_host->power_on) 1637 return -EINVAL; 1638 1639 mutex_lock(&msm_host->cmd_mutex); 1640 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1641 mutex_unlock(&msm_host->cmd_mutex); 1642 1643 return ret; 1644 } 1645 1646 static const struct mipi_dsi_host_ops dsi_host_ops = { 1647 .attach = dsi_host_attach, 1648 .detach = dsi_host_detach, 1649 .transfer = dsi_host_transfer, 1650 }; 1651 1652 /* 1653 * List of supported physical to logical lane mappings. 1654 * For example, the 2nd entry represents the following mapping: 1655 * 1656 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1657 */ 1658 static const int supported_data_lane_swaps[][4] = { 1659 { 0, 1, 2, 3 }, 1660 { 3, 0, 1, 2 }, 1661 { 2, 3, 0, 1 }, 1662 { 1, 2, 3, 0 }, 1663 { 0, 3, 2, 1 }, 1664 { 1, 0, 3, 2 }, 1665 { 2, 1, 0, 3 }, 1666 { 3, 2, 1, 0 }, 1667 }; 1668 1669 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1670 struct device_node *ep) 1671 { 1672 struct device *dev = &msm_host->pdev->dev; 1673 struct property *prop; 1674 u32 lane_map[4]; 1675 int ret, i, len, num_lanes; 1676 1677 prop = of_find_property(ep, "data-lanes", &len); 1678 if (!prop) { 1679 DRM_DEV_DEBUG(dev, 1680 "failed to find data lane mapping, using default\n"); 1681 /* Set the number of date lanes to 4 by default. */ 1682 msm_host->num_data_lanes = 4; 1683 return 0; 1684 } 1685 1686 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4); 1687 if (num_lanes < 0) { 1688 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1689 return num_lanes; 1690 } 1691 1692 msm_host->num_data_lanes = num_lanes; 1693 1694 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1695 num_lanes); 1696 if (ret) { 1697 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1698 return ret; 1699 } 1700 1701 /* 1702 * compare DT specified physical-logical lane mappings with the ones 1703 * supported by hardware 1704 */ 1705 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1706 const int *swap = supported_data_lane_swaps[i]; 1707 int j; 1708 1709 /* 1710 * the data-lanes array we get from DT has a logical->physical 1711 * mapping. The "data lane swap" register field represents 1712 * supported configurations in a physical->logical mapping. 1713 * Translate the DT mapping to what we understand and find a 1714 * configuration that works. 1715 */ 1716 for (j = 0; j < num_lanes; j++) { 1717 if (lane_map[j] < 0 || lane_map[j] > 3) 1718 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1719 lane_map[j]); 1720 1721 if (swap[lane_map[j]] != j) 1722 break; 1723 } 1724 1725 if (j == num_lanes) { 1726 msm_host->dlane_swap = i; 1727 return 0; 1728 } 1729 } 1730 1731 return -EINVAL; 1732 } 1733 1734 static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = { 1735 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, 1736 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e 1737 }; 1738 1739 /* only 8bpc, 8bpp added */ 1740 static char min_qp[DSC_NUM_BUF_RANGES] = { 1741 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13 1742 }; 1743 1744 static char max_qp[DSC_NUM_BUF_RANGES] = { 1745 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15 1746 }; 1747 1748 static char bpg_offset[DSC_NUM_BUF_RANGES] = { 1749 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 1750 }; 1751 1752 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) 1753 { 1754 int i; 1755 u16 bpp = dsc->bits_per_pixel >> 4; 1756 1757 if (dsc->bits_per_pixel & 0xf) { 1758 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); 1759 return -EINVAL; 1760 } 1761 1762 if (dsc->bits_per_component != 8) { 1763 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n"); 1764 return -EOPNOTSUPP; 1765 } 1766 1767 dsc->rc_model_size = 8192; 1768 dsc->first_line_bpg_offset = 12; 1769 dsc->rc_edge_factor = 6; 1770 dsc->rc_tgt_offset_high = 3; 1771 dsc->rc_tgt_offset_low = 3; 1772 dsc->simple_422 = 0; 1773 dsc->convert_rgb = 1; 1774 dsc->vbr_enable = 0; 1775 1776 /* handle only bpp = bpc = 8 */ 1777 for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) 1778 dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i]; 1779 1780 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 1781 dsc->rc_range_params[i].range_min_qp = min_qp[i]; 1782 dsc->rc_range_params[i].range_max_qp = max_qp[i]; 1783 /* 1784 * Range BPG Offset contains two's-complement signed values that fill 1785 * 8 bits, yet the registers and DCS PPS field are only 6 bits wide. 1786 */ 1787 dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK; 1788 } 1789 1790 dsc->initial_offset = 6144; /* Not bpp 12 */ 1791 if (bpp != 8) 1792 dsc->initial_offset = 2048; /* bpp = 12 */ 1793 1794 if (dsc->bits_per_component <= 10) 1795 dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; 1796 else 1797 dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; 1798 1799 dsc->initial_xmit_delay = 512; 1800 dsc->initial_scale_value = 32; 1801 dsc->first_line_bpg_offset = 12; 1802 dsc->line_buf_depth = dsc->bits_per_component + 1; 1803 1804 /* bpc 8 */ 1805 dsc->flatness_min_qp = 3; 1806 dsc->flatness_max_qp = 12; 1807 dsc->rc_quant_incr_limit0 = 11; 1808 dsc->rc_quant_incr_limit1 = 11; 1809 1810 return drm_dsc_compute_rc_parameters(dsc); 1811 } 1812 1813 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1814 { 1815 struct device *dev = &msm_host->pdev->dev; 1816 struct device_node *np = dev->of_node; 1817 struct device_node *endpoint; 1818 int ret = 0; 1819 1820 /* 1821 * Get the endpoint of the output port of the DSI host. In our case, 1822 * this is mapped to port number with reg = 1. Don't return an error if 1823 * the remote endpoint isn't defined. It's possible that there is 1824 * nothing connected to the dsi output. 1825 */ 1826 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1827 if (!endpoint) { 1828 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1829 return 0; 1830 } 1831 1832 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1833 if (ret) { 1834 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1835 __func__, ret); 1836 ret = -EINVAL; 1837 goto err; 1838 } 1839 1840 if (of_property_read_bool(np, "syscon-sfpb")) { 1841 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1842 "syscon-sfpb"); 1843 if (IS_ERR(msm_host->sfpb)) { 1844 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1845 __func__); 1846 ret = PTR_ERR(msm_host->sfpb); 1847 } 1848 } 1849 1850 err: 1851 of_node_put(endpoint); 1852 1853 return ret; 1854 } 1855 1856 static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1857 { 1858 struct platform_device *pdev = msm_host->pdev; 1859 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1860 struct resource *res; 1861 int i, j; 1862 1863 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1864 if (!res) 1865 return -EINVAL; 1866 1867 for (i = 0; i < VARIANTS_MAX; i++) 1868 for (j = 0; j < DSI_MAX; j++) 1869 if (cfg->io_start[i][j] == res->start) 1870 return j; 1871 1872 return -EINVAL; 1873 } 1874 1875 int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1876 { 1877 struct msm_dsi_host *msm_host = NULL; 1878 struct platform_device *pdev = msm_dsi->pdev; 1879 const struct msm_dsi_config *cfg; 1880 int ret; 1881 1882 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1883 if (!msm_host) { 1884 return -ENOMEM; 1885 } 1886 1887 msm_host->pdev = pdev; 1888 msm_dsi->host = &msm_host->base; 1889 1890 ret = dsi_host_parse_dt(msm_host); 1891 if (ret) { 1892 pr_err("%s: failed to parse dt\n", __func__); 1893 return ret; 1894 } 1895 1896 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size); 1897 if (IS_ERR(msm_host->ctrl_base)) { 1898 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1899 return PTR_ERR(msm_host->ctrl_base); 1900 } 1901 1902 pm_runtime_enable(&pdev->dev); 1903 1904 msm_host->cfg_hnd = dsi_get_config(msm_host); 1905 if (!msm_host->cfg_hnd) { 1906 pr_err("%s: get config failed\n", __func__); 1907 return -EINVAL; 1908 } 1909 cfg = msm_host->cfg_hnd->cfg; 1910 1911 msm_host->id = dsi_host_get_id(msm_host); 1912 if (msm_host->id < 0) { 1913 pr_err("%s: unable to identify DSI host index\n", __func__); 1914 return msm_host->id; 1915 } 1916 1917 /* fixup base address by io offset */ 1918 msm_host->ctrl_base += cfg->io_offset; 1919 1920 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators, 1921 cfg->regulator_data, 1922 &msm_host->supplies); 1923 if (ret) 1924 return ret; 1925 1926 ret = dsi_clk_init(msm_host); 1927 if (ret) { 1928 pr_err("%s: unable to initialize dsi clks\n", __func__); 1929 return ret; 1930 } 1931 1932 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1933 if (!msm_host->rx_buf) { 1934 pr_err("%s: alloc rx temp buf failed\n", __func__); 1935 return -ENOMEM; 1936 } 1937 1938 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); 1939 if (ret) 1940 return ret; 1941 /* OPP table is optional */ 1942 ret = devm_pm_opp_of_add_table(&pdev->dev); 1943 if (ret && ret != -ENODEV) { 1944 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1945 return ret; 1946 } 1947 1948 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1949 if (msm_host->irq < 0) { 1950 ret = msm_host->irq; 1951 dev_err(&pdev->dev, "failed to get irq: %d\n", ret); 1952 return ret; 1953 } 1954 1955 /* do not autoenable, will be enabled later */ 1956 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, 1957 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, 1958 "dsi_isr", msm_host); 1959 if (ret < 0) { 1960 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", 1961 msm_host->irq, ret); 1962 return ret; 1963 } 1964 1965 init_completion(&msm_host->dma_comp); 1966 init_completion(&msm_host->video_comp); 1967 mutex_init(&msm_host->dev_mutex); 1968 mutex_init(&msm_host->cmd_mutex); 1969 spin_lock_init(&msm_host->intr_lock); 1970 1971 /* setup workqueue */ 1972 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1973 if (!msm_host->workqueue) 1974 return -ENOMEM; 1975 1976 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1977 1978 msm_dsi->id = msm_host->id; 1979 1980 DBG("Dsi Host %d initialized", msm_host->id); 1981 return 0; 1982 } 1983 1984 void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1985 { 1986 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1987 1988 DBG(""); 1989 dsi_tx_buf_free(msm_host); 1990 if (msm_host->workqueue) { 1991 destroy_workqueue(msm_host->workqueue); 1992 msm_host->workqueue = NULL; 1993 } 1994 1995 mutex_destroy(&msm_host->cmd_mutex); 1996 mutex_destroy(&msm_host->dev_mutex); 1997 1998 pm_runtime_disable(&msm_host->pdev->dev); 1999 } 2000 2001 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 2002 struct drm_device *dev) 2003 { 2004 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2005 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2006 int ret; 2007 2008 msm_host->dev = dev; 2009 2010 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 2011 if (ret) { 2012 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 2013 return ret; 2014 } 2015 2016 return 0; 2017 } 2018 2019 int msm_dsi_host_register(struct mipi_dsi_host *host) 2020 { 2021 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2022 int ret; 2023 2024 /* Register mipi dsi host */ 2025 if (!msm_host->registered) { 2026 host->dev = &msm_host->pdev->dev; 2027 host->ops = &dsi_host_ops; 2028 ret = mipi_dsi_host_register(host); 2029 if (ret) 2030 return ret; 2031 2032 msm_host->registered = true; 2033 } 2034 2035 return 0; 2036 } 2037 2038 void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2039 { 2040 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2041 2042 if (msm_host->registered) { 2043 mipi_dsi_host_unregister(host); 2044 host->dev = NULL; 2045 host->ops = NULL; 2046 msm_host->registered = false; 2047 } 2048 } 2049 2050 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2051 const struct mipi_dsi_msg *msg) 2052 { 2053 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2054 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2055 2056 /* TODO: make sure dsi_cmd_mdp is idle. 2057 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2058 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2059 * How to handle the old versions? Wait for mdp cmd done? 2060 */ 2061 2062 /* 2063 * mdss interrupt is generated in mdp core clock domain 2064 * mdp clock need to be enabled to receive dsi interrupt 2065 */ 2066 pm_runtime_get_sync(&msm_host->pdev->dev); 2067 cfg_hnd->ops->link_clk_set_rate(msm_host); 2068 cfg_hnd->ops->link_clk_enable(msm_host); 2069 2070 /* TODO: vote for bus bandwidth */ 2071 2072 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2073 dsi_set_tx_power_mode(0, msm_host); 2074 2075 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2076 dsi_write(msm_host, REG_DSI_CTRL, 2077 msm_host->dma_cmd_ctrl_restore | 2078 DSI_CTRL_CMD_MODE_EN | 2079 DSI_CTRL_ENABLE); 2080 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2081 2082 return 0; 2083 } 2084 2085 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2086 const struct mipi_dsi_msg *msg) 2087 { 2088 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2089 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2090 2091 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2092 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2093 2094 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2095 dsi_set_tx_power_mode(1, msm_host); 2096 2097 /* TODO: unvote for bus bandwidth */ 2098 2099 cfg_hnd->ops->link_clk_disable(msm_host); 2100 pm_runtime_put(&msm_host->pdev->dev); 2101 } 2102 2103 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2104 const struct mipi_dsi_msg *msg) 2105 { 2106 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2107 2108 return dsi_cmds2buf_tx(msm_host, msg); 2109 } 2110 2111 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2112 const struct mipi_dsi_msg *msg) 2113 { 2114 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2115 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2116 int data_byte, rx_byte, dlen, end; 2117 int short_response, diff, pkt_size, ret = 0; 2118 char cmd; 2119 int rlen = msg->rx_len; 2120 u8 *buf; 2121 2122 if (rlen <= 2) { 2123 short_response = 1; 2124 pkt_size = rlen; 2125 rx_byte = 4; 2126 } else { 2127 short_response = 0; 2128 data_byte = 10; /* first read */ 2129 if (rlen < data_byte) 2130 pkt_size = rlen; 2131 else 2132 pkt_size = data_byte; 2133 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2134 } 2135 2136 buf = msm_host->rx_buf; 2137 end = 0; 2138 while (!end) { 2139 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2140 struct mipi_dsi_msg max_pkt_size_msg = { 2141 .channel = msg->channel, 2142 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2143 .tx_len = 2, 2144 .tx_buf = tx, 2145 }; 2146 2147 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2148 rlen, pkt_size, rx_byte); 2149 2150 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2151 if (ret < 2) { 2152 pr_err("%s: Set max pkt size failed, %d\n", 2153 __func__, ret); 2154 return -EINVAL; 2155 } 2156 2157 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2158 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2159 /* Clear the RDBK_DATA registers */ 2160 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2161 DSI_RDBK_DATA_CTRL_CLR); 2162 wmb(); /* make sure the RDBK registers are cleared */ 2163 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2164 wmb(); /* release cleared status before transfer */ 2165 } 2166 2167 ret = dsi_cmds2buf_tx(msm_host, msg); 2168 if (ret < 0) { 2169 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2170 return ret; 2171 } else if (ret < msg->tx_len) { 2172 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2173 return -ECOMM; 2174 } 2175 2176 /* 2177 * once cmd_dma_done interrupt received, 2178 * return data from client is ready and stored 2179 * at RDBK_DATA register already 2180 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2181 * after that dcs header lost during shift into registers 2182 */ 2183 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2184 2185 if (dlen <= 0) 2186 return 0; 2187 2188 if (short_response) 2189 break; 2190 2191 if (rlen <= data_byte) { 2192 diff = data_byte - rlen; 2193 end = 1; 2194 } else { 2195 diff = 0; 2196 rlen -= data_byte; 2197 } 2198 2199 if (!end) { 2200 dlen -= 2; /* 2 crc */ 2201 dlen -= diff; 2202 buf += dlen; /* next start position */ 2203 data_byte = 14; /* NOT first read */ 2204 if (rlen < data_byte) 2205 pkt_size += rlen; 2206 else 2207 pkt_size += data_byte; 2208 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2209 } 2210 } 2211 2212 /* 2213 * For single Long read, if the requested rlen < 10, 2214 * we need to shift the start position of rx 2215 * data buffer to skip the bytes which are not 2216 * updated. 2217 */ 2218 if (pkt_size < 10 && !short_response) 2219 buf = msm_host->rx_buf + (10 - rlen); 2220 else 2221 buf = msm_host->rx_buf; 2222 2223 cmd = buf[0]; 2224 switch (cmd) { 2225 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2226 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2227 ret = 0; 2228 break; 2229 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2230 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2231 ret = dsi_short_read1_resp(buf, msg); 2232 break; 2233 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2234 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2235 ret = dsi_short_read2_resp(buf, msg); 2236 break; 2237 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2238 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2239 ret = dsi_long_read_resp(buf, msg); 2240 break; 2241 default: 2242 pr_warn("%s:Invalid response cmd\n", __func__); 2243 ret = 0; 2244 } 2245 2246 return ret; 2247 } 2248 2249 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2250 u32 len) 2251 { 2252 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2253 2254 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2255 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2256 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2257 2258 /* Make sure trigger happens */ 2259 wmb(); 2260 } 2261 2262 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host, 2263 struct msm_dsi_phy *src_phy) 2264 { 2265 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2266 2267 msm_host->cphy_mode = src_phy->cphy_mode; 2268 } 2269 2270 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2271 { 2272 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2273 2274 DBG(""); 2275 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2276 /* Make sure fully reset */ 2277 wmb(); 2278 udelay(1000); 2279 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2280 udelay(100); 2281 } 2282 2283 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2284 struct msm_dsi_phy_clk_request *clk_req, 2285 bool is_bonded_dsi) 2286 { 2287 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2288 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2289 int ret; 2290 2291 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); 2292 if (ret) { 2293 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2294 return; 2295 } 2296 2297 /* CPHY transmits 16 bits over 7 clock cycles 2298 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), 2299 * so multiply by 7 to get the "bitclk rate" 2300 */ 2301 if (msm_host->cphy_mode) 2302 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; 2303 else 2304 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2305 clk_req->escclk_rate = msm_host->esc_clk_rate; 2306 } 2307 2308 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) 2309 { 2310 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2311 2312 enable_irq(msm_host->irq); 2313 } 2314 2315 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) 2316 { 2317 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2318 2319 disable_irq(msm_host->irq); 2320 } 2321 2322 int msm_dsi_host_enable(struct mipi_dsi_host *host) 2323 { 2324 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2325 2326 dsi_op_mode_config(msm_host, 2327 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2328 2329 /* TODO: clock should be turned off for command mode, 2330 * and only turned on before MDP START. 2331 * This part of code should be enabled once mdp driver support it. 2332 */ 2333 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2334 * dsi_link_clk_disable(msm_host); 2335 * pm_runtime_put(&msm_host->pdev->dev); 2336 * } 2337 */ 2338 msm_host->enabled = true; 2339 return 0; 2340 } 2341 2342 int msm_dsi_host_disable(struct mipi_dsi_host *host) 2343 { 2344 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2345 2346 msm_host->enabled = false; 2347 dsi_op_mode_config(msm_host, 2348 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2349 2350 /* Since we have disabled INTF, the video engine won't stop so that 2351 * the cmd engine will be blocked. 2352 * Reset to disable video engine so that we can send off cmd. 2353 */ 2354 dsi_sw_reset(msm_host); 2355 2356 return 0; 2357 } 2358 2359 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2360 { 2361 enum sfpb_ahb_arb_master_port_en en; 2362 2363 if (!msm_host->sfpb) 2364 return; 2365 2366 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2367 2368 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2369 SFPB_GPREG_MASTER_PORT_EN__MASK, 2370 SFPB_GPREG_MASTER_PORT_EN(en)); 2371 } 2372 2373 int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2374 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2375 bool is_bonded_dsi, struct msm_dsi_phy *phy) 2376 { 2377 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2378 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2379 int ret = 0; 2380 2381 mutex_lock(&msm_host->dev_mutex); 2382 if (msm_host->power_on) { 2383 DBG("dsi host already on"); 2384 goto unlock_ret; 2385 } 2386 2387 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate; 2388 if (phy_shared_timings->byte_intf_clk_div_2) 2389 msm_host->byte_intf_clk_rate /= 2; 2390 2391 msm_dsi_sfpb_config(msm_host, true); 2392 2393 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators, 2394 msm_host->supplies); 2395 if (ret) { 2396 pr_err("%s:Failed to enable vregs.ret=%d\n", 2397 __func__, ret); 2398 goto unlock_ret; 2399 } 2400 2401 pm_runtime_get_sync(&msm_host->pdev->dev); 2402 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2403 if (!ret) 2404 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2405 if (ret) { 2406 pr_err("%s: failed to enable link clocks. ret=%d\n", 2407 __func__, ret); 2408 goto fail_disable_reg; 2409 } 2410 2411 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2412 if (ret) { 2413 pr_err("%s: failed to set pinctrl default state, %d\n", 2414 __func__, ret); 2415 goto fail_disable_clk; 2416 } 2417 2418 dsi_timing_setup(msm_host, is_bonded_dsi); 2419 dsi_sw_reset(msm_host); 2420 dsi_ctrl_config(msm_host, true, phy_shared_timings, phy); 2421 2422 if (msm_host->disp_en_gpio) 2423 gpiod_set_value(msm_host->disp_en_gpio, 1); 2424 2425 msm_host->power_on = true; 2426 mutex_unlock(&msm_host->dev_mutex); 2427 2428 return 0; 2429 2430 fail_disable_clk: 2431 cfg_hnd->ops->link_clk_disable(msm_host); 2432 pm_runtime_put(&msm_host->pdev->dev); 2433 fail_disable_reg: 2434 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2435 msm_host->supplies); 2436 unlock_ret: 2437 mutex_unlock(&msm_host->dev_mutex); 2438 return ret; 2439 } 2440 2441 int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2442 { 2443 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2444 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2445 2446 mutex_lock(&msm_host->dev_mutex); 2447 if (!msm_host->power_on) { 2448 DBG("dsi host already off"); 2449 goto unlock_ret; 2450 } 2451 2452 dsi_ctrl_config(msm_host, false, NULL, NULL); 2453 2454 if (msm_host->disp_en_gpio) 2455 gpiod_set_value(msm_host->disp_en_gpio, 0); 2456 2457 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2458 2459 cfg_hnd->ops->link_clk_disable(msm_host); 2460 pm_runtime_put(&msm_host->pdev->dev); 2461 2462 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators, 2463 msm_host->supplies); 2464 2465 msm_dsi_sfpb_config(msm_host, false); 2466 2467 DBG("-"); 2468 2469 msm_host->power_on = false; 2470 2471 unlock_ret: 2472 mutex_unlock(&msm_host->dev_mutex); 2473 return 0; 2474 } 2475 2476 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2477 const struct drm_display_mode *mode) 2478 { 2479 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2480 2481 if (msm_host->mode) { 2482 drm_mode_destroy(msm_host->dev, msm_host->mode); 2483 msm_host->mode = NULL; 2484 } 2485 2486 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2487 if (!msm_host->mode) { 2488 pr_err("%s: cannot duplicate mode\n", __func__); 2489 return -ENOMEM; 2490 } 2491 2492 return 0; 2493 } 2494 2495 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, 2496 const struct drm_display_mode *mode) 2497 { 2498 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2499 struct drm_dsc_config *dsc = msm_host->dsc; 2500 int pic_width = mode->hdisplay; 2501 int pic_height = mode->vdisplay; 2502 2503 if (!msm_host->dsc) 2504 return MODE_OK; 2505 2506 if (pic_width % dsc->slice_width) { 2507 pr_err("DSI: pic_width %d has to be multiple of slice %d\n", 2508 pic_width, dsc->slice_width); 2509 return MODE_H_ILLEGAL; 2510 } 2511 2512 if (pic_height % dsc->slice_height) { 2513 pr_err("DSI: pic_height %d has to be multiple of slice %d\n", 2514 pic_height, dsc->slice_height); 2515 return MODE_V_ILLEGAL; 2516 } 2517 2518 return MODE_OK; 2519 } 2520 2521 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2522 { 2523 return to_msm_dsi_host(host)->mode_flags; 2524 } 2525 2526 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) 2527 { 2528 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2529 2530 pm_runtime_get_sync(&msm_host->pdev->dev); 2531 2532 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, 2533 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); 2534 2535 pm_runtime_put_sync(&msm_host->pdev->dev); 2536 } 2537 2538 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) 2539 { 2540 u32 reg; 2541 2542 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2543 2544 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); 2545 /* draw checkered rectangle pattern */ 2546 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, 2547 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); 2548 /* use 24-bit RGB test pttern */ 2549 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, 2550 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | 2551 DSI_TPG_VIDEO_CONFIG_RGB); 2552 2553 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); 2554 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2555 2556 DBG("Video test pattern setup done\n"); 2557 } 2558 2559 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) 2560 { 2561 u32 reg; 2562 2563 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2564 2565 /* initial value for test pattern */ 2566 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); 2567 2568 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); 2569 2570 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); 2571 /* draw checkered rectangle pattern */ 2572 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, 2573 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); 2574 2575 DBG("Cmd test pattern setup done\n"); 2576 } 2577 2578 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) 2579 { 2580 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2581 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); 2582 u32 reg; 2583 2584 if (is_video_mode) 2585 msm_dsi_host_video_test_pattern_setup(msm_host); 2586 else 2587 msm_dsi_host_cmd_test_pattern_setup(msm_host); 2588 2589 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); 2590 /* enable the test pattern generator */ 2591 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); 2592 2593 /* for command mode need to trigger one frame from tpg */ 2594 if (!is_video_mode) 2595 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, 2596 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); 2597 } 2598 2599 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host) 2600 { 2601 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2602 2603 return msm_host->dsc; 2604 } 2605