xref: /linux/drivers/gpu/drm/msm/dsi/dsi_cfg.c (revision 46ff24efe04ac96a129dd01138640c3447a525e1)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4  */
5 
6 #include "dsi_cfg.h"
7 
8 static const char * const dsi_v2_bus_clk_names[] = {
9 	"core_mmss", "iface", "bus",
10 };
11 
12 static const struct regulator_bulk_data apq8064_dsi_regulators[] = {
13 	{ .supply = "vdda", .init_load_uA = 100000 },	/* 1.2 V */
14 	{ .supply = "avdd", .init_load_uA = 10000 },	/* 3.0 V */
15 	{ .supply = "vddio", .init_load_uA = 100000 },	/* 1.8 V */
16 };
17 
18 static const struct msm_dsi_config apq8064_dsi_cfg = {
19 	.io_offset = 0,
20 	.regulator_data = apq8064_dsi_regulators,
21 	.num_regulators = ARRAY_SIZE(apq8064_dsi_regulators),
22 	.bus_clk_names = dsi_v2_bus_clk_names,
23 	.num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names),
24 	.io_start = { 0x4700000, 0x5800000 },
25 	.num_dsi = 2,
26 };
27 
28 static const char * const dsi_6g_bus_clk_names[] = {
29 	"mdp_core", "iface", "bus", "core_mmss",
30 };
31 
32 static const struct regulator_bulk_data msm8974_apq8084_regulators[] = {
33 	{ .supply = "vdd", .init_load_uA = 150000 },	/* 3.0 V */
34 	{ .supply = "vdda", .init_load_uA = 100000 },	/* 1.2 V */
35 	{ .supply = "vddio", .init_load_uA = 100000 },	/* 1.8 V */
36 };
37 
38 static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
39 	.io_offset = DSI_6G_REG_SHIFT,
40 	.regulator_data = msm8974_apq8084_regulators,
41 	.num_regulators = ARRAY_SIZE(msm8974_apq8084_regulators),
42 	.bus_clk_names = dsi_6g_bus_clk_names,
43 	.num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
44 	.io_start = { 0xfd922800, 0xfd922b00 },
45 	.num_dsi = 2,
46 };
47 
48 static const char * const dsi_8916_bus_clk_names[] = {
49 	"mdp_core", "iface", "bus",
50 };
51 
52 static const struct regulator_bulk_data msm8916_dsi_regulators[] = {
53 	{ .supply = "vdda", .init_load_uA = 100000 },	/* 1.2 V */
54 	{ .supply = "vddio", .init_load_uA = 100000 },	/* 1.8 V */
55 };
56 
57 static const struct msm_dsi_config msm8916_dsi_cfg = {
58 	.io_offset = DSI_6G_REG_SHIFT,
59 	.regulator_data = msm8916_dsi_regulators,
60 	.num_regulators = ARRAY_SIZE(msm8916_dsi_regulators),
61 	.bus_clk_names = dsi_8916_bus_clk_names,
62 	.num_bus_clks = ARRAY_SIZE(dsi_8916_bus_clk_names),
63 	.io_start = { 0x1a98000 },
64 	.num_dsi = 1,
65 };
66 
67 static const char * const dsi_8976_bus_clk_names[] = {
68 	"mdp_core", "iface", "bus",
69 };
70 
71 static const struct regulator_bulk_data msm8976_dsi_regulators[] = {
72 	{ .supply = "vdda", .init_load_uA = 100000 },	/* 1.2 V */
73 	{ .supply = "vddio", .init_load_uA = 100000 },	/* 1.8 V */
74 };
75 
76 static const struct msm_dsi_config msm8976_dsi_cfg = {
77 	.io_offset = DSI_6G_REG_SHIFT,
78 	.regulator_data = msm8976_dsi_regulators,
79 	.num_regulators = ARRAY_SIZE(msm8976_dsi_regulators),
80 	.bus_clk_names = dsi_8976_bus_clk_names,
81 	.num_bus_clks = ARRAY_SIZE(dsi_8976_bus_clk_names),
82 	.io_start = { 0x1a94000, 0x1a96000 },
83 	.num_dsi = 2,
84 };
85 
86 static const struct regulator_bulk_data msm8994_dsi_regulators[] = {
87 	{ .supply = "vdda", .init_load_uA = 100000 },	/* 1.25 V */
88 	{ .supply = "vddio", .init_load_uA = 100000 },	/* 1.8 V */
89 	{ .supply = "vcca", .init_load_uA = 10000 },	/* 1.0 V */
90 	{ .supply = "vdd", .init_load_uA = 100000 },	/* 1.8 V */
91 	{ .supply = "lab_reg", .init_load_uA = -1 },
92 	{ .supply = "ibb_reg", .init_load_uA = -1 },
93 };
94 
95 static const struct msm_dsi_config msm8994_dsi_cfg = {
96 	.io_offset = DSI_6G_REG_SHIFT,
97 	.regulator_data = msm8994_dsi_regulators,
98 	.num_regulators = ARRAY_SIZE(msm8994_dsi_regulators),
99 	.bus_clk_names = dsi_6g_bus_clk_names,
100 	.num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names),
101 	.io_start = { 0xfd998000, 0xfd9a0000 },
102 	.num_dsi = 2,
103 };
104 
105 static const char * const dsi_8996_bus_clk_names[] = {
106 	"mdp_core", "iface", "bus", "core_mmss",
107 };
108 
109 static const struct regulator_bulk_data msm8996_dsi_regulators[] = {
110 	{ .supply = "vdda", .init_load_uA = 18160 },	/* 1.25 V */
111 	{ .supply = "vcca", .init_load_uA = 17000 },	/* 0.925 V */
112 	{ .supply = "vddio", .init_load_uA = 100000 },	/* 1.8 V */
113 };
114 
115 static const struct msm_dsi_config msm8996_dsi_cfg = {
116 	.io_offset = DSI_6G_REG_SHIFT,
117 	.regulator_data = msm8996_dsi_regulators,
118 	.num_regulators = ARRAY_SIZE(msm8996_dsi_regulators),
119 	.bus_clk_names = dsi_8996_bus_clk_names,
120 	.num_bus_clks = ARRAY_SIZE(dsi_8996_bus_clk_names),
121 	.io_start = { 0x994000, 0x996000 },
122 	.num_dsi = 2,
123 };
124 
125 static const char * const dsi_msm8998_bus_clk_names[] = {
126 	"iface", "bus", "core",
127 };
128 
129 static const struct regulator_bulk_data msm8998_dsi_regulators[] = {
130 	{ .supply = "vdd", .init_load_uA = 367000 },	/* 0.9 V */
131 	{ .supply = "vdda", .init_load_uA = 62800 },	/* 1.2 V */
132 };
133 
134 static const struct msm_dsi_config msm8998_dsi_cfg = {
135 	.io_offset = DSI_6G_REG_SHIFT,
136 	.regulator_data = msm8998_dsi_regulators,
137 	.num_regulators = ARRAY_SIZE(msm8998_dsi_regulators),
138 	.bus_clk_names = dsi_msm8998_bus_clk_names,
139 	.num_bus_clks = ARRAY_SIZE(dsi_msm8998_bus_clk_names),
140 	.io_start = { 0xc994000, 0xc996000 },
141 	.num_dsi = 2,
142 };
143 
144 static const char * const dsi_sdm660_bus_clk_names[] = {
145 	"iface", "bus", "core", "core_mmss",
146 };
147 
148 static const struct regulator_bulk_data sdm660_dsi_regulators[] = {
149 	{ .supply = "vdda", .init_load_uA = 12560 },	/* 1.2 V */
150 };
151 
152 static const struct msm_dsi_config sdm660_dsi_cfg = {
153 	.io_offset = DSI_6G_REG_SHIFT,
154 	.regulator_data = sdm660_dsi_regulators,
155 	.num_regulators = ARRAY_SIZE(sdm660_dsi_regulators),
156 	.bus_clk_names = dsi_sdm660_bus_clk_names,
157 	.num_bus_clks = ARRAY_SIZE(dsi_sdm660_bus_clk_names),
158 	.io_start = { 0xc994000, 0xc996000 },
159 	.num_dsi = 2,
160 };
161 
162 static const char * const dsi_sdm845_bus_clk_names[] = {
163 	"iface", "bus",
164 };
165 
166 static const char * const dsi_sc7180_bus_clk_names[] = {
167 	"iface", "bus",
168 };
169 
170 static const struct regulator_bulk_data sdm845_dsi_regulators[] = {
171 	{ .supply = "vdda", .init_load_uA = 21800 },	/* 1.2 V */
172 };
173 
174 static const struct msm_dsi_config sdm845_dsi_cfg = {
175 	.io_offset = DSI_6G_REG_SHIFT,
176 	.regulator_data = sdm845_dsi_regulators,
177 	.num_regulators = ARRAY_SIZE(sdm845_dsi_regulators),
178 	.bus_clk_names = dsi_sdm845_bus_clk_names,
179 	.num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names),
180 	.io_start = { 0xae94000, 0xae96000 },
181 	.num_dsi = 2,
182 };
183 
184 static const struct regulator_bulk_data sm8550_dsi_regulators[] = {
185 	{ .supply = "vdda", .init_load_uA = 16800 },	/* 1.2 V */
186 };
187 
188 static const struct msm_dsi_config sm8550_dsi_cfg = {
189 	.io_offset = DSI_6G_REG_SHIFT,
190 	.regulator_data = sm8550_dsi_regulators,
191 	.num_regulators = ARRAY_SIZE(sm8550_dsi_regulators),
192 	.bus_clk_names = dsi_sdm845_bus_clk_names,
193 	.num_bus_clks = ARRAY_SIZE(dsi_sdm845_bus_clk_names),
194 	.io_start = { 0xae94000, 0xae96000 },
195 	.num_dsi = 2,
196 };
197 
198 static const struct regulator_bulk_data sc7180_dsi_regulators[] = {
199 	{ .supply = "vdda", .init_load_uA = 21800 },	/* 1.2 V */
200 };
201 
202 static const struct msm_dsi_config sc7180_dsi_cfg = {
203 	.io_offset = DSI_6G_REG_SHIFT,
204 	.regulator_data = sc7180_dsi_regulators,
205 	.num_regulators = ARRAY_SIZE(sc7180_dsi_regulators),
206 	.bus_clk_names = dsi_sc7180_bus_clk_names,
207 	.num_bus_clks = ARRAY_SIZE(dsi_sc7180_bus_clk_names),
208 	.io_start = { 0xae94000 },
209 	.num_dsi = 1,
210 };
211 
212 static const char * const dsi_sc7280_bus_clk_names[] = {
213 	"iface", "bus",
214 };
215 
216 static const struct regulator_bulk_data sc7280_dsi_regulators[] = {
217 	{ .supply = "vdda", .init_load_uA = 8350 },	/* 1.2 V */
218 };
219 
220 static const struct msm_dsi_config sc7280_dsi_cfg = {
221 	.io_offset = DSI_6G_REG_SHIFT,
222 	.regulator_data = sc7280_dsi_regulators,
223 	.num_regulators = ARRAY_SIZE(sc7280_dsi_regulators),
224 	.bus_clk_names = dsi_sc7280_bus_clk_names,
225 	.num_bus_clks = ARRAY_SIZE(dsi_sc7280_bus_clk_names),
226 	.io_start = { 0xae94000, 0xae96000 },
227 	.num_dsi = 2,
228 };
229 
230 static const char * const dsi_qcm2290_bus_clk_names[] = {
231 	"iface", "bus",
232 };
233 
234 static const struct regulator_bulk_data qcm2290_dsi_cfg_regulators[] = {
235 	{ .supply = "vdda", .init_load_uA = 21800 },	/* 1.2 V */
236 };
237 
238 static const struct msm_dsi_config qcm2290_dsi_cfg = {
239 	.io_offset = DSI_6G_REG_SHIFT,
240 	.regulator_data = qcm2290_dsi_cfg_regulators,
241 	.num_regulators = ARRAY_SIZE(qcm2290_dsi_cfg_regulators),
242 	.bus_clk_names = dsi_qcm2290_bus_clk_names,
243 	.num_bus_clks = ARRAY_SIZE(dsi_qcm2290_bus_clk_names),
244 	.io_start = { 0x5e94000 },
245 	.num_dsi = 1,
246 };
247 
248 static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = {
249 	.link_clk_set_rate = dsi_link_clk_set_rate_v2,
250 	.link_clk_enable = dsi_link_clk_enable_v2,
251 	.link_clk_disable = dsi_link_clk_disable_v2,
252 	.clk_init_ver = dsi_clk_init_v2,
253 	.tx_buf_alloc = dsi_tx_buf_alloc_v2,
254 	.tx_buf_get = dsi_tx_buf_get_v2,
255 	.tx_buf_put = NULL,
256 	.dma_base_get = dsi_dma_base_get_v2,
257 	.calc_clk_rate = dsi_calc_clk_rate_v2,
258 };
259 
260 static const struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = {
261 	.link_clk_set_rate = dsi_link_clk_set_rate_6g,
262 	.link_clk_enable = dsi_link_clk_enable_6g,
263 	.link_clk_disable = dsi_link_clk_disable_6g,
264 	.clk_init_ver = NULL,
265 	.tx_buf_alloc = dsi_tx_buf_alloc_6g,
266 	.tx_buf_get = dsi_tx_buf_get_6g,
267 	.tx_buf_put = dsi_tx_buf_put_6g,
268 	.dma_base_get = dsi_dma_base_get_6g,
269 	.calc_clk_rate = dsi_calc_clk_rate_6g,
270 };
271 
272 static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = {
273 	.link_clk_set_rate = dsi_link_clk_set_rate_6g,
274 	.link_clk_enable = dsi_link_clk_enable_6g,
275 	.link_clk_disable = dsi_link_clk_disable_6g,
276 	.clk_init_ver = dsi_clk_init_6g_v2,
277 	.tx_buf_alloc = dsi_tx_buf_alloc_6g,
278 	.tx_buf_get = dsi_tx_buf_get_6g,
279 	.tx_buf_put = dsi_tx_buf_put_6g,
280 	.dma_base_get = dsi_dma_base_get_6g,
281 	.calc_clk_rate = dsi_calc_clk_rate_6g,
282 };
283 
284 static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
285 	{MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064,
286 		&apq8064_dsi_cfg, &msm_dsi_v2_host_ops},
287 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
288 		&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
289 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
290 		&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
291 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
292 		&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
293 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
294 		&msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops},
295 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3,
296 		&msm8994_dsi_cfg, &msm_dsi_6g_host_ops},
297 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1,
298 		&msm8916_dsi_cfg, &msm_dsi_6g_host_ops},
299 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1,
300 		&msm8996_dsi_cfg, &msm_dsi_6g_host_ops},
301 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_2,
302 		&msm8976_dsi_cfg, &msm_dsi_6g_host_ops},
303 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_1_0,
304 		&sdm660_dsi_cfg, &msm_dsi_6g_v2_host_ops},
305 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0,
306 		&msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops},
307 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
308 		&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
309 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
310 		&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
311 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
312 		&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
313 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
314 		&sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops},
315 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0,
316 		&sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops},
317 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0,
318 		&sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops},
319 	{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0,
320 		&sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops},
321 };
322 
323 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
324 {
325 	const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
326 	int i;
327 
328 	for (i = ARRAY_SIZE(dsi_cfg_handlers) - 1; i >= 0; i--) {
329 		if ((dsi_cfg_handlers[i].major == major) &&
330 			(dsi_cfg_handlers[i].minor == minor)) {
331 			cfg_hnd = &dsi_cfg_handlers[i];
332 			break;
333 		}
334 	}
335 
336 	return cfg_hnd;
337 }
338 
339 /*  Non autodetect configs */
340 const struct msm_dsi_cfg_handler qcm2290_dsi_cfg_handler = {
341 	.cfg = &qcm2290_dsi_cfg,
342 	.ops = &msm_dsi_6g_v2_host_ops,
343 };
344